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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1674200364; x=1676792365; bh=J5GmLYMy12Z9K2jBwR GgeedjbRu4yY9N+HuLVIM+/8I=; b=ikPuJZVxd/YD1iPSGbcXbxngs4/n6sziuM AQniQ0tx0F9+W5lQZEM2Y/QS0dIbzIyj7Mi9hT2OoTvOc2cGKf8r52GKGuU3WjwH MsaZJssTf5NLHIom6EfzKR+jDuaar9Vc6iaVUr5W958rpLR+mBttkS+0L7n14Pg0 coxnhsfMi7NLXrEJQ82PAhQ4TAgR5yN2leyeVgnrNPYjc5duUDr5NY0uioEuEH7I 8/lgPPmzwNulPmmRPLEfPIp36AVzEuBig/1KxrxZNWkUkTZ7Rpaz44e87e6eJYwI NxNTcr2x54OAc0O4W/+BIeaaVVF8X+clDD4KpEACSYIGUEULNKRQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 01/37] hw/char: riscv_htif: Avoid using magic numbers Date: Fri, 20 Jan 2023 17:38:37 +1000 Message-Id: <20230120073913.1028407-2-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200425675100005 Content-Type: text/plain; charset="utf-8" From: Bin Meng The Spike HTIF is poorly documented. The only relevant info we can get from the internet is from Andrew Waterman at [1]. Add a comment block before htif_handle_tohost_write() to explain the tohost register format, and use meaningful macros instead of magic numbers in the codes. While we are here, correct 2 multi-line comment blocks that have wrong format. Link: https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuec= omment-607657754 [1] Signed-off-by: Bin Meng Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-Id: <20221229091828.1945072-2-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- hw/char/riscv_htif.c | 72 ++++++++++++++++++++++++++++++++------------ 1 file changed, 52 insertions(+), 20 deletions(-) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 6577f0e640..088556bb04 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -38,6 +38,16 @@ } = \ } while (0) =20 +#define HTIF_DEV_SHIFT 56 +#define HTIF_CMD_SHIFT 48 + +#define HTIF_DEV_SYSTEM 0 +#define HTIF_DEV_CONSOLE 1 + +#define HTIF_SYSTEM_CMD_SYSCALL 0 +#define HTIF_CONSOLE_CMD_GETC 0 +#define HTIF_CONSOLE_CMD_PUTC 1 + static uint64_t fromhost_addr, tohost_addr; static int address_symbol_set; =20 @@ -81,9 +91,11 @@ static void htif_recv(void *opaque, const uint8_t *buf, = int size) return; } =20 - /* TODO - we need to check whether mfromhost is zero which indicates - the device is ready to receive. The current implementation - will drop characters */ + /* + * TODO - we need to check whether mfromhost is zero which indicates + * the device is ready to receive. The current implementation + * will drop characters + */ =20 uint64_t val_written =3D htifstate->pending_read; uint64_t resp =3D 0x100 | *buf; @@ -110,10 +122,30 @@ static int htif_be_change(void *opaque) return 0; } =20 +/* + * See below the tohost register format. + * + * Bits 63:56 indicate the "device". + * Bits 55:48 indicate the "command". + * + * Device 0 is the syscall device, which is used to emulate Unixy syscalls. + * It only implements command 0, which has two subfunctions: + * - If bit 0 is clear, then bits 47:0 represent a pointer to a struct + * describing the syscall. + * - If bit 1 is set, then bits 47:1 represent an exit code, with a zero + * value indicating success and other values indicating failure. + * + * Device 1 is the blocking character device. + * - Command 0 reads a character + * - Command 1 writes a character from the 8 LSBs of tohost + * + * For RV32, the tohost register is zero-extended, so only device=3D0 and + * command=3D0 (i.e. HTIF syscalls/exit codes) are supported. + */ static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_wr= itten) { - uint8_t device =3D val_written >> 56; - uint8_t cmd =3D val_written >> 48; + uint8_t device =3D val_written >> HTIF_DEV_SHIFT; + uint8_t cmd =3D val_written >> HTIF_CMD_SHIFT; uint64_t payload =3D val_written & 0xFFFFFFFFFFFFULL; int resp =3D 0; =20 @@ -125,9 +157,9 @@ static void htif_handle_tohost_write(HTIFState *htifsta= te, uint64_t val_written) * 0: riscv-tests Pass/Fail Reporting Only (no syscall proxy) * 1: Console */ - if (unlikely(device =3D=3D 0x0)) { + if (unlikely(device =3D=3D HTIF_DEV_SYSTEM)) { /* frontend syscall handler, shutdown and exit code support */ - if (cmd =3D=3D 0x0) { + if (cmd =3D=3D HTIF_SYSTEM_CMD_SYSCALL) { if (payload & 0x1) { /* exit code */ int exit_code =3D payload >> 1; @@ -138,14 +170,14 @@ static void htif_handle_tohost_write(HTIFState *htifs= tate, uint64_t val_written) } else { qemu_log("HTIF device %d: unknown command\n", device); } - } else if (likely(device =3D=3D 0x1)) { + } else if (likely(device =3D=3D HTIF_DEV_CONSOLE)) { /* HTIF Console */ - if (cmd =3D=3D 0x0) { + if (cmd =3D=3D HTIF_CONSOLE_CMD_GETC) { /* this should be a queue, but not yet implemented as such */ htifstate->pending_read =3D val_written; htifstate->env->mtohost =3D 0; /* clear to indicate we read */ return; - } else if (cmd =3D=3D 0x1) { + } else if (cmd =3D=3D HTIF_CONSOLE_CMD_PUTC) { qemu_chr_fe_write(&htifstate->chr, (uint8_t *)&payload, 1); resp =3D 0x100 | (uint8_t)payload; } else { @@ -157,15 +189,15 @@ static void htif_handle_tohost_write(HTIFState *htifs= tate, uint64_t val_written) " payload: %016" PRIx64, device, cmd, payload & 0xFF, payload); } /* - * - latest bbl does not set fromhost to 0 if there is a value in toho= st - * - with this code enabled, qemu hangs waiting for fromhost to go to 0 - * - with this code disabled, qemu works with bbl priv v1.9.1 and v1.10 - * - HTIF needs protocol documentation and a more complete state machi= ne - - while (!htifstate->fromhost_inprogress && - htifstate->env->mfromhost !=3D 0x0) { - } - */ + * Latest bbl does not set fromhost to 0 if there is a value in tohost. + * With this code enabled, qemu hangs waiting for fromhost to go to 0. + * With this code disabled, qemu works with bbl priv v1.9.1 and v1.10. + * HTIF needs protocol documentation and a more complete state machine. + * + * while (!htifstate->fromhost_inprogress && + * htifstate->env->mfromhost !=3D 0x0) { + * } + */ htifstate->env->mfromhost =3D (val_written >> 48 << 48) | (resp << 16 = >> 16); htifstate->env->mtohost =3D 0; /* clear to indicate we read */ } @@ -196,7 +228,7 @@ static uint64_t htif_mm_read(void *opaque, hwaddr addr,= unsigned size) =20 /* CPU wrote to an HTIF register */ static void htif_mm_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) + uint64_t value, unsigned size) { HTIFState *htifstate =3D opaque; if (addr =3D=3D TOHOST_OFFSET1) { --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200521260521.9466923181758; Thu, 19 Jan 2023 23:42:01 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIm02-0007hQ-KC; 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s=dkim; t=1674200366; x=1676792367; bh=1tjsEiMWRJO9aUthDa 7dGdc5q/vCCXImXu/Bv6Avj2k=; b=YLgu4TxThzSkexGJ0Gz5Z4PA8hiAvAwaZx 6VB5jAtzHkICaG8XwOq+jQH2GhJUtCQzwdJrBzC3ZHBToGHWiRgIpqdnWybftCoC mLr4ubtyJ15QU+C0Sq+YjSKreipHH0A5VOmV8nBauVbx6t/f8RcIzIZJYdkZUn9x 8aWcpFRS4BCcQpiAs9aQVmSolHmG0N9rWn4S91B8rednEEdmuwXrJ7bGXPz5LLe6 DfIyavNJWEDipzZp4/HEDify5PjQ6kVB5h5OgDo7vdi5mFKqPXJQ445F8+zFKv4k g6MHBO1WqNyTKgNCVlFmLNDHm5BYCAXai+1/ES7Jz0xCqnfk/0aw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 02/37] hw/char: riscv_htif: Drop {to, from}host_size in HTIFState Date: Fri, 20 Jan 2023 17:38:38 +1000 Message-Id: <20230120073913.1028407-3-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200521732100002 Content-Type: text/plain; charset="utf-8" From: Bin Meng These are not used anywhere. Drop them. Signed-off-by: Bin Meng Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-Id: <20221229091828.1945072-3-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- include/hw/char/riscv_htif.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h index f888ac1b30..3eccc1914f 100644 --- a/include/hw/char/riscv_htif.h +++ b/include/hw/char/riscv_htif.h @@ -33,8 +33,6 @@ typedef struct HTIFState { =20 hwaddr tohost_offset; hwaddr fromhost_offset; - uint64_t tohost_size; - uint64_t fromhost_size; MemoryRegion mmio; MemoryRegion *address_space; MemoryRegion *main_mem; --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200430701382.5093475166167; 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s=dkim; t=1674200367; x=1676792368; bh=CU+wBVzNNII4v6yI3s ENTRDyq6Z7gbdYbVey7yTnsYQ=; b=eecbQ7oBy2UtTGm05KD2YMOAPNybXh+4dq PZaCefKqCOBwhhkFxQxULS0fkSdNm6wXkSRpsmIO0e0a7Hg+WJeNRsBWXtiag351 UtEtbb3uNK9eoB8dGhFUnDHq5rXJuVQzNviB1k6WqbB09zs/RpPZiXsinseXA7kp rNotq3RW2AmqUKyjLqaIwl/wbwPChwm6ploaaDnrMJYrobObqz2h9aW/O3oFenfC tEsojnesH/Xm2Qnt33YWGVIi9EBdp2xuwHQSqQk4eJtBDnc71VM7lN6Ct7Jt0Stz YTPVHIRMEyo4G7+Sfu6gigIlQ9gehbH83LI/IEPvTJ8fhVhkqh4g== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 03/37] hw/char: riscv_htif: Drop useless assignment of memory region Date: Fri, 20 Jan 2023 17:38:39 +1000 Message-Id: <20230120073913.1028407-4-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200431274100003 Content-Type: text/plain; charset="utf-8" From: Bin Meng struct HTIFState has 3 members for address space and memory region, and are initialized during htif_mm_init(). But they are actually useless. Drop them. Signed-off-by: Bin Meng Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-Id: <20221229091828.1945072-4-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- include/hw/char/riscv_htif.h | 7 ++----- hw/char/riscv_htif.c | 7 ++----- hw/riscv/spike.c | 5 ++--- 3 files changed, 6 insertions(+), 13 deletions(-) diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h index 3eccc1914f..6d172ebd6d 100644 --- a/include/hw/char/riscv_htif.h +++ b/include/hw/char/riscv_htif.h @@ -34,9 +34,6 @@ typedef struct HTIFState { hwaddr tohost_offset; hwaddr fromhost_offset; MemoryRegion mmio; - MemoryRegion *address_space; - MemoryRegion *main_mem; - void *main_mem_ram_ptr; =20 CPURISCVState *env; CharBackend chr; @@ -54,7 +51,7 @@ void htif_symbol_callback(const char *st_name, int st_inf= o, uint64_t st_value, bool htif_uses_elf_symbols(void); =20 /* legacy pre qom */ -HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_me= m, - CPURISCVState *env, Chardev *chr, uint64_t nonelf_base); +HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env, + Chardev *chr, uint64_t nonelf_base); =20 #endif diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 088556bb04..e7e319ca1d 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -265,8 +265,8 @@ bool htif_uses_elf_symbols(void) return (address_symbol_set =3D=3D 3) ? true : false; } =20 -HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_me= m, - CPURISCVState *env, Chardev *chr, uint64_t nonelf_base) +HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env, + Chardev *chr, uint64_t nonelf_base) { uint64_t base, size, tohost_offset, fromhost_offset; =20 @@ -281,9 +281,6 @@ HTIFState *htif_mm_init(MemoryRegion *address_space, Me= moryRegion *main_mem, fromhost_offset =3D fromhost_addr - base; =20 HTIFState *s =3D g_new0(HTIFState, 1); - s->address_space =3D address_space; - s->main_mem =3D main_mem; - s->main_mem_ram_ptr =3D memory_region_get_ram_ptr(main_mem); s->env =3D env; s->tohost_offset =3D tohost_offset; s->fromhost_offset =3D fromhost_offset; diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 13946acf0d..bc4953cf4a 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -316,9 +316,8 @@ static void spike_board_init(MachineState *machine) fdt_load_addr); =20 /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, mask_rom, - &s->soc[0].harts[0].env, serial_hd(0), - memmap[SPIKE_HTIF].base); + htif_mm_init(system_memory, &s->soc[0].harts[0].env, + serial_hd(0), memmap[SPIKE_HTIF].base); } =20 static void spike_machine_instance_init(Object *obj) --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200475137506.79734205776606; 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s=dkim; t=1674200369; x=1676792370; bh=bZ8NUI7Xi8BQY+uA/N +c8ofowZfC+0PX5iTKB91CNiY=; b=SRg5WY8eoNGQGHs0H3iGQp4sV/YpwlmGLd d0KBlBOZwqQ3Fmjw62xEb6jM39cCvG1JKODmo7ibSicMSPZXy1DktY2lcqLC7rd9 stRPQyapmeSbWF3/C066xNuRE6/IB8VezUSRZseS253ElVgkfXUEq8Inh0xGyouq vUpEiHDDpjIBDlDS0MHfxFBwIb1XVscq+s5tQPYbtXb1N4DqeNcmXAWdbfoU10k9 BSSwKU27vACmCFmxHrmunCCcuXl1VRwjEPh2p61QOQnaSGePKm1EiA3MumjFPuh4 8Yhlgkfa7cc/l+1XfWYXsJB4h5fsRd/VE0/GZBzF1PJUSEvSehuw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 04/37] hw/char: riscv_htif: Use conventional 's' for HTIFState Date: Fri, 20 Jan 2023 17:38:40 +1000 Message-Id: <20230120073913.1028407-5-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200475503100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng QEMU source codes tend to use 's' to represent the hardware state. Let's use it for HTIFState. Signed-off-by: Bin Meng Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-Id: <20221229091828.1945072-5-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- hw/char/riscv_htif.c | 64 ++++++++++++++++++++++---------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index e7e319ca1d..f28976b110 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -85,7 +85,7 @@ static int htif_can_recv(void *opaque) */ static void htif_recv(void *opaque, const uint8_t *buf, int size) { - HTIFState *htifstate =3D opaque; + HTIFState *s =3D opaque; =20 if (size !=3D 1) { return; @@ -97,10 +97,10 @@ static void htif_recv(void *opaque, const uint8_t *buf,= int size) * will drop characters */ =20 - uint64_t val_written =3D htifstate->pending_read; + uint64_t val_written =3D s->pending_read; uint64_t resp =3D 0x100 | *buf; =20 - htifstate->env->mfromhost =3D (val_written >> 48 << 48) | (resp << 16 = >> 16); + s->env->mfromhost =3D (val_written >> 48 << 48) | (resp << 16 >> 16); } =20 /* @@ -142,7 +142,7 @@ static int htif_be_change(void *opaque) * For RV32, the tohost register is zero-extended, so only device=3D0 and * command=3D0 (i.e. HTIF syscalls/exit codes) are supported. */ -static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_wr= itten) +static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written) { uint8_t device =3D val_written >> HTIF_DEV_SHIFT; uint8_t cmd =3D val_written >> HTIF_CMD_SHIFT; @@ -174,11 +174,11 @@ static void htif_handle_tohost_write(HTIFState *htifs= tate, uint64_t val_written) /* HTIF Console */ if (cmd =3D=3D HTIF_CONSOLE_CMD_GETC) { /* this should be a queue, but not yet implemented as such */ - htifstate->pending_read =3D val_written; - htifstate->env->mtohost =3D 0; /* clear to indicate we read */ + s->pending_read =3D val_written; + s->env->mtohost =3D 0; /* clear to indicate we read */ return; } else if (cmd =3D=3D HTIF_CONSOLE_CMD_PUTC) { - qemu_chr_fe_write(&htifstate->chr, (uint8_t *)&payload, 1); + qemu_chr_fe_write(&s->chr, (uint8_t *)&payload, 1); resp =3D 0x100 | (uint8_t)payload; } else { qemu_log("HTIF device %d: unknown command\n", device); @@ -194,31 +194,31 @@ static void htif_handle_tohost_write(HTIFState *htifs= tate, uint64_t val_written) * With this code disabled, qemu works with bbl priv v1.9.1 and v1.10. * HTIF needs protocol documentation and a more complete state machine. * - * while (!htifstate->fromhost_inprogress && - * htifstate->env->mfromhost !=3D 0x0) { + * while (!s->fromhost_inprogress && + * s->env->mfromhost !=3D 0x0) { * } */ - htifstate->env->mfromhost =3D (val_written >> 48 << 48) | (resp << 16 = >> 16); - htifstate->env->mtohost =3D 0; /* clear to indicate we read */ + s->env->mfromhost =3D (val_written >> 48 << 48) | (resp << 16 >> 16); + s->env->mtohost =3D 0; /* clear to indicate we read */ } =20 -#define TOHOST_OFFSET1 (htifstate->tohost_offset) -#define TOHOST_OFFSET2 (htifstate->tohost_offset + 4) -#define FROMHOST_OFFSET1 (htifstate->fromhost_offset) -#define FROMHOST_OFFSET2 (htifstate->fromhost_offset + 4) +#define TOHOST_OFFSET1 (s->tohost_offset) +#define TOHOST_OFFSET2 (s->tohost_offset + 4) +#define FROMHOST_OFFSET1 (s->fromhost_offset) +#define FROMHOST_OFFSET2 (s->fromhost_offset + 4) =20 /* CPU wants to read an HTIF register */ static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size) { - HTIFState *htifstate =3D opaque; + HTIFState *s =3D opaque; if (addr =3D=3D TOHOST_OFFSET1) { - return htifstate->env->mtohost & 0xFFFFFFFF; + return s->env->mtohost & 0xFFFFFFFF; } else if (addr =3D=3D TOHOST_OFFSET2) { - return (htifstate->env->mtohost >> 32) & 0xFFFFFFFF; + return (s->env->mtohost >> 32) & 0xFFFFFFFF; } else if (addr =3D=3D FROMHOST_OFFSET1) { - return htifstate->env->mfromhost & 0xFFFFFFFF; + return s->env->mfromhost & 0xFFFFFFFF; } else if (addr =3D=3D FROMHOST_OFFSET2) { - return (htifstate->env->mfromhost >> 32) & 0xFFFFFFFF; + return (s->env->mfromhost >> 32) & 0xFFFFFFFF; } else { qemu_log("Invalid htif read: address %016" PRIx64 "\n", (uint64_t)addr); @@ -230,25 +230,25 @@ static uint64_t htif_mm_read(void *opaque, hwaddr add= r, unsigned size) static void htif_mm_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - HTIFState *htifstate =3D opaque; + HTIFState *s =3D opaque; if (addr =3D=3D TOHOST_OFFSET1) { - if (htifstate->env->mtohost =3D=3D 0x0) { - htifstate->allow_tohost =3D 1; - htifstate->env->mtohost =3D value & 0xFFFFFFFF; + if (s->env->mtohost =3D=3D 0x0) { + s->allow_tohost =3D 1; + s->env->mtohost =3D value & 0xFFFFFFFF; } else { - htifstate->allow_tohost =3D 0; + s->allow_tohost =3D 0; } } else if (addr =3D=3D TOHOST_OFFSET2) { - if (htifstate->allow_tohost) { - htifstate->env->mtohost |=3D value << 32; - htif_handle_tohost_write(htifstate, htifstate->env->mtohost); + if (s->allow_tohost) { + s->env->mtohost |=3D value << 32; + htif_handle_tohost_write(s, s->env->mtohost); } } else if (addr =3D=3D FROMHOST_OFFSET1) { - htifstate->fromhost_inprogress =3D 1; - htifstate->env->mfromhost =3D value & 0xFFFFFFFF; + s->fromhost_inprogress =3D 1; + s->env->mfromhost =3D value & 0xFFFFFFFF; } else if (addr =3D=3D FROMHOST_OFFSET2) { - htifstate->env->mfromhost |=3D value << 32; - htifstate->fromhost_inprogress =3D 0; + s->env->mfromhost |=3D value << 32; + s->fromhost_inprogress =3D 0; } else { qemu_log("Invalid htif write: address %016" PRIx64 "\n", (uint64_t)addr); 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1674200371; x=1676792372; bh=yf7KWOAqQj5uEmXiGl PlgmbflZZe24Ms6Lj0x3HmqgM=; b=rSgKnVM2jwaRcnxHqK/lkHY22LMQysrX3H /5LdrIuc+H+3wUiVjUkdUjlWakjlJ9wwEra4il+PD4+Nu/Md2hd64qnViLTEMIQ2 AavY1V75mg35yCgHsgTAFx4UWKxx9729B2ufMciE3zRbXcvwxRdKnaJ2zeClezKo XYmmryqVcx/vvMh28QwR6yZtDeHcePCeVn0H4jYaF6+rn4WDcEC8hwSzkZIB6FF8 3c+uu+vI6DkEwRKn4iPGL7f6a99rm329rhsI6TbsZ+D9+zXHPgsMH4KZH6xTEKv2 AhIev/07XCjfQaMHVPOsDEkJIZu8/MQrh54vYHiM2buJ3RjmMIZg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 05/37] hw/char: riscv_htif: Move registers from CPUArchState to HTIFState Date: Fri, 20 Jan 2023 17:38:41 +1000 Message-Id: <20230120073913.1028407-6-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200467414100003 Content-Type: text/plain; charset="utf-8" From: Bin Meng At present for some unknown reason the HTIF registers (fromhost & tohost) are defined in the RISC-V CPUArchState. It should really be put in the HTIFState struct as it is only meaningful to HTIF. Signed-off-by: Bin Meng Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-Id: <20221229091828.1945072-6-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- include/hw/char/riscv_htif.h | 8 ++++---- target/riscv/cpu.h | 4 ---- hw/char/riscv_htif.c | 35 +++++++++++++++++------------------ hw/riscv/spike.c | 3 +-- target/riscv/machine.c | 6 ++---- 5 files changed, 24 insertions(+), 32 deletions(-) diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h index 6d172ebd6d..55cc352331 100644 --- a/include/hw/char/riscv_htif.h +++ b/include/hw/char/riscv_htif.h @@ -23,7 +23,6 @@ #include "chardev/char.h" #include "chardev/char-fe.h" #include "exec/memory.h" -#include "target/riscv/cpu.h" =20 #define TYPE_HTIF_UART "riscv.htif.uart" =20 @@ -31,11 +30,12 @@ typedef struct HTIFState { int allow_tohost; int fromhost_inprogress; =20 + uint64_t tohost; + uint64_t fromhost; hwaddr tohost_offset; hwaddr fromhost_offset; MemoryRegion mmio; =20 - CPURISCVState *env; CharBackend chr; uint64_t pending_read; } HTIFState; @@ -51,7 +51,7 @@ void htif_symbol_callback(const char *st_name, int st_inf= o, uint64_t st_value, bool htif_uses_elf_symbols(void); =20 /* legacy pre qom */ -HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env, - Chardev *chr, uint64_t nonelf_base); +HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr, + uint64_t nonelf_base); =20 #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f5609b62a2..61a9a40958 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -309,10 +309,6 @@ struct CPUArchState { target_ulong sscratch; target_ulong mscratch; =20 - /* temporary htif regs */ - uint64_t mfromhost; - uint64_t mtohost; - /* Sstc CSRs */ uint64_t stimecmp; =20 diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index f28976b110..3bb0a37a3e 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -100,7 +100,7 @@ static void htif_recv(void *opaque, const uint8_t *buf,= int size) uint64_t val_written =3D s->pending_read; uint64_t resp =3D 0x100 | *buf; =20 - s->env->mfromhost =3D (val_written >> 48 << 48) | (resp << 16 >> 16); + s->fromhost =3D (val_written >> 48 << 48) | (resp << 16 >> 16); } =20 /* @@ -175,7 +175,7 @@ static void htif_handle_tohost_write(HTIFState *s, uint= 64_t val_written) if (cmd =3D=3D HTIF_CONSOLE_CMD_GETC) { /* this should be a queue, but not yet implemented as such */ s->pending_read =3D val_written; - s->env->mtohost =3D 0; /* clear to indicate we read */ + s->tohost =3D 0; /* clear to indicate we read */ return; } else if (cmd =3D=3D HTIF_CONSOLE_CMD_PUTC) { qemu_chr_fe_write(&s->chr, (uint8_t *)&payload, 1); @@ -195,11 +195,11 @@ static void htif_handle_tohost_write(HTIFState *s, ui= nt64_t val_written) * HTIF needs protocol documentation and a more complete state machine. * * while (!s->fromhost_inprogress && - * s->env->mfromhost !=3D 0x0) { + * s->fromhost !=3D 0x0) { * } */ - s->env->mfromhost =3D (val_written >> 48 << 48) | (resp << 16 >> 16); - s->env->mtohost =3D 0; /* clear to indicate we read */ + s->fromhost =3D (val_written >> 48 << 48) | (resp << 16 >> 16); + s->tohost =3D 0; /* clear to indicate we read */ } =20 #define TOHOST_OFFSET1 (s->tohost_offset) @@ -212,13 +212,13 @@ static uint64_t htif_mm_read(void *opaque, hwaddr add= r, unsigned size) { HTIFState *s =3D opaque; if (addr =3D=3D TOHOST_OFFSET1) { - return s->env->mtohost & 0xFFFFFFFF; + return s->tohost & 0xFFFFFFFF; } else if (addr =3D=3D TOHOST_OFFSET2) { - return (s->env->mtohost >> 32) & 0xFFFFFFFF; + return (s->tohost >> 32) & 0xFFFFFFFF; } else if (addr =3D=3D FROMHOST_OFFSET1) { - return s->env->mfromhost & 0xFFFFFFFF; + return s->fromhost & 0xFFFFFFFF; } else if (addr =3D=3D FROMHOST_OFFSET2) { - return (s->env->mfromhost >> 32) & 0xFFFFFFFF; + return (s->fromhost >> 32) & 0xFFFFFFFF; } else { qemu_log("Invalid htif read: address %016" PRIx64 "\n", (uint64_t)addr); @@ -232,22 +232,22 @@ static void htif_mm_write(void *opaque, hwaddr addr, { HTIFState *s =3D opaque; if (addr =3D=3D TOHOST_OFFSET1) { - if (s->env->mtohost =3D=3D 0x0) { + if (s->tohost =3D=3D 0x0) { s->allow_tohost =3D 1; - s->env->mtohost =3D value & 0xFFFFFFFF; + s->tohost =3D value & 0xFFFFFFFF; } else { s->allow_tohost =3D 0; } } else if (addr =3D=3D TOHOST_OFFSET2) { if (s->allow_tohost) { - s->env->mtohost |=3D value << 32; - htif_handle_tohost_write(s, s->env->mtohost); + s->tohost |=3D value << 32; + htif_handle_tohost_write(s, s->tohost); } } else if (addr =3D=3D FROMHOST_OFFSET1) { s->fromhost_inprogress =3D 1; - s->env->mfromhost =3D value & 0xFFFFFFFF; + s->fromhost =3D value & 0xFFFFFFFF; } else if (addr =3D=3D FROMHOST_OFFSET2) { - s->env->mfromhost |=3D value << 32; + s->fromhost |=3D value << 32; s->fromhost_inprogress =3D 0; } else { qemu_log("Invalid htif write: address %016" PRIx64 "\n", @@ -265,8 +265,8 @@ bool htif_uses_elf_symbols(void) return (address_symbol_set =3D=3D 3) ? true : false; } =20 -HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env, - Chardev *chr, uint64_t nonelf_base) +HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr, + uint64_t nonelf_base) { uint64_t base, size, tohost_offset, fromhost_offset; =20 @@ -281,7 +281,6 @@ HTIFState *htif_mm_init(MemoryRegion *address_space, CP= URISCVState *env, fromhost_offset =3D fromhost_addr - base; =20 HTIFState *s =3D g_new0(HTIFState, 1); - s->env =3D env; s->tohost_offset =3D tohost_offset; s->fromhost_offset =3D fromhost_offset; s->pending_read =3D 0; diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index bc4953cf4a..fb4152c2a2 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -316,8 +316,7 @@ static void spike_board_init(MachineState *machine) fdt_load_addr); =20 /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, &s->soc[0].harts[0].env, - serial_hd(0), memmap[SPIKE_HTIF].base); + htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base); } =20 static void spike_machine_instance_init(Object *obj) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 65a8549ec2..c6ce318cce 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -333,8 +333,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = =3D { =20 const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", - .version_id =3D 5, - .minimum_version_id =3D 5, + .version_id =3D 6, + .minimum_version_id =3D 6, .post_load =3D riscv_cpu_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), @@ -384,8 +384,6 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVEN= TS), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), - VMSTATE_UINT64(env.mfromhost, RISCVCPU), - VMSTATE_UINT64(env.mtohost, RISCVCPU), VMSTATE_UINT64(env.stimecmp, RISCVCPU), =20 VMSTATE_END_OF_LIST() --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1674200373; x=1676792374; bh=d1thO4oePkp3zh110L 9bI4kQhD6/p9FCdae8Xbqu4pk=; b=syfu/HhO6Mbpq+8pS1uCs8P+bX9SKMoukL zprzIEG/y7g6fj5FzYs8fGdD8oFudkw136wT006wY1/ZjZ1wWdIpwB1UvioNyhJX YJWUvM/Yo5IKTf4yXp/hyiipCKSVtjA1s8jQMouSUb5VAVRvYuBZXkvFkgYrsqmy XgYe301h1RqKDb9m9A5e01GK5eVO4trchO1Txj3/xEf6hhUoFpOQ7NvsFr7/7X7c CsRXXMKunuWqbk5ZG9Vkq8CLIZ+7OgDFmge/ZR7oE3vv0UAr5PJLJuIZ0RYEacGy jhqolI3NbLf5rBX3Z3I5YL0+yq1+qBEOqC2VU6wkD6QnX63P+RHA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 06/37] hw/char: riscv_htif: Remove forward declarations for non-existent variables Date: Fri, 20 Jan 2023 17:38:42 +1000 Message-Id: <20230120073913.1028407-7-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200439253100005 Content-Type: text/plain; charset="utf-8" From: Bin Meng There are forward declarations for 'vmstate_htif' and 'htif_io_ops' in riscv_htif.h however there are no definitions in the C codes. Signed-off-by: Bin Meng Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-Id: <20221229091828.1945072-7-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- include/hw/char/riscv_htif.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h index 55cc352331..9e8ebbe017 100644 --- a/include/hw/char/riscv_htif.h +++ b/include/hw/char/riscv_htif.h @@ -40,9 +40,6 @@ typedef struct HTIFState { uint64_t pending_read; } HTIFState; =20 -extern const VMStateDescription vmstate_htif; -extern const MemoryRegionOps htif_io_ops; - /* HTIF symbol callback */ void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_va= lue, uint64_t st_size); --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1674200375; x=1676792376; bh=YgqIy2dMtYDfHr6ysw 5QTe/uCyGkNi3HjNfCfNK58Gw=; b=srv6sijrrLb9BJvaN3fklOdFU/PYh+xtic sGzevO2kHbulzR1X0duq9Jcdqu1P+t+0ixhi137oUOT7Lm+TWerKcl26tWldvvmh P2uQArKX2ysd23FzVfVCyUmpGXPOnke5hiGLwHX+QlRtST31J8zqr9g5Ipw+ifZG VZJb1s3uLCrhy89/MmbAiQaGnrbfomuqfvFyxTRf59dZSHwbMT3QaUlmn9+rysDZ /P/rZ4QQoSX0QmYZHHlSrj8ons1WUYOttT7WQPGydKbFq4IXYyIBQRgEdlLfhjIS PcOv0EuiLFi0xxdtwKQu4u+Y1+AjEcoeZvVxET0AZJ6IzPGcGu7Q== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 07/37] hw/char: riscv_htif: Support console output via proxy syscall Date: Fri, 20 Jan 2023 17:38:43 +1000 Message-Id: <20230120073913.1028407-8-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200446372100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng At present the HTIF proxy syscall is unsupported. On RV32, only device 0 is supported so there is no console device for RV32. The only way to implement console funtionality on RV32 is to support the SYS_WRITE syscall. With this commit, the Spike machine is able to boot the 32-bit OpenSBI generic image. Signed-off-by: Bin Meng Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-Id: <20221229091828.1945072-8-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- hw/char/riscv_htif.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 3bb0a37a3e..1477fc0090 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -48,6 +48,9 @@ #define HTIF_CONSOLE_CMD_GETC 0 #define HTIF_CONSOLE_CMD_PUTC 1 =20 +/* PK system call number */ +#define PK_SYS_WRITE 64 + static uint64_t fromhost_addr, tohost_addr; static int address_symbol_set; =20 @@ -165,7 +168,19 @@ static void htif_handle_tohost_write(HTIFState *s, uin= t64_t val_written) int exit_code =3D payload >> 1; exit(exit_code); } else { - qemu_log_mask(LOG_UNIMP, "pk syscall proxy not supported\n= "); + uint64_t syscall[8]; + cpu_physical_memory_read(payload, syscall, sizeof(syscall)= ); + if (syscall[0] =3D=3D PK_SYS_WRITE && + syscall[1] =3D=3D HTIF_DEV_CONSOLE && + syscall[3] =3D=3D HTIF_CONSOLE_CMD_PUTC) { + uint8_t ch; + cpu_physical_memory_read(syscall[2], &ch, 1); + qemu_chr_fe_write(&s->chr, &ch, 1); + resp =3D 0x100 | (uint8_t)payload; + } else { + qemu_log_mask(LOG_UNIMP, + "pk syscall proxy not supported\n"); + } } } else { qemu_log("HTIF device %d: unknown command\n", device); --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167420080691246.851367148133704; Thu, 19 Jan 2023 23:46:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIm0A-0007oo-VZ; Fri, 20 Jan 2023 02:39:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIlzw-0007gh-HJ for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1674200377; x=1676792378; bh=RrU4nYJ19k3rIFe7Cm hKAO0jzgTQSTnqBRFFTnuBj1o=; b=XxVtEOj4yXpNWM/I+CwbYZo7WQ+hXNx6ZU f7DEjTpT2QvbvCLHCcMpZCELkms1eabcq4LHh8iAIHMXt8MCmaGCAomfs9FPkbJc awgFjkMaymRBGabgcCOp+fBy8++o2CHMsfI8UKg0bInAx6jCdfncBxdo1srJIo/B lnksJo/5MzGXm8kSLeDSksWb0zX6rN3yi8CtbQDljXTSbAoE3rC4rtQpzhplstQ2 vk5x41lqBEL+p9Ox1aUsPU3rZ2QTxTgEjf+YPouTbNTXlhsys9rXqwwr7o/g03U0 CaT2tCguZ1/T8vUkjl1jdQ1H1h/0ArzNs/8hVuiks02o2dgMS8iQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 08/37] hw/riscv: spike: Remove the out-of-date comments Date: Fri, 20 Jan 2023 17:38:44 +1000 Message-Id: <20230120073913.1028407-9-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200807402100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng Spike machine now supports OpenSBI plain binary bios image, so the comments are no longer valid. Signed-off-by: Bin Meng Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-Id: <20221229091828.1945072-9-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- hw/riscv/spike.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index fb4152c2a2..df9f070707 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -255,11 +255,6 @@ static void spike_board_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, mask_rom); =20 - /* - * Not like other RISC-V machines that use plain binary bios images, - * keeping ELF files here was intentional because BIN files don't work - * for the Spike machine as HTIF emulation depends on ELF parsing. - */ if (riscv_is_32bit(&s->soc[0])) { firmware_end_addr =3D riscv_find_and_load_firmware(machine, RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].b= ase, --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1674200379; x=1676792380; bh=Dn0Zj4R zxYf4APRsmtpX9Q+QAR9mj1mPr4QlaOcuf7s=; b=GY1nMVGIFJqWWizekdvVoUH 38TJdT7I0Z4ImPK58z7vemhAhPdlpJtJ9Hsq8q0ZtNoUB6VTHRy89GHSjAd3sO5L 9rFUCwsjI12SQ5ebgzhOGIeFGUVxwJZHSz3m5EO9AOMXUCaFkGBrHuXQCMLE5WLF nJyEytxNlar6Ye8idVirsE8GcsIBOP0XlxW3gr04ELxcN+6i32i+pg+lajXkmuDZ D2iFm78UI2Ska1Pb/FKSd/hfYo4lHU+rq7s6BpgcJDAoLvBOvuT5fyoRlul93kAJ RoE6MzPhu729cm5/kYo9xqTIof5CF00JDFZbkFZ6BuKnpoNB+OYazSsqfF3/LcQ= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Bin Meng Subject: [PULL 09/37] hw/riscv/boot.c: make riscv_find_firmware() static Date: Fri, 20 Jan 2023 17:38:45 +1000 Message-Id: <20230120073913.1028407-10-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200511704100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza The only caller is riscv_find_and_load_firmware(), which is in the same file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Bin Meng Message-Id: <20221221182300.307900-5-dbarboza@ventanamicro.com> Message-Id: <20221229091828.1945072-10-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- include/hw/riscv/boot.h | 1 - hw/riscv/boot.c | 44 ++++++++++++++++++++--------------------- 2 files changed, 22 insertions(+), 23 deletions(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 93e5f8760d..c03e4e74c5 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -37,7 +37,6 @@ target_ulong riscv_find_and_load_firmware(MachineState *m= achine, const char *default_machine_firm= ware, hwaddr firmware_load_addr, symbol_fn_t sym_cb); -char *riscv_find_firmware(const char *firmware_filename); target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index ebd351c840..7361d5c0d8 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -75,6 +75,28 @@ target_ulong riscv_calc_kernel_start_addr(RISCVHartArray= State *harts, } } =20 +static char *riscv_find_firmware(const char *firmware_filename) +{ + char *filename; + + filename =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); + if (filename =3D=3D NULL) { + if (!qtest_enabled()) { + /* + * We only ship OpenSBI binary bios images in the QEMU source. + * For machines that use images other than the default bios, + * running QEMU test will complain hence let's suppress the er= ror + * report for QEMU testing. + */ + error_report("Unable to load the RISC-V firmware \"%s\"", + firmware_filename); + exit(1); + } + } + + return filename; +} + target_ulong riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firm= ware, hwaddr firmware_load_addr, @@ -104,28 +126,6 @@ target_ulong riscv_find_and_load_firmware(MachineState= *machine, return firmware_end_addr; } =20 -char *riscv_find_firmware(const char *firmware_filename) -{ - char *filename; - - filename =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); - if (filename =3D=3D NULL) { - if (!qtest_enabled()) { - /* - * We only ship OpenSBI binary bios images in the QEMU source. - * For machines that use images other than the default bios, - * running QEMU test will complain hence let's suppress the er= ror - * report for QEMU testing. - */ - error_report("Unable to load the RISC-V firmware \"%s\"", - firmware_filename); - exit(1); - } - } - - return filename; -} - target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb) --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200511858778.9686470021059; Thu, 19 Jan 2023 23:41:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIm0B-0007q9-V2; Fri, 20 Jan 2023 02:39:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIm01-0007hO-KI for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1674200381; x=1676792382; bh=94cjWS/JRpFzc8QyOm lgNZLD1Ef6wv9Z0i19VVCZzzQ=; b=eZKF9NBf85nRRCmdLYnCJxpIWgoJk3sJT3 esazImGlEiwa253py7pVQ2cHTTwTKE7+Hi+r1QXMve1DSfJjDFlbTx5CtD/rdnqk tLGtty4uHpAcSP3pZg56I++cT+CGAJkelQX16GioYu3UAiefuDMnJxlBw9ILfFPK QRD8lX+UFM4hLRgCLDZ2JubaUlrliKM2dYnQDbmqh0YeXCgxUq0TgOnx823Czenl rQ4p9LGLLWlcvTkDEz4GzkekjZ2QVazB1ReZtEEOzTcC0dgLze6bvfoEw0vP5bzK HJvGKw3PW9nzTARtLpG1FRwuX1EbHqj8NezA6RMI7jRqmM9KDTgQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Bin Meng Subject: [PULL 10/37] hw/riscv/boot.c: introduce riscv_default_firmware_name() Date: Fri, 20 Jan 2023 17:38:46 +1000 Message-Id: <20230120073913.1028407-11-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200513721100014 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Some boards are duplicating the 'riscv_find_and_load_firmware' call because the 32 and 64 bits images have different names. Create a function to handle this detail instead of hardcoding it in the boards. Ideally we would bake this logic inside riscv_find_and_load_firmware(), or even create a riscv_load_default_firmware(), but at this moment we cannot infer whether the machine is running 32 or 64 bits without accessing RISCVHartArrayState, which in turn can't be accessed via the common code from boot.c. In the end we would exchange 'firmware_name' for a flag with riscv_is_32bit(), which isn't much better than what we already have today. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Bin Meng Message-Id: <20221221182300.307900-6-dbarboza@ventanamicro.com> Message-Id: <20221229091828.1945072-11-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- include/hw/riscv/boot.h | 1 + hw/riscv/boot.c | 9 +++++++++ hw/riscv/sifive_u.c | 11 ++++------- hw/riscv/spike.c | 14 +++++--------- hw/riscv/virt.c | 10 +++------- 5 files changed, 22 insertions(+), 23 deletions(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index c03e4e74c5..60cf320c88 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -37,6 +37,7 @@ target_ulong riscv_find_and_load_firmware(MachineState *m= achine, const char *default_machine_firm= ware, hwaddr firmware_load_addr, symbol_fn_t sym_cb); +const char *riscv_default_firmware_name(RISCVHartArrayState *harts); target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 7361d5c0d8..e1a544b1d9 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -75,6 +75,15 @@ target_ulong riscv_calc_kernel_start_addr(RISCVHartArray= State *harts, } } =20 +const char *riscv_default_firmware_name(RISCVHartArrayState *harts) +{ + if (riscv_is_32bit(harts)) { + return RISCV32_BIOS_BIN; + } + + return RISCV64_BIOS_BIN; +} + static char *riscv_find_firmware(const char *firmware_filename) { char *filename; diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index b40a4767e2..a58ddb36ac 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -533,6 +533,7 @@ static void sifive_u_machine_init(MachineState *machine) MemoryRegion *flash0 =3D g_new(MemoryRegion, 1); target_ulong start_addr =3D memmap[SIFIVE_U_DEV_DRAM].base; target_ulong firmware_end_addr, kernel_start_addr; + const char *firmware_name; uint32_t start_addr_hi32 =3D 0x00000000; int i; uint32_t fdt_load_addr; @@ -595,13 +596,9 @@ static void sifive_u_machine_init(MachineState *machin= e) break; } =20 - if (riscv_is_32bit(&s->soc.u_cpus)) { - firmware_end_addr =3D riscv_find_and_load_firmware(machine, - RISCV32_BIOS_BIN, start_addr, NULL); - } else { - firmware_end_addr =3D riscv_find_and_load_firmware(machine, - RISCV64_BIOS_BIN, start_addr, NULL); - } + firmware_name =3D riscv_default_firmware_name(&s->soc.u_cpus); + firmware_end_addr =3D riscv_find_and_load_firmware(machine, firmware_n= ame, + start_addr, NULL); =20 if (machine->kernel_filename) { kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index df9f070707..3c8a8de673 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -190,6 +190,7 @@ static void spike_board_init(MachineState *machine) MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); target_ulong firmware_end_addr, kernel_start_addr; + const char *firmware_name; uint32_t fdt_load_addr; uint64_t kernel_entry; char *soc_name; @@ -255,15 +256,10 @@ static void spike_board_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, mask_rom); =20 - if (riscv_is_32bit(&s->soc[0])) { - firmware_end_addr =3D riscv_find_and_load_firmware(machine, - RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].b= ase, - htif_symbol_callback); - } else { - firmware_end_addr =3D riscv_find_and_load_firmware(machine, - RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].b= ase, - htif_symbol_callback); - } + firmware_name =3D riscv_default_firmware_name(&s->soc[0]); + firmware_end_addr =3D riscv_find_and_load_firmware(machine, firmware_n= ame, + memmap[SPIKE_DRAM].ba= se, + htif_symbol_callback); =20 /* Load kernel */ if (machine->kernel_filename) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 94ff2a1584..408f7a2256 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1237,6 +1237,7 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) MachineState *machine =3D MACHINE(s); target_ulong start_addr =3D memmap[VIRT_DRAM].base; target_ulong firmware_end_addr, kernel_start_addr; + const char *firmware_name =3D riscv_default_firmware_name(&s->soc[0]); uint32_t fdt_load_addr; uint64_t kernel_entry; =20 @@ -1256,13 +1257,8 @@ static void virt_machine_done(Notifier *notifier, vo= id *data) } } =20 - if (riscv_is_32bit(&s->soc[0])) { - firmware_end_addr =3D riscv_find_and_load_firmware(machine, - RISCV32_BIOS_BIN, start_addr, NULL); - } else { - firmware_end_addr =3D riscv_find_and_load_firmware(machine, - RISCV64_BIOS_BIN, start_addr, NULL); - } + firmware_end_addr =3D riscv_find_and_load_firmware(machine, firmware_n= ame, + start_addr, NULL); =20 /* * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the dev= ice --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200676848437.8855182533712; Thu, 19 Jan 2023 23:44:36 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIm0E-0007uw-UY; Fri, 20 Jan 2023 02:39:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIm0C-0007qd-Sh for qemu-devel@nongnu.org; Fri, 20 Jan 2023 02:39:56 -0500 Received: from esa5.hgst.iphmx.com ([216.71.153.144]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIm0B-0004pU-0X for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1674200383; x=1676792384; bh=nqQG7k5fhFlJn1OmbI YfAXBTtjCCcG5eoJ1I/boo0bQ=; b=jUFNnvthHlVKCxjaKTCkuNm8d/PH5gwx+x +B4jqTQfu6OP/6UBMz06hBrnmaNzt3GDs5rOXeThF11s2CNPPGEMFtcOX1PiTCym hlPV6zx191zbZrD6SYPzOLBdV/1bQCa//PiiJ7P9PhJW3PjiCp5Dv87QplmTHLb3 nKi4uEPl4rtBpWdZJ7a46sVsFsTMVb9QZjBvpPTBMcZbt40wNUU7LePbjeIvK7OF V0Mqx6NFJ9pv+Zvs3a8xNwBRD8KfZDeJeqpolzQcvXSbwe1N3YZGPchQpseQQJyl mX4FYj2UC1sddfsmI4oyjL329tonkkvQndRSiFHdFBrmgwzVVeUA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 11/37] hw/riscv/boot.c: Introduce riscv_find_firmware() Date: Fri, 20 Jan 2023 17:38:47 +1000 Message-Id: <20230120073913.1028407-12-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200678660100017 Content-Type: text/plain; charset="utf-8" From: Bin Meng Rename previous riscv_find_firmware() to riscv_find_bios(), and introduce a new riscv_find_firmware() to implement the first half part of the work done in riscv_find_and_load_firmware(). This new API is helpful for machine that wants to know the final chosen firmware file name but does not want to load it. Signed-off-by: Bin Meng Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-Id: <20221229091828.1945072-12-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- include/hw/riscv/boot.h | 2 ++ hw/riscv/boot.c | 39 +++++++++++++++++++++++++-------------- 2 files changed, 27 insertions(+), 14 deletions(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 60cf320c88..b273ab22f7 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -38,6 +38,8 @@ target_ulong riscv_find_and_load_firmware(MachineState *m= achine, hwaddr firmware_load_addr, symbol_fn_t sym_cb); const char *riscv_default_firmware_name(RISCVHartArrayState *harts); +char *riscv_find_firmware(const char *firmware_filename, + const char *default_machine_firmware); target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index e1a544b1d9..98b80af51b 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -84,11 +84,11 @@ const char *riscv_default_firmware_name(RISCVHartArrayS= tate *harts) return RISCV64_BIOS_BIN; } =20 -static char *riscv_find_firmware(const char *firmware_filename) +static char *riscv_find_bios(const char *bios_filename) { char *filename; =20 - filename =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); + filename =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_filename); if (filename =3D=3D NULL) { if (!qtest_enabled()) { /* @@ -97,8 +97,8 @@ static char *riscv_find_firmware(const char *firmware_fil= ename) * running QEMU test will complain hence let's suppress the er= ror * report for QEMU testing. */ - error_report("Unable to load the RISC-V firmware \"%s\"", - firmware_filename); + error_report("Unable to find the RISC-V BIOS \"%s\"", + bios_filename); exit(1); } } @@ -106,25 +106,36 @@ static char *riscv_find_firmware(const char *firmware= _filename) return filename; } =20 -target_ulong riscv_find_and_load_firmware(MachineState *machine, - const char *default_machine_firm= ware, - hwaddr firmware_load_addr, - symbol_fn_t sym_cb) +char *riscv_find_firmware(const char *firmware_filename, + const char *default_machine_firmware) { - char *firmware_filename =3D NULL; - target_ulong firmware_end_addr =3D firmware_load_addr; + char *filename =3D NULL; =20 - if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) { + if ((!firmware_filename) || (!strcmp(firmware_filename, "default"))) { /* * The user didn't specify -bios, or has specified "-bios default". * That means we are going to load the OpenSBI binary included in * the QEMU source. */ - firmware_filename =3D riscv_find_firmware(default_machine_firmware= ); - } else if (strcmp(machine->firmware, "none")) { - firmware_filename =3D riscv_find_firmware(machine->firmware); + filename =3D riscv_find_bios(default_machine_firmware); + } else if (strcmp(firmware_filename, "none")) { + filename =3D riscv_find_bios(firmware_filename); } =20 + return filename; +} + +target_ulong riscv_find_and_load_firmware(MachineState *machine, + const char *default_machine_firm= ware, + hwaddr firmware_load_addr, + symbol_fn_t sym_cb) +{ + char *firmware_filename; + target_ulong firmware_end_addr =3D firmware_load_addr; + + firmware_filename =3D riscv_find_firmware(machine->firmware, + default_machine_firmware); + if (firmware_filename) { /* If not "none" load the firmware */ firmware_end_addr =3D riscv_load_firmware(firmware_filename, --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200878216105.19401113437505; Thu, 19 Jan 2023 23:47:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIm0I-0007wC-Vf; Fri, 20 Jan 2023 02:40:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIm0G-0007vF-Ga for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1674200385; x=1676792386; bh=Bn30vjVPAWSQy0gjD1 ACYzE8Lg6WPT3P+Hv3PjnBeHU=; b=f/HKifnzHskHE2GpJqtnANranbXsPFGiRA tLdpUpr0CNRb770LBSRrgvsiSfsMdvfRNPPXhRBdI+/INSlkdu6rZEPquzUzE0ua nMhX1mCnJzrPy5vCZV+5XQCJBaeLtBvmd8LS4fWzKL/0kOdt0oD0uwMBceV4gUNU FUtwdxwkNdvFztpkHfX4EOF3tPp3bNyQBckCgunprLS89v8tOp+hM15aA2z3Axyh o3FZYTfxE52sSMpjCx6lNS/vpS3Q6WAgToxkWk1hBl59hLZQylNLdRwArTPpneVq WRdy/ZoYZcRyp3PzA7Wc5V6TXirabMs9dfOOA4YjSi2R02rQCZ1g== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 12/37] hw/riscv: spike: Decouple create_fdt() dependency to ELF loading Date: Fri, 20 Jan 2023 17:38:48 +1000 Message-Id: <20230120073913.1028407-13-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200879814100006 Content-Type: text/plain; charset="utf-8" From: Bin Meng At present create_fdt() calls htif_uses_elf_symbols() to determine whether to insert a property for the HTIF. This unfortunately creates a hidden dependency to riscv_load_{firmware,kernel} that create_fdt() must be called after the ELF {firmware,kernel} image has been loaded. Decouple such dependency be adding a new parameter to create_fdt(), whether custom HTIF base address is used. The flag will be set if non ELF {firmware,kernel} image is given by user. Signed-off-by: Bin Meng Reviewed-by: Daniel Henrique Barboza Message-Id: <20221229091828.1945072-13-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- include/hw/char/riscv_htif.h | 5 +-- hw/char/riscv_htif.c | 17 +++++----- hw/riscv/spike.c | 61 ++++++++++++++++++++++++++++++------ 3 files changed, 59 insertions(+), 24 deletions(-) diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h index 9e8ebbe017..5958c5b986 100644 --- a/include/hw/char/riscv_htif.h +++ b/include/hw/char/riscv_htif.h @@ -44,11 +44,8 @@ typedef struct HTIFState { void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_va= lue, uint64_t st_size); =20 -/* Check if HTIF uses ELF symbols */ -bool htif_uses_elf_symbols(void); - /* legacy pre qom */ HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr, - uint64_t nonelf_base); + uint64_t nonelf_base, bool custom_base); =20 #endif diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 1477fc0090..098de50e35 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -52,20 +52,17 @@ #define PK_SYS_WRITE 64 =20 static uint64_t fromhost_addr, tohost_addr; -static int address_symbol_set; =20 void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_va= lue, uint64_t st_size) { if (strcmp("fromhost", st_name) =3D=3D 0) { - address_symbol_set |=3D 1; fromhost_addr =3D st_value; if (st_size !=3D 8) { error_report("HTIF fromhost must be 8 bytes"); exit(1); } } else if (strcmp("tohost", st_name) =3D=3D 0) { - address_symbol_set |=3D 2; tohost_addr =3D st_value; if (st_size !=3D 8) { error_report("HTIF tohost must be 8 bytes"); @@ -275,19 +272,19 @@ static const MemoryRegionOps htif_mm_ops =3D { .write =3D htif_mm_write, }; =20 -bool htif_uses_elf_symbols(void) -{ - return (address_symbol_set =3D=3D 3) ? true : false; -} - HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr, - uint64_t nonelf_base) + uint64_t nonelf_base, bool custom_base) { uint64_t base, size, tohost_offset, fromhost_offset; =20 - if (!htif_uses_elf_symbols()) { + if (custom_base) { fromhost_addr =3D nonelf_base; tohost_addr =3D nonelf_base + 8; + } else { + if (!fromhost_addr || !tohost_addr) { + error_report("Invalid HTIF fromhost or tohost address"); + exit(1); + } } =20 base =3D MIN(tohost_addr, fromhost_addr); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 3c8a8de673..1679c325d5 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -49,7 +49,8 @@ static const MemMapEntry spike_memmap[] =3D { }; =20 static void create_fdt(SpikeState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_= bit) + uint64_t mem_size, const char *cmdline, + bool is_32_bit, bool htif_custom_base) { void *fdt; uint64_t addr, size; @@ -77,7 +78,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *= memmap, =20 qemu_fdt_add_subnode(fdt, "/htif"); qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); - if (!htif_uses_elf_symbols()) { + if (htif_custom_base) { qemu_fdt_setprop_cells(fdt, "/htif", "reg", 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size); } @@ -183,18 +184,33 @@ static void create_fdt(SpikeState *s, const MemMapEnt= ry *memmap, } } =20 +static bool spike_test_elf_image(char *filename) +{ + Error *err =3D NULL; + + load_elf_hdr(filename, NULL, NULL, &err); + if (err) { + error_free(err); + return false; + } else { + return true; + } +} + static void spike_board_init(MachineState *machine) { const MemMapEntry *memmap =3D spike_memmap; SpikeState *s =3D SPIKE_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); - target_ulong firmware_end_addr, kernel_start_addr; - const char *firmware_name; + target_ulong firmware_end_addr =3D memmap[SPIKE_DRAM].base; + target_ulong kernel_start_addr; + char *firmware_name; uint32_t fdt_load_addr; uint64_t kernel_entry; char *soc_name; int i, base_hartid, hart_count; + bool htif_custom_base =3D false; =20 /* Check socket count limit */ if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) { @@ -256,10 +272,34 @@ static void spike_board_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, mask_rom); =20 - firmware_name =3D riscv_default_firmware_name(&s->soc[0]); - firmware_end_addr =3D riscv_find_and_load_firmware(machine, firmware_n= ame, - memmap[SPIKE_DRAM].ba= se, - htif_symbol_callback); + /* Find firmware */ + firmware_name =3D riscv_find_firmware(machine->firmware, + riscv_default_firmware_name(&s->soc[0])); + + /* + * Test the given firmware or kernel file to see if it is an ELF image. + * If it is an ELF, we assume it contains the symbols required for + * the HTIF console, otherwise we fall back to use the custom base + * passed from device tree for the HTIF console. + */ + if (!firmware_name && !machine->kernel_filename) { + htif_custom_base =3D true; + } else { + if (firmware_name) { + htif_custom_base =3D !spike_test_elf_image(firmware_name); + } + if (!htif_custom_base && machine->kernel_filename) { + htif_custom_base =3D !spike_test_elf_image(machine->kernel_fil= ename); + } + } + + /* Load firmware */ + if (firmware_name) { + firmware_end_addr =3D riscv_load_firmware(firmware_name, + memmap[SPIKE_DRAM].base, + htif_symbol_callback); + g_free(firmware_name); + } =20 /* Load kernel */ if (machine->kernel_filename) { @@ -279,7 +319,7 @@ static void spike_board_init(MachineState *machine) =20 /* Create device tree */ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc[0])); + riscv_is_32bit(&s->soc[0]), htif_custom_base); =20 /* Load initrd */ if (machine->kernel_filename && machine->initrd_filename) { @@ -307,7 +347,8 @@ static void spike_board_init(MachineState *machine) fdt_load_addr); =20 /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base); + htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base, + htif_custom_base); } =20 static void spike_machine_instance_init(Object *obj) --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1674200387; x=1676792388; bh=YFEhYOIOyI5zToAKjl CL4h8TbBuXrF043NOmLfxNuWk=; b=rJ05VvVBzMkraoiL0guSLVvbJn5Myz1Odo OGajQqzQKJSaVp+Hd9RHQNDSrVvMba7iXtcqnJ5w+Enw2b2t08A0/Un+Kb+r9Ya0 KCaZ4AGYGqCvBNAO0n8zy5uNK/eFPy+ALslg/K0fHYjotjZ+lznF0oXdKBiCS35d eAGDw1XNPBrCQ8au0y0YYTckCM54t7EixuAtRpRjyY3vlKu4g0+YsW9nPbNT7Ec5 GOuJQaTGOZZws1VtDyTRE7HF0NimkMXfzVDLWOPQL8XNP+IfZAV4BMAPN8Pikh7r Rp81YR+ohXIZ+o795QHxgZuJugFkbeSSuukXRtREkYCFVtwUNMFw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Dongxue Zhang , LIU Zhiwei , Frank Chang , Alistair Francis Subject: [PULL 13/37] target/riscv/cpu.c: Fix elen check Date: Fri, 20 Jan 2023 17:38:49 +1000 Message-Id: <20230120073913.1028407-14-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200511717100006 Content-Type: text/plain; charset="utf-8" From: Dongxue Zhang The elen check should be cpu->cfg.elen in range [8, 64]. Signed-off-by: Dongxue Zhang Reviewed-by: LIU Zhiwei Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <167236721596.15277.2653405273227256289-0@git.sr.ht> [ Changes by AF: - Tidy up commit message ] Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cc75ca7667..a2e6238bd7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -882,7 +882,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) "Vector extension ELEN must be power of 2"); return; } - if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { + if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { error_setg(errp, "Vector extension implementation only supports ELE= N " "in the range [8, 64]"); --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1674200390; x=1676792391; bh=rawTC32 xlC8ut2sfg3SnNJDmDpHewXm7PUHLZFwL2D4=; b=rA5kSpC385/+7wtb1H72mlL QZuPIHf62Kila5ebywgPsUG/cvD+bdMiu2ZlaS8dr+xMmzDUHeFCzAKu9fR3lwdV Q/VN+IPpDEzIqYBh09OjVZ2ibcwiT+zRhJRlPjlJ1hnYKvi0y/0SqUqSC2cTMoEu AbwIl3Xi8AJxvZ9KjWweP/zVk8cwCdJatj++EMZH8S0xAuPbf/cG3txhEeAyPkse Rj86/ErcKUYpEF0M2px7zxX4MUCSYxTq2ujB2YtjU/WNcHo3zt8ghBHzYfdfJRW4 +auGJKb6tKPdZp7T3rRvEQzcQz+ldhdlUW2bjEItkypXuDF4UVrtdd+WNCTgQXw= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Cleber Rosa , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Alistair Francis Subject: [PULL 14/37] tests/avocado: add RISC-V OpenSBI boot test Date: Fri, 20 Jan 2023 17:38:50 +1000 Message-Id: <20230120073913.1028407-15-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200469406100005 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza This test is used to do a quick sanity check to ensure that we're able to run the existing QEMU FW image. 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | RISCV32_BIOS_BIN firmware with minimal options. The riscv32 'spike' machine isn't bootable at this moment, requiring an OpenSBI fix [1] and QEMU side changes [2]. We could just leave at that or add a 'skip' test to remind us about it. To work as a reminder that we have a riscv32 'spike' test that should be enabled as soon as OpenSBI QEMU rom receives the fix, we're adding a 'skip' test: (06/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv32_spike: SKIP: requires OpenSBI fix to work [1] https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.18605= 69-1-bmeng@tinylab.org/ [2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=3D334159 Cc: Cleber Rosa Cc: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-Id: <20230102115241.25733-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 tests/avocado/riscv_opensbi.py diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py new file mode 100644 index 0000000000..e02f0d404a --- /dev/null +++ b/tests/avocado/riscv_opensbi.py @@ -0,0 +1,65 @@ +# OpenSBI boot test for RISC-V machines +# +# Copyright (c) 2022, Ventana Micro +# +# This work is licensed under the terms of the GNU GPL, version 2 or +# later. See the COPYING file in the top-level directory. + +from avocado_qemu import QemuSystemTest +from avocado import skip +from avocado_qemu import wait_for_console_pattern + +class RiscvOpenSBI(QemuSystemTest): + """ + :avocado: tags=3Daccel:tcg + """ + timeout =3D 5 + + def boot_opensbi(self): + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + @skip("requires OpenSBI fix to work") + def test_riscv32_spike(self): + """ + :avocado: tags=3Darch:riscv32 + :avocado: tags=3Dmachine:spike + """ + self.boot_opensbi() + + def test_riscv64_spike(self): + """ + :avocado: tags=3Darch:riscv64 + :avocado: tags=3Dmachine:spike + """ + self.boot_opensbi() + + def test_riscv32_sifive_u(self): + """ + :avocado: tags=3Darch:riscv32 + :avocado: tags=3Dmachine:sifive_u + """ + self.boot_opensbi() + + def test_riscv64_sifive_u(self): + """ + :avocado: tags=3Darch:riscv64 + :avocado: tags=3Dmachine:sifive_u + """ + self.boot_opensbi() + + def test_riscv32_virt(self): + """ + :avocado: tags=3Darch:riscv32 + :avocado: tags=3Dmachine:virt + """ + self.boot_opensbi() + + def test_riscv64_virt(self): + """ + :avocado: tags=3Darch:riscv64 + :avocado: tags=3Dmachine:virt + """ + self.boot_opensbi() --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200499643100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza The MachineState object provides a 'fdt' pointer that is already being used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP command. Remove the 'fdt' pointer from SpikeState and use MachineState::fdt instead. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-Id: <20230102115241.25733-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- include/hw/riscv/spike.h | 2 -- hw/riscv/spike.c | 12 +++++------- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index 73bf2a9aad..0c2a223763 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -37,8 +37,6 @@ struct SpikeState { =20 /*< public >*/ RISCVHartArrayState soc[SPIKE_SOCKETS_MAX]; - void *fdt; - int fdt_size; }; =20 enum { diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 1679c325d5..25c5420ee6 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -53,6 +53,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *= memmap, bool is_32_bit, bool htif_custom_base) { void *fdt; + int fdt_size; uint64_t addr, size; unsigned long clint_addr; int cpu, socket; @@ -65,7 +66,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *= memmap, "sifive,clint0", "riscv,clint0" }; =20 - fdt =3D s->fdt =3D create_device_tree(&s->fdt_size); + fdt =3D mc->fdt =3D create_device_tree(&fdt_size); if (!fdt) { error_report("create_device_tree() failed"); exit(1); @@ -327,18 +328,15 @@ static void spike_board_init(MachineState *machine) hwaddr end =3D riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, &start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", end); } =20 /* Compute the fdt load address in dram */ fdt_load_addr =3D riscv_load_fdt(memmap[SPIKE_DRAM].base, - machine->ram_size, s->fdt); - - /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ - machine->fdt =3D s->fdt; + machine->ram_size, machine->fdt); =20 /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1674200394; x=1676792395; bh=xVaa9JY NmmkdEbD+oVQeErPcR9zJk0gv+SPzAgaeL0k=; b=qH1uyp7hA04FPV+woZxs4/N Rk5ZN9wLJIp6jQx6KerfVVAQy/dgacXKjjbvT/PrNOMzdAqqdFbESWjXVZs0utTI ZNvsBgFEi0u2EhLQYuS/vPlBa+A+7MmCFZD4kK0CTQlRgJlGP8yWJA66ic2M6dSp DNj9yFuWpFL1OsCpA5bt2XnTj92xLJC067SJjXrFQ+Eh1yzLa3X/8I/UQuP97A3p 3DKlwo2aw+Z3Lv+wUbbst9f8Nw/h82Ma3HhUXfeidXObgGCYQmKFYtvBr0YIoEi5 mkhkQ6sDa2OXo1DBuHr2YNzorNoxp9KalCf7bZb5RX+wcwgmO8ccG/44qeGo0sQ= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Bin Meng Subject: [PULL 16/37] hw/riscv/sifive_u: use 'fdt' from MachineState Date: Fri, 20 Jan 2023 17:38:52 +1000 Message-Id: <20230120073913.1028407-17-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200511696100002 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza The MachineState object provides a 'fdt' pointer that is already being used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP command. Remove the 'fdt' pointer from SiFiveUState and use MachineState::fdt instead. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-Id: <20230102115241.25733-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- include/hw/riscv/sifive_u.h | 3 --- hw/riscv/sifive_u.c | 15 ++++++--------- 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index a67328f7ad..65af306963 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -69,9 +69,6 @@ typedef struct SiFiveUState { /*< public >*/ SiFiveUSoCState soc; =20 - void *fdt; - int fdt_size; - bool start_in_flash; uint32_t msel; uint32_t serial; diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index a58ddb36ac..ddceb750ea 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -98,7 +98,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry= *memmap, { MachineState *ms =3D MACHINE(qdev_get_machine()); void *fdt; - int cpu; + int cpu, fdt_size; uint32_t *cells; char *nodename; uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle =3D 1; @@ -112,14 +112,14 @@ static void create_fdt(SiFiveUState *s, const MemMapE= ntry *memmap, }; =20 if (ms->dtb) { - fdt =3D s->fdt =3D load_device_tree(ms->dtb, &s->fdt_size); + fdt =3D ms->fdt =3D load_device_tree(ms->dtb, &fdt_size); if (!fdt) { error_report("load_device_tree() failed"); exit(1); } goto update_bootargs; } else { - fdt =3D s->fdt =3D create_device_tree(&s->fdt_size); + fdt =3D ms->fdt =3D create_device_tree(&fdt_size); if (!fdt) { error_report("create_device_tree() failed"); exit(1); @@ -612,9 +612,9 @@ static void sifive_u_machine_init(MachineState *machine) hwaddr end =3D riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, &start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-e= nd", end); } } else { @@ -627,14 +627,11 @@ static void sifive_u_machine_init(MachineState *machi= ne) =20 /* Compute the fdt load address in dram */ fdt_load_addr =3D riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, - machine->ram_size, s->fdt); + machine->ram_size, machine->fdt); if (!riscv_is_32bit(&s->soc.u_cpus)) { start_addr_hi32 =3D (uint64_t)start_addr >> 32; } =20 - /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ - machine->fdt =3D s->fdt; - /* reset vector */ uint32_t reset_vec[12] =3D { s->msel, /* MSEL pin state */ --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200788952118.15511675140374; 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s=dkim; t=1674200396; x=1676792397; bh=ck3adrg I9AADtz7/lYYVfG9ETFGWlDw3wpKpvxh73zo=; b=WlrAry3GKJhYtM+xqPahv0o KS2hLWLLZzLbJdY8uWJdapAoxEZV3nTlDgppLYR16CRbXK30QI5YNWbY6un4ir57 g3bIL5z+B3kbHXoQZZoy1yTEkeEIc5HvMcmKQcemnBH/JjvoszxWavmJ56sp3Y0J xITo/G9/uIDIZ7x+6S/O+s5JUqaOukSoJkzwfWaoPBqtP7e+8n+2de4codsvKxSh LaT8+fmVHjxgHsMASOo0cFzCl+aEyjttJhv0ury1x3kyD1kajYQyfwOrX6K0MwYa 6YIx93UQ6uro+gtk/U5ETiwUSFxXVFclQYZ8ZTjCvIdJ5UylZdePS+mWHYPNP7g= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Alistair Francis Subject: [PULL 17/37] hw/riscv/boot.c: exit early if filename is NULL in load functions Date: Fri, 20 Jan 2023 17:38:53 +1000 Message-Id: <20230120073913.1028407-18-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200789349100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza riscv_load_firmware(), riscv_load_initrd() and riscv_load_kernel() works under the assumption that a 'filename' parameter is always not NULL. This is currently the case since all callers of these functions are checking for NULL before calling them. Add an g_assert() to make sure that a NULL value in these cases are to be considered a bug. Suggested-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20230102115241.25733-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/boot.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 98b80af51b..31aa3385a0 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -153,6 +153,8 @@ target_ulong riscv_load_firmware(const char *firmware_f= ilename, uint64_t firmware_entry, firmware_end; ssize_t firmware_size; =20 + g_assert(firmware_filename !=3D NULL); + if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, &firmware_entry, NULL, &firmware_end, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { @@ -177,6 +179,8 @@ target_ulong riscv_load_kernel(const char *kernel_filen= ame, { uint64_t kernel_load_base, kernel_entry; =20 + g_assert(kernel_filename !=3D NULL); + /* * NB: Use low address not ELF entry point to ensure that the fw_dynam= ic * behaviour when loading an ELF matches the fw_payload, fw_jump and B= BL @@ -209,6 +213,8 @@ hwaddr riscv_load_initrd(const char *filename, uint64_t= mem_size, { ssize_t size; =20 + g_assert(filename !=3D NULL); + /* * We want to put the initrd far enough into RAM that when the * kernel is uncompressed it will not clobber the initrd. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200503685100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza This will make the code more in line with what the other boards are doing. We'll also avoid an extra check to machine->kernel_filename since we already checked that before executing riscv_load_kernel(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-Id: <20230102115241.25733-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/spike.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 25c5420ee6..004dfb2d5b 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -302,6 +302,10 @@ static void spike_board_init(MachineState *machine) g_free(firmware_name); } =20 + /* Create device tree */ + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, + riscv_is_32bit(&s->soc[0]), htif_custom_base); + /* Load kernel */ if (machine->kernel_filename) { kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], @@ -310,6 +314,17 @@ static void spike_board_init(MachineState *machine) kernel_entry =3D riscv_load_kernel(machine->kernel_filename, kernel_start_addr, htif_symbol_callback); + + if (machine->initrd_filename) { + hwaddr start; + hwaddr end =3D riscv_load_initrd(machine->initrd_filename, + machine->ram_size, kernel_entry, + &start); + qemu_fdt_setprop_cell(machine->fdt, "/chosen", + "linux,initrd-start", start); + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-e= nd", + end); + } } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode @@ -318,22 +333,6 @@ static void spike_board_init(MachineState *machine) kernel_entry =3D 0; } =20 - /* Create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc[0]), htif_custom_base); - - /* Load initrd */ - if (machine->kernel_filename && machine->initrd_filename) { - hwaddr start; - hwaddr end =3D riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", - end); - } - /* Compute the fdt load address in dram */ fdt_load_addr =3D riscv_load_fdt(memmap[SPIKE_DRAM].base, machine->ram_size, machine->fdt); --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200815975756.6205935976517; Thu, 19 Jan 2023 23:46:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIm0h-0000Mj-QX; Fri, 20 Jan 2023 02:40:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIm0f-0000HL-KQ for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1674200400; x=1676792401; bh=tn29utQ FVeAYdugmhcxslFftDxtVJbhVei3WGKUZ43Q=; b=GSzEYkJ54u8XS1NQcocA53G QG8GhL1MycyT9cPy/n1ZiARE49YSZ7ElDl4cy49+0RBnQ1yHfPr+UiCj5MPIG5Hp ut//z1O97uqehk8fBF9/k4NoMPPRRTrr7TQSOjAoXqeRek0VCHemmLaEVd8SqQ71 cU3zhsjRLJOz8FxY94tBIS0yubtzTZsj2brBZ3F/CwztSIy8YwuONm2ap0LS6nAc ns8jo19QZwbjDh+fBKa3Hkz2/pCE5yeb6tHBNJYZZG7n7I2cWeHXPVDyR9s0SK7b djHr0GuV3QZhLfLxE7qKRKF1SxWmGyUGIcswiWkOaH3h0wX90F/Miswr2KJgrmA= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Palmer Dabbelt , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 19/37] hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() Date: Fri, 20 Jan 2023 17:38:55 +1000 Message-Id: <20230120073913.1028407-20-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200817453100011 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza riscv_load_initrd() returns the initrd end addr while also writing a 'start' var to mark the addr start. These informations are being used just to write the initrd FDT node. Every existing caller of riscv_load_initrd() is writing the FDT in the same manner. We can simplify things by writing the FDT inside riscv_load_initrd(), sparing callers from having to manage start/end addrs to write the FDT themselves. An 'if (fdt)' check is already inserted at the end of the function because we'll end up using it later on with other boards that doesn=C2=B4t have a FDT. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-Id: <20230102115241.25733-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- include/hw/riscv/boot.h | 4 ++-- hw/riscv/boot.c | 18 ++++++++++++------ hw/riscv/microchip_pfsoc.c | 10 ++-------- hw/riscv/sifive_u.c | 10 ++-------- hw/riscv/spike.c | 10 ++-------- hw/riscv/virt.c | 10 ++-------- 6 files changed, 22 insertions(+), 40 deletions(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index b273ab22f7..e37e1d1238 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -46,8 +46,8 @@ target_ulong riscv_load_firmware(const char *firmware_fil= ename, target_ulong riscv_load_kernel(const char *kernel_filename, target_ulong firmware_end_addr, symbol_fn_t sym_cb); -hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, - uint64_t kernel_entry, hwaddr *start); +void riscv_load_initrd(const char *filename, uint64_t mem_size, + uint64_t kernel_entry, void *fdt); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState = *harts, hwaddr saddr, diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 31aa3385a0..6b948d1c9e 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -208,9 +208,10 @@ target_ulong riscv_load_kernel(const char *kernel_file= name, exit(1); } =20 -hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, - uint64_t kernel_entry, hwaddr *start) +void riscv_load_initrd(const char *filename, uint64_t mem_size, + uint64_t kernel_entry, void *fdt) { + hwaddr start, end; ssize_t size; =20 g_assert(filename !=3D NULL); @@ -226,18 +227,23 @@ hwaddr riscv_load_initrd(const char *filename, uint64= _t mem_size, * halfway into RAM, and for boards with 256MB of RAM or more we put * the initrd at 128MB. */ - *start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); + start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); =20 - size =3D load_ramdisk(filename, *start, mem_size - *start); + size =3D load_ramdisk(filename, start, mem_size - start); if (size =3D=3D -1) { - size =3D load_image_targphys(filename, *start, mem_size - *start); + size =3D load_image_targphys(filename, start, mem_size - start); if (size =3D=3D -1) { error_report("could not load ramdisk '%s'", filename); exit(1); } } =20 - return *start + size; + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ + if (fdt) { + end =3D start + size; + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + } } =20 uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index b10321b564..593a799549 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -633,14 +633,8 @@ static void microchip_icicle_kit_machine_init(MachineS= tate *machine) kernel_start_addr, NULL); =20 if (machine->initrd_filename) { - hwaddr start; - hwaddr end =3D riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-end", end); + riscv_load_initrd(machine->initrd_filename, machine->ram_size, + kernel_entry, machine->fdt); } =20 if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index ddceb750ea..37f5087172 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -608,14 +608,8 @@ static void sifive_u_machine_init(MachineState *machin= e) kernel_start_addr, NULL); =20 if (machine->initrd_filename) { - hwaddr start; - hwaddr end =3D riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-e= nd", - end); + riscv_load_initrd(machine->initrd_filename, machine->ram_size, + kernel_entry, machine->fdt); } } else { /* diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 004dfb2d5b..5668fe0694 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -316,14 +316,8 @@ static void spike_board_init(MachineState *machine) htif_symbol_callback); =20 if (machine->initrd_filename) { - hwaddr start; - hwaddr end =3D riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-e= nd", - end); + riscv_load_initrd(machine->initrd_filename, machine->ram_size, + kernel_entry, machine->fdt); } } else { /* diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 408f7a2256..5967b136b4 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1291,14 +1291,8 @@ static void virt_machine_done(Notifier *notifier, vo= id *data) kernel_start_addr, NULL); =20 if (machine->initrd_filename) { - hwaddr start; - hwaddr end =3D riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-e= nd", - end); + riscv_load_initrd(machine->initrd_filename, machine->ram_size, + kernel_entry, machine->fdt); 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1674200403; x=1676792404; bh=dlqfE8U TZByMyYH8+2PqfMLUoQlV5O1p2CVl0RQXwHI=; b=GDdTbNYHvd4ojKpSAnEI3jO dENA3TK/XB9Mfl4KxAwFovGyBjcQwYd7I5U6zEtPAGBQweeGoLAXQltvPslnx4ff WhzT7c9otK0Y3xD42KzUQmAwzkrrsty1EUbeApeTLPvT8SWHz7sBrssKagtzI3j+ iJP7540zlpeRdeE9wW8VKQV9unbJlCVVeatq3f6lLSIdBAWGZ+mAizTeiUJ0dtvp UH7KGG62BdZ7qdswxq5olfIpSrf11Eyur7MfXR7CQmExUADqsfnPlbJwMekvrZAk klsEvprgOf0GtsYiyWGjY6SH20vPKGI2Z1Nli7EruS0yJDFB05OjGY9TrIf224g= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Palmer Dabbelt , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 20/37] hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() Date: Fri, 20 Jan 2023 17:38:56 +1000 Message-Id: <20230120073913.1028407-21-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200779275100006 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza The sifive_u, spike and virt machines are writing the 'bootargs' FDT node during their respective create_fdt(). Given that bootargs is written only when '-append' is used, and this option is only allowed with the '-kernel' option, which in turn is already being check before executing riscv_load_kernel(), write 'bootargs' in the same code path as riscv_load_kernel(). Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-Id: <20230102115241.25733-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 11 +++++------ hw/riscv/spike.c | 9 +++++---- hw/riscv/virt.c | 11 +++++------ 3 files changed, 15 insertions(+), 16 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 37f5087172..3e6df87b5b 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -117,7 +117,6 @@ static void create_fdt(SiFiveUState *s, const MemMapEnt= ry *memmap, error_report("load_device_tree() failed"); exit(1); } - goto update_bootargs; } else { fdt =3D ms->fdt =3D create_device_tree(&fdt_size); if (!fdt) { @@ -510,11 +509,6 @@ static void create_fdt(SiFiveUState *s, const MemMapEn= try *memmap, qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); =20 g_free(nodename); - -update_bootargs: - if (cmdline && *cmdline) { - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); - } } =20 static void sifive_u_machine_reset(void *opaque, int n, int level) @@ -611,6 +605,11 @@ static void sifive_u_machine_init(MachineState *machin= e) riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, machine->fdt); } + + if (machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 5668fe0694..60e2912be5 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -179,10 +179,6 @@ static void create_fdt(SpikeState *s, const MemMapEntr= y *memmap, =20 qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); - - if (cmdline && *cmdline) { - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); - } } =20 static bool spike_test_elf_image(char *filename) @@ -319,6 +315,11 @@ static void spike_board_init(MachineState *machine) riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, machine->fdt); } + + if (machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 5967b136b4..6c946b6def 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1012,7 +1012,6 @@ static void create_fdt(RISCVVirtState *s, const MemMa= pEntry *memmap, error_report("load_device_tree() failed"); exit(1); } - goto update_bootargs; } else { mc->fdt =3D create_device_tree(&s->fdt_size); if (!mc->fdt) { @@ -1050,11 +1049,6 @@ static void create_fdt(RISCVVirtState *s, const MemM= apEntry *memmap, create_fdt_fw_cfg(s, memmap); create_fdt_pmu(s); =20 -update_bootargs: - if (cmdline && *cmdline) { - qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline); - } - /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_= seed)); @@ -1294,6 +1288,11 @@ static void virt_machine_done(Notifier *notifier, vo= id *data) riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, machine->fdt); } + + if (machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200814283911.2402545057403; Thu, 19 Jan 2023 23:46:54 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIm0t-0000eK-4G; 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s=dkim; t=1674200405; x=1676792406; bh=KKw2hOa mbB31lcakp0JSBvCoz5OfdQijlPxzoRckMTk=; b=ZX+XULCP8I9xP0q+Eps4oNX zw99nuFYTTQu88oxg66jyIpDwBAuegmtbIDcUEwWcq/W2RwSJ6oug6o0Tns5fe4p FQsb2n5ANa4fcauY3Ix1UKs+j7T4HavLhbnqJAqo+B2+u1X61y9FdyUXyjLRo5R7 4PTkAu+AMEnCN/Zumh8JJJN9dszGDOOJudB6R8Ix4Ule8DNL4CWUfhAqK+cN1Gdi CbfwsL8WS6eoNzgNHi97MI4belaw9EWe+NNdVM5YkOAQPEv397S0WklWl/xIzr9u MQ6IPa91LPpUpDu40Fof0VdeBiNSqNnwcZVUVzF74zP0YY2G9L4Ur3iv6ZA0XcA= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Alistair Francis Subject: [PULL 21/37] hw/riscv/boot.c: use MachineState in riscv_load_initrd() Date: Fri, 20 Jan 2023 17:38:57 +1000 Message-Id: <20230120073913.1028407-22-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200815438100007 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza 'filename', 'mem_size' and 'fdt' from riscv_load_initrd() can all be retrieved by the MachineState object for all callers. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20230102115241.25733-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- include/hw/riscv/boot.h | 3 +-- hw/riscv/boot.c | 6 ++++-- hw/riscv/microchip_pfsoc.c | 3 +-- hw/riscv/sifive_u.c | 3 +-- hw/riscv/spike.c | 3 +-- hw/riscv/virt.c | 3 +-- 6 files changed, 9 insertions(+), 12 deletions(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index e37e1d1238..cfd72ecabf 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -46,8 +46,7 @@ target_ulong riscv_load_firmware(const char *firmware_fil= ename, target_ulong riscv_load_kernel(const char *kernel_filename, target_ulong firmware_end_addr, symbol_fn_t sym_cb); -void riscv_load_initrd(const char *filename, uint64_t mem_size, - uint64_t kernel_entry, void *fdt); +void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState = *harts, hwaddr saddr, diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 6b948d1c9e..d3e780c3b6 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -208,9 +208,11 @@ target_ulong riscv_load_kernel(const char *kernel_file= name, exit(1); } =20 -void riscv_load_initrd(const char *filename, uint64_t mem_size, - uint64_t kernel_entry, void *fdt) +void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) { + const char *filename =3D machine->initrd_filename; + uint64_t mem_size =3D machine->ram_size; + void *fdt =3D machine->fdt; hwaddr start, end; ssize_t size; =20 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 593a799549..1e9b0a420e 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -633,8 +633,7 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) kernel_start_addr, NULL); =20 if (machine->initrd_filename) { - riscv_load_initrd(machine->initrd_filename, machine->ram_size, - kernel_entry, machine->fdt); + riscv_load_initrd(machine, kernel_entry); } =20 if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 3e6df87b5b..c40885ed5c 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -602,8 +602,7 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr, NULL); =20 if (machine->initrd_filename) { - riscv_load_initrd(machine->initrd_filename, machine->ram_size, - kernel_entry, machine->fdt); + riscv_load_initrd(machine, kernel_entry); } =20 if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 60e2912be5..99dec74fe8 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -312,8 +312,7 @@ static void spike_board_init(MachineState *machine) htif_symbol_callback); =20 if (machine->initrd_filename) { - riscv_load_initrd(machine->initrd_filename, machine->ram_size, - kernel_entry, machine->fdt); + riscv_load_initrd(machine, kernel_entry); } =20 if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 6c946b6def..02f1369843 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1285,8 +1285,7 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) kernel_start_addr, NULL); =20 if (machine->initrd_filename) { - riscv_load_initrd(machine->initrd_filename, machine->ram_size, - kernel_entry, machine->fdt); + riscv_load_initrd(machine, kernel_entry); } =20 if (machine->kernel_cmdline && *machine->kernel_cmdline) { --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200811694666.8476183477989; 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s=dkim; t=1674200408; x=1676792409; bh=Vdf5BHz 2p/olUyMSeiSnuNYCzgkQaqMpc0wgM242sb0=; b=iCkxXR9e88xhF7GoN/3BSmb irWrAX7D6XeT31JC6+jfsPFHNfNUL8j7hi0rQr/Lfh9/6QybiMFWEZMqIlkAc9vx qMHGVcVAV7KVatfpGjCyxH/NROiX6RbyjCuVV7R2HqeuvGmiQnt4zXQLRkBIhZ6M FNpqT149MjphuPEuKQYkkStmLWFPtle05kY2x//SYbPa7844im9Fiy7V+lkyBCgF IzGoO8psiyzYGXT7Mw6XVfTO7vTuQQSgGcz+zokDyzBRvGh8VjoTCijeY/sFyafl q4J77/3J7/k3PCWnxHwO2uq8S003wFN3A0t6DMzoKvOA+EUiK2gKqPcVZleEzhg= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Alistair Francis Subject: [PULL 22/37] hw/riscv/boot.c: use MachineState in riscv_load_kernel() Date: Fri, 20 Jan 2023 17:38:58 +1000 Message-Id: <20230120073913.1028407-23-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200813450100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza All callers are using kernel_filename as machine->kernel_filename. This will also simplify the changes in riscv_load_kernel() that we're going to do next. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20230102115241.25733-10-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- include/hw/riscv/boot.h | 2 +- hw/riscv/boot.c | 3 ++- hw/riscv/microchip_pfsoc.c | 3 +-- hw/riscv/opentitan.c | 3 +-- hw/riscv/sifive_e.c | 3 +-- hw/riscv/sifive_u.c | 3 +-- hw/riscv/spike.c | 3 +-- hw/riscv/virt.c | 3 +-- 8 files changed, 9 insertions(+), 14 deletions(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index cfd72ecabf..f94653a09b 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -43,7 +43,7 @@ char *riscv_find_firmware(const char *firmware_filename, target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); -target_ulong riscv_load_kernel(const char *kernel_filename, +target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, symbol_fn_t sym_cb); void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index d3e780c3b6..2594276223 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -173,10 +173,11 @@ target_ulong riscv_load_firmware(const char *firmware= _filename, exit(1); } =20 -target_ulong riscv_load_kernel(const char *kernel_filename, +target_ulong riscv_load_kernel(MachineState *machine, target_ulong kernel_start_addr, symbol_fn_t sym_cb) { + const char *kernel_filename =3D machine->kernel_filename; uint64_t kernel_load_base, kernel_entry; =20 g_assert(kernel_filename !=3D NULL); diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 1e9b0a420e..82ae5e7023 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -629,8 +629,7 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, NULL); + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); =20 if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 85ffdac5be..64d5d435b9 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -101,8 +101,7 @@ static void opentitan_board_init(MachineState *machine) } =20 if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename, - memmap[IBEX_DEV_RAM].base, NULL); + riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); } } =20 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index d65d2fd869..3e3f4b0088 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,8 +114,7 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_m= emory); =20 if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename, - memmap[SIFIVE_E_DEV_DTIM].base, NULL); + riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); } } =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index c40885ed5c..bac394c959 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -598,8 +598,7 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, NULL); + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); =20 if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 99dec74fe8..bff9475686 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -307,8 +307,7 @@ static void spike_board_init(MachineState *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, htif_symbol_callback); =20 if (machine->initrd_filename) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 02f1369843..c8e35f861e 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1281,8 +1281,7 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, NULL); + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); =20 if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200878893201.27830284382117; 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s=dkim; t=1674200409; x=1676792410; bh=75p6q6papmZYiiyu7h uH6SZQbAyDQNAew4tAaHInoTU=; b=S364zsjV5MEfEdk21CHKywBUaszMVj1AID c2QpKujq0cSYe2SxE8TVi+Mjm6dYl5ImTa82YjLzbVPcBqZpDFiBuX/URZa4VUWl +wAFJE5fQs1tfeRi1MHPT1rhS9646pOAzo6PkTilLa7cTKZC+LMrsaah0A81RrgN PnasKefY+7qpkpRFgTLUuJ/0Y2/poSLtNym78PA4mBj+KKY8Oh5Wi4v7gzojeDkd ZEvg4tiQKhhEJSGi98o9SSYLEWV+6o3wyEZ2hMsBEsADuWfDtisuiZevxpFSA8lm QIL1K+6fxyMLUhRq5yYVOc4Isb/K5VeFCLZfJaCPOzBrg/zRHHlg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis Subject: [PULL 23/37] target/riscv/cpu: set cpu->cfg in register_cpu_props() Date: Fri, 20 Jan 2023 17:38:59 +1000 Message-Id: <20230120073913.1028407-24-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200879809100005 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza There is an informal contract between the cpu_init() functions and riscv_cpu_realize(): if cpu->env.misa_ext is zero, assume that the default settings were loaded via register_cpu_props() and do validations to set env.misa_ext. If it's not zero, skip this whole process and assume that the board somehow did everything. At this moment, all SiFive CPUs are setting a non-zero misa_ext during their cpu_init() and skipping a good chunk of riscv_cpu_realize(). This causes problems when the code being skipped in riscv_cpu_realize() contains fixes or assumptions that affects all CPUs, meaning that SiFive CPUs are missing out. To allow this code to not be skipped anymore, all the cpu->cfg.ext_* attributes needs to be set during cpu_init() time. At this moment this is being done in register_cpu_props(). The SiFive boards are setting their own extensions during cpu_init() though, meaning that they don't want all the defaults from register_cpu_props(). Let's move the contract between *_cpu_init() and riscv_cpu_realize() to register_cpu_props(). Inside this function we'll check if cpu->env.misa_ext was set and, if that's the case, set all relevant cpu->cfg.ext_* attributes, and only that. Leave the 'misa_ext' =3D 0 case as is today, i.e. loading all the defaults from riscv_cpu_extensions[]. register_cpu_props() can then be called by all the cpu_init() functions, including the SiFive ones. This will make all CPUs behave more in line with what riscv_cpu_realize() expects. This will also make the cpu_init() functions even more alike, but at this moment we would need some design changes in how we're initializing extensions/attributes (e.g. some CPUs are setting cfg options after register_cpu_props(), so we can't simply add the function to a common post_init() hook) to make a common cpu_init() code across all CPUs. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-Id: <20230113175230.473975-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 4 ++++ target/riscv/cpu.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 61a9a40958..bcf0826753 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -63,6 +63,10 @@ =20 #define RV(x) ((target_ulong)1 << (x - 'A')) =20 +/* + * Consider updating register_cpu_props() when adding + * new MISA bits here. + */ #define RVI RV('I') #define RVE RV('E') /* E and I are mutually exclusive */ #define RVM RV('M') diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a2e6238bd7..e682102c2a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -256,6 +256,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); } =20 @@ -265,6 +266,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; } @@ -299,6 +301,7 @@ static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); } =20 @@ -308,6 +311,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; } @@ -318,6 +322,7 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu =3D false; cpu->cfg.epmp =3D true; @@ -329,6 +334,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; } @@ -1083,10 +1089,44 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +/* + * Register CPU props based on env.misa_ext. If a non-zero + * value was set, register only the required cpu->cfg.ext_* + * properties and leave. env.misa_ext =3D 0 means that we want + * all the default properties to be registered. + */ static void register_cpu_props(DeviceState *dev) { + RISCVCPU *cpu =3D RISCV_CPU(OBJECT(dev)); + uint32_t misa_ext =3D cpu->env.misa_ext; Property *prop; =20 + /* + * If misa_ext is not zero, set cfg properties now to + * allow them to be read during riscv_cpu_realize() + * later on. + */ + if (cpu->env.misa_ext !=3D 0) { + cpu->cfg.ext_i =3D misa_ext & RVI; + cpu->cfg.ext_e =3D misa_ext & RVE; + cpu->cfg.ext_m =3D misa_ext & RVM; + cpu->cfg.ext_a =3D misa_ext & RVA; + cpu->cfg.ext_f =3D misa_ext & RVF; + cpu->cfg.ext_d =3D misa_ext & RVD; + cpu->cfg.ext_v =3D misa_ext & RVV; + cpu->cfg.ext_c =3D misa_ext & RVC; + cpu->cfg.ext_s =3D misa_ext & RVS; + cpu->cfg.ext_u =3D misa_ext & RVU; + cpu->cfg.ext_h =3D misa_ext & RVH; + cpu->cfg.ext_j =3D misa_ext & RVJ; + + /* + * We don't want to set the default riscv_cpu_extensions + * in this case. + */ + return; + } + for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200674270618.8206062786506; Thu, 19 Jan 2023 23:44:34 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIm1d-0001ld-W6; Fri, 20 Jan 2023 02:41:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIm13-0000pJ-UX for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1674200411; x=1676792412; bh=ux/YK7yCtbbj+1lS74 siEIsxHU18w5+gaMSdUfmwMLI=; b=CzAB9gzK92LJdcXLu7KdPEZhwJX/vTvnxu CCLmIR9bgF6b6JQ5gdX3WRaTG0lk3UlQcUwFXLUTFcgkbf00Nk5mQ0UCiZvz3ep5 RqqJJZWIRp7RXd/l+/pLGK5uyvvgeAdabibbIDY8oOb4GzKHAikJDrNnPcfXX0rO dJ5/mswR2jgOFASugyJNM+RcHSeOf2/9xqsudNz+ghdPtd034bnULHls8h3h/7ZY v6Y39Fzv+6gQOdFsKWmkwkrO7SfWnn18/yJvOz/x1tJFgMmMXj2ssLtuXlfy8WGd DEuegLybmZIa9H95RJ7L1z/NdCMuexgssnqlz7DCL0BSMe2jCoOQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis , Bin Meng Subject: [PULL 24/37] target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() Date: Fri, 20 Jan 2023 17:39:00 +1000 Message-Id: <20230120073913.1028407-25-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200674688100007 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza All RISCV CPUs are setting cpu->cfg during their cpu_init() functions, meaning that there's no reason to skip all the misa validation and setup if misa_ext was set beforehand - especially since we're setting an updated value in set_misa() in the end. Put this code chunk into a new riscv_cpu_validate_set_extensions() helper and always execute it regardless of what the board set in env->misa_ext. This will put more responsibility in how each board is going to init their attributes and extensions if they're not using the defaults. It'll also allow realize() to do its job looking only at the extensions enabled per se, not corner cases that some CPUs might have, and we won't have to change multiple code paths to fix or change how extensions work. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-Id: <20230113175230.473975-3-dbarboza@ventanamicro.com> [ Changes by AF: - Rebase ] Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 399 +++++++++++++++++++++++---------------------- 1 file changed, 205 insertions(+), 194 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e682102c2a..c192d96a94 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -625,6 +625,207 @@ static void riscv_cpu_disas_set_info(CPUState *s, dis= assemble_info *info) } } =20 +/* + * Check consistency between chosen extensions while setting + * cpu->cfg accordingly, doing a set_misa() in the end. + */ +static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + uint32_t ext =3D 0; + + /* Do some ISA extension error checking */ + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && + cpu->cfg.ext_a && cpu->cfg.ext_f && + cpu->cfg.ext_d && + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { + warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); + cpu->cfg.ext_i =3D true; + cpu->cfg.ext_m =3D true; + cpu->cfg.ext_a =3D true; + cpu->cfg.ext_f =3D true; + cpu->cfg.ext_d =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.ext_ifencei =3D true; + } + + if (cpu->cfg.ext_i && cpu->cfg.ext_e) { + error_setg(errp, + "I and E extensions are incompatible"); + return; + } + + if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { + error_setg(errp, + "Either I or E extension must be set"); + return; + } + + if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { + error_setg(errp, + "Setting S extension without U extension is illegal"); + return; + } + + if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { + error_setg(errp, + "H depends on an I base integer ISA with 32 x registers= "); + return; + } + + if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { + error_setg(errp, "H extension implicitly requires S-mode"); + return; + } + + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { + error_setg(errp, "F extension requires Zicsr"); + return; + } + + if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { + error_setg(errp, "Zawrs extension requires A extension"); + return; + } + + if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { + error_setg(errp, "Zfh/Zfhmin extensions require F extension"); + return; + } + + if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { + error_setg(errp, "D extension requires F extension"); + return; + } + + if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { + error_setg(errp, "V extension requires D extension"); + return; + } + + if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { + error_setg(errp, "Zve32f/Zve64f extensions require F extension"); + return; + } + + /* Set the ISA extensions, checks should have happened above */ + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || + cpu->cfg.ext_zhinxmin) { + cpu->cfg.ext_zfinx =3D true; + } + + if (cpu->cfg.ext_zfinx) { + if (!cpu->cfg.ext_icsr) { + error_setg(errp, "Zfinx extension requires Zicsr"); + return; + } + if (cpu->cfg.ext_f) { + error_setg(errp, + "Zfinx cannot be supported together with F extension"); + return; + } + } + + if (cpu->cfg.ext_zk) { + cpu->cfg.ext_zkn =3D true; + cpu->cfg.ext_zkr =3D true; + cpu->cfg.ext_zkt =3D true; + } + + if (cpu->cfg.ext_zkn) { + cpu->cfg.ext_zbkb =3D true; + cpu->cfg.ext_zbkc =3D true; + cpu->cfg.ext_zbkx =3D true; + cpu->cfg.ext_zkne =3D true; + cpu->cfg.ext_zknd =3D true; + cpu->cfg.ext_zknh =3D true; + } + + if (cpu->cfg.ext_zks) { + cpu->cfg.ext_zbkb =3D true; + cpu->cfg.ext_zbkc =3D true; + cpu->cfg.ext_zbkx =3D true; + cpu->cfg.ext_zksed =3D true; + cpu->cfg.ext_zksh =3D true; + } + + if (cpu->cfg.ext_i) { + ext |=3D RVI; + } + if (cpu->cfg.ext_e) { + ext |=3D RVE; + } + if (cpu->cfg.ext_m) { + ext |=3D RVM; + } + if (cpu->cfg.ext_a) { + ext |=3D RVA; + } + if (cpu->cfg.ext_f) { + ext |=3D RVF; + } + if (cpu->cfg.ext_d) { + ext |=3D RVD; + } + if (cpu->cfg.ext_c) { + ext |=3D RVC; + } + if (cpu->cfg.ext_s) { + ext |=3D RVS; + } + if (cpu->cfg.ext_u) { + ext |=3D RVU; + } + if (cpu->cfg.ext_h) { + ext |=3D RVH; + } + if (cpu->cfg.ext_v) { + int vext_version =3D VEXT_VERSION_1_00_0; + ext |=3D RVV; + if (!is_power_of_2(cpu->cfg.vlen)) { + error_setg(errp, + "Vector extension VLEN must be power of 2"); + return; + } + if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { + error_setg(errp, + "Vector extension implementation only supports VLEN " + "in the range [128, %d]", RV_VLEN_MAX); + return; + } + if (!is_power_of_2(cpu->cfg.elen)) { + error_setg(errp, + "Vector extension ELEN must be power of 2"); + return; + } + if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { + error_setg(errp, + "Vector extension implementation only supports ELEN " + "in the range [8, 64]"); + return; + } + if (cpu->cfg.vext_spec) { + if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { + vext_version =3D VEXT_VERSION_1_00_0; + } else { + error_setg(errp, + "Unsupported vector spec version '%s'", + cpu->cfg.vext_spec); + return; + } + } else { + qemu_log("vector version is not specified, " + "use the default value v1.0\n"); + } + set_vext_version(env, vext_version); + } + if (cpu->cfg.ext_j) { + ext |=3D RVJ; + } + + set_misa(env, env->misa_mxl, ext); +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -720,200 +921,10 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) } assert(env->misa_mxl_max =3D=3D env->misa_mxl); =20 - /* If only MISA_EXT is unset for misa, then set it from properties */ - if (env->misa_ext =3D=3D 0) { - uint32_t ext =3D 0; - - /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && - cpu->cfg.ext_a && cpu->cfg.ext_f && - cpu->cfg.ext_d && - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)= ) { - warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_i =3D true; - cpu->cfg.ext_m =3D true; - cpu->cfg.ext_a =3D true; - cpu->cfg.ext_f =3D true; - cpu->cfg.ext_d =3D true; - cpu->cfg.ext_icsr =3D true; - cpu->cfg.ext_ifencei =3D true; - } - - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { - error_setg(errp, - "I and E extensions are incompatible"); - return; - } - - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { - error_setg(errp, - "Either I or E extension must be set"); - return; - } - - if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { - error_setg(errp, - "Setting S extension without U extension is illegal= "); - return; - } - - if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { - error_setg(errp, - "H depends on an I base integer ISA with 32 x regis= ters"); - return; - } - - if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { - error_setg(errp, "H extension implicitly requires S-mode"); - return; - } - - if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { - error_setg(errp, "F extension requires Zicsr"); - return; - } - - if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { - error_setg(errp, "Zawrs extension requires A extension"); - return; - } - - if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { - error_setg(errp, "Zfh/Zfhmin extensions require F extension"); - return; - } - - if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { - error_setg(errp, "D extension requires F extension"); - return; - } - - if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { - error_setg(errp, "V extension requires D extension"); - return; - } - - if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_= f) { - error_setg(errp, "Zve32f/Zve64f extensions require F extension= "); - return; - } - - /* Set the ISA extensions, checks should have happened above */ - if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || - cpu->cfg.ext_zhinxmin) { - cpu->cfg.ext_zfinx =3D true; - } - - if (cpu->cfg.ext_zfinx) { - if (!cpu->cfg.ext_icsr) { - error_setg(errp, "Zfinx extension requires Zicsr"); - return; - } - if (cpu->cfg.ext_f) { - error_setg(errp, - "Zfinx cannot be supported together with F extension"); - return; - } - } - - if (cpu->cfg.ext_zk) { - cpu->cfg.ext_zkn =3D true; - cpu->cfg.ext_zkr =3D true; - cpu->cfg.ext_zkt =3D true; - } - - if (cpu->cfg.ext_zkn) { - cpu->cfg.ext_zbkb =3D true; - cpu->cfg.ext_zbkc =3D true; - cpu->cfg.ext_zbkx =3D true; - cpu->cfg.ext_zkne =3D true; - cpu->cfg.ext_zknd =3D true; - cpu->cfg.ext_zknh =3D true; - } - - if (cpu->cfg.ext_zks) { - cpu->cfg.ext_zbkb =3D true; - cpu->cfg.ext_zbkc =3D true; - cpu->cfg.ext_zbkx =3D true; - cpu->cfg.ext_zksed =3D true; - cpu->cfg.ext_zksh =3D true; - } - - if (cpu->cfg.ext_i) { - ext |=3D RVI; - } - if (cpu->cfg.ext_e) { - ext |=3D RVE; - } - if (cpu->cfg.ext_m) { - ext |=3D RVM; - } - if (cpu->cfg.ext_a) { - ext |=3D RVA; - } - if (cpu->cfg.ext_f) { - ext |=3D RVF; - } - if (cpu->cfg.ext_d) { - ext |=3D RVD; - } - if (cpu->cfg.ext_c) { - ext |=3D RVC; - } - if (cpu->cfg.ext_s) { - ext |=3D RVS; - } - if (cpu->cfg.ext_u) { - ext |=3D RVU; - } - if (cpu->cfg.ext_h) { - ext |=3D RVH; - } - if (cpu->cfg.ext_v) { - int vext_version =3D VEXT_VERSION_1_00_0; - ext |=3D RVV; - if (!is_power_of_2(cpu->cfg.vlen)) { - error_setg(errp, - "Vector extension VLEN must be power of 2"); - return; - } - if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { - error_setg(errp, - "Vector extension implementation only supports VLE= N " - "in the range [128, %d]", RV_VLEN_MAX); - return; - } - if (!is_power_of_2(cpu->cfg.elen)) { - error_setg(errp, - "Vector extension ELEN must be power of 2"); - return; - } - if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { - error_setg(errp, - "Vector extension implementation only supports ELE= N " - "in the range [8, 64]"); - return; - } - if (cpu->cfg.vext_spec) { - if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { - vext_version =3D VEXT_VERSION_1_00_0; - } else { - error_setg(errp, - "Unsupported vector spec version '%s'", - cpu->cfg.vext_spec); - return; - } - } else { - qemu_log("vector version is not specified, " - "use the default value v1.0\n"); - } - set_vext_version(env, vext_version); - } - if (cpu->cfg.ext_j) { - ext |=3D RVJ; - } - - set_misa(env, env->misa_mxl, ext); + riscv_cpu_validate_set_extensions(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; } =20 #ifndef CONFIG_USER_ONLY --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200645148993.0297574826799; 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s=dkim; t=1674200413; x=1676792414; bh=F5UmDhHdivyXvZXkB+ ebiNtlq6eeUv4uMJna0z0QHno=; b=Y6I2YSIJq1biJgKr2aqF9YnWReRr91Ym0C 70JGLWdADN2sErYeo9fyekxOBaDiMOFIZAMZ3Gjc8pd3nb0AXrTwPfTplIXsWAcu yBVBMw/cRj9SGSCvsQoLyfLFuLT3C+htqY8IE6wtkEHCgLXt2jKlchSdGcKWbPHm UcdVX9/cqaqbMIh/xaAmvidAmOdsQD83QEg1iIH26/numDmA63akex0z0Ai/dlel DXOKdqYuqcH4B6kUbJqtMk4DLctXSid9wunHxh+G9k4eYnPvFt1gkUXBmBhksFH5 C9mH506mfYiQzd/Ryp00AlxkUuABeYWUgqrdzOQ0HfsG9Lov02Tw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Alistair Francis Subject: [PULL 25/37] target/riscv: Use TARGET_FMT_lx for env->mhartid Date: Fri, 20 Jan 2023 17:39:01 +1000 Message-Id: <20230120073913.1028407-26-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200646508100003 Content-Type: text/plain; charset="utf-8" From: Bin Meng env->mhartid is currently casted to long before printed, which drops the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20230109152655.340114-1-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c192d96a94..14a7027095 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -867,9 +867,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) (env->priv_ver < isa_edata_arr[i].min_version)) { isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); #ifndef CONFIG_USER_ONLY - warn_report("disabling %s extension for hart 0x%lx because " - "privilege spec version does not match", - isa_edata_arr[i].name, (unsigned long)env->mhartid= ); + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx + " because privilege spec version does not match", + isa_edata_arr[i].name, env->mhartid); #else warn_report("disabling %s extension because " "privilege spec version does not match", --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200529772100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza 'mem_size' and 'cmdline' are unused. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-Id: <20230111170948.316276-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/spike.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index bff9475686..c7550abfc7 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -49,7 +49,6 @@ static const MemMapEntry spike_memmap[] =3D { }; =20 static void create_fdt(SpikeState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_bit, bool htif_custom_base) { void *fdt; @@ -299,8 +298,7 @@ static void spike_board_init(MachineState *machine) } =20 /* Create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc[0]), htif_custom_base); + create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base); =20 /* Load kernel */ if (machine->kernel_filename) { --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200674650100004 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza 'mem_size' and 'cmdline' aren't being used. Remove them. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-Id: <20230111170948.316276-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c8e35f861e..1921d3caa3 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -999,7 +999,7 @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const = MemMapEntry *memmap) } =20 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_= bit) + bool is_32_bit) { MachineState *mc =3D MACHINE(s); uint32_t phandle =3D 1, irq_mmio_phandle =3D 1, msi_pcie_phandle =3D 1; @@ -1507,8 +1507,7 @@ static void virt_machine_init(MachineState *machine) virt_flash_map(s, system_memory); =20 /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc[0])); + create_fdt(s, memmap, riscv_is_32bit(&s->soc[0])); =20 s->machine_done.notify =3D virt_machine_done; qemu_add_machine_init_done_notifier(&s->machine_done); --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200674309571.4022921531881; Thu, 19 Jan 2023 23:44:34 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIm1m-0002KS-SI; Fri, 20 Jan 2023 02:41:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIm1H-0001DF-F5 for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1674200420; x=1676792421; bh=hehPgQW OMMZWoDAuH5kxYAfsiSPA2nS6XH2RvSM0D5w=; b=TFDAXeJpCfL/PYCQv3/aC4a T25iGsAugp9VfQFAMk5UH3F9LzXF8QelSx7KgsUOekIgCf4BUrE+e9a8FUZEbRZe yV9Mz5FTD2Yzc2v6XvrQjdGSxCDTczU6upkSO6s+MolFrNxnZZZPP/2qkPIgYoPj Et+kbousN66XnDWKOrPE9E8xYeUs53bF8kmf1WaF8jUUsQ5RYEIIGENuCJRFSZNB vz/AkF6Egle8i3XO6Y4TbyuCNxSiDigm7CWtAU+XfvaS2DrYzDwov1z9CvHv9K1B sMBL/qWZ8c4IRDcK80xQ+OTWcCAa9yh+pXfTvw05Smmrzuzxt+l+OTIMCBXBSBA= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 28/37] hw/riscv/sifive_u.c: simplify create_fdt() Date: Fri, 20 Jan 2023 17:39:04 +1000 Message-Id: <20230120073913.1028407-29-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200674647100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza 'cmdline' isn't being used. Remove it. A MachineState pointer is being retrieved via a MACHINE() macro calling qdev_get_machine(). Use MACHINE(s) instead to avoid calling qdev(). 'mem_size' is being set as machine->ram_size by the caller. Retrieve it via ms->ram_size. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-Id: <20230111170948.316276-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index bac394c959..2fb6ee231f 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -94,9 +94,10 @@ static const MemMapEntry sifive_u_memmap[] =3D { #define GEM_REVISION 0x10070109 =20 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_= bit) + bool is_32_bit) { - MachineState *ms =3D MACHINE(qdev_get_machine()); + MachineState *ms =3D MACHINE(s); + uint64_t mem_size =3D ms->ram_size; void *fdt; int cpu, fdt_size; uint32_t *cells; @@ -560,8 +561,7 @@ static void sifive_u_machine_init(MachineState *machine) qemu_allocate_irq(sifive_u_machine_reset, NULL, = 0)); =20 /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc.u_cpus)); + create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus)); =20 if (s->start_in_flash) { /* --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200776670508.4734821071671; Thu, 19 Jan 2023 23:46:16 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIm1m-0002IK-I6; Fri, 20 Jan 2023 02:41:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIm1Q-0001ZO-SF for qemu-devel@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200777345100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza create_fdt_socket_cpus() writes a different 'mmu-type' value if we're running in 32 or 64 bits. However, the flag is being calculated during virt_machine_init(), and is passed around in create_fdt(), then create_fdt_socket(), and then finally create_fdt_socket_cpus(). None of the intermediate functions are using the flag, which is a bit misleading. Remove 'is_32_bit' flag from create_fdt_socket_cpus() and calculate it using the already available RISCVVirtState pointer. This will also change the signature of create_fdt_socket() and create_fdt(), making it clear that these functions don't do anything special when we're running in 32 bit mode. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-Id: <20230111170948.316276-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 1921d3caa3..99cb571024 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -223,12 +223,13 @@ static void create_pcie_irq_map(RISCVVirtState *s, vo= id *fdt, char *nodename, =20 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, char *clust_name, uint32_t *phandle, - bool is_32_bit, uint32_t *intc_phandles) + uint32_t *intc_phandles) { int cpu; uint32_t cpu_phandle; MachineState *mc =3D MACHINE(s); char *name, *cpu_name, *core_name, *intc_name; + bool is_32_bit =3D riscv_is_32bit(&s->soc[0]); =20 for (cpu =3D s->soc[socket].num_harts - 1; cpu >=3D 0; cpu--) { cpu_phandle =3D (*phandle)++; @@ -721,7 +722,7 @@ static void create_fdt_pmu(RISCVVirtState *s) } =20 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memma= p, - bool is_32_bit, uint32_t *phandle, + uint32_t *phandle, uint32_t *irq_mmio_phandle, uint32_t *irq_pcie_phandle, uint32_t *irq_virtio_phandle, @@ -750,7 +751,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, qemu_fdt_add_subnode(mc->fdt, clust_name); =20 create_fdt_socket_cpus(s, socket, clust_name, phandle, - is_32_bit, &intc_phandles[phandle_pos]); + &intc_phandles[phandle_pos]); =20 create_fdt_socket_memory(s, memmap, socket); =20 @@ -998,8 +999,7 @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const = MemMapEntry *memmap) g_free(nodename); } =20 -static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - bool is_32_bit) +static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) { MachineState *mc =3D MACHINE(s); uint32_t phandle =3D 1, irq_mmio_phandle =3D 1, msi_pcie_phandle =3D 1; @@ -1031,9 +1031,9 @@ static void create_fdt(RISCVVirtState *s, const MemMa= pEntry *memmap, qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); =20 - create_fdt_sockets(s, memmap, is_32_bit, &phandle, - &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, - &msi_pcie_phandle); + create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle, + &irq_pcie_phandle, &irq_virtio_phandle, + &msi_pcie_phandle); =20 create_fdt_virtio(s, memmap, irq_virtio_phandle); =20 @@ -1507,7 +1507,7 @@ static void virt_machine_init(MachineState *machine) virt_flash_map(s, system_memory); =20 /* create device tree */ - create_fdt(s, memmap, riscv_is_32bit(&s->soc[0])); + create_fdt(s, memmap); =20 s->machine_done.notify =3D virt_machine_done; qemu_add_machine_init_done_notifier(&s->machine_done); --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200675464866.8291303727963; Thu, 19 Jan 2023 23:44:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIm1k-000254-2k; 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s=dkim; t=1674200423; x=1676792424; bh=zZvEpv4 rPGsN2APAPO4ea4PwHMq9ix+ravFcIefjXNU=; b=nw6yXdDG2U6OhJe2tpDmGM+ 6swLl7kfVbbU+tky6+0FIel+1TAH6xn4lzqNHXFLkEdupOwpxhpgSP57toXCMIAY 6Jd/c03Lvvk4DO5yAQ2DkQlFxDssLA/9zD+rEoxzoKkNh6lEzzMHd+2FL0T/3JSI dKIJxUk+gvq2D5xVzd3iAquzz3ZxNfxFy+aqGwyc/NzJo41n93R0SmM2iOvvFCsp 1qQJVFKbcEUvnbgRe9jkdCIt12lMNQNTVKhNwXFqxaxTRIysZUKqP7/U+PkaeQPr rrZA3Ygd9NoibJeJ/tKr6UlarSFEMpd+Q8h3mXKu46YWGbEiTwnnVEQCV1XtclQ= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 30/37] hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() Date: Fri, 20 Jan 2023 17:39:06 +1000 Message-Id: <20230120073913.1028407-31-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200676688100015 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza There's no need to use a MachineState pointer and a fdt pointer now that all RISC-V machines are using the FDT from the MachineState. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-Id: <20230111170948.316276-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- include/hw/riscv/numa.h | 6 +++--- hw/riscv/numa.c | 6 +++--- hw/riscv/spike.c | 6 +++--- hw/riscv/virt.c | 18 +++++++++--------- 4 files changed, 18 insertions(+), 18 deletions(-) diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h index 1a9cce3344..634df6673f 100644 --- a/include/hw/riscv/numa.h +++ b/include/hw/riscv/numa.h @@ -90,10 +90,10 @@ bool riscv_socket_check_hartids(const MachineState *ms,= int socket_id); * @ms: pointer to machine state * @socket_id: socket index * - * Write NUMA node-id FDT property for given FDT node + * Write NUMA node-id FDT property in MachineState->fdt */ -void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt, - const char *node_name, int socket_id); +void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_na= me, + int socket_id); =20 /** * riscv_socket_fdt_write_distance_matrix: diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c index 7fe92d402f..f4343f5cde 100644 --- a/hw/riscv/numa.c +++ b/hw/riscv/numa.c @@ -156,11 +156,11 @@ uint64_t riscv_socket_mem_size(const MachineState *ms= , int socket_id) ms->numa_state->nodes[socket_id].node_mem : 0; } =20 -void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt, - const char *node_name, int socket_id) +void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_na= me, + int socket_id) { if (numa_enabled(ms)) { - qemu_fdt_setprop_cell(fdt, node_name, "numa-node-id", socket_id); + qemu_fdt_setprop_cell(ms->fdt, node_name, "numa-node-id", socket_i= d); } } =20 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index c7550abfc7..5f12d80317 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -121,7 +121,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry= *memmap, qemu_fdt_setprop_cell(fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); + riscv_socket_fdt_write_id(mc, cpu_name, socket); qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); =20 intc_name =3D g_strdup_printf("%s/interrupt-controller", cpu_n= ame); @@ -154,7 +154,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry= *memmap, qemu_fdt_setprop_cells(fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); + riscv_socket_fdt_write_id(mc, mem_name, socket); g_free(mem_name); =20 clint_addr =3D memmap[SPIKE_CLINT].base + @@ -167,7 +167,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry= *memmap, 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); + riscv_socket_fdt_write_id(mc, clint_name, socket); =20 g_free(clint_name); g_free(clint_cells); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 99cb571024..6a2422a8cf 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -253,7 +253,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, i= nt socket, qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); + riscv_socket_fdt_write_id(mc, cpu_name, socket); qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); =20 intc_phandles[cpu] =3D (*phandle)++; @@ -291,7 +291,7 @@ static void create_fdt_socket_memory(RISCVVirtState *s, qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); + riscv_socket_fdt_write_id(mc, mem_name, socket); g_free(mem_name); } =20 @@ -327,7 +327,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s, 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); + riscv_socket_fdt_write_id(mc, clint_name, socket); g_free(clint_name); =20 g_free(clint_cells); @@ -372,7 +372,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, aclint_mswi_cells, aclint_cells_size); qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); + riscv_socket_fdt_write_id(mc, name, socket); g_free(name); } =20 @@ -396,7 +396,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, 0x0, RISCV_ACLINT_DEFAULT_MTIME); qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", aclint_mtimer_cells, aclint_cells_size); - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); + riscv_socket_fdt_write_id(mc, name, socket); g_free(name); =20 if (s->aia_type !=3D VIRT_AIA_TYPE_APLIC_IMSIC) { @@ -412,7 +412,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, aclint_sswi_cells, aclint_cells_size); qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); + riscv_socket_fdt_write_id(mc, name, socket); g_free(name); } =20 @@ -471,7 +471,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s, 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRT_IRQCHIP_NUM_SOURCES - 1); - riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); + riscv_socket_fdt_write_id(mc, plic_name, socket); qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", plic_phandles[socket]); =20 @@ -663,7 +663,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_s_phandle); qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); + riscv_socket_fdt_write_id(mc, aplic_name, socket); qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); g_free(aplic_name); =20 @@ -691,7 +691,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); + riscv_socket_fdt_write_id(mc, aplic_name, socket); qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); =20 if (!socket) { --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1674200426; x=1676792427; bh=rfY2u8d hIoaTPk78wdVT5ZKWXL++drd/MLsDGfqJElw=; b=X7K71gQ6jEcIP78q5FFot0k Ru4Vf87th5QLtA1erQT52CIQRuTdJiq1PLMKw9GK8e38u8n5nv9NvKg/rKa4nQ1x zGgtw+wyM5N37fmeKwkgw6RPjGG3dcBIK2jHIc8CsfR4P7wJVOVNIGyEHb5v+e8K y66o1YBErSfOrJBDNtlLq3iDOthj3jALtuv+Jt8uHdLQXZoGnR4CEKv9sU7w9y1/ LaSxrt9vhNmEuC+xhV1pJc95xbNG/MJ+jM/7f3Gg53G/EB3yR0N0KwQCBK52O0G2 LKbWGhf3kPU3p7FpPY5um25r71dUXMUHOdLHerzi/TgCeHM6nHcrP2czGOr/AHg= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 31/37] hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() Date: Fri, 20 Jan 2023 17:39:07 +1000 Message-Id: <20230120073913.1028407-32-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200612385100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza There's no need to use a MachineState pointer and a fdt pointer now that all RISC-V machines are using the FDT from the MachineState. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-Id: <20230111170948.316276-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- include/hw/riscv/numa.h | 4 ++-- hw/riscv/numa.c | 8 ++++---- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h index 634df6673f..8f5280211d 100644 --- a/include/hw/riscv/numa.h +++ b/include/hw/riscv/numa.h @@ -100,9 +100,9 @@ void riscv_socket_fdt_write_id(const MachineState *ms, = const char *node_name, * @ms: pointer to machine state * @socket_id: socket index * - * Write NUMA distance matrix in FDT for given machine + * Write NUMA distance matrix in MachineState->fdt */ -void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *= fdt); +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms); =20 CpuInstanceProperties riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index); diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c index f4343f5cde..4720102561 100644 --- a/hw/riscv/numa.c +++ b/hw/riscv/numa.c @@ -164,7 +164,7 @@ void riscv_socket_fdt_write_id(const MachineState *ms, = const char *node_name, } } =20 -void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *= fdt) +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms) { int i, j, idx; uint32_t *dist_matrix, dist_matrix_size; @@ -184,10 +184,10 @@ void riscv_socket_fdt_write_distance_matrix(const Mac= hineState *ms, void *fdt) } } =20 - qemu_fdt_add_subnode(fdt, "/distance-map"); - qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", + qemu_fdt_add_subnode(ms->fdt, "/distance-map"); + qemu_fdt_setprop_string(ms->fdt, "/distance-map", "compatible", "numa-distance-map-v1"); - qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", + qemu_fdt_setprop(ms->fdt, "/distance-map", "distance-matrix", dist_matrix, dist_matrix_size); g_free(dist_matrix); } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 5f12d80317..badc11ec43 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -174,7 +174,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry= *memmap, g_free(clust_name); } =20 - riscv_socket_fdt_write_distance_matrix(mc, fdt); + riscv_socket_fdt_write_distance_matrix(mc); =20 qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 6a2422a8cf..e6d4f06e8d 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -805,7 +805,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, } } =20 - riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); + riscv_socket_fdt_write_distance_matrix(mc); } =20 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200778509276.8454477704289; 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s=dkim; t=1674200427; x=1676792428; bh=6zDRbpI+Q7JXwc0jYA FaDT8R3hpXBbhu63OtfuPQzPs=; b=AjRJR3H9RuVxIzpmdjr/juB02D1jszT7ER d3xI+wH1j1eWDmCCUfhmRxleVUwofLrmkbRq2lGKQ8JfGHBa7w8dKuXHs65LVs/q j+VdjSL2jWZ6oY7KLaygLI1cNxTwu6JH7oBWE7RBqofZe4ZYUzQfq1Bj5SQNYdZV z2zG40dokCChrX0yxGAo85JOvsBBgmfgXO9VfqS3V35+vNhyXhX9H8YbdMvIWqHN 6WR1ey7JTxWBedOwSh8z74BcivttqU4UNV7HS9PJ6W326gXchqX4pphMyiFdlOKz lmhYQgps5LwJR3lmcAQVYtOgvzmuWDJhEVvxJd7miHo7ZA6VOisw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Andrew Bresticker , Alistair Francis Subject: [PULL 32/37] target/riscv: Fix up masking of vsip/vsie accesses Date: Fri, 20 Jan 2023 17:39:08 +1000 Message-Id: <20230120073913.1028407-33-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200779259100005 Content-Type: text/plain; charset="utf-8" From: Andrew Bresticker The current logic attempts to shift the VS-level bits into their correct position in mip while leaving the remaining bits in-tact. This is both pointless and likely incorrect since one would expect that any new, future VS-level interrupts will get their own position in mip rather than sharing with their (H)S-level equivalent. Fix this, and make the logic more readable, by just making off the VS-level bits and shifting them into position. This also fixes reads of vsip, which would only ever report vsip.VSSIP since the non-writable bits got masked off as well. Fixes: d028ac7512f1 ("arget/riscv: Implement AIA CSRs for 64 local interrup= ts on RV32") Signed-off-by: Andrew Bresticker Reviewed-by: Alistair Francis Message-Id: <20221215224541.1423431-1-abrestic@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 35 +++++++++++------------------------ 1 file changed, 11 insertions(+), 24 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0db2c233e5..270de7b1a8 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2305,22 +2305,15 @@ static RISCVException rmw_vsie64(CPURISCVState *env= , int csrno, uint64_t new_val, uint64_t wr_mask) { RISCVException ret; - uint64_t rval, vsbits, mask =3D env->hideleg & VS_MODE_INTERRUPTS; + uint64_t rval, mask =3D env->hideleg & VS_MODE_INTERRUPTS; =20 /* Bring VS-level bits to correct position */ - vsbits =3D new_val & (VS_MODE_INTERRUPTS >> 1); - new_val &=3D ~(VS_MODE_INTERRUPTS >> 1); - new_val |=3D vsbits << 1; - vsbits =3D wr_mask & (VS_MODE_INTERRUPTS >> 1); - wr_mask &=3D ~(VS_MODE_INTERRUPTS >> 1); - wr_mask |=3D vsbits << 1; + new_val =3D (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; + wr_mask =3D (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; =20 ret =3D rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask); if (ret_val) { - rval &=3D mask; - vsbits =3D rval & VS_MODE_INTERRUPTS; - rval &=3D ~VS_MODE_INTERRUPTS; - *ret_val =3D rval | (vsbits >> 1); + *ret_val =3D (rval & mask) >> 1; } =20 return ret; @@ -2521,22 +2514,16 @@ static RISCVException rmw_vsip64(CPURISCVState *env= , int csrno, uint64_t new_val, uint64_t wr_mask) { RISCVException ret; - uint64_t rval, vsbits, mask =3D env->hideleg & vsip_writable_mask; + uint64_t rval, mask =3D env->hideleg & VS_MODE_INTERRUPTS; =20 /* Bring VS-level bits to correct position */ - vsbits =3D new_val & (VS_MODE_INTERRUPTS >> 1); - new_val &=3D ~(VS_MODE_INTERRUPTS >> 1); - new_val |=3D vsbits << 1; - vsbits =3D wr_mask & (VS_MODE_INTERRUPTS >> 1); - wr_mask &=3D ~(VS_MODE_INTERRUPTS >> 1); - wr_mask |=3D vsbits << 1; - - ret =3D rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask); + new_val =3D (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; + wr_mask =3D (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; + + ret =3D rmw_mip64(env, csrno, &rval, new_val, + wr_mask & mask & vsip_writable_mask); if (ret_val) { - rval &=3D mask; - vsbits =3D rval & VS_MODE_INTERRUPTS; - rval &=3D ~VS_MODE_INTERRUPTS; - *ret_val =3D rval | (vsbits >> 1); + *ret_val =3D (rval & mask) >> 1; } =20 return ret; --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200875147634.2469816486445; Thu, 19 Jan 2023 23:47:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIm1u-0002zz-D0; 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s=dkim; t=1674200429; x=1676792430; bh=T772Us8m1gVIqd2SaH YeUWEzriOVRUmxs+boIsGHG+8=; b=JghP6dkcfkga/Cqw06mcGkw5zrXuJKsjZU U1voXDRDq2vHyerB8UULzczDrTZrYokyBSheCxhhgNQuBtMUN2PTuJr8itfM3/5p Pw4wG/96CTWaF/AC9+55WhV1GZkhluvAUI8FVq/+xCQYNtCtGRsVpdYhjUMymg1v FlVKHqej1Z1NwSfRgxPllWhOW19jgsFuhNCYOhPmSc54ILDZVzbTEwR6XUKo4H9f C0BRW3HoDxjEgG5cfka2YA74I8I4DsMW/L3yVIFiFCrc7l3NHg1Weza6jnZTe5OD 8J/rbK/2F9GogcoSvVvMd9Wl5MZStDripu4XVaOw04shyLf6BiTw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Andrew Bresticker , Alistair Francis Subject: [PULL 33/37] target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1 Date: Fri, 20 Jan 2023 17:39:09 +1000 Message-Id: <20230120073913.1028407-34-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200875732100003 Content-Type: text/plain; charset="utf-8" From: Andrew Bresticker Per the AIA specification, writes to stimecmp from VS level should trap when hvictl.VTI is set since the write may cause vsip.STIP to become unset. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp support") Signed-off-by: Andrew Bresticker Reviewed-by: Alistair Francis Message-Id: <20221215224541.1423431-2-abrestic@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 270de7b1a8..62e6c4acbd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1037,6 +1037,9 @@ static RISCVException write_stimecmp(CPURISCVState *e= nv, int csrno, RISCVCPU *cpu =3D env_archcpu(env); =20 if (riscv_cpu_virt_enabled(env)) { + if (env->hvictl & HVICTL_VTI) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } return write_vstimecmp(env, csrno, val); } =20 @@ -1057,6 +1060,9 @@ static RISCVException write_stimecmph(CPURISCVState *= env, int csrno, RISCVCPU *cpu =3D env_archcpu(env); =20 if (riscv_cpu_virt_enabled(env)) { + if (env->hvictl & HVICTL_VTI) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } return write_vstimecmph(env, csrno, val); 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1674200430; x=1676792431; bh=cDRw4IBpTpo6zSRlPl UYTu4a56emOYbfmxDFaCQi4Bc=; b=UXoiUpzJW5wFplIwVgec0bbuEEONVSFnYE K2sPyKc8m2qAbFv4lt7zinP37swnuWVxb9lLy5GKosic8JMGnYkZHsfjRYUhlrAj KC1jJFXUVWT05YAQw7GY/Cno86i2UNeRacdfv2APsfKhTtqLB8M5PPTw0kaFTQmC hWbAu3msPANJ6SjdLTmOLDQGEb+2wLSml2Ep+JbnaqUcUPYcIl09KnBJAGzZL+VM TXDXebMbuW9QHY5TfkftUvGe5GcM4uaZ/ZgON7226vqg5X1FfrEpRhBhBGM3L6ZB YS+TlRjiLdir8hC7ndpjPHhKoVHkU12w+jv9JJcWHZWAbJfsrQ1Q== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis Subject: [PULL 34/37] tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst Date: Fri, 20 Jan 2023 17:39:10 +1000 Message-Id: <20230120073913.1028407-35-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200871696100005 Content-Type: text/plain; charset="utf-8" From: Richard Henderson We failed to update this with the w^x split, so misses the fact that true pc-relative offsets are usually small. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20230117230415.354239-1-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- tcg/riscv/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index fc0edd811f..01cb67ef7b 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -599,7 +599,7 @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, = TCGReg data, intptr_t imm12 =3D sextreg(offset, 0, 12); =20 if (offset !=3D imm12) { - intptr_t diff =3D offset - (uintptr_t)s->code_ptr; + intptr_t diff =3D tcg_pcrel_diff(s, (void *)offset); =20 if (addr =3D=3D TCG_REG_ZERO && diff =3D=3D (int32_t)diff) { imm12 =3D sextreg(diff, 0, 12); --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1674200433; x=1676792434; bh=Q7SUXXHsk115w6NotA 000eLTiwAW407mCxAvfoZAmt8=; b=Oe1tXcYKgYLITM3MBsN2SaNwZQ1wKllxar EoC7t2Opdz2bzhp0lxXcZtl3PqU9sAGgUkkHZ9NkQu4f+26UpxazycIGLxSdN55a CL4UWfvXkS0zsS8Tb5sRK7K9bqrA5XNQzQocYP1XdEJBEU4hkE2HIlrJRwjJrMbX A9HocHE5DQJN+wPuTOXv5tD46YqDFFESU9ra2ju9LiTZaZ6Pvih3hAyQpNApHQVW nVrVrS1ZKKKWYHhjhQWYs40o0VFb/H+Xe295fargS+f7qE3vELBMDvdIWJpobgGN yUYccDkg7TxWmk/auwGIxUvU/floZN1Kmuepxo/tO+PD+F6pG+kg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 35/37] target/riscv: Introduce helper_set_rounding_mode_chkfrm Date: Fri, 20 Jan 2023 17:39:11 +1000 Message-Id: <20230120073913.1028407-36-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200686740100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson The new helper always validates the contents of FRM, even if the new rounding mode is not DYN. This is required by the vector unit. Track whether we've validated FRM separately from whether we've updated fp_status with a given rounding mode, so that we can elide calls correctly. This partially reverts d6c4d3f2a69 which attempted the to do the same thing, but with two calls to gen_set_rm(), which is both inefficient and tickles an assertion in decode_save_opc. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1441 Signed-off-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-Id: <20230115160657.3169274-2-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 1 + target/riscv/fpu_helper.c | 37 +++++++++++++++++++++++++ target/riscv/translate.c | 19 +++++++++++++ target/riscv/insn_trans/trans_rvv.c.inc | 24 +++------------- 4 files changed, 61 insertions(+), 20 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 227c7122ef..9792ab5086 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -3,6 +3,7 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32) =20 /* Floating Point - rounding mode */ DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_FLAGS_2(set_rounding_mode_chkfrm, TCG_CALL_NO_WG, void, env, i3= 2) DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env) =20 /* Floating Point - fused */ diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 5699c9517f..96817df8ef 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -81,6 +81,43 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32= _t rm) set_float_rounding_mode(softrm, &env->fp_status); } =20 +void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm) +{ + int softrm; + + /* Always validate frm, even if rm !=3D DYN. */ + if (unlikely(env->frm >=3D 5)) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + if (rm =3D=3D RISCV_FRM_DYN) { + rm =3D env->frm; + } + switch (rm) { + case RISCV_FRM_RNE: + softrm =3D float_round_nearest_even; + break; + case RISCV_FRM_RTZ: + softrm =3D float_round_to_zero; + break; + case RISCV_FRM_RDN: + softrm =3D float_round_down; + break; + case RISCV_FRM_RUP: + softrm =3D float_round_up; + break; + case RISCV_FRM_RMM: + softrm =3D float_round_ties_away; + break; + case RISCV_FRM_ROD: + softrm =3D float_round_to_odd; + break; + default: + g_assert_not_reached(); + } + + set_float_rounding_mode(softrm, &env->fp_status); +} + void helper_set_rod_rounding_mode(CPURISCVState *env) { set_float_rounding_mode(float_round_to_odd, &env->fp_status); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index df38db7553..493c3815e1 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -114,6 +114,8 @@ typedef struct DisasContext { bool pm_base_enabled; /* Use icount trigger for native debug */ bool itrigger; + /* FRM is known to contain a valid value. */ + bool frm_valid; /* TCG of the current insn_start */ TCGOp *insn_start; } DisasContext; @@ -674,12 +676,29 @@ static void gen_set_rm(DisasContext *ctx, int rm) gen_helper_set_rod_rounding_mode(cpu_env); return; } + if (rm =3D=3D RISCV_FRM_DYN) { + /* The helper will return only if frm valid. */ + ctx->frm_valid =3D true; + } =20 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ decode_save_opc(ctx); gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); } =20 +static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) +{ + if (ctx->frm =3D=3D rm && ctx->frm_valid) { + return; + } + ctx->frm =3D rm; + ctx->frm_valid =3D true; + + /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ + decode_save_opc(ctx); + gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); +} + static int ex_plus_1(DisasContext *ctx, int nf) { return nf + 1; diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index d455acedbf..bbb5c3a7b5 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2679,13 +2679,9 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, int rm) { if (checkfn(s, a)) { - if (rm !=3D RISCV_FRM_DYN) { - gen_set_rm(s, RISCV_FRM_DYN); - } - uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); - gen_set_rm(s, rm); + gen_set_rm_chkfrm(s, rm); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 @@ -2882,17 +2878,13 @@ static bool opffv_widen_check(DisasContext *s, arg_= rmr *a) static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ if (CHECK(s, a)) { \ - if (FRM !=3D RISCV_FRM_DYN) { \ - gen_set_rm(s, RISCV_FRM_DYN); \ - } \ - \ uint32_t data =3D 0; \ static gen_helper_gvec_3_ptr * const fns[2] =3D { \ gen_helper_##HELPER##_h, \ gen_helper_##HELPER##_w, \ }; \ TCGLabel *over =3D gen_new_label(); \ - gen_set_rm(s, FRM); \ + gen_set_rm_chkfrm(s, FRM); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ @@ -3005,17 +2997,13 @@ static bool opffv_narrow_check(DisasContext *s, arg= _rmr *a) static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ if (CHECK(s, a)) { \ - if (FRM !=3D RISCV_FRM_DYN) { \ - gen_set_rm(s, RISCV_FRM_DYN); \ - } \ - \ uint32_t data =3D 0; \ static gen_helper_gvec_3_ptr * const fns[2] =3D { \ gen_helper_##HELPER##_h, \ gen_helper_##HELPER##_w, \ }; \ TCGLabel *over =3D gen_new_label(); \ - gen_set_rm(s, FRM); \ + gen_set_rm_chkfrm(s, FRM); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ @@ -3060,10 +3048,6 @@ static bool opxfv_narrow_check(DisasContext *s, arg_= rmr *a) static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ if (opxfv_narrow_check(s, a)) { \ - if (FRM !=3D RISCV_FRM_DYN) { \ - gen_set_rm(s, RISCV_FRM_DYN); \ - } \ - \ uint32_t data =3D 0; \ static gen_helper_gvec_3_ptr * const fns[3] =3D { \ gen_helper_##HELPER##_b, \ @@ -3071,7 +3055,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ gen_helper_##HELPER##_w, \ }; \ TCGLabel *over =3D gen_new_label(); \ - gen_set_rm(s, FRM); \ + gen_set_rm_chkfrm(s, FRM); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200827467100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson The only setting of RISCV_FRM_ROD is from the vector unit, and now handled by helper_set_rounding_mode_chkfrm. This helper is now unused. Signed-off-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-Id: <20230115160657.3169274-3-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 1 - target/riscv/fpu_helper.c | 5 ----- target/riscv/translate.c | 4 ---- 3 files changed, 10 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 9792ab5086..58a30f03d6 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -4,7 +4,6 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32) /* Floating Point - rounding mode */ DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) DEF_HELPER_FLAGS_2(set_rounding_mode_chkfrm, TCG_CALL_NO_WG, void, env, i3= 2) -DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env) =20 /* Floating Point - fused */ DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 96817df8ef..449d236df6 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -118,11 +118,6 @@ void helper_set_rounding_mode_chkfrm(CPURISCVState *en= v, uint32_t rm) set_float_rounding_mode(softrm, &env->fp_status); } =20 -void helper_set_rod_rounding_mode(CPURISCVState *env) -{ - set_float_rounding_mode(float_round_to_odd, &env->fp_status); -} - static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2, uint64_t rs3, int flags) { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 493c3815e1..01cc30a365 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -672,10 +672,6 @@ static void gen_set_rm(DisasContext *ctx, int rm) } ctx->frm =3D rm; =20 - if (rm =3D=3D RISCV_FRM_ROD) { - gen_helper_set_rod_rounding_mode(cpu_env); - return; - } if (rm =3D=3D RISCV_FRM_DYN) { /* The helper will return only if frm valid. */ ctx->frm_valid =3D true; --=20 2.39.0 From nobody Sat May 18 17:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674200682053778.8437173930272; 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s=dkim; t=1674200436; x=1676792437; bh=EhCTA0uOIpz+G/q3i9 pexF41wYJQaVRzdVObkvGZqwE=; b=hHqeyZi1d6OZd2ePA7tpbW3HoyzeUDENw1 4w2vKVrQHFHJZ326/40XZgV1AhMAHkn+LEhN+RN9IqCao9hq5gMor+oUvj7IbOAO sb+xi5wh4JyUBcBI23BKMFp1Hs8o7cIWm19G65ydNRapFmLtAvaWeKpgvoYwK6gk wSEJgIN2qWbx3Z6wgB7Sh3Zz4ng8Md/mfgeuK6ljaNneBf9XdIPRAWMi2lr8fhjx 8KSGV+Zc3SfQzadXqGfXLzGtkRLbYD8Uai/4sCMqUGJKexkbrH5zQjpBTRujXlCI JL+mmx9DZmBHeWGX1hjENkACiPiwEQNt6DpEK05WmLxF7I1Uykow== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis Subject: [PULL 37/37] hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init() Date: Fri, 20 Jan 2023 17:39:13 +1000 Message-Id: <20230120073913.1028407-38-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674200682672100023 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Commit 1c20d3ff6004 ("hw/riscv: virt: Add a machine done notifier") moved the initialization of fw_cfg to the virt_machine_done() callback. Problem is that the validation of fw_cfg by devices such as ramfb is done before the machine done notifier is called. Moving create_fw_cfg() to machine_done() results in QEMU failing to boot when using a ramfb device: ./qemu-system-riscv64 -machine virt -device ramfb -serial stdio qemu-system-riscv64: -device ramfb: ramfb device requires fw_cfg with DMA The fix is simple: move create_fw_cfg() config back to virt_machine_init(). This happens to be the same way the ARM 'virt' machine deals with fw_cfg (see machvirt_init() and virt_machine_done() in hw/arm/virt.c), so we're keeping consistency with how other machines handle this device. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1343 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-Id: <20230117132751.229738-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e6d4f06e8d..4a11b4b010 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1254,13 +1254,6 @@ static void virt_machine_done(Notifier *notifier, vo= id *data) firmware_end_addr =3D riscv_find_and_load_firmware(machine, firmware_n= ame, start_addr, NULL); =20 - /* - * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the dev= ice - * tree cannot be altered and we get FDT_ERR_NOSPACE. - */ - s->fw_cfg =3D create_fw_cfg(machine); - rom_set_fw(s->fw_cfg); - if (drive_get(IF_PFLASH, 0, 1)) { /* * S-mode FW like EDK2 will be kept in second plash (unit 1). @@ -1468,6 +1461,13 @@ static void virt_machine_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, mask_rom); =20 + /* + * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the + * device tree cannot be altered and we get FDT_ERR_NOSPACE. + */ + s->fw_cfg =3D create_fw_cfg(machine); + rom_set_fw(s->fw_cfg); + /* SiFive Test MMIO device */ sifive_test_create(memmap[VIRT_TEST].base); =20 --=20 2.39.0