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a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1674136593; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1RDHtritFygm6eJnmEZlHYwe8MdQIdG1gDA8/PW8tH4=; b=v58GSH2LmXhVtBKCM1DTv1+wLrefsrXuumh1PxBwnanzVJchi62Hfs0XTz1wCVJJPdNZ5I rjK2VcjDBUXM0ADg== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf , Cornelia Huck Subject: [RFC PATCH v4 01/15] target/arm: Move 64-bit TCG CPUs into tcg/ Date: Thu, 19 Jan 2023 10:54:10 -0300 Message-Id: <20230119135424.5417-2-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230119135424.5417-1-farosas@suse.de> References: <20230119135424.5417-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:67c:2178:6::1d; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1674143327755100001 Content-Type: text/plain; charset="utf-8" Move the 64-bit CPUs that are TCG-only: - cortex-a35 - cortex-a55 - cortex-a72 - cortex-a76 - a64fx - neoverse-n1 Keep the CPUs that can be used with KVM: - cortex-a57 - cortex-a53 - max - host For the special case "max" CPU, there's a nuance that while KVM/HVF use the "host" model instead, we still cannot move all of the TCG code into the tcg directory because the qtests might reach the !kvm && !hvf branch. Keep the cortex_a57_initfn() call to cover that scenario. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 633 +---------------------------------- target/arm/internals.h | 4 + target/arm/tcg/cpu64.c | 654 +++++++++++++++++++++++++++++++++++++ target/arm/tcg/meson.build | 1 + 4 files changed, 671 insertions(+), 621 deletions(-) create mode 100644 target/arm/tcg/cpu64.c diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 5dfdae7bd2..226f57c669 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -24,6 +24,8 @@ #include "qemu/module.h" #include "sysemu/kvm.h" #include "sysemu/hvf.h" +#include "sysemu/qtest.h" +#include "sysemu/tcg.h" #include "kvm_arm.h" #include "hvf_arm.h" #include "qapi/visitor.h" @@ -31,86 +33,6 @@ #include "internals.h" #include "cpregs.h" =20 -static void aarch64_a35_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a35"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - - /* From B2.2 AArch64 identification registers. */ - cpu->midr =3D 0x411fd040; - cpu->revidr =3D 0; - cpu->ctr =3D 0x84448004; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_dfr0 =3D 0x03010066; - cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_aa64pfr0 =3D 0x00002222; - cpu->isar.id_aa64pfr1 =3D 0; - cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64dfr1 =3D 0; - cpu->isar.id_aa64isar0 =3D 0x00011120; - cpu->isar.id_aa64isar1 =3D 0; - cpu->isar.id_aa64mmfr0 =3D 0x00101122; - cpu->isar.id_aa64mmfr1 =3D 0; - cpu->clidr =3D 0x0a200023; - cpu->dcz_blocksize =3D 4; - - /* From B2.4 AArch64 Virtual Memory control registers */ - cpu->reset_sctlr =3D 0x00c50838; - - /* From B2.10 AArch64 performance monitor registers */ - cpu->isar.reset_pmcr_el0 =3D 0x410a3000; - - /* From B2.29 Cache ID registers */ - cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe00a; /* 32KB L1 icache */ - cpu->ccsidr[2] =3D 0x703fe03a; /* 512KB L2 cache */ - - /* From B3.5 VGIC Type register */ - cpu->gic_num_lrs =3D 4; - cpu->gic_vpribits =3D 5; - cpu->gic_vprebits =3D 5; - cpu->gic_pribits =3D 5; - - /* From C6.4 Debug ID Register */ - cpu->isar.dbgdidr =3D 0x3516d000; - /* From C6.5 Debug Device ID Register */ - cpu->isar.dbgdevid =3D 0x00110f13; - /* From C6.6 Debug Device ID Register 1 */ - cpu->isar.dbgdevid1 =3D 0x2; - - /* From Cortex-A35 SIMD and Floating-point Support r1p0 */ - /* From 3.2 AArch32 register summary */ - cpu->reset_fpsid =3D 0x41034043; - - /* From 2.2 AArch64 register summary */ - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x12111111; - cpu->isar.mvfr2 =3D 0x00000043; - - /* These values are the same with A53/A57/A72. */ - define_cortex_a72_a57_a53_cp_reginfo(cpu); -} - void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* @@ -310,47 +232,6 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) cpu->sve_vq.map =3D vq_map; } =20 -static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *na= me, - void *opaque, Error **errp) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - uint32_t value; - - /* All vector lengths are disabled when SVE is off. */ - if (!cpu_isar_feature(aa64_sve, cpu)) { - value =3D 0; - } else { - value =3D cpu->sve_max_vq; - } - visit_type_uint32(v, name, &value, errp); -} - -static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *na= me, - void *opaque, Error **errp) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - uint32_t max_vq; - - if (!visit_type_uint32(v, name, &max_vq, errp)) { - return; - } - - if (kvm_enabled() && !kvm_arm_sve_supported()) { - error_setg(errp, "cannot set sve-max-vq"); - error_append_hint(errp, "SVE not supported by KVM on this host\n"); - return; - } - - if (max_vq =3D=3D 0 || max_vq > ARM_MAX_VQ) { - error_setg(errp, "unsupported SVE vector length"); - error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n", - ARM_MAX_VQ); - return; - } - - cpu->sve_max_vq =3D max_vq; -} - /* * Note that cpu_arm_{get,set}_vq cannot use the simpler * object_property_add_bool interface because they make use of the @@ -541,7 +422,7 @@ static void cpu_arm_get_default_vec_len(Object *obj, Vi= sitor *v, } #endif =20 -static void aarch64_add_sve_properties(Object *obj) +void aarch64_add_sve_properties(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); uint32_t vq; @@ -564,7 +445,7 @@ static void aarch64_add_sve_properties(Object *obj) #endif } =20 -static void aarch64_add_sme_properties(Object *obj) +void aarch64_add_sme_properties(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); uint32_t vq; @@ -629,7 +510,7 @@ static Property arm_cpu_pauth_property =3D static Property arm_cpu_pauth_impdef_property =3D DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); =20 -static void aarch64_add_pauth_properties(Object *obj) +void aarch64_add_pauth_properties(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); =20 @@ -650,9 +531,6 @@ static void aarch64_add_pauth_properties(Object *obj) } } =20 -static Property arm_cpu_lpa2_property =3D - DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true); - void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { uint64_t t; @@ -787,316 +665,6 @@ static void aarch64_a53_initfn(Object *obj) define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 -static void aarch64_a55_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a55"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - - /* Ordered by B2.4 AArch64 registers by functional group */ - cpu->clidr =3D 0x82000023; - cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ - cpu->dcz_blocksize =3D 4; /* 64 bytes */ - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; - cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; - cpu->isar.id_aa64pfr0 =3D 0x0000000010112222ull; - cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_pfr2 =3D 0x00000011; - cpu->midr =3D 0x412FD050; /* r2p0 */ - cpu->revidr =3D 0; - - /* From B2.23 CCSIDR_EL1 */ - cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ - cpu->ccsidr[1] =3D 0x200fe01a; /* 32KB L1 icache */ - cpu->ccsidr[2] =3D 0x703fe07a; /* 512KB L2 cache */ - - /* From B2.96 SCTLR_EL3 */ - cpu->reset_sctlr =3D 0x30c50838; - - /* From B4.45 ICH_VTR_EL2 */ - cpu->gic_num_lrs =3D 4; - cpu->gic_vpribits =3D 5; - cpu->gic_vprebits =3D 5; - cpu->gic_pribits =3D 5; - - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x13211111; - cpu->isar.mvfr2 =3D 0x00000043; - - /* From D5.4 AArch64 PMU register summary */ - cpu->isar.reset_pmcr_el0 =3D 0x410b3000; -} - -static void aarch64_a72_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a72"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->midr =3D 0x410fd083; - cpu->revidr =3D 0x00000000; - cpu->reset_fpsid =3D 0x41034080; - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x12111111; - cpu->isar.mvfr2 =3D 0x00000043; - cpu->ctr =3D 0x8444c004; - cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_dfr0 =3D 0x03010066; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_aa64pfr0 =3D 0x00002222; - cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; - cpu->isar.id_aa64mmfr0 =3D 0x00001124; - cpu->isar.dbgdidr =3D 0x3516d000; - cpu->isar.dbgdevid =3D 0x01110f13; - cpu->isar.dbgdevid1 =3D 0x2; - cpu->isar.reset_pmcr_el0 =3D 0x41023000; - cpu->clidr =3D 0x0a200023; - cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ - cpu->ccsidr[2] =3D 0x707fe07a; /* 1MB L2 cache */ - cpu->dcz_blocksize =3D 4; /* 64 bytes */ - cpu->gic_num_lrs =3D 4; - cpu->gic_vpribits =3D 5; - cpu->gic_vprebits =3D 5; - cpu->gic_pribits =3D 5; - define_cortex_a72_a57_a53_cp_reginfo(cpu); -} - -static void aarch64_a76_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a76"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - - /* Ordered by B2.4 AArch64 registers by functional group */ - cpu->clidr =3D 0x82000023; - cpu->ctr =3D 0x8444C004; - cpu->dcz_blocksize =3D 4; - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; - cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; - cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ - cpu->isar.id_pfr2 =3D 0x00000011; - cpu->midr =3D 0x414fd0b1; /* r4p1 */ - cpu->revidr =3D 0; - - /* From B2.18 CCSIDR_EL1 */ - cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ - cpu->ccsidr[2] =3D 0x707fe03a; /* 512KB L2 cache */ - - /* From B2.93 SCTLR_EL3 */ - cpu->reset_sctlr =3D 0x30c50838; - - /* From B4.23 ICH_VTR_EL2 */ - cpu->gic_num_lrs =3D 4; - cpu->gic_vpribits =3D 5; - cpu->gic_vprebits =3D 5; - cpu->gic_pribits =3D 5; - - /* From B5.1 AdvSIMD AArch64 register summary */ - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x13211111; - cpu->isar.mvfr2 =3D 0x00000043; - - /* From D5.1 AArch64 PMU register summary */ - cpu->isar.reset_pmcr_el0 =3D 0x410b3000; -} - -static void aarch64_a64fx_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,a64fx"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->midr =3D 0x461f0010; - cpu->revidr =3D 0x00000000; - cpu->ctr =3D 0x86668006; - cpu->reset_sctlr =3D 0x30000180; - cpu->isar.id_aa64pfr0 =3D 0x0000000101111111; /* No RAS Extensions */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000000; - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408; - cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; - cpu->id_aa64afr0 =3D 0x0000000000000000; - cpu->id_aa64afr1 =3D 0x0000000000000000; - cpu->isar.id_aa64mmfr0 =3D 0x0000000000001122; - cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; - cpu->isar.id_aa64isar0 =3D 0x0000000010211120; - cpu->isar.id_aa64isar1 =3D 0x0000000000010001; - cpu->isar.id_aa64zfr0 =3D 0x0000000000000000; - cpu->clidr =3D 0x0000000080000023; - cpu->ccsidr[0] =3D 0x7007e01c; /* 64KB L1 dcache */ - cpu->ccsidr[1] =3D 0x2007e01c; /* 64KB L1 icache */ - cpu->ccsidr[2] =3D 0x70ffe07c; /* 8MB L2 cache */ - cpu->dcz_blocksize =3D 6; /* 256 bytes */ - cpu->gic_num_lrs =3D 4; - cpu->gic_vpribits =3D 5; - cpu->gic_vprebits =3D 5; - cpu->gic_pribits =3D 5; - - /* The A64FX supports only 128, 256 and 512 bit vector lengths */ - aarch64_add_sve_properties(obj); - cpu->sve_vq.supported =3D (1 << 0) /* 128bit */ - | (1 << 1) /* 256bit */ - | (1 << 3); /* 512bit */ - - cpu->isar.reset_pmcr_el0 =3D 0x46014040; - - /* TODO: Add A64FX specific HPC extension registers */ -} - -static void aarch64_neoverse_n1_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,neoverse-n1"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - - /* Ordered by B2.4 AArch64 registers by functional group */ - cpu->clidr =3D 0x82000023; - cpu->ctr =3D 0x8444c004; - cpu->dcz_blocksize =3D 4; - cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; - cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; - cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000020ull; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ - cpu->isar.id_pfr2 =3D 0x00000011; - cpu->midr =3D 0x414fd0c1; /* r4p1 */ - cpu->revidr =3D 0; - - /* From B2.23 CCSIDR_EL1 */ - cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ - cpu->ccsidr[2] =3D 0x70ffe03a; /* 1MB L2 cache */ - - /* From B2.98 SCTLR_EL3 */ - cpu->reset_sctlr =3D 0x30c50838; - - /* From B4.23 ICH_VTR_EL2 */ - cpu->gic_num_lrs =3D 4; - cpu->gic_vpribits =3D 5; - cpu->gic_vprebits =3D 5; - cpu->gic_pribits =3D 5; - - /* From B5.1 AdvSIMD AArch64 register summary */ - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x13211111; - cpu->isar.mvfr2 =3D 0x00000043; - - /* From D5.1 AArch64 PMU register summary */ - cpu->isar.reset_pmcr_el0 =3D 0x410c3000; -} - static void aarch64_host_initfn(Object *obj) { #if defined(CONFIG_KVM) @@ -1115,203 +683,26 @@ static void aarch64_host_initfn(Object *obj) #endif } =20 -/* -cpu max: if KVM is enabled, like -cpu host (best possible with this ho= st); - * otherwise, a CPU with as many features enabled as our emulation support= s. - * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; - * this only needs to handle 64 bits. - */ static void aarch64_max_initfn(Object *obj) { - ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t t; - uint32_t u; - if (kvm_enabled() || hvf_enabled()) { /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ aarch64_host_initfn(obj); - return; } =20 - /* '-cpu max' for TCG: we currently do this as "A57 with extra things"= */ - - aarch64_a57_initfn(obj); - - /* - * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a re= al - * one and try to apply errata workarounds or use impdef features we - * don't provide. - * An IMPLEMENTER field of 0 means "reserved for software use"; - * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers - * to see which features are present"; - * the VARIANT, PARTNUM and REVISION fields are all implementation - * defined and we choose to define PARTNUM just in case guest - * code needs to distinguish this QEMU CPU from other software - * implementations, though this shouldn't be needed. - */ - t =3D FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); - t =3D FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); - t =3D FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); - t =3D FIELD_DP64(t, MIDR_EL1, VARIANT, 0); - t =3D FIELD_DP64(t, MIDR_EL1, REVISION, 0); - cpu->midr =3D t; - - /* - * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,= LoUIS} - * are zero. - */ - u =3D cpu->clidr; - u =3D FIELD_DP32(u, CLIDR_EL1, LOUIS, 0); - u =3D FIELD_DP32(u, CLIDR_EL1, LOUU, 0); - cpu->clidr =3D u; - - t =3D cpu->isar.id_aa64isar0; - t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ - cpu->isar.id_aa64isar0 =3D t; - - t =3D cpu->isar.id_aa64isar1; - t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ - cpu->isar.id_aa64isar1 =3D t; - - t =3D cpu->isar.id_aa64pfr0; - t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ - t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ - t =3D FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT= _DoubleFault */ - t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ - t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ - t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ - t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ - cpu->isar.id_aa64pfr0 =3D t; - - t =3D cpu->isar.id_aa64pfr1; - t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ - t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ - /* - * Begin with full support for MTE. This will be downgraded to MTE=3D0 - * during realize if the board provides no tag memory, much like - * we do for EL2 with the virtualization=3Don property. - */ - t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ - t =3D FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT= _DoubleFault */ - t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ - t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ - cpu->isar.id_aa64pfr1 =3D t; - - t =3D cpu->isar.id_aa64mmfr0; - t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supporte= d */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 support= ed */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 support= ed */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 support= ed */ - cpu->isar.id_aa64mmfr0 =3D t; - - t =3D cpu->isar.id_aa64mmfr1; - t =3D FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ - cpu->isar.id_aa64mmfr1 =3D t; - - t =3D cpu->isar.id_aa64mmfr2; - t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2= */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ - cpu->isar.id_aa64mmfr2 =3D t; - - t =3D cpu->isar.id_aa64zfr0; - t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ - cpu->isar.id_aa64zfr0 =3D t; - - t =3D cpu->isar.id_aa64dfr0; - t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ - t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ - cpu->isar.id_aa64dfr0 =3D t; - - t =3D cpu->isar.id_aa64smfr0; - t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ - cpu->isar.id_aa64smfr0 =3D t; - - /* Replicate the same data to the 32-bit id registers. */ - aa32_max_features(cpu); - -#ifdef CONFIG_USER_ONLY - /* - * For usermode -cpu max we can use a larger and more efficient DCZ - * blocksize since we don't have to follow what the hardware does. - */ - cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ - cpu->dcz_blocksize =3D 7; /* 512 bytes */ -#endif - - cpu->sve_vq.supported =3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); - cpu->sme_vq.supported =3D SVE_VQ_POW2_MAP; + if (tcg_enabled() || qtest_enabled()) { + aarch64_a57_initfn(obj); + } =20 - aarch64_add_pauth_properties(obj); - aarch64_add_sve_properties(obj); - aarch64_add_sme_properties(obj); - object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_v= q, - cpu_max_set_sve_max_vq, NULL, NULL); - qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); + if (tcg_enabled()) { + /* '-cpu max' for TCG: we currently do this as "A57 with extra thi= ngs" */ + aarch64_max_tcg_initfn(obj); + } } =20 static const ARMCPUInfo aarch64_cpus[] =3D { - { .name =3D "cortex-a35", .initfn =3D aarch64_a35_initfn }, { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, - { .name =3D "cortex-a55", .initfn =3D aarch64_a55_initfn }, - { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, - { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, - { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, - { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, #if defined(CONFIG_KVM) || defined(CONFIG_HVF) { .name =3D "host", .initfn =3D aarch64_host_initfn }, diff --git a/target/arm/internals.h b/target/arm/internals.h index a8fb8aa363..72e3d2fef2 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1364,6 +1364,10 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); +void aarch64_max_tcg_initfn(Object *obj); +void aarch64_add_pauth_properties(Object *obj); +void aarch64_add_sve_properties(Object *obj); +void aarch64_add_sme_properties(Object *obj); #endif =20 bool el_is_in_host(CPUARMState *env, int el); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c new file mode 100644 index 0000000000..4d5bdddae4 --- /dev/null +++ b/target/arm/tcg/cpu64.c @@ -0,0 +1,654 @@ +/* + * QEMU AArch64 TCG CPUs + * + * Copyright (c) 2013 Linaro Ltd + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "cpu.h" +#include "qemu/module.h" +#include "qapi/visitor.h" +#include "hw/qdev-properties.h" +#include "internals.h" +#include "cpregs.h" + +static void aarch64_a35_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a35"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* From B2.2 AArch64 identification registers. */ + cpu->midr =3D 0x411fd040; + cpu->revidr =3D 0; + cpu->ctr =3D 0x84448004; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x03010066; + cpu->id_afr0 =3D 0; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x00011121; + cpu->isar.id_aa64pfr0 =3D 0x00002222; + cpu->isar.id_aa64pfr1 =3D 0; + cpu->isar.id_aa64dfr0 =3D 0x10305106; + cpu->isar.id_aa64dfr1 =3D 0; + cpu->isar.id_aa64isar0 =3D 0x00011120; + cpu->isar.id_aa64isar1 =3D 0; + cpu->isar.id_aa64mmfr0 =3D 0x00101122; + cpu->isar.id_aa64mmfr1 =3D 0; + cpu->clidr =3D 0x0a200023; + cpu->dcz_blocksize =3D 4; + + /* From B2.4 AArch64 Virtual Memory control registers */ + cpu->reset_sctlr =3D 0x00c50838; + + /* From B2.10 AArch64 performance monitor registers */ + cpu->isar.reset_pmcr_el0 =3D 0x410a3000; + + /* From B2.29 Cache ID registers */ + cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe00a; /* 32KB L1 icache */ + cpu->ccsidr[2] =3D 0x703fe03a; /* 512KB L2 cache */ + + /* From B3.5 VGIC Type register */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + + /* From C6.4 Debug ID Register */ + cpu->isar.dbgdidr =3D 0x3516d000; + /* From C6.5 Debug Device ID Register */ + cpu->isar.dbgdevid =3D 0x00110f13; + /* From C6.6 Debug Device ID Register 1 */ + cpu->isar.dbgdevid1 =3D 0x2; + + /* From Cortex-A35 SIMD and Floating-point Support r1p0 */ + /* From 3.2 AArch32 register summary */ + cpu->reset_fpsid =3D 0x41034043; + + /* From 2.2 AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + + /* These values are the same with A53/A57/A72. */ + define_cortex_a72_a57_a53_cp_reginfo(cpu); +} + +static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *na= me, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t value; + + /* All vector lengths are disabled when SVE is off. */ + if (!cpu_isar_feature(aa64_sve, cpu)) { + value =3D 0; + } else { + value =3D cpu->sve_max_vq; + } + visit_type_uint32(v, name, &value, errp); +} + +static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *na= me, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t max_vq; + + if (!visit_type_uint32(v, name, &max_vq, errp)) { + return; + } + + if (max_vq =3D=3D 0 || max_vq > ARM_MAX_VQ) { + error_setg(errp, "unsupported SVE vector length"); + error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n", + ARM_MAX_VQ); + return; + } + + cpu->sve_max_vq =3D max_vq; +} + +static Property arm_cpu_lpa2_property =3D + DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true); + +static void aarch64_a55_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a55"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr =3D 0x82000023; + cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ + cpu->dcz_blocksize =3D 4; /* 64 bytes */ + cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 =3D 0x0000000010112222ull; + cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_dfr0 =3D 0x04010088; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x01011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_mmfr4 =3D 0x00021110; + cpu->isar.id_pfr0 =3D 0x10010131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->midr =3D 0x412FD050; /* r2p0 */ + cpu->revidr =3D 0; + + /* From B2.23 CCSIDR_EL1 */ + cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x200fe01a; /* 32KB L1 icache */ + cpu->ccsidr[2] =3D 0x703fe07a; /* 512KB L2 cache */ + + /* From B2.96 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.45 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; + + /* From D5.4 AArch64 PMU register summary */ + cpu->isar.reset_pmcr_el0 =3D 0x410b3000; +} + +static void aarch64_a72_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a72"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x410fd083; + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034080; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x8444c004; + cpu->reset_sctlr =3D 0x00c50838; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x03010066; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x00011121; + cpu->isar.id_aa64pfr0 =3D 0x00002222; + cpu->isar.id_aa64dfr0 =3D 0x10305106; + cpu->isar.id_aa64isar0 =3D 0x00011120; + cpu->isar.id_aa64mmfr0 =3D 0x00001124; + cpu->isar.dbgdidr =3D 0x3516d000; + cpu->isar.dbgdevid =3D 0x01110f13; + cpu->isar.dbgdevid1 =3D 0x2; + cpu->isar.reset_pmcr_el0 =3D 0x41023000; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] =3D 0x707fe07a; /* 1MB L2 cache */ + cpu->dcz_blocksize =3D 4; /* 64 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + define_cortex_a72_a57_a53_cp_reginfo(cpu); +} + +static void aarch64_a76_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a76"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr =3D 0x82000023; + cpu->ctr =3D 0x8444C004; + cpu->dcz_blocksize =3D 4; + cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_dfr0 =3D 0x04010088; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x01011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_mmfr4 =3D 0x00021110; + cpu->isar.id_pfr0 =3D 0x10010131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->midr =3D 0x414fd0b1; /* r4p1 */ + cpu->revidr =3D 0; + + /* From B2.18 CCSIDR_EL1 */ + cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x707fe03a; /* 512KB L2 cache */ + + /* From B2.93 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; + + /* From D5.1 AArch64 PMU register summary */ + cpu->isar.reset_pmcr_el0 =3D 0x410b3000; +} + +static void aarch64_a64fx_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,a64fx"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x461f0010; + cpu->revidr =3D 0x00000000; + cpu->ctr =3D 0x86668006; + cpu->reset_sctlr =3D 0x30000180; + cpu->isar.id_aa64pfr0 =3D 0x0000000101111111; /* No RAS Extensions */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000000; + cpu->isar.id_aa64dfr0 =3D 0x0000000010305408; + cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; + cpu->id_aa64afr0 =3D 0x0000000000000000; + cpu->id_aa64afr1 =3D 0x0000000000000000; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000001122; + cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; + cpu->isar.id_aa64isar0 =3D 0x0000000010211120; + cpu->isar.id_aa64isar1 =3D 0x0000000000010001; + cpu->isar.id_aa64zfr0 =3D 0x0000000000000000; + cpu->clidr =3D 0x0000000080000023; + cpu->ccsidr[0] =3D 0x7007e01c; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x2007e01c; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe07c; /* 8MB L2 cache */ + cpu->dcz_blocksize =3D 6; /* 256 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + + /* The A64FX supports only 128, 256 and 512 bit vector lengths */ + aarch64_add_sve_properties(obj); + cpu->sve_vq.supported =3D (1 << 0) /* 128bit */ + | (1 << 1) /* 256bit */ + | (1 << 3); /* 512bit */ + + cpu->isar.reset_pmcr_el0 =3D 0x46014040; + + /* TODO: Add A64FX specific HPC extension registers */ +} + +static void aarch64_neoverse_n1_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,neoverse-n1"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr =3D 0x82000023; + cpu->ctr =3D 0x8444c004; + cpu->dcz_blocksize =3D 4; + cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000020ull; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_dfr0 =3D 0x04010088; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x01011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_mmfr4 =3D 0x00021110; + cpu->isar.id_pfr0 =3D 0x10010131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->midr =3D 0x414fd0c1; /* r4p1 */ + cpu->revidr =3D 0; + + /* From B2.23 CCSIDR_EL1 */ + cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe03a; /* 1MB L2 cache */ + + /* From B2.98 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; + + /* From D5.1 AArch64 PMU register summary */ + cpu->isar.reset_pmcr_el0 =3D 0x410c3000; +} + +/* + * -cpu max: a CPU with as many features enabled as our emulation supports. + * The version of '-cpu max' for qemu-system-arm is defined in cpu_tcg.c; + * this only needs to handle 64 bits. + */ +void aarch64_max_tcg_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + uint64_t t; + uint32_t u; + + /* + * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a re= al + * one and try to apply errata workarounds or use impdef features we + * don't provide. + * An IMPLEMENTER field of 0 means "reserved for software use"; + * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers + * to see which features are present"; + * the VARIANT, PARTNUM and REVISION fields are all implementation + * defined and we choose to define PARTNUM just in case guest + * code needs to distinguish this QEMU CPU from other software + * implementations, though this shouldn't be needed. + */ + t =3D FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); + t =3D FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); + t =3D FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); + t =3D FIELD_DP64(t, MIDR_EL1, VARIANT, 0); + t =3D FIELD_DP64(t, MIDR_EL1, REVISION, 0); + cpu->midr =3D t; + + /* + * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,= LoUIS} + * are zero. + */ + u =3D cpu->clidr; + u =3D FIELD_DP32(u, CLIDR_EL1, LOUIS, 0); + u =3D FIELD_DP32(u, CLIDR_EL1, LOUU, 0); + cpu->clidr =3D u; + + t =3D cpu->isar.id_aa64isar0; + t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ + cpu->isar.id_aa64isar0 =3D t; + + t =3D cpu->isar.id_aa64isar1; + t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ + cpu->isar.id_aa64isar1 =3D t; + + t =3D cpu->isar.id_aa64pfr0; + t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT= _DoubleFault */ + t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ + cpu->isar.id_aa64pfr0 =3D t; + + t =3D cpu->isar.id_aa64pfr1; + t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ + t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ + /* + * Begin with full support for MTE. This will be downgraded to MTE=3D0 + * during realize if the board provides no tag memory, much like + * we do for EL2 with the virtualization=3Don property. + */ + t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT= _DoubleFault */ + t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ + cpu->isar.id_aa64pfr1 =3D t; + + t =3D cpu->isar.id_aa64mmfr0; + t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supporte= d */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 support= ed */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 support= ed */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 support= ed */ + cpu->isar.id_aa64mmfr0 =3D t; + + t =3D cpu->isar.id_aa64mmfr1; + t =3D FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ + cpu->isar.id_aa64mmfr1 =3D t; + + t =3D cpu->isar.id_aa64mmfr2; + t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2= */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ + cpu->isar.id_aa64mmfr2 =3D t; + + t =3D cpu->isar.id_aa64zfr0; + t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); + t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ + cpu->isar.id_aa64zfr0 =3D t; + + t =3D cpu->isar.id_aa64dfr0; + t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ + t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ + cpu->isar.id_aa64dfr0 =3D t; + + t =3D cpu->isar.id_aa64smfr0; + t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ + cpu->isar.id_aa64smfr0 =3D t; + + /* Replicate the same data to the 32-bit id registers. */ + aa32_max_features(cpu); + +#ifdef CONFIG_USER_ONLY + /* + * For usermode -cpu max we can use a larger and more efficient DCZ + * blocksize since we don't have to follow what the hardware does. + */ + cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ + cpu->dcz_blocksize =3D 7; /* 512 bytes */ +#endif + + cpu->sve_vq.supported =3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); + cpu->sme_vq.supported =3D SVE_VQ_POW2_MAP; + + aarch64_add_pauth_properties(obj); + aarch64_add_sve_properties(obj); + aarch64_add_sme_properties(obj); + object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_v= q, + cpu_max_set_sve_max_vq, NULL, NULL); + qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); +} + +static const ARMCPUInfo aarch64_cpus[] =3D { + { .name =3D "cortex-a35", .initfn =3D aarch64_a35_initfn }, + { .name =3D "cortex-a55", .initfn =3D aarch64_a55_initfn }, + { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, + { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, + { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, + { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, +}; + +static void aarch64_cpu_register_types(void) +{ + size_t i; + + for (i =3D 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { + aarch64_cpu_register(&aarch64_cpus[i]); + } +} + +type_init(aarch64_cpu_register_types) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 25bc98999e..8debe81fd5 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -36,6 +36,7 @@ arm_ss.add(files( )) =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( + 'cpu64.c', 'translate-a64.c', 'translate-sve.c', 'translate-sme.c', --=20 2.35.3 From nobody Sat May 18 14:25:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1674136597; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ra1qat97EQPLudkBbHcze3B8+J/jBfibJTx/9Jf2oPk=; b=CmeqMOLt3Dh34k4MvQ+qUFBbZKSdV2JuN/xwEA16vRBXN+1yWaZUguAeF6cqfirJ0C6NdF k1sSxrvhqzdljWCg== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf , Cornelia Huck Subject: [RFC PATCH v4 02/15] target/arm: move cpu_tcg to tcg/cpu32.c Date: Thu, 19 Jan 2023 10:54:11 -0300 Message-Id: <20230119135424.5417-3-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230119135424.5417-1-farosas@suse.de> References: <20230119135424.5417-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.29; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1674143694200100003 Content-Type: text/plain; charset="utf-8" From: Claudio Fontana move the module containing cpu models definitions for 32bit TCG-only CPUs to tcg/ and rename it for clarity. Signed-off-by: Claudio Fontana Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson --- target/arm/meson.build | 1 - target/arm/{cpu_tcg.c =3D> tcg/cpu32.c} | 13 +++---------- target/arm/tcg/cpu64.c | 2 +- target/arm/tcg/meson.build | 1 + 4 files changed, 5 insertions(+), 12 deletions(-) rename target/arm/{cpu_tcg.c =3D> tcg/cpu32.c} (99%) diff --git a/target/arm/meson.build b/target/arm/meson.build index 595d22a099..88f1a5c570 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -5,7 +5,6 @@ arm_ss.add(files( 'gdbstub.c', 'helper.c', 'vfp_helper.c', - 'cpu_tcg.c', )) arm_ss.add(zlib) =20 diff --git a/target/arm/cpu_tcg.c b/target/arm/tcg/cpu32.c similarity index 99% rename from target/arm/cpu_tcg.c rename to target/arm/tcg/cpu32.c index 64d5a785c1..caa5252ad9 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/tcg/cpu32.c @@ -1,5 +1,5 @@ /* - * QEMU ARM TCG CPUs. + * QEMU ARM TCG-only CPUs. * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -10,9 +10,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" -#endif /* CONFIG_TCG */ #include "internals.h" #include "target/arm/idau.h" #if !defined(CONFIG_USER_ONLY) @@ -93,7 +91,7 @@ void aa32_max_features(ARMCPU *cpu) /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 -#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) +#if !defined(CONFIG_USER_ONLY) static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc =3D CPU_GET_CLASS(cs); @@ -117,7 +115,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, in= t interrupt_request) } return ret; } -#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ +#endif /* !CONFIG_USER_ONLY */ =20 static void arm926_initfn(Object *obj) { @@ -1013,7 +1011,6 @@ static void pxa270c5_initfn(Object *obj) cpu->reset_sctlr =3D 0x00000078; } =20 -#ifdef CONFIG_TCG static const struct TCGCPUOps arm_v7m_tcg_ops =3D { .initialize =3D arm_translate_init, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, @@ -1034,7 +1031,6 @@ static const struct TCGCPUOps arm_v7m_tcg_ops =3D { .debug_check_breakpoint =3D arm_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ }; -#endif /* CONFIG_TCG */ =20 static void arm_v7m_class_init(ObjectClass *oc, void *data) { @@ -1042,10 +1038,7 @@ static void arm_v7m_class_init(ObjectClass *oc, void= *data) CPUClass *cc =3D CPU_CLASS(oc); =20 acc->info =3D data; -#ifdef CONFIG_TCG cc->tcg_ops =3D &arm_v7m_tcg_ops; -#endif /* CONFIG_TCG */ - cc->gdb_core_xml_file =3D "arm-m-profile.xml"; } =20 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 4d5bdddae4..92943853ce 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -457,7 +457,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) =20 /* * -cpu max: a CPU with as many features enabled as our emulation supports. - * The version of '-cpu max' for qemu-system-arm is defined in cpu_tcg.c; + * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c; * this only needs to handle 64 bits. */ void aarch64_max_tcg_initfn(Object *obj) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 8debe81fd5..cea1e594c1 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -18,6 +18,7 @@ gen =3D [ arm_ss.add(gen) =20 arm_ss.add(files( + 'cpu32.c', 'translate.c', 'translate-m-nocp.c', 'translate-mve.c', --=20 2.35.3 From nobody Sat May 18 14:25:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1674136601; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vNdn5MPI5AOTr7lKP6lfdpZLD0+9Efs6p4/kTTR5bA4=; b=uORhP+lymcjMo+JaWPzYlr35Tx9uDN8M/ZLNbgvxHeq2v2yq558/01wsgM/sQYAfpuVibG GOz4VKkT7DY+ORCQ== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf , Cornelia Huck , Thomas Huth , Laurent Vivier Subject: [RFC PATCH v4 03/15] target/arm: Remove default cpu for KVM-only builds Date: Thu, 19 Jan 2023 10:54:12 -0300 Message-Id: <20230119135424.5417-4-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230119135424.5417-1-farosas@suse.de> References: <20230119135424.5417-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:67c:2178:6::1c; envelope-from=farosas@suse.de; helo=smtp-out1.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1674147886524100001 Content-Type: text/plain; charset="utf-8" We'd prefer if the user always had to specify the machine and cpu options in the command line instead of relying on defaults. Since the KVM build already doesn't work with the current default of cortex-a15, remove the default altogether for KVM builds. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson --- hw/arm/virt.c | 9 +++++++++ tests/qtest/arm-cpu-features.c | 12 +++++++++--- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ea2413a0ba..fa8baf3156 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -203,8 +203,10 @@ static const int a15irqmap[] =3D { }; =20 static const char *valid_cpus[] =3D { +#ifdef CONFIG_TCG ARM_CPU_TYPE_NAME("cortex-a7"), ARM_CPU_TYPE_NAME("cortex-a15"), +#endif ARM_CPU_TYPE_NAME("cortex-a35"), ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a55"), @@ -2025,6 +2027,11 @@ static void machvirt_init(MachineState *machine) unsigned int smp_cpus =3D machine->smp.cpus; unsigned int max_cpus =3D machine->smp.max_cpus; =20 + if (!machine->cpu_type) { + error_report("No -cpu specified, and there is no default"); + exit(1); + } + if (!cpu_type_valid(machine->cpu_type)) { error_report("mach-virt: CPU type %s not supported", machine->cpu_= type); exit(1); @@ -3003,7 +3010,9 @@ static void virt_machine_class_init(ObjectClass *oc, = void *data) mc->minimum_page_bits =3D 12; mc->possible_cpu_arch_ids =3D virt_possible_cpu_arch_ids; mc->cpu_index_to_instance_props =3D virt_cpu_index_to_props; +#ifdef CONFIG_TCG mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a15"); +#endif mc->get_default_cpu_node_id =3D virt_get_default_cpu_node_id; mc->kvm_type =3D virt_kvm_type; assert(!mc->get_hotplug_handler); diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index 8691802950..4ff2014bea 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -506,9 +506,15 @@ static void test_query_cpu_model_expansion_kvm(const v= oid *data) QDict *resp; char *error; =20 - assert_error(qts, "cortex-a15", - "We cannot guarantee the CPU type 'cortex-a15' works " - "with KVM on this host", NULL); + if (qtest_has_accel("tcg")) { + assert_error(qts, "cortex-a15", + "We cannot guarantee the CPU type 'cortex-a15' wo= rks " + "with KVM on this host", NULL); + } else { + assert_error(qts, "cortex-a15", + "The CPU type 'cortex-a15' is not a " + "recognized ARM CPU type", NULL); + } =20 assert_has_feature_enabled(qts, "host", "aarch64"); =20 --=20 2.35.3 From nobody Sat May 18 14:25:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=suse.de ARC-Seal: i=1; a=rsa-sha256; t=1674146070; cv=none; d=zohomail.com; s=zohoarc; b=burXk2wqo4fmlLE4iWNtUuqnY1XGVgnmpyxsuy8F/tVD7lgLFpRllaCjuJztI6dvkuxXJGQv/y9i/bU1epLunXZPKpu8wneJzfCAF5u1vl1q6z1KQ1TZY5kvf0L8gaOurZ/HOKcpJVi+gq1TLHcMJM4hBfsh96HDFtLhNKqGmyA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674146070; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.29; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1674146072192100009 Content-Type: text/plain; charset="utf-8" Signed-off-by: Fabiano Rosas Acked-by: Thomas Huth Reviewed-by: Richard Henderson --- tests/qtest/arm-cpu-features.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index 4ff2014bea..1555b0bab8 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -21,7 +21,7 @@ #define SVE_MAX_VQ 16 =20 #define MACHINE "-machine virt,gic-version=3Dmax -accel tcg " -#define MACHINE_KVM "-machine virt,gic-version=3Dmax -accel kvm -accel tcg= " +#define MACHINE_KVM "-machine virt,gic-version=3Dmax -accel kvm " #define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \ " 'arguments': { 'type': 'full', " #define QUERY_TAIL "}}" @@ -613,31 +613,39 @@ int main(int argc, char **argv) { g_test_init(&argc, &argv, NULL); =20 - qtest_add_data_func("/arm/query-cpu-model-expansion", - NULL, test_query_cpu_model_expansion); + if (qtest_has_accel("tcg")) { + qtest_add_data_func("/arm/query-cpu-model-expansion", + NULL, test_query_cpu_model_expansion); + } + + if (!g_str_equal(qtest_get_arch(), "aarch64")) { + goto out; + } =20 /* * For now we only run KVM specific tests with AArch64 QEMU in * order avoid attempting to run an AArch32 QEMU with KVM on * AArch64 hosts. That won't work and isn't easy to detect. */ - if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")= ) { + if (qtest_has_accel("kvm")) { /* * This tests target the 'host' CPU type, so register it only if * KVM is available. */ qtest_add_data_func("/arm/kvm/query-cpu-model-expansion", NULL, test_query_cpu_model_expansion_kvm); + + qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off", + NULL, sve_tests_sve_off_kvm); } =20 - if (g_str_equal(qtest_get_arch(), "aarch64")) { + if (qtest_has_accel("tcg")) { qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq= -8", NULL, sve_tests_sve_max_vq_8); qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off", NULL, sve_tests_sve_off); - qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off", - NULL, sve_tests_sve_off_kvm); } =20 +out: return g_test_run(); } --=20 2.35.3 From nobody Sat May 18 14:25:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1674136609; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pOHcxdY1LhPmAxt6QcRmCOJFL4WbnqEVMCoD9cJwpTA=; b=CGUaP/62tDPP6DugZZloOkD0nOe4mw9AnWYRNdZDNeCIcEKZXjggw63aPXrih6e3V+Xq5+ Dg5Fz0AlDO1Bf/Bg== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf , Cornelia Huck , Thomas Huth , Laurent Vivier Subject: [RFC PATCH v4 05/15] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG Date: Thu, 19 Jan 2023 10:54:14 -0300 Message-Id: <20230119135424.5417-6-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230119135424.5417-1-farosas@suse.de> References: <20230119135424.5417-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:67c:2178:6::1c; envelope-from=farosas@suse.de; helo=smtp-out1.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1674145250049100001 Content-Type: text/plain; charset="utf-8" These tests set -accel tcg, so restrict them to when TCG is present. Signed-off-by: Fabiano Rosas Acked-by: Richard Henderson Reviewed-by: Thomas Huth --- tests/qtest/meson.build | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 1af63f8bd2..9dd5c2de6e 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -204,8 +204,8 @@ qtests_arm =3D \ # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-tes= t unconditional qtests_aarch64 =3D \ (cpu !=3D 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) + = \ - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-= test'] : []) + \ - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-= swtpm-test'] : []) + \ + (config_all_devices.has_key('CONFIG_TCG') and config_all_devices.has_key= ('CONFIG_TPM_TIS_SYSBUS') ? \ + ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + = \ (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test'= , 'fuzz-xlnx-dp-test'] : []) + \ (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : [])= + \ ['arm-cpu-features', @@ -295,11 +295,15 @@ qtests =3D { 'tpm-crb-test': [io, tpmemu_files], 'tpm-tis-swtpm-test': [io, tpmemu_files, 'tpm-tis-util.c'], 'tpm-tis-test': [io, tpmemu_files, 'tpm-tis-util.c'], - 'tpm-tis-device-swtpm-test': [io, tpmemu_files, 'tpm-tis-util.c'], - 'tpm-tis-device-test': [io, tpmemu_files, 'tpm-tis-util.c'], 'vmgenid-test': files('boot-sector.c', 'acpi-utils.c'), } =20 +if config_all_devices.has_key('CONFIG_TCG') + qtests +=3D { 'tpm-tis-device-swtpm-test': [io, tpmemu_files, 'tpm-tis-= util.c'], + 'tpm-tis-device-test': [io, tpmemu_files, 'tpm-tis-util.c']= , } +endif + + gvnc =3D dependency('gvnc-1.0', required: false) if gvnc.found() qtests +=3D {'vnc-display-test': [gvnc]} --=20 2.35.3 From nobody Sat May 18 14:25:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1674136613; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6CmwGZPr+sEROw2OjOLTe6Bx+FJD/SCltpgT+RRPahk=; b=sHSc3urze9GKBSplZ6yge/8bqDgxR9vbGGYjoZEyV4Qj7f+kFvSxqboLIlCeMWSaw2xa1u kUqYUVxktgugm2Dg== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf , Cornelia Huck , Thomas Huth , Laurent Vivier Subject: [RFC PATCH v4 06/15] tests/qtest: Add qtest_get_machine_args Date: Thu, 19 Jan 2023 10:54:15 -0300 Message-Id: <20230119135424.5417-7-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230119135424.5417-1-farosas@suse.de> References: <20230119135424.5417-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:67c:2178:6::1c; envelope-from=farosas@suse.de; helo=smtp-out1.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1674145284258100001 Content-Type: text/plain; charset="utf-8" QEMU machines might not have a default value defined for the -cpu option. Add a custom init function that takes care of selecting the default cpu in case the test did not specify one. For the machines that do not have a default, the value MUST be provided by the test. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson --- tests/qtest/libqtest.c | 99 ++++++++++++++++++++++++++++++++++++++++++ tests/qtest/libqtest.h | 11 +++++ 2 files changed, 110 insertions(+) diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c index 5cb38f90da..db8a40f0c7 100644 --- a/tests/qtest/libqtest.c +++ b/tests/qtest/libqtest.c @@ -1265,8 +1265,57 @@ static bool qtest_is_old_versioned_machine(const cha= r *mname) struct MachInfo { char *name; char *alias; + char *default_cpu; }; =20 +static char *qtest_get_cpu_name(QString *type) +{ + QDict *response, *cpuinfo; + QList *list; + const QListEntry *p; + QObject *qobj; + QString *qstr; + QTestState *qts; + char *cname =3D NULL; + + qts =3D qtest_init("-machine none"); + response =3D qtest_qmp(qts, "{ 'execute': 'query-cpu-definitions' }"); + g_assert(response); + list =3D qdict_get_qlist(response, "return"); + + if (!list) { + /* Not all architectures implement query-cpu-definitions */ + goto out; + } + + for (p =3D qlist_first(list); p; p =3D qlist_next(p)) { + cpuinfo =3D qobject_to(QDict, qlist_entry_obj(p)); + g_assert(cpuinfo); + + qobj =3D qdict_get(cpuinfo, "typename"); + g_assert(qobj); + qstr =3D qobject_to(QString, qobj); + g_assert(qstr); + + if (g_str_equal(qstring_get_str(qstr), + qstring_get_str(type))) { + qobj =3D qdict_get(cpuinfo, "name"); + g_assert(qobj); + qstr =3D qobject_to(QString, qobj); + g_assert(qstr); + + cname =3D g_strdup(qstring_get_str(qstr)); + break; + } + } + +out: + qtest_quit(qts); + qobject_unref(response); + + return cname; +} + /* * Returns an array with pointers to the available machine names. * The terminating entry has the name set to NULL. @@ -1312,6 +1361,15 @@ static struct MachInfo *qtest_get_machines(void) } else { machines[idx].alias =3D NULL; } + + qobj =3D qdict_get(minfo, "default-cpu-type"); + if (qobj) { /* The default cpu is option= al */ + qstr =3D qobject_to(QString, qobj); + g_assert(qstr); + machines[idx].default_cpu =3D qtest_get_cpu_name(qstr); + } else { + machines[idx].default_cpu =3D NULL; + } } =20 qtest_quit(qts); @@ -1321,6 +1379,47 @@ static struct MachInfo *qtest_get_machines(void) return machines; } =20 +static const char *qtest_get_default_cpu(const char* machine) +{ + struct MachInfo *machines; + char *cpu =3D NULL; + int i; + + if (g_str_equal(machine, "none")) { + return cpu; + } + + machines =3D qtest_get_machines(); + + for (i =3D 0; machines[i].name !=3D NULL; i++) { + if (g_str_equal(machines[i].name, machine)) { + cpu =3D machines[i].default_cpu; + break; + } + } + + return cpu; +} + +char *qtest_get_machine_args(const char *mname, const char *cname, + const char *extra_args) +{ + const char *cpu; + + cpu =3D cname ?: qtest_get_default_cpu(mname); + if (!cpu) { + /* + * There is no default cpu and the test did not provide a cpu + * name for this architecture/machine combination. The QEMU + * binary might still know how to select a cpu, so leave the + * -cpu option out. + */ + return g_strdup_printf("-machine %s %s", mname, extra_args ?: ""); + } + return g_strdup_printf("-machine %s -cpu %s %s", mname, cpu, + extra_args ?: ""); +} + void qtest_cb_for_every_machine(void (*cb)(const char *machine), bool skip_old_versioned) { diff --git a/tests/qtest/libqtest.h b/tests/qtest/libqtest.h index fcf1c3c3b3..f86f876c17 100644 --- a/tests/qtest/libqtest.h +++ b/tests/qtest/libqtest.h @@ -75,6 +75,17 @@ QTestState *qtest_init_without_qmp_handshake(const char = *extra_args); */ QTestState *qtest_init_with_serial(const char *extra_args, int *sock_fd); =20 +/** + * qtest_get_machine_args: + * @mname: the machine name. + * @cname: the cpu name. + * @extra_args: other arguments to concatenated in the args string. + * + * Returns: pointer to args. + */ +char *qtest_get_machine_args(const char *mname, const char *cname, + const char *extra_args); + /** * qtest_wait_qemu: * @s: #QTestState instance to operate on. --=20 2.35.3 From nobody Sat May 18 14:25:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 19 Jan 2023 13:56:57 +0000 (UTC) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id D118D134F5; Thu, 19 Jan 2023 13:56:53 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id 0OMhJSVMyWOCFAAAMHmgww (envelope-from ); Thu, 19 Jan 2023 13:56:53 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1674136617; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lxrWaE16yozIzsy6MYwQ2ElnYdRKzu+lkQhgFbpYZCs=; b=NlRRNdGAvSOg6zR76ssvfseWB89iZx3hK7Ot12ezt/RrypwCfxVM07eempfSN/1B6BHYSl oNj11537Lfsc6nHonWNYqubX1ZL1lK9Tfwqj41ki2PJJDnHihNug+3uONhsFxuumvKtgB5 plajpx8dfQmFy5IyyKpYNzR1o69CyCU= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1674136617; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lxrWaE16yozIzsy6MYwQ2ElnYdRKzu+lkQhgFbpYZCs=; b=3syI/HaJ3PkKJOQyQY9hlyKStjMYczEkIgbNbxq/f43izSdTFscuiaEsVMupxq04zbOkEp NyoYd20DfqabmjBA== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf , Cornelia Huck , Thomas Huth , Laurent Vivier Subject: [RFC PATCH v4 07/15] tests/qtest: Adjust qom-test to always set a -cpu option Date: Thu, 19 Jan 2023 10:54:16 -0300 Message-Id: <20230119135424.5417-8-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230119135424.5417-1-farosas@suse.de> References: <20230119135424.5417-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.28; envelope-from=farosas@suse.de; helo=smtp-out1.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1674144850983100001 Content-Type: text/plain; charset="utf-8" Start using the qtest_get_machine_args function, which explicitly sets the -cpu option according to the machine default. Signed-off-by: Fabiano Rosas --- tests/qtest/qom-test.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/tests/qtest/qom-test.c b/tests/qtest/qom-test.c index d380261f8f..462e3c4281 100644 --- a/tests/qtest/qom-test.c +++ b/tests/qtest/qom-test.c @@ -78,14 +78,28 @@ static void test_properties(QTestState *qts, const char= *path, bool recurse) qobject_unref(response); } =20 +static const char *arch_get_cpu(const char *machine) +{ + const char *arch =3D qtest_get_arch(); + + if (g_str_equal(arch, "aarch64")) { + if (!strncmp(machine, "virt", 4)) { + return "cortex-a57"; + } + } + + return NULL; +} + static void test_machine(gconstpointer data) { const char *machine =3D data; + char *args; QDict *response; QTestState *qts; =20 - qts =3D qtest_initf("-machine %s", machine); - + args =3D qtest_get_machine_args(machine, arch_get_cpu(machine), NULL); + qts =3D qtest_init(args); test_properties(qts, "/machine", true); =20 response =3D qtest_qmp(qts, "{ 'execute': 'quit' }"); @@ -94,6 +108,7 @@ static void test_machine(gconstpointer data) =20 qtest_quit(qts); g_free((void *)machine); + g_free((void *)args); } =20 static void add_machine_test_case(const char *mname) --=20 2.35.3 From nobody Sat May 18 14:25:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=suse.de ARC-Seal: i=1; a=rsa-sha256; t=1674143715; cv=none; d=zohomail.com; s=zohoarc; b=G0us5FKX+iRKjktbSY3RrAZEYco0FERAuAOfc8v7xRm4BYNUOuBWE8Mx8PkmmbT7UkIPXdq/kmmV6sP38nd8yG61ffyN2c4M4TgGGixzVlXr2NVarfLlFOJqw6GiI63xQ5pBx0461NF40VW+CS61SGK5Qfoeq8164P/v5f0gk9Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674143715; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jVIAoajRUGSfIyuCmuIYwLpNRsCSx50sO+LkAUTEiBQ=; b=b47EtG+3hHfdBHb7Q1kuWl1Rvud7VOQIAiPSxNMZG8JpGdOxQOy5mc8Pkr1JBXNnLwoTpc 5hhdtND/mGDtATABmWoaO13RHVbQ51wLG9cW2lE0SDcV9TOppKSSJHqqq8zQlvNpR0ErqM RrblfZKPI/6OlwYgtR3V4kc8XYNSC1I= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1674136621; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jVIAoajRUGSfIyuCmuIYwLpNRsCSx50sO+LkAUTEiBQ=; b=Ufvsker160jzUSC9OqfDZqBGmOVMgrlzw4DkAtb3a99EteIAGOLz4Av5fMTEEMaFy2eDdY j/ER5pTj5bfnU/Dw== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf , Cornelia Huck , "Dr. David Alan Gilbert" , Thomas Huth , Laurent Vivier Subject: [RFC PATCH v4 08/15] tests/qtest: Adjust test-hmp to always pass -cpu option Date: Thu, 19 Jan 2023 10:54:17 -0300 Message-Id: <20230119135424.5417-9-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230119135424.5417-1-farosas@suse.de> References: <20230119135424.5417-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:67c:2178:6::1d; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1674143715714100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Fabiano Rosas --- tests/qtest/test-hmp.c | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/tests/qtest/test-hmp.c b/tests/qtest/test-hmp.c index f8b22abe4c..c367612d4a 100644 --- a/tests/qtest/test-hmp.c +++ b/tests/qtest/test-hmp.c @@ -121,21 +121,49 @@ static void test_info_commands(QTestState *qts) g_free(info_buf); } =20 +static const char *arch_get_cpu(const char *machine) +{ + const char *arch =3D qtest_get_arch(); + + if (g_str_equal(arch, "aarch64")) { + if (!strncmp(machine, "virt", 4)) { + return "cortex-a57"; + } + } + + return NULL; +} + static void test_machine(gconstpointer data) { const char *machine =3D data; char *args; QTestState *qts; =20 - args =3D g_strdup_printf("-S -M %s", machine); + args =3D qtest_get_machine_args(machine, arch_get_cpu(machine), "-S"); qts =3D qtest_init(args); =20 test_info_commands(qts); test_commands(qts); =20 qtest_quit(qts); - g_free(args); g_free((void *)data); + g_free((void *)args); +} + +static void test_none_with_memory(void) +{ + QTestState *qts; + char *args; + + args =3D qtest_get_machine_args("none", NULL, "-S -m 2"); + qts =3D qtest_init(args); + + test_info_commands(qts); + test_commands(qts); + + qtest_quit(qts); + g_free((void *)args); } =20 static void add_machine_test_case(const char *mname) @@ -160,7 +188,7 @@ int main(int argc, char **argv) qtest_cb_for_every_machine(add_machine_test_case, g_test_quick()); =20 /* as none machine has no memory by default, add a test case with memo= ry */ - qtest_add_data_func("hmp/none+2MB", g_strdup("none -m 2"), test_machin= e); + qtest_add_func("hmp/none+2MB", test_none_with_memory); =20 return g_test_run(); } --=20 2.35.3 From nobody Sat May 18 14:25:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=suse.de ARC-Seal: i=1; a=rsa-sha256; t=1674146135; cv=none; d=zohomail.com; s=zohoarc; b=M6vmltFBX41KmXEp97S0oFjo2WYCMg7bhXQjubYc+cHZa5e6xn2ZreOIup+Ol4P+QHTa6zEPRv9D8wJyCyXOFDMjOu1ajppi6q5Ncd59T3Cn1P3JcFR1/CkRQlJMMCbHsZMdXoJYxiYgHb1zuF2gzKNZRChGDfDv1n4HvphOahk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674146135; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:67c:2178:6::1d; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1674146136748100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Fabiano Rosas --- tests/qtest/device-introspect-test.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/tests/qtest/device-introspect-test.c b/tests/qtest/device-intr= ospect-test.c index 5b0ffe43f5..7d6ff6e3ef 100644 --- a/tests/qtest/device-introspect-test.c +++ b/tests/qtest/device-introspect-test.c @@ -304,17 +304,30 @@ static void test_abstract_interfaces(void) qtest_quit(qts); } =20 +static const char *arch_get_cpu(const char *mname) +{ + const char *arch =3D qtest_get_arch(); + + if (g_str_equal(arch, "aarch64")) { + if (!strncmp(mname, "virt", 4)) { + return "cortex-a57"; + } + } + + return NULL; +} + static void add_machine_test_case(const char *mname) { char *path, *args; =20 path =3D g_strdup_printf("device/introspect/concrete/defaults/%s", mna= me); - args =3D g_strdup_printf("-M %s", mname); + args =3D qtest_get_machine_args(mname, arch_get_cpu(mname), NULL); qtest_add_data_func(path, args, test_device_intro_concrete); g_free(path); =20 path =3D g_strdup_printf("device/introspect/concrete/nodefaults/%s", m= name); - args =3D g_strdup_printf("-nodefaults -M %s", mname); + args =3D qtest_get_machine_args(mname, arch_get_cpu(mname), "-nodefaul= ts"); qtest_add_data_func(path, args, test_device_intro_concrete); g_free(path); } --=20 2.35.3 From nobody Sat May 18 14:25:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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Thu, 19 Jan 2023 13:57:09 +0000 (UTC) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 00E03134F5; Thu, 19 Jan 2023 13:57:05 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id KLH4LTFMyWOCFAAAMHmgww (envelope-from ); Thu, 19 Jan 2023 13:57:05 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1674136629; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SoROsn94cX/HEtXMIBdno9N1fGnMg0pFEZJS8bDdoF4=; b=CgcSH5tbldlyc+scsiaiuX+nNTSzWszsN6AVnQw0l363vuI0tnWS36WFEjl2lCYipo7bhe tpmxMTcEoXP2cWl310Z7prCyuaAgoFhfHdALz9p1knDpfZnUp3btwuO8cjxLdMCf9u7jMU RItv3bMGrvxw4o40+mPjNXpDCLlEKEA= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1674136629; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SoROsn94cX/HEtXMIBdno9N1fGnMg0pFEZJS8bDdoF4=; b=hOkEjj6FiQvOg0CAjPj7CPH68UJxSPWxrnwKwraK1+PLksQKKMNeJhSuZWpo7KCxhnj1EG 05s9wLvgjTuNpqCw== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf , Cornelia Huck , Thomas Huth , Laurent Vivier Subject: [RFC PATCH v4 10/15] tests/qtest: aarch64: Set -cpu for numa-test Date: Thu, 19 Jan 2023 10:54:19 -0300 Message-Id: <20230119135424.5417-11-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230119135424.5417-1-farosas@suse.de> References: <20230119135424.5417-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.29; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1674153366003100001 Content-Type: text/plain; charset="utf-8" The aarch64 KVM-only builds no longer have a default cpu. We need to explicitly give one in the command line. Signed-off-by: Fabiano Rosas --- tests/qtest/numa-test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c index c5eb13f349..7a6cf17b2a 100644 --- a/tests/qtest/numa-test.c +++ b/tests/qtest/numa-test.c @@ -559,6 +559,7 @@ int main(int argc, char **argv) =20 if (g_str_equal(arch, "aarch64")) { g_string_append(args, " -machine virt"); + g_string_append(args, " -cpu cortex-a57"); } =20 g_test_init(&argc, &argv, NULL); --=20 2.35.3 From nobody Sat May 18 14:25:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=suse.de ARC-Seal: i=1; a=rsa-sha256; t=1674154322; cv=none; d=zohomail.com; s=zohoarc; b=KmXISbftqSVuV+vNQd+F+lVhfuJFZmpVQHa7fEUpSErAXWyEHbq8l9xAzA3mjNQMVSvwrqwGIZx8SqgYRgE49DgqRqPniBUtleVulNFPe/Gmbk7Ld/LJ+YjzYINnZ1guut8pvBelLWT1pXztF28F1h+JJlcUGS+HPkau7mcoiGM= ARC-Message-Signature: i=1; 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Thu, 19 Jan 2023 13:57:09 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id GLIPMDVMyWOCFAAAMHmgww (envelope-from ); Thu, 19 Jan 2023 13:57:09 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1674136633; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=h4d91xynMc5IIw1RU4/KLmHgzvnhALzMPZPXiX5/5wA=; b=XSQYS8nIX8qWFSfewC1zP9Yqwd+CDsgo/bqVNUsaA39TNuy94Fhrwsfe2Jsn5lO440DawY 7wxsdZ2V6UcK0qFpW9JpYIpdPAwzO+nNqsSK+gxKJrCyvxSg7VDIoKfPekWfG3H6wcPRMy aAO6Upfh43ui7AWi9OGH7+r+yCqKCkM= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1674136633; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=h4d91xynMc5IIw1RU4/KLmHgzvnhALzMPZPXiX5/5wA=; b=kqgHQaBmmAFcN7sLN9r8R5tDoGrsQ7ICzPcmPkE/425yC7pyY/NAm2KdygxYJmYeAFdMDB 8k09tKI6aPb3MdDw== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf , Cornelia Huck , Kevin Wolf , Hanna Reitz Subject: [RFC PATCH v4 11/15] tests/qemu-iotests: Allow passing a -cpu option in the QEMU cmdline Date: Thu, 19 Jan 2023 10:54:20 -0300 Message-Id: <20230119135424.5417-12-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230119135424.5417-1-farosas@suse.de> References: <20230119135424.5417-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.28; envelope-from=farosas@suse.de; helo=smtp-out1.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1674154324867100003 Content-Type: text/plain; charset="utf-8" We're removing the default CPU from aarch64. Every QEMU invocation is expected to have an explicit -cpu value. Signed-off-by: Fabiano Rosas --- tests/qemu-iotests/testenv.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tests/qemu-iotests/testenv.py b/tests/qemu-iotests/testenv.py index a864c74b12..4bb80ea656 100644 --- a/tests/qemu-iotests/testenv.py +++ b/tests/qemu-iotests/testenv.py @@ -244,6 +244,13 @@ def __init__(self, imgfmt: str, imgproto: str, aiomode= : str, if self.qemu_prog.endswith(f'qemu-system-{suffix}'): self.qemu_options +=3D f' -machine {machine}' =20 + cpu_map =3D ( + ('aarch64', 'cortex-a57'), + ) + for suffix, cpu in cpu_map: + if self.qemu_prog.endswith(f'qemu-system-{suffix}'): + self.qemu_options +=3D f' -cpu {cpu}' + # QEMU_DEFAULT_MACHINE self.qemu_default_machine =3D get_default_machine(self.qemu_prog) =20 --=20 2.35.3 From nobody Sat May 18 14:25:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 19 Jan 2023 13:57:17 +0000 (UTC) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 09AAE134F5; Thu, 19 Jan 2023 13:57:13 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id 4HIiMDlMyWOCFAAAMHmgww (envelope-from ); Thu, 19 Jan 2023 13:57:13 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1674136637; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+ek2plUhT6cYZ08vwAGsINrJigng7r+gmkaUGahZEZ4=; b=ih3ztUW1ikhb6FhBu3jtUr1uO3nJluculKz5WXHzU7pRVyM3wzr4dSfLEsZUhHjB6bngcO Dq7mPPobB/DUzhBkECQOYzkcBRVC8BeRsSifUCJxnGnf0ExgMtVwb9wDQolSijg+AAH9RF nhNo8j+OdZQahZ+ZvhbzkmgW6PUUwxQ= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1674136637; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+ek2plUhT6cYZ08vwAGsINrJigng7r+gmkaUGahZEZ4=; b=zxmSc2sCO18Cx0GcWlXwZdGzXetXooAlNBUZwrkjvE4wcaFwaIPe47c+U4MdoDe2uMR5Dn 5jVbN8HOElpKkEDg== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf , Cornelia Huck , Thomas Huth Subject: [RFC PATCH v4 12/15] tests/tcg: Do not build/run TCG tests if TCG is disabled Date: Thu, 19 Jan 2023 10:54:21 -0300 Message-Id: <20230119135424.5417-13-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230119135424.5417-1-farosas@suse.de> References: <20230119135424.5417-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.28; envelope-from=farosas@suse.de; helo=smtp-out1.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1674145455252100003 Content-Type: text/plain; charset="utf-8" The tests under tests/tcg depend on the TCG accelerator. Do not build them if --disable-tcg was given in the configure line. Signed-off-by: Fabiano Rosas Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- configure | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/configure b/configure index 9e407ce2e3..64960c6000 100755 --- a/configure +++ b/configure @@ -2483,7 +2483,11 @@ for target in $target_list; do tcg_tests_targets=3D"$tcg_tests_targets $target" fi done -echo "TCG_TESTS_TARGETS=3D$tcg_tests_targets" >> config-host.mak) + +if test "$tcg" =3D "enabled"; then + echo "TCG_TESTS_TARGETS=3D$tcg_tests_targets" >> config-host.mak +fi +) =20 if test "$skip_meson" =3D no; then cross=3D"config-meson.cross.new" --=20 2.35.3 From nobody Sat May 18 14:25:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=suse.de ARC-Seal: i=1; a=rsa-sha256; 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Thu, 19 Jan 2023 13:57:17 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id CALcIz1MyWOCFAAAMHmgww (envelope-from ); Thu, 19 Jan 2023 13:57:17 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1674136641; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9ssIovT5K/V/p+0ZYlWssPZdHDeOwPRIwfvvL6OqWME=; b=cDsylV+noth70jWTPFQIiYYcTBbVoiPzRR/MIxb761PrbSeAm8xTUzjVuBKY+qJabDBJjY F+L2odGvl6g9WObmGdoZuAGktdKrDn8gQtzsMm42TkMFPLPA3BSy50yR6DAo7/p3BGI9kd EdQqPVcOFmAEzYrcx2AHhj3QUlGCm24= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1674136641; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9ssIovT5K/V/p+0ZYlWssPZdHDeOwPRIwfvvL6OqWME=; b=xFER7pINKsIp67uZXj8mf67F24VKh3YreLp71hgMaGazvheKDyzUeaL/DTLNN/802tm590 6VqtrlI8PnGVSAAA== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf , Cornelia Huck , Cleber Rosa , Wainer dos Santos Moschetta , Beraldo Leal Subject: [RFC PATCH v4 13/15] target/avocado: Pass parameters to migration test on aarch64 Date: Thu, 19 Jan 2023 10:54:22 -0300 Message-Id: <20230119135424.5417-14-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230119135424.5417-1-farosas@suse.de> References: <20230119135424.5417-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:67c:2178:6::1d; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1674137423253100001 Content-Type: text/plain; charset="utf-8" The migration tests are currently broken for an aarch64 host because the tests pass no 'machine' and 'cpu' options on the QEMU command line. Most other architectures define a default value in QEMU for these options, but arm does not. Add these options to the test class in case the test is being executed in an aarch64 host. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson --- Don't we want to run migration tests for all the built targets? A cleaner approach would be to just subclass Migration for each archictecture like in boot_linux.py. --- tests/avocado/migration.py | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/tests/avocado/migration.py b/tests/avocado/migration.py index 4b25680c50..f1c43622c0 100644 --- a/tests/avocado/migration.py +++ b/tests/avocado/migration.py @@ -11,6 +11,8 @@ =20 =20 import tempfile +import os + from avocado_qemu import QemuSystemTest from avocado import skipUnless =20 @@ -26,6 +28,14 @@ class Migration(QemuSystemTest): =20 timeout =3D 10 =20 + def setUp(self): + super().setUp() + + arch =3D os.uname()[4] + if arch =3D=3D 'aarch64': + self.machine =3D 'virt' + self.cpu =3D 'max' + @staticmethod def migration_finished(vm): return vm.command('query-migrate')['status'] in ('completed', 'fai= led') @@ -62,7 +72,6 @@ def _get_free_port(self): self.cancel('Failed to find a free port') return port =20 - def test_migration_with_tcp_localhost(self): dest_uri =3D 'tcp:localhost:%u' % self._get_free_port() self.do_migrate(dest_uri) --=20 2.35.3 From nobody Sat May 18 14:25:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 19 Jan 2023 13:57:25 +0000 (UTC) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 13CC2134F5; Thu, 19 Jan 2023 13:57:21 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id GGZjMkFMyWOCFAAAMHmgww (envelope-from ); Thu, 19 Jan 2023 13:57:21 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1674136645; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AuqrwC97+9Z1Th4V0AydpH0eXGT097zQTCDCeGSE7aQ=; b=EsBz738q6x9qqSp9tcKqH1Pnp6wdqj+EWPM38WJ7Wf2zes19bV1zWN1+ms5muyB4GfeC1G 4/JRfKA8rCE64PhOwRYfx6+u17SY1nQ5zHow1lLEO9j4Z81RVgWBvzRrpxIuf/D9ldkqhP x6KIkBOedP0b8JJjoj5MU6Anw12FCaM= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1674136645; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AuqrwC97+9Z1Th4V0AydpH0eXGT097zQTCDCeGSE7aQ=; b=mYrT/UPT5poGHFzAmXD0Y5oiCo1qnIthekz+ggXtTUDuYw0nY5YPQjnpLZ9kkNfoopts81 MI5I+R1Z6i8yoECA== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf , Cornelia Huck Subject: [RFC PATCH v4 14/15] arm/Kconfig: Always select SEMIHOSTING when TCG is present Date: Thu, 19 Jan 2023 10:54:23 -0300 Message-Id: <20230119135424.5417-15-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230119135424.5417-1-farosas@suse.de> References: <20230119135424.5417-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:67c:2178:6::1d; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1674142374334100001 Content-Type: text/plain; charset="utf-8" We are about to enable the build without TCG, so CONFIG_SEMIHOSTING and CONFIG_ARM_COMPATIBLE_SEMIHOSTING cannot be unconditionally set in default.mak anymore. So reflect the change in a Kconfig. Instead of using semihosting/Kconfig, use a target-specific file, so that the change doesn't affect other architectures which might implement semihosting in a way compatible with KVM. The selection from ARM_v7M needs to be removed to avoid a cycle during parsing. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson --- The linux-user build does not use Kconfig. Is it worth it to add support to it? There's just the semihosting config so far. --- configs/devices/arm-softmmu/default.mak | 2 -- hw/arm/Kconfig | 1 - target/arm/Kconfig | 7 +++++++ 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-= softmmu/default.mak index 1b49a7830c..cb3e5aea65 100644 --- a/configs/devices/arm-softmmu/default.mak +++ b/configs/devices/arm-softmmu/default.mak @@ -40,6 +40,4 @@ CONFIG_MICROBIT=3Dy CONFIG_FSL_IMX25=3Dy CONFIG_FSL_IMX7=3Dy CONFIG_FSL_IMX6UL=3Dy -CONFIG_SEMIHOSTING=3Dy -CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy CONFIG_ALLWINNER_H3=3Dy diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 19d6b9d95f..e0da8841db 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -316,7 +316,6 @@ config ARM_V7M # currently v7M must be included in a TCG build due to translate.c default y if TCG && (ARM || AARCH64) select PTIMER - select ARM_COMPATIBLE_SEMIHOSTING =20 config ALLWINNER_A10 bool diff --git a/target/arm/Kconfig b/target/arm/Kconfig index 3f3394a22b..39f05b6420 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -4,3 +4,10 @@ config ARM config AARCH64 bool select ARM + +# This config exists just so we can make SEMIHOSTING default when TCG +# is selected without also changing it for other architectures. +config ARM_SEMIHOSTING + bool + default y if TCG && ARM + select ARM_COMPATIBLE_SEMIHOSTING --=20 2.35.3 From nobody Sat May 18 14:25:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1674136648; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LgAAk/tLn57Rj5xG8Js8OUtSbZPEhStqL3FDCZ22ceY=; b=FsygTZRgq12YOScJV+KGntLrB2YJUYq/3cUwIEzwzvnSfAFBTzR+MuMzjeWbjITuUj0Pae zmDZlWMAqrhAGNCg== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf , Cornelia Huck Subject: [RFC PATCH v4 15/15] arm/Kconfig: Do not build TCG-only boards on a KVM-only build Date: Thu, 19 Jan 2023 10:54:24 -0300 Message-Id: <20230119135424.5417-16-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230119135424.5417-1-farosas@suse.de> References: <20230119135424.5417-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:67c:2178:6::1d; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1674146007819100003 Content-Type: text/plain; charset="utf-8" Move all the CONFIG_FOO=3Dy from default.mak into "default y if TCG" statements in Kconfig. That way they won't be selected when CONFIG_TCG=3Dn. I'm leaving CONFIG_ARM_VIRT in default.mak because it allows us to keep the two default.mak files not empty and keep aarch64-default.mak including arm-default.mak. That way we don't surprise anyone that's used to altering these files. With this change we can start building with --disable-tcg. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson --- sbsa-ref has an explicit check to avoid running with KVM xlnx-versal-virt has avocado tests tagged with tcg --- configs/devices/aarch64-softmmu/default.mak | 4 -- configs/devices/arm-softmmu/default.mak | 37 ------------------ hw/arm/Kconfig | 42 ++++++++++++++++++++- 3 files changed, 41 insertions(+), 42 deletions(-) diff --git a/configs/devices/aarch64-softmmu/default.mak b/configs/devices/= aarch64-softmmu/default.mak index cf43ac8da1..70e05a197d 100644 --- a/configs/devices/aarch64-softmmu/default.mak +++ b/configs/devices/aarch64-softmmu/default.mak @@ -2,7 +2,3 @@ =20 # We support all the 32 bit boards so need all their config include ../arm-softmmu/default.mak - -CONFIG_XLNX_ZYNQMP_ARM=3Dy -CONFIG_XLNX_VERSAL=3Dy -CONFIG_SBSA_REF=3Dy diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-= softmmu/default.mak index cb3e5aea65..647fbce88d 100644 --- a/configs/devices/arm-softmmu/default.mak +++ b/configs/devices/arm-softmmu/default.mak @@ -4,40 +4,3 @@ # CONFIG_TEST_DEVICES=3Dn =20 CONFIG_ARM_VIRT=3Dy -CONFIG_CUBIEBOARD=3Dy -CONFIG_EXYNOS4=3Dy -CONFIG_HIGHBANK=3Dy -CONFIG_INTEGRATOR=3Dy -CONFIG_FSL_IMX31=3Dy -CONFIG_MUSICPAL=3Dy -CONFIG_MUSCA=3Dy -CONFIG_CHEETAH=3Dy -CONFIG_SX1=3Dy -CONFIG_NSERIES=3Dy -CONFIG_STELLARIS=3Dy -CONFIG_STM32VLDISCOVERY=3Dy -CONFIG_REALVIEW=3Dy -CONFIG_VERSATILE=3Dy -CONFIG_VEXPRESS=3Dy -CONFIG_ZYNQ=3Dy -CONFIG_MAINSTONE=3Dy -CONFIG_GUMSTIX=3Dy -CONFIG_SPITZ=3Dy -CONFIG_TOSA=3Dy -CONFIG_Z2=3Dy -CONFIG_NPCM7XX=3Dy -CONFIG_COLLIE=3Dy -CONFIG_ASPEED_SOC=3Dy -CONFIG_NETDUINO2=3Dy -CONFIG_NETDUINOPLUS2=3Dy -CONFIG_OLIMEX_STM32_H405=3Dy -CONFIG_MPS2=3Dy -CONFIG_RASPI=3Dy -CONFIG_DIGIC=3Dy -CONFIG_SABRELITE=3Dy -CONFIG_EMCRAFT_SF2=3Dy -CONFIG_MICROBIT=3Dy -CONFIG_FSL_IMX25=3Dy -CONFIG_FSL_IMX7=3Dy -CONFIG_FSL_IMX6UL=3Dy -CONFIG_ALLWINNER_H3=3Dy diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e0da8841db..4a2460311a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -34,20 +34,24 @@ config ARM_VIRT =20 config CHEETAH bool + default y if TCG && ARM select OMAP select TSC210X =20 config CUBIEBOARD bool + default y if TCG && ARM select ALLWINNER_A10 =20 config DIGIC bool + default y if TCG && ARM select PTIMER select PFLASH_CFI02 =20 config EXYNOS4 bool + default y if TCG && ARM imply I2C_DEVICES select A9MPCORE select I2C @@ -60,6 +64,7 @@ config EXYNOS4 =20 config HIGHBANK bool + default y if TCG && ARM select A9MPCORE select A15MPCORE select AHCI @@ -74,6 +79,7 @@ config HIGHBANK =20 config INTEGRATOR bool + default y if TCG && ARM select ARM_TIMER select INTEGRATOR_DEBUG select PL011 # UART @@ -86,12 +92,14 @@ config INTEGRATOR =20 config MAINSTONE bool + default y if TCG && ARM select PXA2XX select PFLASH_CFI01 select SMC91C111 =20 config MUSCA bool + default y if TCG && ARM select ARMSSE select PL011 select PL031 @@ -103,6 +111,7 @@ config MARVELL_88W8618 =20 config MUSICPAL bool + default y if TCG && ARM select OR_IRQ select BITBANG_I2C select MARVELL_88W8618 @@ -113,18 +122,22 @@ config MUSICPAL =20 config NETDUINO2 bool + default y if TCG && ARM select STM32F205_SOC =20 config NETDUINOPLUS2 bool + default y if TCG && ARM select STM32F405_SOC =20 config OLIMEX_STM32_H405 bool + default y if TCG && ARM select STM32F405_SOC =20 config NSERIES bool + default y if TCG && ARM select OMAP select TMP105 # tempature sensor select BLIZZARD # LCD/TV controller @@ -157,12 +170,14 @@ config PXA2XX =20 config GUMSTIX bool + default y if TCG && ARM select PFLASH_CFI01 select SMC91C111 select PXA2XX =20 config TOSA bool + default y if TCG && ARM select ZAURUS # scoop select MICRODRIVE select PXA2XX @@ -170,6 +185,7 @@ config TOSA =20 config SPITZ bool + default y if TCG && ARM select ADS7846 # touch-screen controller select MAX111X # A/D converter select WM8750 # audio codec @@ -182,6 +198,7 @@ config SPITZ =20 config Z2 bool + default y if TCG && ARM select PFLASH_CFI01 select WM8750 select PL011 # UART @@ -189,6 +206,7 @@ config Z2 =20 config REALVIEW bool + default y if TCG && ARM imply PCI_DEVICES imply PCI_TESTDEV imply I2C_DEVICES @@ -217,6 +235,7 @@ config REALVIEW =20 config SBSA_REF bool + default y if TCG && AARCH64 imply PCI_DEVICES select AHCI select ARM_SMMUV3 @@ -232,11 +251,13 @@ config SBSA_REF =20 config SABRELITE bool + default y if TCG && ARM select FSL_IMX6 select SSI_M25P80 =20 config STELLARIS bool + default y if TCG && ARM imply I2C_DEVICES select ARM_V7M select CMSDK_APB_WATCHDOG @@ -254,6 +275,7 @@ config STELLARIS =20 config STM32VLDISCOVERY bool + default y if TCG && ARM select STM32F100_SOC =20 config STRONGARM @@ -262,16 +284,19 @@ config STRONGARM =20 config COLLIE bool + default y if TCG && ARM select PFLASH_CFI01 select ZAURUS # scoop select STRONGARM =20 config SX1 bool + default y if TCG && ARM select OMAP =20 config VERSATILE bool + default y if TCG && ARM select ARM_TIMER # sp804 select PFLASH_CFI01 select LSI_SCSI_PCI @@ -283,6 +308,7 @@ config VERSATILE =20 config VEXPRESS bool + default y if TCG && ARM select A9MPCORE select A15MPCORE select ARM_MPTIMER @@ -298,6 +324,7 @@ config VEXPRESS =20 config ZYNQ bool + default y if TCG && ARM select A9MPCORE select CADENCE # UART select PFLASH_CFI02 @@ -314,7 +341,7 @@ config ZYNQ config ARM_V7M bool # currently v7M must be included in a TCG build due to translate.c - default y if TCG && (ARM || AARCH64) + default y if TCG && ARM select PTIMER =20 config ALLWINNER_A10 @@ -332,6 +359,7 @@ config ALLWINNER_A10 =20 config ALLWINNER_H3 bool + default y if TCG && ARM select ALLWINNER_A10_PIT select ALLWINNER_SUN8I_EMAC select ALLWINNER_I2C @@ -345,6 +373,7 @@ config ALLWINNER_H3 =20 config RASPI bool + default y if TCG && ARM select FRAMEBUFFER select PL011 # UART select SDHCI @@ -375,6 +404,7 @@ config STM32F405_SOC =20 config XLNX_ZYNQMP_ARM bool + default y if TCG && AARCH64 select AHCI select ARM_GIC select CADENCE @@ -391,6 +421,7 @@ config XLNX_ZYNQMP_ARM =20 config XLNX_VERSAL bool + default y if TCG && AARCH64 select ARM_GIC select PL011 select CADENCE @@ -404,6 +435,7 @@ config XLNX_VERSAL =20 config NPCM7XX bool + default y if TCG && ARM select A9MPCORE select ADM1272 select ARM_GIC @@ -420,6 +452,7 @@ config NPCM7XX =20 config FSL_IMX25 bool + default y if TCG && ARM imply I2C_DEVICES select IMX select IMX_FEC @@ -429,6 +462,7 @@ config FSL_IMX25 =20 config FSL_IMX31 bool + default y if TCG && ARM imply I2C_DEVICES select SERIAL select IMX @@ -449,6 +483,7 @@ config FSL_IMX6 =20 config ASPEED_SOC bool + default y if TCG && ARM select DS1338 select FTGMAC100 select I2C @@ -469,6 +504,7 @@ config ASPEED_SOC =20 config MPS2 bool + default y if TCG && ARM imply I2C_DEVICES select ARMSSE select LAN9118 @@ -484,6 +520,7 @@ config MPS2 =20 config FSL_IMX7 bool + default y if TCG && ARM imply PCI_DEVICES imply TEST_DEVICES imply I2C_DEVICES @@ -502,6 +539,7 @@ config ARM_SMMUV3 =20 config FSL_IMX6UL bool + default y if TCG && ARM imply I2C_DEVICES select A15MPCORE select IMX @@ -513,6 +551,7 @@ config FSL_IMX6UL =20 config MICROBIT bool + default y if TCG && ARM select NRF51_SOC =20 config NRF51_SOC @@ -524,6 +563,7 @@ config NRF51_SOC =20 config EMCRAFT_SF2 bool + default y if TCG && ARM select MSF2 select SSI_M25P80 =20 --=20 2.35.3