From nobody Sat May 18 15:08:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673872273; cv=none; d=zohomail.com; s=zohoarc; b=jo//p9n671JeSHeeXmr6iTd0vdTQ6zt3m1BOCWvDGAEPzr7x+VmrGGftyBw+QLSl/nARBXHrgUHRYELNIBDc25lP+DLL+dNBbSXTe6iHvBKdiCoqJLyoZCvjByfb6bLBGv/Tn5VADHJ3n1kmeXUZx7mH0lutcmJsd0lGVvfqFys= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673872273; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RmlaSf4agWGz7+gWU7Vna+xOkpByetLr1UplEidZSlY=; b=X9bLNYTlFzuA/048a0FNQ351vGSrS3kVCDIbH2AwEAh4AR0tScdvLVlOvcimk5P+7uAd5LmD96fI18DG0ZnpWHXX6wW2gO5YZj1lhQsPE4+Gg4w8a7eYN4o7sk70Iu9qJ1ZJm//wVLulVePF4i/Z7DkW2WyVJY8CEf2gehMgOyM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673872273841539.9444150987284; Mon, 16 Jan 2023 04:31:13 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pHOco-0008Uu-Pm; Mon, 16 Jan 2023 07:30:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHOck-0008QH-Ev for qemu-devel@nongnu.org; Mon, 16 Jan 2023 07:30:02 -0500 Received: from mail-oi1-x22e.google.com ([2607:f8b0:4864:20::22e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHOcg-0003HD-Ve for qemu-devel@nongnu.org; Mon, 16 Jan 2023 07:30:01 -0500 Received: by mail-oi1-x22e.google.com with SMTP id r9so12449198oie.13 for ; Mon, 16 Jan 2023 04:29:58 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id g21-20020a0568080dd500b00360f68d509csm12814540oic.49.2023.01.16.04.29.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 04:29:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RmlaSf4agWGz7+gWU7Vna+xOkpByetLr1UplEidZSlY=; b=ncuTX8Jhn+wW3IUD+9wGSMQMdtl4tJSwvCdS9K4NNNZVA0yUPR4U2WAHbavcWbzQaz ghVbLHJ/0d+IvzLx6lq/Vqw4pS3kfcJfxHylyz2y42i7KiACluqVnwOfsGQManF/1Q7N buLYh/mkUrgYzohD8rbFUmifLrm1RcqFl8j/G+OWFyAk0ltS2HDxjnHEkmRKWjIcadYl 35quM0sK0YTyDAgOASnxiRg237Yd8U8muU9Uto2h5xFTN0L563LeoC1zIRsZ1zW3WvVp C1+bkIMYmFQHu1CI6QMLO8PkuUKcnOdpAnulINgN5iPolpjQG1xrr5lcEMY1pER9AxbI 6HAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RmlaSf4agWGz7+gWU7Vna+xOkpByetLr1UplEidZSlY=; b=tRXQY4A8ndAGLGcRWPYGh8QgLTZJH7kz/ck0d4KEhxMcKCRvTHfSR/0ngAVf5bpBpX 9U1aCL1lnu8RrjfGfoT2pqLlxMKbbdHf3O+dAtWNp8nSxpgphMuh2JfnLC6gd4lQrL7Q wt6807YzuGItbaTSg4oGIM04+88wi8vpsoSk1B5r30qJCHhL658nc2N2qv9mzmvNH4mo tsa8QtGhuRqNUAK76lhl6FnE835m24+E6tWMFoNbuqdzWIg0Xk91MBgY8AuATzMnsNwY 1hjokT3HtL7D00P7Y2chZ3g5+qgbnTUcJCKPE2NLipLwwpBgNk/o4CLJVE1KBqhHeFte hzkQ== X-Gm-Message-State: AFqh2kqeSWPAvqGlPv2SxlDHjiyohXpXcP0Qft5yOnY8JjIgHIjznLnZ R3TAQr6GOwtk5fYajl+2ldMRTq+t4rHth7oSXZ8= X-Google-Smtp-Source: AMrXdXsT8K0WhEgNbu90eYblQ6J3JRsS/N51z0C1f/Y/sN97zIqDE1ZYhWnIvVNrkbEl6hxwrvhn4Q== X-Received: by 2002:aca:e155:0:b0:364:ebef:819b with SMTP id y82-20020acae155000000b00364ebef819bmr2280124oig.28.1673872197323; Mon, 16 Jan 2023 04:29:57 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Palmer Dabbelt , Bin Meng Subject: [PATCH v8 1/3] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() Date: Mon, 16 Jan 2023 09:29:46 -0300 Message-Id: <20230116122948.757515-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230116122948.757515-1-dbarboza@ventanamicro.com> References: <20230116122948.757515-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1673872276065100003 Content-Type: text/plain; charset="utf-8" The microchip_icicle_kit, sifive_u, spike and virt boards are now doing the same steps when '-kernel' is used: - execute load_kernel() - load init_rd() - write kernel_cmdline Let's fold everything inside riscv_load_kernel() to avoid code repetition. To not change the behavior of boards that aren't calling riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and allow these boards to opt out from initrd loading. Cc: Palmer Dabbelt Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 22 +++++++++++++++++++--- hw/riscv/microchip_pfsoc.c | 12 ++---------- hw/riscv/opentitan.c | 2 +- hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 12 ++---------- hw/riscv/spike.c | 11 +---------- hw/riscv/virt.c | 12 ++---------- include/hw/riscv/boot.h | 1 + 8 files changed, 30 insertions(+), 45 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 2594276223..4888d5c1e0 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -175,10 +175,12 @@ target_ulong riscv_load_firmware(const char *firmware= _filename, =20 target_ulong riscv_load_kernel(MachineState *machine, target_ulong kernel_start_addr, + bool load_initrd, symbol_fn_t sym_cb) { const char *kernel_filename =3D machine->kernel_filename; uint64_t kernel_load_base, kernel_entry; + void *fdt =3D machine->fdt; =20 g_assert(kernel_filename !=3D NULL); =20 @@ -192,21 +194,35 @@ target_ulong riscv_load_kernel(MachineState *machine, if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL, &kernel_load_base, NULL, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { - return kernel_load_base; + kernel_entry =3D kernel_load_base; + goto out; } =20 if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, NULL, NULL, NULL) > 0) { - return kernel_entry; + goto out; } =20 if (load_image_targphys_as(kernel_filename, kernel_start_addr, current_machine->ram_size, NULL) > 0) { - return kernel_start_addr; + kernel_entry =3D kernel_start_addr; + goto out; } =20 error_report("could not load kernel '%s'", kernel_filename); exit(1); + +out: + if (load_initrd && machine->initrd_filename) { + riscv_load_initrd(machine, kernel_entry); + } + + if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } + + return kernel_entry; } =20 void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 82ae5e7023..c45023a2b1 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -629,16 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineS= tate *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", - "bootargs", machine->kernel_cmdline); - } + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, + true, NULL); =20 /* Compute the fdt load address in dram */ fdt_load_addr =3D riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].b= ase, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 64d5d435b9..f6fd9725a5 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -101,7 +101,7 @@ static void opentitan_board_init(MachineState *machine) } =20 if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); + riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, false, NULL); } } =20 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 3e3f4b0088..6835d1c807 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_m= emory); =20 if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); + riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, + false, NULL); } } =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 2fb6ee231f..ccad386920 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -598,16 +598,8 @@ static void sifive_u_machine_init(MachineState *machin= e) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, + true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index badc11ec43..91bf194ec1 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -306,16 +306,7 @@ static void spike_board_init(MachineState *machine) firmware_end_addr= ); =20 kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, - htif_symbol_callback); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + true, htif_symbol_callback); } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e6d4f06e8d..e374b58f89 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1281,16 +1281,8 @@ static void virt_machine_done(Notifier *notifier, vo= id *data) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, + true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index f94653a09b..c3de897371 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -45,6 +45,7 @@ target_ulong riscv_load_firmware(const char *firmware_fil= ename, symbol_fn_t sym_cb); target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, + bool load_initrd, symbol_fn_t sym_cb); void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); --=20 2.39.0 From nobody Sat May 18 15:08:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673872264; cv=none; d=zohomail.com; s=zohoarc; b=C/ZIIaOxYhiVcuR+hJCMwfaQ+VAS04Rkq/5rcK2H7kVtlBfJQreZ7gflsEad8Lb33++HWJ0DYQ2j70q3W//QnZU/ZN+ksuHYdqOzz+z0pS8Cz6m25XBqqm10CLhc/K7ajfuy//TLVhRldcZVvo/xgTSg0xeTXstz4bVhBTUn3AU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673872264; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=f0lm/oJWWa+MhCTCBNn1qSE+0b1IOIjShGN0DTgF9G0=; b=GEQNiWzmgFPPxdhD9D4opL4jiYAP+B81v5T/dltKg5jCEXKWuz5PL2YMzVULdzIc86oJfDdFxBI0BCfAkEH99+rwdi9IRWITMGx4PW93LSt7Re6YvUGWZeQS6hFQKQSwAtEUx2FDmaFQ8c5uSY1NNWK6ESqZOmAPa6poXdrpXPk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673872263966898.399987304704; Mon, 16 Jan 2023 04:31:03 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pHOcp-0008WT-Fi; Mon, 16 Jan 2023 07:30:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHOcm-0008RK-Ai for qemu-devel@nongnu.org; Mon, 16 Jan 2023 07:30:04 -0500 Received: from mail-oi1-x236.google.com ([2607:f8b0:4864:20::236]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHOcj-0003HX-JU for qemu-devel@nongnu.org; Mon, 16 Jan 2023 07:30:03 -0500 Received: by mail-oi1-x236.google.com with SMTP id d188so12068874oia.3 for ; Mon, 16 Jan 2023 04:30:01 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id g21-20020a0568080dd500b00360f68d509csm12814540oic.49.2023.01.16.04.29.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 04:29:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f0lm/oJWWa+MhCTCBNn1qSE+0b1IOIjShGN0DTgF9G0=; b=h1+4w2EBwnvQF8wqn49/RJfMEkwMYGDou0CpmL1o0Vf/KaZUTyA5ln/1BWC8uSEXMV rKKBuN2QA6kGEu9Lhmjqq2Zsuugt9cIM+aCVREde3DYU/XFpF9RAMaupu2B+6Cou2/Ya plTDLvB0ZrRXo7xm3oycHNzldUm7R5g9szc/qvCuYqxS/vuNHRZgcn1pXO/hCQIjey/U FoWA0YLcfX7LrhMZpanfrjc4qdnf6RpfS87+dpxthTjmw3HIUrC4PZXVdx8bGLvKXp2u OYhlf+3ipSUoRwndsg/iel/v8aagJnAJbCTbhXqW5wUbal4RdNbQhcs9TJH5bcqs7UT/ hKng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f0lm/oJWWa+MhCTCBNn1qSE+0b1IOIjShGN0DTgF9G0=; b=ttBwA6v5fOQS9YMI4+3Mx028ZJVBjvL5gr2nL3KaoNYDvJ594Hp+eONuf8SLPx0pVW 0xbvKuVrW5Y1Gx0qKANvd3hm5qIWPKG90xJznDZLA5d+pKBvPS4OePmucB0q7adkszDG GDaAjNSfNIo1H4mJBOYDEIJRCjwS1758WuwEW0LpVssAOAceS+4WNhfMjIu43qXGpy1n ev7YLBqBLSX3kqP+aiX7GyZWMR7eA3l2Midna0wPf7VtaxPu4JZlwdJD5FqZSXRyuL7Q Xw0ztMNEkHe4s8MY/Zx7pVl6umaf4lkKyz7e2Jx+ah7jM9oMnp6zo8mf8Qnlep/zJ1fO lYnQ== X-Gm-Message-State: AFqh2kqVzA1VSZHgs8mKZZOvwao/Zxqr2qEyzQSe0tlJXx5HNI5LbbDb gd6nv8pmL+wbsR2ZwaCEGtIUirh1PfBWhvgC1LY= X-Google-Smtp-Source: AMrXdXsWgbJjcH3qLpHVUENAO3DAbs8UbuOsMr9zpY20u4pAyk/6/Lt9TjT6ozCnGHxjpf/00obJMA== X-Received: by 2002:a05:6808:21a9:b0:364:5c9b:5f7d with SMTP id be41-20020a05680821a900b003645c9b5f7dmr13813466oib.22.1673872200017; Mon, 16 Jan 2023 04:30:00 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v8 2/3] hw/riscv/boot.c: make riscv_load_initrd() static Date: Mon, 16 Jan 2023 09:29:47 -0300 Message-Id: <20230116122948.757515-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230116122948.757515-1-dbarboza@ventanamicro.com> References: <20230116122948.757515-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1673872266247100001 The only remaining caller is riscv_load_kernel_and_initrd() which belongs to the same file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/boot.c | 80 ++++++++++++++++++++--------------------- include/hw/riscv/boot.h | 1 - 2 files changed, 40 insertions(+), 41 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 4888d5c1e0..e868fb6ade 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -173,6 +173,46 @@ target_ulong riscv_load_firmware(const char *firmware_= filename, exit(1); } =20 +static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) +{ + const char *filename =3D machine->initrd_filename; + uint64_t mem_size =3D machine->ram_size; + void *fdt =3D machine->fdt; + hwaddr start, end; + ssize_t size; + + g_assert(filename !=3D NULL); + + /* + * We want to put the initrd far enough into RAM that when the + * kernel is uncompressed it will not clobber the initrd. However + * on boards without much RAM we must ensure that we still leave + * enough room for a decent sized initrd, and on boards with large + * amounts of RAM we must avoid the initrd being so far up in RAM + * that it is outside lowmem and inaccessible to the kernel. + * So for boards with less than 256MB of RAM we put the initrd + * halfway into RAM, and for boards with 256MB of RAM or more we put + * the initrd at 128MB. + */ + start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); + + size =3D load_ramdisk(filename, start, mem_size - start); + if (size =3D=3D -1) { + size =3D load_image_targphys(filename, start, mem_size - start); + if (size =3D=3D -1) { + error_report("could not load ramdisk '%s'", filename); + exit(1); + } + } + + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ + if (fdt) { + end =3D start + size; + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + } +} + target_ulong riscv_load_kernel(MachineState *machine, target_ulong kernel_start_addr, bool load_initrd, @@ -225,46 +265,6 @@ out: return kernel_entry; } =20 -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) -{ - const char *filename =3D machine->initrd_filename; - uint64_t mem_size =3D machine->ram_size; - void *fdt =3D machine->fdt; - hwaddr start, end; - ssize_t size; - - g_assert(filename !=3D NULL); - - /* - * We want to put the initrd far enough into RAM that when the - * kernel is uncompressed it will not clobber the initrd. However - * on boards without much RAM we must ensure that we still leave - * enough room for a decent sized initrd, and on boards with large - * amounts of RAM we must avoid the initrd being so far up in RAM - * that it is outside lowmem and inaccessible to the kernel. - * So for boards with less than 256MB of RAM we put the initrd - * halfway into RAM, and for boards with 256MB of RAM or more we put - * the initrd at 128MB. - */ - start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); - - size =3D load_ramdisk(filename, start, mem_size - start); - if (size =3D=3D -1) { - size =3D load_image_targphys(filename, start, mem_size - start); - if (size =3D=3D -1) { - error_report("could not load ramdisk '%s'", filename); - exit(1); - } - } - - /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ - if (fdt) { - end =3D start + size; - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); - } -} - uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) { uint64_t temp, fdt_addr; diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index c3de897371..cbd131bad7 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -47,7 +47,6 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, bool load_initrd, symbol_fn_t sym_cb); -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState = *harts, hwaddr saddr, --=20 2.39.0 From nobody Sat May 18 15:08:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673872285; cv=none; d=zohomail.com; s=zohoarc; b=bdpDeRbjCAfoOqSNsfHBmf5ZVPXIoxtK/9Xf1kDELYfy4a96jXd7Prn5mws5Sgl1wH8HM2/W+MmkNhRogRLXocozXN4me/Z/Tg84H/DwkIhzcqRFh6dxcrNAyxL2aXckL9rFk8ZO758BKirmPcYXHWgCKVAesj9ni3OxmxHH/hQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673872285; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=R4qtclHJ1n0/XaLxnevTHDvTqEpS8d67utZqEr3tpBw=; b=Vv25VCf30sgeG8gLkim9is8FhLoJLb2IazaqFSAbTronNWHDSGoXwZG0Jl3x6vNWPGKJb7KyweFxHCh1xVSru7NKXg2Yfz/xWtMemY4sxZK5+2/KrcYxkNOEQoOQshKqdkpPjQ6lON2INEpNemFp30DX1Ql3WP02zCiKKNVY4bw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167387228501772.17220892811349; Mon, 16 Jan 2023 04:31:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pHOcr-000092-KU; Mon, 16 Jan 2023 07:30:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHOcp-00005T-IB for qemu-devel@nongnu.org; Mon, 16 Jan 2023 07:30:07 -0500 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHOcm-0003J4-DJ for qemu-devel@nongnu.org; Mon, 16 Jan 2023 07:30:07 -0500 Received: by mail-oi1-x243.google.com with SMTP id i5so4980395oih.11 for ; Mon, 16 Jan 2023 04:30:03 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id g21-20020a0568080dd500b00360f68d509csm12814540oic.49.2023.01.16.04.30.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 04:30:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=R4qtclHJ1n0/XaLxnevTHDvTqEpS8d67utZqEr3tpBw=; b=htuXy9SD87E8R9pP8uRDP3IyBjjuXm3hoc5DGjzLq80oW+k8FFcUr5faLmD04H/dDt trBgOxRQzHot0XjrxYCjvqkUJHGkI8QkMoGUdjJYhdmcRBc7v3y7rPPkGpOt6zcxPp8L a+0cg/rwQFnrTc9JaGaa9M7EXIXkz5NvB6JqUETu5ugfbmMraJtC86gR15ebyMAOelYx FLns4uNQH8dCn6uATc8Qj5GSrM9pahQGOT/zTq704K67BXt+8Z+8gLhDhsN3xNEBSYAa 2D5o2byp4atJGXww9csS2WXoE8iArDOd65/yyscFJOMpV1wosemUn9JA17ZI5JOchR83 FHOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R4qtclHJ1n0/XaLxnevTHDvTqEpS8d67utZqEr3tpBw=; b=dt9n2q/6Q50ju8zog355l8ae2Yn0Id3v2fXtR+sWWk4nZnGeCvIByCxY05PwhYTW79 2j8QI/4lLSfyI7KvetwByR/i2PC0I9GF+ieqGb/dYkEBHKU67FJn77pzj33fP2d780Fh fk9q1nw8B6oZjr+JW1Ht/aiwF8e9ogUvtGU6EEFOyK8zOdveg1lUbiPEjNJVp9q2hDkt bb0ktC71I3KBVmMJIJHrZHsYq5Cy4VFm6By1HolmAESqPcaLttga2+1GDtL5rWImZeck R4fL3ER9azbGBUVn/Ixy0wYzcKxtJGDftqcU8Mv7eLhOF8naWPoBHK7ZH479Xi7ZKJTh QN5A== X-Gm-Message-State: AFqh2kqD/fAtrYczkJV3t8+3O0ldsVukYso0VkVh76Rar9vnqI3GIVJj n2fxnicehOLI9Z1GmiYnnIrDxvS/ujmsBHSTz1w= X-Google-Smtp-Source: AMrXdXul1tSBWV0KSY3iZ5MKWWAvMSMrRvaXaVTrknAUi02w+e8gHs1KvewRhzuiHStfvh+tlh6XAA== X-Received: by 2002:a05:6808:657:b0:364:914b:2f02 with SMTP id z23-20020a056808065700b00364914b2f02mr6929775oih.40.1673872202399; Mon, 16 Jan 2023 04:30:02 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v8 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() Date: Mon, 16 Jan 2023 09:29:48 -0300 Message-Id: <20230116122948.757515-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230116122948.757515-1-dbarboza@ventanamicro.com> References: <20230116122948.757515-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::243; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x243.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1673872286126100001 Recent hw/risc/boot.c changes caused a regression in an use case with the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel' stopped working. The reason seems to be that Xvisor is using 64 bit to encode the 32 bit addresses from the guest, and load_elf_ram_sym() is sign-extending the result with '1's [1]. Use a translate_fn() callback to be called by load_elf_ram_sym() and return only the 32 bits address if we're running a 32 bit CPU. [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html Suggested-by: Philippe Mathieu-Daud=C3=A9 Suggested-by: Bin Meng Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/boot.c | 20 +++++++++++++++++++- hw/riscv/microchip_pfsoc.c | 4 ++-- hw/riscv/opentitan.c | 3 ++- hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 4 ++-- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 4 ++-- include/hw/riscv/boot.h | 1 + target/riscv/cpu_bits.h | 1 + 9 files changed, 32 insertions(+), 10 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index e868fb6ade..0fd39df7f3 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -213,7 +213,24 @@ static void riscv_load_initrd(MachineState *machine, u= int64_t kernel_entry) } } =20 +static uint64_t translate_kernel_address(void *opaque, uint64_t addr) +{ + RISCVHartArrayState *harts =3D opaque; + + /* + * For 32 bit CPUs, kernel_load_base is sign-extended (i.e. + * it can be padded with '1's) if the hypervisor is using + * 64 bit addresses with 32 bit guests. + */ + if (riscv_is_32bit(harts)) { + return extract64(addr, 0, RV32_KERNEL_ADDR_LEN); + } + + return addr; +} + target_ulong riscv_load_kernel(MachineState *machine, + RISCVHartArrayState *harts, target_ulong kernel_start_addr, bool load_initrd, symbol_fn_t sym_cb) @@ -231,7 +248,8 @@ target_ulong riscv_load_kernel(MachineState *machine, * the (expected) load address load address. This allows kernels to ha= ve * separate SBI and ELF entry points (used by FreeBSD, for example). */ - if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, + if (load_elf_ram_sym(kernel_filename, NULL, + translate_kernel_address, NULL, NULL, &kernel_load_base, NULL, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { kernel_entry =3D kernel_load_base; diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index c45023a2b1..b7e171b605 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -629,8 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, - true, NULL); + kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, + kernel_start_addr, true, NULL); =20 /* Compute the fdt load address in dram */ fdt_load_addr =3D riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].b= ase, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index f6fd9725a5..1404a52da0 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -101,7 +101,8 @@ static void opentitan_board_init(MachineState *machine) } =20 if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, false, NULL); + riscv_load_kernel(machine, &s->soc.cpus, + memmap[IBEX_DEV_RAM].base, false, NULL); } } =20 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 6835d1c807..04939b60c3 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_m= emory); =20 if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, + riscv_load_kernel(machine, &s->soc.cpus, + memmap[SIFIVE_E_DEV_DTIM].base, false, NULL); } } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index ccad386920..b0b3e6f03a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -598,8 +598,8 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, - true, NULL); + kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, + kernel_start_addr, true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 91bf194ec1..3c0ac916c0 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -305,7 +305,7 @@ static void spike_board_init(MachineState *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, + kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], kernel_sta= rt_addr, true, htif_symbol_callback); } else { /* diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e374b58f89..cf64da65bf 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1281,8 +1281,8 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, - true, NULL); + kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], + kernel_start_addr, true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index cbd131bad7..bc9faed397 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -44,6 +44,7 @@ target_ulong riscv_load_firmware(const char *firmware_fil= ename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); target_ulong riscv_load_kernel(MachineState *machine, + RISCVHartArrayState *harts, target_ulong firmware_end_addr, bool load_initrd, symbol_fn_t sym_cb); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8b0d7e20ea..8fcaeae342 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -751,6 +751,7 @@ typedef enum RISCVException { #define MENVCFG_STCE (1ULL << 63) =20 /* For RV32 */ +#define RV32_KERNEL_ADDR_LEN 32 #define MENVCFGH_PBMTE BIT(30) #define MENVCFGH_STCE BIT(31) =20 --=20 2.39.0