On Thu, Jan 12, 2023 at 3:12 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> This is a follow-up of:
>
> "[PATCH v5 00/11] riscv: OpenSBI boot test and cleanups"
>
> Patches were based on top of riscv-to-apply.next [1] + the series above.
>
> The recent FDT changes made in hw/riscv (all machines are now using the
> FDT via MachineState::fdt) allowed for most of the cleanups made here.
>
> Patches 9 and 10 were based on a suggestion made by Phil a few weeks ago.
> I decided to go for it.
>
> [1] https://github.com/alistair23/qemu/tree/riscv-to-apply.next
>
> Daniel Henrique Barboza (10):
> hw/riscv/spike.c: simplify create_fdt()
> hw/riscv/virt.c: simplify create_fdt()
> hw/riscv/sifive_u.c: simplify create_fdt()
> hw/riscv/virt.c: remove 'is_32_bit' param from
> create_fdt_socket_cpus()
> hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id()
> hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()
> hw/riscv: simplify riscv_load_fdt()
> hw/riscv/virt.c: calculate socket count once in create_fdt_imsic()
> hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms'
> hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms'
Applied patches 1 to 6.
Alistair
>
> hw/riscv/boot.c | 4 +-
> hw/riscv/microchip_pfsoc.c | 4 +-
> hw/riscv/numa.c | 14 +-
> hw/riscv/sifive_u.c | 11 +-
> hw/riscv/spike.c | 25 +-
> hw/riscv/virt.c | 484 +++++++++++++++++++------------------
> include/hw/riscv/boot.h | 2 +-
> include/hw/riscv/numa.h | 10 +-
> 8 files changed, 277 insertions(+), 277 deletions(-)
>
> --
> 2.39.0
>
>