From nobody Sun May 19 10:01:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673381766; cv=none; d=zohomail.com; s=zohoarc; b=KGvguEzSXZPri3Ox9rkKX3eMHzAUz7wplgqN1RLqhmOEP1/+au0rUXXPo16NpX7hPH0cyQ/m9eTu9qgzmREHi0JAbGOo8273YgdGvEHhosl1kRpCiyaCISpT86YBzbOMFcVbXf0hGrk6RD7SBXOZesSOks4qNTF8tZ8lDFdP9iY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673381766; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=W3FF41oQMn8zqiEm/hd7dm9Rda9j4Id6q5Oa/vMVqWY=; b=KCtwZsnMH2+I9pAhmwZHBPy1DckKSVsDWIn24czGxtsfuxmENqQYhGbQpaQ/ub4zqMb6yXtvkp5kNX96Nf0K39b8SrH6znn0iYpHIyhyRBmFOaY/k0qbK+CmQVS2zpAOhQ2kzO4gdECuB5hU7MFP3FY8ODSk2GGloCFbO6kuwu0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTP id 16733817661552.173793487034459; Tue, 10 Jan 2023 12:16:06 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFL0s-0003RT-6g; Tue, 10 Jan 2023 15:14:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFL0n-0003M7-Eo for qemu-devel@nongnu.org; Tue, 10 Jan 2023 15:14:21 -0500 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFL0k-0000pr-8F for qemu-devel@nongnu.org; Tue, 10 Jan 2023 15:14:21 -0500 Received: by mail-oi1-x22c.google.com with SMTP id n8so11103817oih.0 for ; Tue, 10 Jan 2023 12:14:15 -0800 (PST) Received: from grind.. ([152.250.93.24]) by smtp.gmail.com with ESMTPSA id l21-20020a9d7a95000000b0067c87f23476sm6453978otn.57.2023.01.10.12.14.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 12:14:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W3FF41oQMn8zqiEm/hd7dm9Rda9j4Id6q5Oa/vMVqWY=; b=OBA5gO5E1wZY68VhKDrQ4kYaYuRWh9iF/gE1P1erQJ01dCQfUIX+JXK6eiF3KvMl2Q iGKXVYZLip1t5RvqjNJ7NxwrGUPA8gS/nlcJ1PiuoL6oLiAARBliErwjauyLu6SRdh3h Vdc1UbucqQOfW12vELO3xcENI0Rvsd4kNbzMXl6vKGJS3cMKWA0xD2OdeIVc4Z759jmC 8wdhmAT5Cs9Isf0LizYKfoLDNIq1As91CCQBDXtjxnjga7dAy0qVe5aSeuztKejhA/wG 6J4Pr0x2ujXKQXnnzBAY1KJN5Il4/pnyt7qKiKuinJ97VFF4YqbRLIXIlTW7jgCG5sfr RlVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W3FF41oQMn8zqiEm/hd7dm9Rda9j4Id6q5Oa/vMVqWY=; b=29t54mJMx+tUituTh+zDzjDvIfLbpMfU27Jzv9gmLQbts2saxmUwIcHFdOH8IcpuDH m500iEWMNvVmxIZip1nP2HV7rmBhAOntXbAuMZ6XHewmvi2c2MMgK+h5niogfDiILxb2 DRhhtRh9sZP389zbmN4uvjJqAo5Y1ryejHQH0cXY2+EpqdkoUDIdxKZbTH62mKvFlAWc S6MZo3ar1ZhMtXtdb+3cWxcANOpMRgkY2Tel5Yjzkrlsd2emPvLk8LR28ZN0tahVLcO4 3mHABAggM4pRO4T4Ll53YHFoEzaLv3sUKY3NpIwzKlPMHu5Nr87yorFbyfTA7f6XUnHY K/OA== X-Gm-Message-State: AFqh2kqYlSkwPjAgIqlTL96znCDtKAIML0gPrxjJsB2I4KnkvZJYQthc aOF/crr6TfK4dpb48AlaNAVg2LceM/bAekkozhs= X-Google-Smtp-Source: AMrXdXuh65erJv2FgYlPE7mBVJ7maNxnTaGqo41o+Jr32CeWBdvSAT00420XU4ItGrlW2i/jrh89Vw== X-Received: by 2002:a05:6808:144c:b0:363:acf6:7843 with SMTP id x12-20020a056808144c00b00363acf67843mr27381799oiv.27.1673381654144; Tue, 10 Jan 2023 12:14:14 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, richard.henderson@linaro.org, Daniel Henrique Barboza Subject: [PATCH 1/2] target/riscv/cpu: set cpu->cfg in register_cpu_props() Date: Tue, 10 Jan 2023 17:14:04 -0300 Message-Id: <20230110201405.247785-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230110201405.247785-1-dbarboza@ventanamicro.com> References: <20230110201405.247785-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1673381767204100001 Content-Type: text/plain; charset="utf-8" There is an informal contract between the cpu_init() functions and riscv_cpu_realize(): if cpu->env.misa_ext is zero, assume that the default settings were loaded via register_cpu_props() and do validations to set env.misa_ext. If it's not zero, skip this whole process and assume that the board somehow did everything. At this moment, all SiFive CPUs are setting a non-zero misa_ext during their cpu_init() and skipping a good chunk of riscv_cpu_realize(). This causes problems when the code being skipped in riscv_cpu_realize() contains fixes or assumptions that affects all CPUs, meaning that SiFive CPUs are missing out. To allow this code to not be skipped anymore, all the cpu->cfg.ext_* attrib= utes needs to be set during cpu_init() time. At this moment this is being done in register_cpu_props(). The SiFive oards are setting their own extensions dur= ing cpu_init() though, meaning that they don't want all the defaults from register_cpu_props(). Let's move the contract between *_cpu_init() and riscv_cpu_realize() to register_cpu_props(). Inside this function we'll check if cpu->env.misa_ext was set and, if that's the case, set all relevant cpu->cfg.ext_* attributes, and only that. Leave the 'misa_ext' =3D 0 case as is today, i.e. loading all the defaults from riscv_cpu_extensions[]. register_cpu_props() can then be called by all the cpu_init() functions, including the SiFive ones. This will make all CPUs behave more in line with that riscv_cpu_realize() expects. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 40 ++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 4 ++++ 2 files changed, 44 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ee3659cc7e..b8c1edb7c2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -262,6 +262,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); } =20 @@ -271,6 +272,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; } @@ -305,6 +307,7 @@ static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); } =20 @@ -314,6 +317,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; } @@ -324,6 +328,7 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu =3D false; cpu->cfg.epmp =3D true; @@ -335,6 +340,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; } @@ -1139,10 +1145,44 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +/* + * Register CPU props based on env.misa_ext. If a non-zero + * value was set, register only the required cpu->cfg.ext_* + * properties and leave. env.misa_ext =3D 0 means that we want + * all the default properties to be registered. + */ static void register_cpu_props(DeviceState *dev) { + RISCVCPU *cpu =3D RISCV_CPU(OBJECT(dev)); + uint32_t misa_ext =3D cpu->env.misa_ext; Property *prop; =20 + /* + * If misa_ext is not zero, set cfg properties now to + * allow them to be read during riscv_cpu_realize() + * later on. + */ + if (cpu->env.misa_ext !=3D 0) { + cpu->cfg.ext_i =3D misa_ext & RVI; + cpu->cfg.ext_e =3D misa_ext & RVE; + cpu->cfg.ext_m =3D misa_ext & RVM; + cpu->cfg.ext_a =3D misa_ext & RVA; + cpu->cfg.ext_f =3D misa_ext & RVF; + cpu->cfg.ext_d =3D misa_ext & RVD; + cpu->cfg.ext_v =3D misa_ext & RVV; + cpu->cfg.ext_c =3D misa_ext & RVC; + cpu->cfg.ext_s =3D misa_ext & RVS; + cpu->cfg.ext_u =3D misa_ext & RVU; + cpu->cfg.ext_h =3D misa_ext & RVH; + cpu->cfg.ext_j =3D misa_ext & RVJ; + + /* + * We don't want to set the default riscv_cpu_extensions + * in this case. + */ + return; + } + for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0158932dc5..798bd081de 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -63,6 +63,10 @@ =20 #define RV(x) ((target_ulong)1 << (x - 'A')) =20 +/* + * Consider updating register_cpu_props() when adding + * new MISA bits here. + */ #define RVI RV('I') #define RVE RV('E') /* E and I are mutually exclusive */ #define RVM RV('M') --=20 2.39.0 From nobody Sun May 19 10:01:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1673381772; cv=none; d=zohomail.com; s=zohoarc; b=MdgPdzMYe2+oa+C4j+P544tI+D6uUzhXEYIEExHhXlLRM57B1zkyQ6zMCBNLL2gqZVCXn68zLJoOwSl8jV54g6y9d7QYlPG7pnpBrLrr7lUNvqmOCqSeXqR5DbNXM1H0/QFG+U9nHX2yctNxCxiAiTer2uXMgNBjzT9rcrJdMEU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673381772; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EUfZtab7ItHi76p6G7etytF2gLMXOVfh6cZM4zDyA+o=; b=cpLEIU7uH23buXz0DL0Phf4UedEPi69AcoxKUi4CrqKLqs0qj2hYaQMHtoQfg108CG9irADLsul/vbTzx28Oyp6qNwRtA+TJZ8tgrQEgLV0pr6MYkHD6v/Ol013MOWjTuXH/YYdSuc0pMJLf9IG2ouexkvI6NNXH9Te7HzEjz70= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTP id 1673381772293364.6088239411903; Tue, 10 Jan 2023 12:16:12 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFL0w-0003Sa-Ne; Tue, 10 Jan 2023 15:14:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFL0o-0003Na-1X for qemu-devel@nongnu.org; Tue, 10 Jan 2023 15:14:23 -0500 Received: from mail-ot1-x32a.google.com ([2607:f8b0:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFL0k-0000q8-DB for qemu-devel@nongnu.org; Tue, 10 Jan 2023 15:14:21 -0500 Received: by mail-ot1-x32a.google.com with SMTP id x44-20020a05683040ac00b006707c74330eso7636179ott.10 for ; Tue, 10 Jan 2023 12:14:18 -0800 (PST) Received: from grind.. ([152.250.93.24]) by smtp.gmail.com with ESMTPSA id l21-20020a9d7a95000000b0067c87f23476sm6453978otn.57.2023.01.10.12.14.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 12:14:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EUfZtab7ItHi76p6G7etytF2gLMXOVfh6cZM4zDyA+o=; b=EVAqj53DJCHmN+azr7GDjAh+IWeksVHmwJR+hgUdEf88ikQVV6CW9ssQzjW40XKqgf xCsB0KdsG5d4xUVfg3MO0LYEXbj05xLSMzrHpm2131ioCAonsUNcbabJCE1EnG6kz115 cUgKErY0ypktYIE8glq93/Yaih+f9HhMYsghA0ge94+IErrZA+8BpejYI9LoMzjU1nUf bTsn+ADr16TYPeQxrOg7umAJYtSLEhuFId+fJl8fyJdH7Vq1KfiQvQ4y09Xd4BHMxJU0 zDEf8oTh+cSd0qwvvF+F/+KzBcIhtDu6wBEvoL2O/yG3t3hpqyFy7ig+8RVZsNyNcIK5 /1dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EUfZtab7ItHi76p6G7etytF2gLMXOVfh6cZM4zDyA+o=; b=0sY4jzo5u5x8Idi0u1T9KLpiAqN2oxndlyvuMUd3JXXYiOQYm3U3jBZVktG11j4qQy +EMijUgcVTSvuFeZIEbb6kZqfu51N9zOY58r8J/kgV9ctdf1RJ0dEAc+ZbRqJpdYxzge TrN/KQjQsFVJ/4YLpvaIYpzj466J8pp4kPL3YAUgRMHx6WmgIXcTmwKjLXAdcnPWbXPD W/iI+GRU7ZC3ywxLxsLbGRKMq0fDGYM8a0MxaC99iyhDNG8LKOH/zHewst+91nR5lmD3 D8yUi+kssvnBW2W9N7N4B9Upy3N4Nz9P/IsbGVlUCJoRlUyLo9J+PrMghdIhTruZyW+R P/1g== X-Gm-Message-State: AFqh2kpiQMjzJNspmM840HxstVhNN4aZYivZziufvTlQqB1nC+2nTx7F wb0WMVT/x1XqFj0KIkzVY8b5WjN6NUqBnZZZzdU= X-Google-Smtp-Source: AMrXdXvWFnFYRTcT8IvBX+R578K2qTe9KKbtdGKXgtbtP7X78kW4Vd1aGjqik8S3omTeAKmCGolvZw== X-Received: by 2002:a9d:4685:0:b0:66e:c096:126c with SMTP id z5-20020a9d4685000000b0066ec096126cmr36461010ote.29.1673381656770; Tue, 10 Jan 2023 12:14:16 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, richard.henderson@linaro.org, Daniel Henrique Barboza Subject: [PATCH 2/2] target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() Date: Tue, 10 Jan 2023 17:14:05 -0300 Message-Id: <20230110201405.247785-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230110201405.247785-1-dbarboza@ventanamicro.com> References: <20230110201405.247785-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1673381773086100001 Content-Type: text/plain; charset="utf-8" All RISCV CPUs are setting cpu->cfg during their cpu_init() functions, meaning that there's no reason to skip all the misa validation and setup if misa_ext was set beforehand - especially since we're setting an updated value in set_misa() in the end. Put this code chunk into a new riscv_cpu_validate_set_extensions() helper and always execute it regardless of what the board set in env->misa_ext. This will put more responsibility in how each board is going to init their attributes and extensions if they're not using the defaults. It'll also allow realize() to do its job looking only at the extensions enabled per se, not corner cases that some CPUs might have, and we won't have to change multiple code paths to fix or change how extensions work. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.c | 485 +++++++++++++++++++++++---------------------- 1 file changed, 248 insertions(+), 237 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b8c1edb7c2..33ed59a1b6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -631,6 +631,250 @@ static void riscv_cpu_disas_set_info(CPUState *s, dis= assemble_info *info) } } =20 +/* + * Check consistency between chosen extensions while setting + * cpu->cfg accordingly, doing a set_misa() in the end. + */ +static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + uint32_t ext =3D 0; + + /* Do some ISA extension error checking */ + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && + cpu->cfg.ext_a && cpu->cfg.ext_f && + cpu->cfg.ext_d && + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { + warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); + cpu->cfg.ext_i =3D true; + cpu->cfg.ext_m =3D true; + cpu->cfg.ext_a =3D true; + cpu->cfg.ext_f =3D true; + cpu->cfg.ext_d =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.ext_ifencei =3D true; + } + + if (cpu->cfg.ext_i && cpu->cfg.ext_e) { + error_setg(errp, + "I and E extensions are incompatible"); + return; + } + + if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { + error_setg(errp, + "Either I or E extension must be set"); + return; + } + + if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { + error_setg(errp, + "Setting S extension without U extension is illegal"); + return; + } + + if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { + error_setg(errp, + "H depends on an I base integer ISA with 32 x registers= "); + return; + } + + if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { + error_setg(errp, "H extension implicitly requires S-mode"); + return; + } + + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { + error_setg(errp, "F extension requires Zicsr"); + return; + } + + if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { + error_setg(errp, "Zawrs extension requires A extension"); + return; + } + + if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { + error_setg(errp, "Zfh/Zfhmin extensions require F extension"); + return; + } + + if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { + error_setg(errp, "D extension requires F extension"); + return; + } + + if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { + error_setg(errp, "V extension requires D extension"); + return; + } + + if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { + error_setg(errp, "Zve32f/Zve64f extensions require F extension"); + return; + } + + /* Set the ISA extensions, checks should have happened above */ + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || + cpu->cfg.ext_zhinxmin) { + cpu->cfg.ext_zfinx =3D true; + } + + if (cpu->cfg.ext_zfinx) { + if (!cpu->cfg.ext_icsr) { + error_setg(errp, "Zfinx extension requires Zicsr"); + return; + } + if (cpu->cfg.ext_f) { + error_setg(errp, + "Zfinx cannot be supported together with F extension"); + return; + } + } + + if (cpu->cfg.ext_c) { + cpu->cfg.ext_zca =3D true; + if (cpu->cfg.ext_f && env->misa_mxl_max =3D=3D MXL_RV32) { + cpu->cfg.ext_zcf =3D true; + } + if (cpu->cfg.ext_d) { + cpu->cfg.ext_zcd =3D true; + } + } + + if (env->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { + error_setg(errp, "Zcf extension is only relevant to RV32"); + return; + } + + if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) { + error_setg(errp, "Zcf extension requires F extension"); + return; + } + + if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) { + error_setg(errp, "Zcd extension requires D extension"); + return; + } + + if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || + cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { + error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " + "extension"); + return; + } + + if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { + error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " + "Zcd extension"); + return; + } + + if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { + error_setg(errp, "Zcmt extension requires Zicsr extension"); + return; + } + + if (cpu->cfg.ext_zk) { + cpu->cfg.ext_zkn =3D true; + cpu->cfg.ext_zkr =3D true; + cpu->cfg.ext_zkt =3D true; + } + + if (cpu->cfg.ext_zkn) { + cpu->cfg.ext_zbkb =3D true; + cpu->cfg.ext_zbkc =3D true; + cpu->cfg.ext_zbkx =3D true; + cpu->cfg.ext_zkne =3D true; + cpu->cfg.ext_zknd =3D true; + cpu->cfg.ext_zknh =3D true; + } + + if (cpu->cfg.ext_zks) { + cpu->cfg.ext_zbkb =3D true; + cpu->cfg.ext_zbkc =3D true; + cpu->cfg.ext_zbkx =3D true; + cpu->cfg.ext_zksed =3D true; + cpu->cfg.ext_zksh =3D true; + } + + if (cpu->cfg.ext_i) { + ext |=3D RVI; + } + if (cpu->cfg.ext_e) { + ext |=3D RVE; + } + if (cpu->cfg.ext_m) { + ext |=3D RVM; + } + if (cpu->cfg.ext_a) { + ext |=3D RVA; + } + if (cpu->cfg.ext_f) { + ext |=3D RVF; + } + if (cpu->cfg.ext_d) { + ext |=3D RVD; + } + if (cpu->cfg.ext_c) { + ext |=3D RVC; + } + if (cpu->cfg.ext_s) { + ext |=3D RVS; + } + if (cpu->cfg.ext_u) { + ext |=3D RVU; + } + if (cpu->cfg.ext_h) { + ext |=3D RVH; + } + if (cpu->cfg.ext_v) { + int vext_version =3D VEXT_VERSION_1_00_0; + ext |=3D RVV; + if (!is_power_of_2(cpu->cfg.vlen)) { + error_setg(errp, + "Vector extension VLEN must be power of 2"); + return; + } + if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { + error_setg(errp, + "Vector extension implementation only supports VLEN " + "in the range [128, %d]", RV_VLEN_MAX); + return; + } + if (!is_power_of_2(cpu->cfg.elen)) { + error_setg(errp, + "Vector extension ELEN must be power of 2"); + return; + } + if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { + error_setg(errp, + "Vector extension implementation only supports ELEN " + "in the range [8, 64]"); + return; + } + if (cpu->cfg.vext_spec) { + if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { + vext_version =3D VEXT_VERSION_1_00_0; + } else { + error_setg(errp, + "Unsupported vector spec version '%s'", + cpu->cfg.vext_spec); + return; + } + } else { + qemu_log("vector version is not specified, " + "use the default value v1.0\n"); + } + set_vext_version(env, vext_version); + } + if (cpu->cfg.ext_j) { + ext |=3D RVJ; + } + + set_misa(env, env->misa_mxl, ext); +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -726,243 +970,10 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) } assert(env->misa_mxl_max =3D=3D env->misa_mxl); =20 - /* If only MISA_EXT is unset for misa, then set it from properties */ - if (env->misa_ext =3D=3D 0) { - uint32_t ext =3D 0; - - /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && - cpu->cfg.ext_a && cpu->cfg.ext_f && - cpu->cfg.ext_d && - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)= ) { - warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_i =3D true; - cpu->cfg.ext_m =3D true; - cpu->cfg.ext_a =3D true; - cpu->cfg.ext_f =3D true; - cpu->cfg.ext_d =3D true; - cpu->cfg.ext_icsr =3D true; - cpu->cfg.ext_ifencei =3D true; - } - - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { - error_setg(errp, - "I and E extensions are incompatible"); - return; - } - - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { - error_setg(errp, - "Either I or E extension must be set"); - return; - } - - if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { - error_setg(errp, - "Setting S extension without U extension is illegal= "); - return; - } - - if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { - error_setg(errp, - "H depends on an I base integer ISA with 32 x regis= ters"); - return; - } - - if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { - error_setg(errp, "H extension implicitly requires S-mode"); - return; - } - - if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { - error_setg(errp, "F extension requires Zicsr"); - return; - } - - if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { - error_setg(errp, "Zawrs extension requires A extension"); - return; - } - - if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { - error_setg(errp, "Zfh/Zfhmin extensions require F extension"); - return; - } - - if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { - error_setg(errp, "D extension requires F extension"); - return; - } - - if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { - error_setg(errp, "V extension requires D extension"); - return; - } - - if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_= f) { - error_setg(errp, "Zve32f/Zve64f extensions require F extension= "); - return; - } - - /* Set the ISA extensions, checks should have happened above */ - if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || - cpu->cfg.ext_zhinxmin) { - cpu->cfg.ext_zfinx =3D true; - } - - if (cpu->cfg.ext_zfinx) { - if (!cpu->cfg.ext_icsr) { - error_setg(errp, "Zfinx extension requires Zicsr"); - return; - } - if (cpu->cfg.ext_f) { - error_setg(errp, - "Zfinx cannot be supported together with F extension"); - return; - } - } - - if (cpu->cfg.ext_c) { - cpu->cfg.ext_zca =3D true; - if (cpu->cfg.ext_f && env->misa_mxl_max =3D=3D MXL_RV32) { - cpu->cfg.ext_zcf =3D true; - } - if (cpu->cfg.ext_d) { - cpu->cfg.ext_zcd =3D true; - } - } - - if (env->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { - error_setg(errp, "Zcf extension is only relevant to RV32"); - return; - } - - if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) { - error_setg(errp, "Zcf extension requires F extension"); - return; - } - - if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) { - error_setg(errp, "Zcd extension requires D extension"); - return; - } - - if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || - cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca)= { - error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca= " - "extension"); - return; - } - - if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { - error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " - "Zcd extension"); - return; - } - - if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { - error_setg(errp, "Zcmt extension requires Zicsr extension"); - return; - } - - if (cpu->cfg.ext_zk) { - cpu->cfg.ext_zkn =3D true; - cpu->cfg.ext_zkr =3D true; - cpu->cfg.ext_zkt =3D true; - } - - if (cpu->cfg.ext_zkn) { - cpu->cfg.ext_zbkb =3D true; - cpu->cfg.ext_zbkc =3D true; - cpu->cfg.ext_zbkx =3D true; - cpu->cfg.ext_zkne =3D true; - cpu->cfg.ext_zknd =3D true; - cpu->cfg.ext_zknh =3D true; - } - - if (cpu->cfg.ext_zks) { - cpu->cfg.ext_zbkb =3D true; - cpu->cfg.ext_zbkc =3D true; - cpu->cfg.ext_zbkx =3D true; - cpu->cfg.ext_zksed =3D true; - cpu->cfg.ext_zksh =3D true; - } - - if (cpu->cfg.ext_i) { - ext |=3D RVI; - } - if (cpu->cfg.ext_e) { - ext |=3D RVE; - } - if (cpu->cfg.ext_m) { - ext |=3D RVM; - } - if (cpu->cfg.ext_a) { - ext |=3D RVA; - } - if (cpu->cfg.ext_f) { - ext |=3D RVF; - } - if (cpu->cfg.ext_d) { - ext |=3D RVD; - } - if (cpu->cfg.ext_c) { - ext |=3D RVC; - } - if (cpu->cfg.ext_s) { - ext |=3D RVS; - } - if (cpu->cfg.ext_u) { - ext |=3D RVU; - } - if (cpu->cfg.ext_h) { - ext |=3D RVH; - } - if (cpu->cfg.ext_v) { - int vext_version =3D VEXT_VERSION_1_00_0; - ext |=3D RVV; - if (!is_power_of_2(cpu->cfg.vlen)) { - error_setg(errp, - "Vector extension VLEN must be power of 2"); - return; - } - if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { - error_setg(errp, - "Vector extension implementation only supports VLE= N " - "in the range [128, %d]", RV_VLEN_MAX); - return; - } - if (!is_power_of_2(cpu->cfg.elen)) { - error_setg(errp, - "Vector extension ELEN must be power of 2"); - return; - } - if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { - error_setg(errp, - "Vector extension implementation only supports ELE= N " - "in the range [8, 64]"); - return; - } - if (cpu->cfg.vext_spec) { - if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { - vext_version =3D VEXT_VERSION_1_00_0; - } else { - error_setg(errp, - "Unsupported vector spec version '%s'", - cpu->cfg.vext_spec); - return; - } - } else { - qemu_log("vector version is not specified, " - "use the default value v1.0\n"); - } - set_vext_version(env, vext_version); - } - if (cpu->cfg.ext_j) { - ext |=3D RVJ; - } - - set_misa(env, env->misa_mxl, ext); + riscv_cpu_validate_set_extensions(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; } =20 #ifndef CONFIG_USER_ONLY --=20 2.39.0