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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id 18-20020a170906201200b00846734faa9asm3925625ejo.164.2023.01.09.09.24.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 09:24:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Md1ht9BenAS9gT+l4PHU2nQxwV72/gQGjTwkecQpBFU=; b=AW9bdWLqcZnbcIrxb0E5y6wx61MwiQ6ykdZSreG9dW6EfVUjDbTv89yH1Bt8ndq2a/ VZogJs3SI4IxDPQ+l7Mjz+ojU/nM1wZpeI6kTc3B6F5P6dJbbVs3x7wk2QV+waxT2Y0I eXXKMHV9ca0MXxTtQC1G8m9b8roJt+ywi+NQfgOcfsXitina+lZBnTr1NBxIv4w57YsX 9qa3PATPDjFYKBha977mEzEJNld0TkMnx39K1+Lkk5+LMQfUHMWQONeC7juiwxJinXmg LsKyMABRv/Sf5Twl4L9O39ysnu7UzHSwdjbF0y+o2WAWJhw4nU2lkZk6oFetCS2RiUd/ R/Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Md1ht9BenAS9gT+l4PHU2nQxwV72/gQGjTwkecQpBFU=; b=inI9052/Q8ZdSsqogwT5RE9kwcg482P19e9IVZW7pcTxLg06eGcEl/+QUDQixXLBf9 KYky0tz2Qw+lVR6iXUgfj/Q0Gbk4b7qMoYBwT589b4QeNlimZNGFPgjlqbQodafvE72H Ebg/1f9PdDUCqnEjC2V9tdMlsTXb+g1mHL/6CYO3vDXjsjZj2Iyiom0DUlq8Nx1r6HDO SfaL9aCCUsAgEJ+51OEuM1oylx6kgGhaHzQMEIpUVUUoUtCWAyExH/UjSTetWPPPBrjn U0yZRW8EFFQ27P8BBeQ0Xf5F+TYA7ArOUO0UYWyrwspL+dVvkbKJBrAiIu9bLkD2pMqz z8aA== X-Gm-Message-State: AFqh2kqbdNKAc1zwVZgzZ6wiHZUzyd+Ojr5XBa4ltYoH9nAaxNw+Uvr4 7Z/QcFHOSReA2zgyOdaYgUb7eGpjW0MUZg== X-Google-Smtp-Source: AMrXdXsVHekHf4tpsraH+oedZ/jA6nZFkTaiJ9nHQkQGJvBqx2k3V59EsWJoFMc3YoThNcQA+NqzWA== X-Received: by 2002:a17:907:c70c:b0:81e:9027:dedc with SMTP id ty12-20020a170907c70c00b0081e9027dedcmr56100887ejc.39.1673285092522; Mon, 09 Jan 2023 09:24:52 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: John G Johnson , Richard Henderson , Igor Mammedov , Elena Ufimtseva , Ani Sinha , Eduardo Habkost , Gerd Hoffmann , Jagannathan Raman , "Michael S. Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= Subject: [PATCH v6 01/33] hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition Date: Mon, 9 Jan 2023 18:23:14 +0100 Message-Id: <20230109172347.1830-2-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=shentey@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285228352100002 From: Philippe Mathieu-Daud=C3=A9 The PIIX4 PCI-ISA bridge function is always located at 10:0. Since we want to re-use its address, add the PIIX4_PCI_DEVFN definition. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20221027204720.33611-2-philmd@linaro.org> --- hw/mips/malta.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index c0a2e0ab04..9bffa1b128 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -71,6 +71,8 @@ =20 #define FLASH_SIZE 0x400000 =20 +#define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0) + typedef struct { MemoryRegion iomem; MemoryRegion iomem_lo; /* 0 - 0x900 */ @@ -1401,7 +1403,7 @@ void mips_malta_init(MachineState *machine) empty_slot_init("GT64120", 0, 0x20000000); =20 /* Southbridge */ - piix4 =3D pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), t= rue, + piix4 =3D pci_create_simple_multifunction(pci_bus, PIIX4_PCI_DEVFN, tr= ue, TYPE_PIIX4_PCI_DEVICE); isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); =20 --=20 2.39.0 From nobody Sun May 19 05:00:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673285677; cv=none; d=zohomail.com; s=zohoarc; b=QivoXAk0KiDS7RVGA3taBBxKpW1/JxeUQK+jecLujzutsJDI1QEMNDCsO8qDgPlxennlQOlrpw997R58iIpfEG+EVxLqfGzP6UT8fPC/9BkgyBnNwDbi3iR+optdpvfbkD074GQbCireQJHO9ySc248Pz4cWcRUUqWzm+vx09mc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673285677; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yD2Nt3sc65GXyJk9LaQMyT8j1pCfMA2t4DX/1jlVSvA=; b=fSAR5SwWqUZSpvbVUHQGCj8zM+c7K6K5e9t+/Q969dygWkEgkjSLVsqiwQAS7hSvlWYr4qljLE80oo1UVfWQCsJWi1T7i91dXM3qh0JaM+cfHFtoItemhuN4ghcbmKvYHbJTDmajELWEygA/6Hq62VVPsZwglWoeIghAQIaV0l8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673285677481788.0231962208194; Mon, 9 Jan 2023 09:34:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEvtM-0002RF-EZ; Mon, 09 Jan 2023 12:25:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEvtK-0002PF-Na; Mon, 09 Jan 2023 12:24:58 -0500 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEvtI-0000yw-Lm; Mon, 09 Jan 2023 12:24:58 -0500 Received: by mail-ej1-x62d.google.com with SMTP id fy8so21837643ejc.13; Mon, 09 Jan 2023 09:24:55 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id 18-20020a170906201200b00846734faa9asm3925625ejo.164.2023.01.09.09.24.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 09:24:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yD2Nt3sc65GXyJk9LaQMyT8j1pCfMA2t4DX/1jlVSvA=; b=YPvx685NNHH+OeuQABNKzGkOQCepCahtqtF9labqsDeGjCw3pZUR7W5Y5voZuJd3O9 Yr78SR/DXEgjLo9qoDuHNtQXMxkk02EVsKogkbA/TFl49sfmOdOQCIjD63RNBe+CYsSj BhoUImI3A6rIsNP4wpdfVlmm+jCKxgxp9xIOCcoNq+zt4p6UseNzQ0pW/aZE4m6FsX2r 6kE2pJTwnoJ359v7KAAEqjWtoQ6K08p1TltVw9exrhu/5kZUqjgg1nClVL6fQGGLYRFa /gXHUdjkN2fa274gCalsscGd2QjAnUlEDxdUxJhNPE/8vV+O5NvEyGEgmJ5CIQPJ7y2P ZRqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yD2Nt3sc65GXyJk9LaQMyT8j1pCfMA2t4DX/1jlVSvA=; b=5MFquZxLs9Gs6K4T1eRAPPYeTBRdwPyVPzeLOLRrw0iitshK85y6XFc4REKGfj3rmi mATE+MGZ3Rnmtv6gJWFi9TadyvcSP9smXt5CFZAY2Sn1BhkBzTyVISVRSkjbP+eRvazQ ViNaULIfZAgo2ax2Z5/e58nsBGzIWlLdJtAZXKq3lVx5yxikBo2a8wMu2JO2IUA5RWqE y04IA48h4PMkC5BePUBo86geLxzRjadJp7haYWbmDUS1+Dc9dQMD27ay6ZHQvoPnLYu2 BVVdnyNJzHNFxo6GvC4U1c3WPJ7bdFGTJzViPqmqWbgRNk8ml6QLrDFkIgYY8cJcHQpY hSZw== X-Gm-Message-State: AFqh2kqRwheo6kSrwTixgvAFMUwzmO4j8z9d5kkKtMO/g59/q5Rna86f YvUErIM+tUVMzoS+5Mn0oRLuOAWC9u7/Dg== X-Google-Smtp-Source: AMrXdXu+g9udVWr60xRBp3fM/6En2UTIuhOFvhIREU4I1g0Ed6OCTdaSlvUBPFXb2UCbHuuw9/5HCw== X-Received: by 2002:a17:906:3993:b0:844:de87:8684 with SMTP id h19-20020a170906399300b00844de878684mr64741397eje.46.1673285094028; Mon, 09 Jan 2023 09:24:54 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: John G Johnson , Richard Henderson , Igor Mammedov , Elena Ufimtseva , Ani Sinha , Eduardo Habkost , Gerd Hoffmann , Jagannathan Raman , "Michael S. Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= Subject: [PATCH v6 02/33] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader Date: Mon, 9 Jan 2023 18:23:15 +0100 Message-Id: <20230109172347.1830-3-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=shentey@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285679796100003 From: Philippe Mathieu-Daud=C3=A9 Linux kernel expects the northbridge & southbridge chipsets configured by the BIOS firmware. We emulate that by writing a tiny bootloader code in write_bootloader(). Upon introduction in commit 5c2b87e34d ("PIIX4 support"), the PIIX4 configuration space included values specific to the Malta board. Set the Malta-specific IRQ routing values in the embedded bootloader, so the next commit can remove the Malta specific bits from the PIIX4 PCI-ISA bridge and make it generic (matching the real hardware). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20221027204720.33611-3-philmd@linaro.org> --- hw/mips/malta.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 9bffa1b128..c3dcd43f37 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -803,6 +803,8 @@ static void write_bootloader_nanomips(uint8_t *base, ui= nt64_t run_addr, stw_p(p++, 0x8422); stw_p(p++, 0x9088); /* sw t0, 0x88(t1) */ =20 + /* TODO set PIIX IRQC[A:D] routing values! */ + stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); =20 stw_p(p++, NM_HI2(kernel_entry)); @@ -840,6 +842,9 @@ static void write_bootloader_nanomips(uint8_t *base, ui= nt64_t run_addr, static void write_bootloader(uint8_t *base, uint64_t run_addr, uint64_t kernel_entry) { + const char pci_pins_cfg[PCI_NUM_PINS] =3D { + 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ + }; uint32_t *p; =20 /* Small bootloader */ @@ -914,6 +919,20 @@ static void write_bootloader(uint8_t *base, uint64_t r= un_addr, =20 #undef cpu_to_gt32 =20 + /* + * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0. + * Load the PIIX IRQC[A:D] routing config address, then + * write routing configuration to the config data register. + */ + bl_gen_write_u32(&p, /* GT_PCI0_CFGADDR */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), + tswap32((1 << 31) /* ConfigEn */ + | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 + | PIIX_PIRQCA)); + bl_gen_write_u32(&p, /* GT_PCI0_CFGDATA */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), + tswap32(ldl_be_p(pci_pins_cfg))); + bl_gen_jump_kernel(&p, true, ENVP_VADDR - 64, /* --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673286378; cv=none; d=zohomail.com; s=zohoarc; b=DsKJgZAauqjMB+hTU6DReHh/zuBeV3t/WPFzqdn3CdS7cuvS4h5joSyAEJb6XnyXc+dIA9juH8NBj81NBXQaDlzceAwFclPiM4K+0GFSzd0U5LRD/Grt3J8aeaMy8QIKtBQajZBURUrxEKRsgkyk//1veiTduqk9FPMN53KaR3k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673286378; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=b0zxx8tPOrJ/ctNq1xpYzBZctNT1tt/hlM+VII09Kv0=; b=XduCY0Dj9z6+h/Ay+tPtQCHXivgq/leZOQ/TYG96EK1P8aSf+PbFZ+98SJutBxEYirxlvC3q+qDk1wdseQd3ZABZrBXk7q+GJLetWUAouTakw7c1ZH1U6sNbKmSDtufdB8TixpAkrq9slpWGf06ev22hWn/WeS3JDUor9EqVcUI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16732863784901000.7778960324043; Mon, 9 Jan 2023 09:46:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEvtN-0002RW-AK; Mon, 09 Jan 2023 12:25:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEvtL-0002QB-IM; Mon, 09 Jan 2023 12:24:59 -0500 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEvtJ-0000zU-Qg; Mon, 09 Jan 2023 12:24:59 -0500 Received: by mail-ej1-x62e.google.com with SMTP id vm8so21929901ejc.2; Mon, 09 Jan 2023 09:24:56 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= Subject: [PATCH v6 03/33] hw/isa/piix4: Correct IRQRC[A:D] reset values Date: Mon, 9 Jan 2023 18:23:16 +0100 Message-Id: <20230109172347.1830-4-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=shentey@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673286380338100001 From: Philippe Mathieu-Daud=C3=A9 IRQRC[A:D] registers reset value is 0x80. We were forcing the MIPS Malta machine routing to be able to boot a Linux kernel without any bootloader. We now have these registers initialized in the Malta machine write_bootloader(), so we can use the correct reset values. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20221027204720.33611-4-philmd@linaro.org> --- hw/isa/piix4.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 8fc1db6dc9..0d23e11a39 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -116,10 +116,10 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0x4c] =3D 0x4d; pci_conf[0x4e] =3D 0x03; pci_conf[0x4f] =3D 0x00; - pci_conf[0x60] =3D 0x0a; // PCI A -> IRQ 10 - pci_conf[0x61] =3D 0x0a; // PCI B -> IRQ 10 - pci_conf[0x62] =3D 0x0b; // PCI C -> IRQ 11 - pci_conf[0x63] =3D 0x0b; // PCI D -> IRQ 11 + pci_conf[0x60] =3D 0x80; + pci_conf[0x61] =3D 0x80; + pci_conf[0x62] =3D 0x80; + pci_conf[0x63] =3D 0x80; pci_conf[0x69] =3D 0x02; pci_conf[0x70] =3D 0x80; pci_conf[0x76] =3D 0x0c; --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673286442; cv=none; d=zohomail.com; s=zohoarc; b=kzzxpDz8QKTXr9ylF/eF2sm1pb2JmfjZ/YAVBGNa79bZ87JKwhfdTiKxGN2CILRRgp17RS2bWPi/8zBEjFZ7VYNvMQoTMtYJBDM75iI8OOD3lEw/Ep/vsoJlCpRhzXILhmsiwZP9HDqeZt0kqIurtsVO/8rhWhGYXXQDrXAQwfM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673286442; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8jrOub/s1hNNY+Y6dIq5uqtkEpcH/mb81af1xqTfykQ=; b=dZxus/rA+qfJ9ouxR77UFoZ0w/ABNP4miiYfdjIEnWLcPAbFk9uUfcFDA5/knjIbpubyuVUcFAs6N8nEqaoo4+8C9kE3ELqWjrtCYjEqKR2lAc9N0a3enBGOcoBAEzYom4TZbEh3RSJk4T1eKCt3S8ssjtOa9iIFdEXnl1P6jTI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673286442212571.354330668483; Mon, 9 Jan 2023 09:47:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEvtR-0002Vp-Do; Mon, 09 Jan 2023 12:25:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEvtN-0002Ra-Bd; Mon, 09 Jan 2023 12:25:01 -0500 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEvtL-0000zp-73; Mon, 09 Jan 2023 12:25:01 -0500 Received: by mail-ej1-x629.google.com with SMTP id fy8so21837879ejc.13; Mon, 09 Jan 2023 09:24:57 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 04/33] hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs() Date: Mon, 9 Jan 2023 18:23:17 +0100 Message-Id: <20230109172347.1830-5-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=shentey@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673286442938100001 pci_bus_irqs() coupled together the assignment of pci_set_irq_fn and pci_map_irq_fn to a PCI bus. This coupling gets in the way when the pci_map_irq_fn is board-specific while the pci_set_irq_fn is device- specific. For example, both of QEMU's PIIX south bridge models have different pci_map_irq_fn implementations which are board-specific rather than device-specific. These implementations should therefore reside in board code. The pci_set_irq_fn's, however, should stay in the device models because they access memory internal to the model. Factoring out pci_bus_map_irqs() from pci_bus_irqs() allows the assignments to be decoupled, resolving the problem described above. Note also how pci_vpb_realize() which gets touched in this commit assigns different pci_map_irq_fn's depending on the board. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/pci/pci.h | 3 ++- hw/i386/pc_q35.c | 4 ++-- hw/isa/piix3.c | 8 ++++---- hw/isa/piix4.c | 3 ++- hw/pci-host/raven.c | 3 ++- hw/pci-host/versatile.c | 3 ++- hw/pci/pci.c | 12 +++++++++--- hw/remote/machine.c | 3 ++- 8 files changed, 25 insertions(+), 14 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 7048a373d1..85ee458cd2 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -282,8 +282,9 @@ PCIBus *pci_root_bus_new(DeviceState *parent, const cha= r *name, MemoryRegion *address_space_io, uint8_t devfn_min, const char *typename); void pci_root_bus_cleanup(PCIBus *bus); -void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_= irq, +void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, void *irq_opaque, int nirq); +void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq); void pci_bus_irqs_cleanup(PCIBus *bus); int pci_bus_get_irq_level(PCIBus *bus, int irq_num); /* 0 <=3D pin <=3D 3 0 =3D INTA, 1 =3D INTB, 2 =3D INTC, 3 =3D INTD */ diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 67ceb04bcc..65ea226211 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -268,8 +268,8 @@ static void pc_q35_init(MachineState *machine) for (i =3D 0; i < GSI_NUM_PINS; i++) { qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[= i]); } - pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, - ICH9_LPC_NB_PIRQS); + pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc, ICH9_LPC_NB_PIRQS); + pci_bus_map_irqs(host_bus, ich9_lpc_map_irq); pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); isa_bus =3D ich9_lpc->isa_bus; =20 diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index eabad7ba58..666e794f77 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -384,8 +384,8 @@ static void piix3_realize(PCIDevice *dev, Error **errp) return; } =20 - pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, - piix3, PIIX_NUM_PIRQS); + pci_bus_irqs(pci_bus, piix3_set_irq, piix3, PIIX_NUM_PIRQS); + pci_bus_map_irqs(pci_bus, pci_slot_get_pirq); pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); } =20 @@ -420,8 +420,8 @@ static void piix3_xen_realize(PCIDevice *dev, Error **e= rrp) * connected to the IOAPIC directly. * These additional routes can be discovered through ACPI. */ - pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq, - piix3, XEN_PIIX_NUM_PIRQS); + pci_bus_irqs(pci_bus, xen_piix3_set_irq, piix3, XEN_PIIX_NUM_PIRQS); + pci_bus_map_irqs(pci_bus, xen_pci_slot_get_pirq); } =20 static void piix3_xen_class_init(ObjectClass *klass, void *data) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 0d23e11a39..9c79c9677b 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -271,7 +271,8 @@ static void piix4_realize(PCIDevice *dev, Error **errp) } qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]); =20 - pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PI= RQS); + pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); + pci_bus_map_irqs(pci_bus, pci_slot_get_pirq); } =20 static void piix4_init(Object *obj) diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c index 2c96ddf8fe..5b00b4e462 100644 --- a/hw/pci-host/raven.c +++ b/hw/pci-host/raven.c @@ -258,7 +258,8 @@ static void raven_pcihost_realizefn(DeviceState *d, Err= or **errp) =20 qdev_init_gpio_in(d, raven_change_gpio, 1); =20 - pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s, PCI_NUM_PIN= S); + pci_bus_irqs(&s->pci_bus, raven_set_irq, s, PCI_NUM_PINS); + pci_bus_map_irqs(&s->pci_bus, raven_map_irq); =20 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, = s, "pci-conf-idx", 4); diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c index 0d50ea4cc0..60d4e7cd92 100644 --- a/hw/pci-host/versatile.c +++ b/hw/pci-host/versatile.c @@ -422,7 +422,8 @@ static void pci_vpb_realize(DeviceState *dev, Error **e= rrp) mapfn =3D pci_vpb_map_irq; } =20 - pci_bus_irqs(&s->pci_bus, pci_vpb_set_irq, mapfn, s->irq, 4); + pci_bus_irqs(&s->pci_bus, pci_vpb_set_irq, s->irq, 4); + pci_bus_map_irqs(&s->pci_bus, mapfn); =20 /* Our memory regions are: * 0 : our control registers diff --git a/hw/pci/pci.c b/hw/pci/pci.c index c2fb88f9a3..39a7bb32aa 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -280,6 +280,7 @@ static void pci_change_irq_level(PCIDevice *pci_dev, in= t irq_num, int change) PCIBus *bus; for (;;) { bus =3D pci_get_bus(pci_dev); + assert(bus->map_irq); irq_num =3D bus->map_irq(pci_dev, irq_num); if (bus->set_irq) break; @@ -518,16 +519,20 @@ void pci_root_bus_cleanup(PCIBus *bus) qbus_unrealize(BUS(bus)); } =20 -void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_= irq, +void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, void *irq_opaque, int nirq) { bus->set_irq =3D set_irq; - bus->map_irq =3D map_irq; bus->irq_opaque =3D irq_opaque; bus->nirq =3D nirq; bus->irq_count =3D g_malloc0(nirq * sizeof(bus->irq_count[0])); } =20 +void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq) +{ + bus->map_irq =3D map_irq; +} + void pci_bus_irqs_cleanup(PCIBus *bus) { bus->set_irq =3D NULL; @@ -549,7 +554,8 @@ PCIBus *pci_register_root_bus(DeviceState *parent, cons= t char *name, =20 bus =3D pci_root_bus_new(parent, name, address_space_mem, address_space_io, devfn_min, typename); - pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); + pci_bus_irqs(bus, set_irq, irq_opaque, nirq); + pci_bus_map_irqs(bus, map_irq); return bus; } =20 diff --git a/hw/remote/machine.c b/hw/remote/machine.c index 75d550daae..519f855ec1 100644 --- a/hw/remote/machine.c +++ b/hw/remote/machine.c @@ -63,8 +63,9 @@ static void remote_machine_init(MachineState *machine) } else { remote_iohub_init(&s->iohub); =20 - pci_bus_irqs(pci_host->bus, remote_iohub_set_irq, remote_iohub_map= _irq, + pci_bus_irqs(pci_host->bus, remote_iohub_set_irq, &s->iohub, REMOTE_IOHUB_NB_PIRQS); + pci_bus_map_irqs(pci_host->bus, remote_iohub_map_irq); } =20 qbus_set_hotplug_handler(BUS(pci_host->bus), OBJECT(s)); --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673285153; cv=none; d=zohomail.com; s=zohoarc; b=KifRRsgX0UIZTQZR7jFgUBRJhk+io71kRsG4AIItnEdnUk2/PEkwoAsesBeqx/yPyqZXBu4REjyhJ2vrPkTDMbeFuN7ajcb7RaGXIQCIrUnWJ9TCVMX7alsq/0wdBblXBWpWbwnBiNSfWQneje7u5pov9yAHAzqgwW+ZcjRo1E0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673285153; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id 18-20020a170906201200b00846734faa9asm3925625ejo.164.2023.01.09.09.24.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 09:24:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KdSAwJSzEqA+I9v6UkRG9aJr/cFnqZhXxsUKNpwRs1s=; b=R+VnQQ6LUC+pO4dLmxA3NqVLJS5HBrGbqhdTvfXXOlQn5/6LcIX5N9RBFya7gIX7Oq JY5ULQRoySzHrZqOIJ3v2Aiz4tZmZ+7tcvaZHZ5h3tsKW6YEN2xgMMR/0U6gxJqRfoFy woEJA5RW01iv/R/+MAo2gCDFE39+UMQ7Eudl6WjL7IhmRM7YDTV0BcYRNhpTx8wYfO1/ /y456Q6U7ESNaUyTMUJPIQF+Ldm4UK+MvpOH0+63bGvtgfHvIISpc3CqOBT3OaSradoW 0HeKrrV2Xj0Xo/L2now4YBEQPmOh0zXWcvjtGbcPBgYF/EpHj0qKF2H+kqbtX2os+bPG V9rQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KdSAwJSzEqA+I9v6UkRG9aJr/cFnqZhXxsUKNpwRs1s=; b=KvIL8Up+zHArphPCJe68Qp2sed1Aw2ZviDmfYVogQYlR68WfkSAFhm8nlJNiIIt4r6 gYsCND0jJMEKkltlkgx7xOPwf1RmLgt8Ly9dfa3hQOsZSjgypncw18b0aC1kE8Im/Av5 mDCamCq13nPQvGnPmITg9VHXfiCuJR5x7Ybqn3HBLwtkfZTfaE2Tr+aZDuf+B3TPmWWp u7tBe2wj4kLfIvi6NKUhdpsS+1lI30A4lnJbVFaUqEbxVmBawqL2FEGFNtw0CuwTNbjQ 6Fow+EnPG+NgZwFFcHeUZZrQuIDVp4jL2KgQTLPBShAN5U59ZWbgbN8JbtFM/zKlWgTR P/lA== X-Gm-Message-State: AFqh2krFCbA19e7iSd7M4gvveeUz5RaQ2NboXDLcwqwmTgnLV/E/A2AT p3XPfCYnteBsz4Upm9gFzY0vu+iAV2f8Sg== X-Google-Smtp-Source: AMrXdXugRPYnRnPa4GA0niab/ga9uEHI0s3eQN8mgdOtvdpf/8NRVad6NbXEZWAmHfPUZVyxbFmPqg== X-Received: by 2002:a17:907:a488:b0:84d:2171:d79 with SMTP id vp8-20020a170907a48800b0084d21710d79mr11353631ejc.54.1673285097362; Mon, 09 Jan 2023 09:24:57 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: John G Johnson , Richard Henderson , Igor Mammedov , Elena Ufimtseva , Ani Sinha , Eduardo Habkost , Gerd Hoffmann , Jagannathan Raman , "Michael S. Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 05/33] hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific Date: Mon, 9 Jan 2023 18:23:18 +0100 Message-Id: <20230109172347.1830-6-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=shentey@gmail.com; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285155882100003 pci_map_irq_fn's in general seem to be board-specific. So move PIIX3's pci_slot_get_pirq() to board code to not have PIIX3 make assuptions about its board. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/i386/pc_piix.c | 15 +++++++++++++++ hw/isa/piix3.c | 13 ------------- 2 files changed, 15 insertions(+), 13 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index b48047f50c..bb3b10557f 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -47,6 +47,7 @@ #include "hw/sysbus.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/xen/xen-x86.h" +#include "hw/xen/xen.h" #include "exec/memory.h" #include "hw/acpi/acpi.h" #include "hw/acpi/piix4.h" @@ -73,6 +74,17 @@ static const int ide_iobase2[MAX_IDE_BUS] =3D { 0x3f6, 0= x376 }; static const int ide_irq[MAX_IDE_BUS] =3D { 14, 15 }; #endif =20 +/* + * Return the global irq number corresponding to a given device irq + * pin. We could also use the bus number to have a more precise mapping. + */ +static int pc_pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) +{ + int slot_addend; + slot_addend =3D PCI_SLOT(pci_dev->devfn) - 1; + return (pci_intx + slot_addend) & 3; +} + /* PC hardware initialisation */ static void pc_init1(MachineState *machine, const char *host_type, const char *pci_type) @@ -216,6 +228,9 @@ static void pc_init1(MachineState *machine, x86ms->below_4g_mem_size, x86ms->above_4g_mem_size, pci_memory, ram_memory); + pci_bus_map_irqs(pci_bus, + xen_enabled() ? xen_pci_slot_get_pirq + : pc_pci_slot_get_pirq); pcms->bus =3D pci_bus; =20 pci_dev =3D pci_create_simple_multifunction(pci_bus, -1, true, typ= e); diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 666e794f77..283b971ec4 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -79,17 +79,6 @@ static void piix3_set_irq(void *opaque, int pirq, int le= vel) piix3_set_irq_level(piix3, pirq, level); } =20 -/* - * Return the global irq number corresponding to a given device irq - * pin. We could also use the bus number to have a more precise mapping. - */ -static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) -{ - int slot_addend; - slot_addend =3D PCI_SLOT(pci_dev->devfn) - 1; - return (pci_intx + slot_addend) & 3; -} - static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { PIIX3State *piix3 =3D opaque; @@ -385,7 +374,6 @@ static void piix3_realize(PCIDevice *dev, Error **errp) } =20 pci_bus_irqs(pci_bus, piix3_set_irq, piix3, PIIX_NUM_PIRQS); - pci_bus_map_irqs(pci_bus, pci_slot_get_pirq); pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); } =20 @@ -421,7 +409,6 @@ static void piix3_xen_realize(PCIDevice *dev, Error **e= rrp) * These additional routes can be discovered through ACPI. */ pci_bus_irqs(pci_bus, xen_piix3_set_irq, piix3, XEN_PIIX_NUM_PIRQS); - pci_bus_map_irqs(pci_bus, xen_pci_slot_get_pirq); } =20 static void piix3_xen_class_init(ObjectClass *klass, void *data) --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673285227; cv=none; d=zohomail.com; s=zohoarc; b=EcAhn0ReOW+7q2zKUnAZHjmxPx4vefq7B4OGz3ljaTBvoiJbtXwcDJV/O2acVadF7A4CW8R0Rqfz0vJXiUGlfAY/p9OrWcyLWA8HHoOW07KtBp4OIsLPRXrNYKBrmLNE4XlbJL2x+WxZIi0UTjyyLXVdS+TQxn20w+iK8q/xOsY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673285227; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HFZLkOaHIgvv7qhFZA095vQcTQAdXZAkOVZq4bJbsfE=; b=BllI/Agx7bS9kyeXiVvK73Y3c/x8ybWlLDRekpcvxP/ZBv3ohkzYxZmrd7sbCAMuNF5q2iGGnpFuceV3iIhlSNCfAv5X+RPVZVuYE+iRJUJeZrc11JLwub8Nysxav9hJ7qJJXjA6e7+jYn0G9Eil8U3K/seTOyvoEXonCHDBNGQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673285227935385.3915932230781; Mon, 9 Jan 2023 09:27:07 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEvtS-0002XQ-K2; Mon, 09 Jan 2023 12:25:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEvtQ-0002V6-JW; Mon, 09 Jan 2023 12:25:04 -0500 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEvtN-00011P-Iz; Mon, 09 Jan 2023 12:25:03 -0500 Received: by mail-ej1-x62a.google.com with SMTP id az20so2851990ejc.1; Mon, 09 Jan 2023 09:25:00 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id 18-20020a170906201200b00846734faa9asm3925625ejo.164.2023.01.09.09.24.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 09:24:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HFZLkOaHIgvv7qhFZA095vQcTQAdXZAkOVZq4bJbsfE=; b=g9araM3lg2wNSJzfp7RczUUcwINUOSLD3Mo8jgyiqMVkWwqFW6JCD05juS6vcquNgx fHYW9hidr6/St7fjR8rTIwyzRXsNXsPIFJjHQJK8zAIbjj2UOlAJ0HkQNLSTaJWALMtX etiB3VmGqS5P0J3klKnroOJFsnVxu8M6DnSFahYchELEO09vZKDwl6PwM+byHwvjZp2w 8VXG2Tfl0ebk3KwL1w3p0Nrfh/BtYDfj/KxtTKgGBVYwi5s5+igyRT5OVjiU93iLv8x8 Nx3W9+LSUkdTZjMPlLaW5Zi+PRxzWyJeHo0ljR/iOJ/E7UYL8nOMDVmhlniFS6sZTGfY GZ1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HFZLkOaHIgvv7qhFZA095vQcTQAdXZAkOVZq4bJbsfE=; b=iwCX6q2vg7fgK3zCtLLsGnBf0AGFuIHgYtiHa+0ms6VvzDra5G7cwjMfgXJILXPtNy aMCQZUNjhOOzrL+QJkOEj+zidQjecmFQeO0PVYkNW5y4IggA63Qw3n8iQHZXZscmjd9c d8W06DJryxlmGddo3RBsvelcJ9u/DKtNg5DGrXcSw/+Ov3zlEVWGsaU3Xpk+YYd4ar/I oVe74WNHeZwb/sVVEpF9fKo/5kaUtWKsmxQSgTzntBLpGTGcVrwjXLtJsDQvmufZNn8f 8giZafKJ84Wc0OokKhM3Oy1QGeckBoD6/6wOERm+KrJzMeoWqKV3KRyHR0X9BHuMiN06 DZxw== X-Gm-Message-State: AFqh2krPUot9ZgqaHLGy81KB2chMoBMbNDvPmA5xymC5r/a9bTeFlmDA ey+A+lIMD4uNFTXIMG2QIuayAbCTDrlFXg== X-Google-Smtp-Source: AMrXdXutevugZNah43TQK1WxTCGu9IZqHbGVJ6UuSfI0k3nFmawfb7leXuGcprbwJz5QhsSiRLRQfg== X-Received: by 2002:a17:906:2859:b0:7c1:32:3574 with SMTP id s25-20020a170906285900b007c100323574mr45893559ejc.12.1673285098622; Mon, 09 Jan 2023 09:24:58 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: John G Johnson , Richard Henderson , Igor Mammedov , Elena Ufimtseva , Ani Sinha , Eduardo Habkost , Gerd Hoffmann , Jagannathan Raman , "Michael S. Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 06/33] hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific Date: Mon, 9 Jan 2023 18:23:19 +0100 Message-Id: <20230109172347.1830-7-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=shentey@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285228344100001 pci_map_irq_fn's in general seem to be board-specific, and PIIX4's pci_slot_get_pirq() in particular seems very Malta-specific. So move the latter to malta.c to 1/ keep the board logic in one place and 2/ avoid PIIX4 to make assumptions about its board. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/isa/piix4.c | 26 -------------------------- hw/mips/malta.c | 27 +++++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 26 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 9c79c9677b..6e9434129d 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -79,31 +79,6 @@ static void piix4_set_irq(void *opaque, int irq_num, int= level) } } =20 -static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) -{ - int slot; - - slot =3D PCI_SLOT(pci_dev->devfn); - - switch (slot) { - /* PIIX4 USB */ - case 10: - return 3; - /* AMD 79C973 Ethernet */ - case 11: - return 1; - /* Crystal 4281 Sound */ - case 12: - return 2; - /* PCI slot 1 to 4 */ - case 18 ... 21: - return ((slot - 18) + irq_num) & 0x03; - /* Unknown device, don't do any translation */ - default: - return irq_num; - } -} - static void piix4_isa_reset(DeviceState *dev) { PIIX4State *d =3D PIIX4_PCI_DEVICE(dev); @@ -272,7 +247,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]); =20 pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); - pci_bus_map_irqs(pci_bus, pci_slot_get_pirq); } =20 static void piix4_init(Object *obj) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index c3dcd43f37..94d4c49bf5 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -39,6 +39,7 @@ #include "hw/mips/bootloader.h" #include "hw/mips/cpudevs.h" #include "hw/pci/pci.h" +#include "hw/pci/pci_bus.h" #include "qemu/log.h" #include "hw/mips/bios.h" #include "hw/ide/pci.h" @@ -1161,6 +1162,31 @@ static void malta_mips_config(MIPSCPU *cpu) } } =20 +static int malta_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) +{ + int slot; + + slot =3D PCI_SLOT(pci_dev->devfn); + + switch (slot) { + /* PIIX4 USB */ + case 10: + return 3; + /* AMD 79C973 Ethernet */ + case 11: + return 1; + /* Crystal 4281 Sound */ + case 12: + return 2; + /* PCI slot 1 to 4 */ + case 18 ... 21: + return ((slot - 18) + irq_num) & 0x03; + /* Unknown device, don't do any translation */ + default: + return irq_num; + } +} + static void main_cpu_reset(void *opaque) { MIPSCPU *cpu =3D opaque; @@ -1414,6 +1440,7 @@ void mips_malta_init(MachineState *machine) /* Northbridge */ dev =3D sysbus_create_simple("gt64120", -1, NULL); pci_bus =3D PCI_BUS(qdev_get_child_bus(dev, "pci")); + pci_bus_map_irqs(pci_bus, malta_pci_slot_get_pirq); /* * The whole address space decoded by the GT-64120A doesn't generate * exception when accessing invalid memory. Create an empty slot to --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673285166; cv=none; d=zohomail.com; s=zohoarc; b=DyXK6CbFxeCBo8i0rp8fEN6Gxl9w76sRVG47sZBOiIcroDcvkrMgWmCQPXaBXJnt9rWcvQARe4/76pQC6oL2ynVsQRFRZGXDByn4g8zv47HiC04R9wvIlwdz9LDMhC0FjY8P7cxgHcDFb5z0aMmjJo91EiG8iwCLASgCcsfxLXo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673285166; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=p6J2v0tgeCkV2MZ5+hrgzpQYTQ8Rtc49tSsYVauuw7Y=; b=ICncXt2AzREsoWip8Ugp3uaalimuyoPCtfZFpjzqWH4uTof/eDqpSHYSzgRzNVi51f7DeAud80HLW86iJP2q7KEZ3aTUjKii72ydttTD5r7HcHeMvNcjD8BKixt3mYx4pNwOGknLWVIEtVcEEU0oos6QaIG5KKx0oP5n8oKWMds= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673285166302866.702313786514; Mon, 9 Jan 2023 09:26:06 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEvtT-0002Yt-Hi; Mon, 09 Jan 2023 12:25:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEvtQ-0002VN-Oz; Mon, 09 Jan 2023 12:25:04 -0500 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEvtO-00011o-M9; Mon, 09 Jan 2023 12:25:04 -0500 Received: by mail-ej1-x634.google.com with SMTP id ss4so14653060ejb.11; Mon, 09 Jan 2023 09:25:00 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 07/33] hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig Date: Mon, 9 Jan 2023 18:23:20 +0100 Message-Id: <20230109172347.1830-8-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=shentey@gmail.com; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285167951100003 Tracking dependencies via Kconfig seems much cleaner. Note that PIIX4 already depends on ACPI_PIIX4. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Michael S. Tsirkin --- configs/devices/mips-softmmu/common.mak | 2 -- hw/mips/Kconfig | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/configs/devices/mips-softmmu/common.mak b/configs/devices/mips= -softmmu/common.mak index 88aff94625..8ed6b62ae7 100644 --- a/configs/devices/mips-softmmu/common.mak +++ b/configs/devices/mips-softmmu/common.mak @@ -17,9 +17,7 @@ CONFIG_I8254=3Dy CONFIG_PCSPK=3Dy CONFIG_PCKBD=3Dy CONFIG_FDC=3Dy -CONFIG_ACPI_PIIX4=3Dy CONFIG_I8257=3Dy -CONFIG_PIIX4=3Dy CONFIG_IDE_ISA=3Dy CONFIG_PFLASH_CFI01=3Dy CONFIG_I8259=3Dy diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index 725525358d..4e7042f03d 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -1,6 +1,7 @@ config MALTA bool select ISA_SUPERIO + select PIIX4 =20 config MIPSSIM bool --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673285782; cv=none; d=zohomail.com; s=zohoarc; b=PMAacFfQPkKbOeGk5wRpDqML0mrmIc9YQCWggiqYtB6QWsYxIK8Q2xGDw16CkaWdFnx5rDZylYKEtJXIdcKhjlG8+PWlE9QgDDoYGQ7WGAUgetQnxY0qRo7QSqkPErJPTTy1F6BPnuaRoxZevk+grXJvxoF0MxUV1qEUcqM9pWw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673285782; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PbEEYbX4NaIwLmsFYjtNVSJvUS1kjPfAvN1bwZmGWzk=; b=Ywr5rjd/c7AjAIa+DMwMXGTpGwNaNw1aP+u+3UttXmjOA9QGgpdi/0GrX7XozXM+hbOtlP4M89iRNdAqrZ9blAR1YqtaRvSlpcdgHsQOpQn1r3ayIABCh8CXmMACSGUfLOcnQyBMDBPCAKkIBQl/hOKt4c36IkfRw6egsqYHe90= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167328578255565.63935499941442; Mon, 9 Jan 2023 09:36:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEvtW-0002cL-7u; Mon, 09 Jan 2023 12:25:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEvtS-0002XC-6m; Mon, 09 Jan 2023 12:25:06 -0500 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEvtP-00012N-RD; Mon, 09 Jan 2023 12:25:05 -0500 Received: by mail-ej1-x630.google.com with SMTP id cf18so15589680ejb.5; Mon, 09 Jan 2023 09:25:02 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow , Mark Cave-Ayland Subject: [PATCH v6 08/33] hw/usb/hcd-uhci: Introduce TYPE_ defines for device models Date: Mon, 9 Jan 2023 18:23:21 +0100 Message-Id: <20230109172347.1830-9-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=shentey@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285784712100003 Suggested-by: Mark Cave-Ayland Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-10-shentey@gmail.com> --- hw/usb/hcd-uhci.h | 4 ++++ hw/i386/pc_piix.c | 3 ++- hw/i386/pc_q35.c | 13 +++++++------ hw/isa/piix4.c | 2 +- hw/usb/hcd-uhci.c | 16 ++++++++-------- 5 files changed, 22 insertions(+), 16 deletions(-) diff --git a/hw/usb/hcd-uhci.h b/hw/usb/hcd-uhci.h index 5843af504a..e0fdb98ef1 100644 --- a/hw/usb/hcd-uhci.h +++ b/hw/usb/hcd-uhci.h @@ -91,4 +91,8 @@ typedef struct UHCIInfo { void uhci_data_class_init(ObjectClass *klass, void *data); void usb_uhci_common_realize(PCIDevice *dev, Error **errp); =20 +#define TYPE_PIIX3_USB_UHCI "piix3-usb-uhci" +#define TYPE_PIIX4_USB_UHCI "piix4-usb-uhci" +#define TYPE_ICH9_USB_UHCI(fn) "ich9-usb-uhci" #fn + #endif diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index bb3b10557f..df64dd8dcc 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -51,6 +51,7 @@ #include "exec/memory.h" #include "hw/acpi/acpi.h" #include "hw/acpi/piix4.h" +#include "hw/usb/hcd-uhci.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/xen.h" @@ -305,7 +306,7 @@ static void pc_init1(MachineState *machine, #endif =20 if (pcmc->pci_enabled && machine_usb(machine)) { - pci_create_simple(pci_bus, piix3_devfn + 2, "piix3-usb-uhci"); + pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI); } =20 if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms)= )) { diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 65ea226211..83c57c6eb1 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -48,6 +48,7 @@ #include "hw/ide/pci.h" #include "hw/ide/ahci.h" #include "hw/usb.h" +#include "hw/usb/hcd-uhci.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/numa.h" @@ -65,15 +66,15 @@ struct ehci_companions { }; =20 static const struct ehci_companions ich9_1d[] =3D { - { .name =3D "ich9-usb-uhci1", .func =3D 0, .port =3D 0 }, - { .name =3D "ich9-usb-uhci2", .func =3D 1, .port =3D 2 }, - { .name =3D "ich9-usb-uhci3", .func =3D 2, .port =3D 4 }, + { .name =3D TYPE_ICH9_USB_UHCI(1), .func =3D 0, .port =3D 0 }, + { .name =3D TYPE_ICH9_USB_UHCI(2), .func =3D 1, .port =3D 2 }, + { .name =3D TYPE_ICH9_USB_UHCI(3), .func =3D 2, .port =3D 4 }, }; =20 static const struct ehci_companions ich9_1a[] =3D { - { .name =3D "ich9-usb-uhci4", .func =3D 0, .port =3D 0 }, - { .name =3D "ich9-usb-uhci5", .func =3D 1, .port =3D 2 }, - { .name =3D "ich9-usb-uhci6", .func =3D 2, .port =3D 4 }, + { .name =3D TYPE_ICH9_USB_UHCI(4), .func =3D 0, .port =3D 0 }, + { .name =3D TYPE_ICH9_USB_UHCI(5), .func =3D 1, .port =3D 2 }, + { .name =3D TYPE_ICH9_USB_UHCI(6), .func =3D 2, .port =3D 4 }, }; =20 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 6e9434129d..de60ceef73 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -255,7 +255,7 @@ static void piix4_init(Object *obj) =20 object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); - object_initialize_child(obj, "uhci", &s->uhci, "piix4-usb-uhci"); + object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI); =20 object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM); qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", 0x1100); diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c index d1b5657d72..30ae0104bb 100644 --- a/hw/usb/hcd-uhci.c +++ b/hw/usb/hcd-uhci.c @@ -1292,56 +1292,56 @@ void uhci_data_class_init(ObjectClass *klass, void = *data) =20 static UHCIInfo uhci_info[] =3D { { - .name =3D "piix3-usb-uhci", + .name =3D TYPE_PIIX3_USB_UHCI, .vendor_id =3D PCI_VENDOR_ID_INTEL, .device_id =3D PCI_DEVICE_ID_INTEL_82371SB_2, .revision =3D 0x01, .irq_pin =3D 3, .unplug =3D true, },{ - .name =3D "piix4-usb-uhci", + .name =3D TYPE_PIIX4_USB_UHCI, .vendor_id =3D PCI_VENDOR_ID_INTEL, .device_id =3D PCI_DEVICE_ID_INTEL_82371AB_2, .revision =3D 0x01, .irq_pin =3D 3, .unplug =3D true, },{ - .name =3D "ich9-usb-uhci1", /* 00:1d.0 */ + .name =3D TYPE_ICH9_USB_UHCI(1), /* 00:1d.0 */ .vendor_id =3D PCI_VENDOR_ID_INTEL, .device_id =3D PCI_DEVICE_ID_INTEL_82801I_UHCI1, .revision =3D 0x03, .irq_pin =3D 0, .unplug =3D false, },{ - .name =3D "ich9-usb-uhci2", /* 00:1d.1 */ + .name =3D TYPE_ICH9_USB_UHCI(2), /* 00:1d.1 */ .vendor_id =3D PCI_VENDOR_ID_INTEL, .device_id =3D PCI_DEVICE_ID_INTEL_82801I_UHCI2, .revision =3D 0x03, .irq_pin =3D 1, .unplug =3D false, },{ - .name =3D "ich9-usb-uhci3", /* 00:1d.2 */ + .name =3D TYPE_ICH9_USB_UHCI(3), /* 00:1d.2 */ .vendor_id =3D PCI_VENDOR_ID_INTEL, .device_id =3D PCI_DEVICE_ID_INTEL_82801I_UHCI3, .revision =3D 0x03, .irq_pin =3D 2, .unplug =3D false, },{ - .name =3D "ich9-usb-uhci4", /* 00:1a.0 */ + .name =3D TYPE_ICH9_USB_UHCI(4), /* 00:1a.0 */ .vendor_id =3D PCI_VENDOR_ID_INTEL, .device_id =3D PCI_DEVICE_ID_INTEL_82801I_UHCI4, .revision =3D 0x03, .irq_pin =3D 0, .unplug =3D false, },{ - .name =3D "ich9-usb-uhci5", /* 00:1a.1 */ + .name =3D TYPE_ICH9_USB_UHCI(5), /* 00:1a.1 */ .vendor_id =3D PCI_VENDOR_ID_INTEL, .device_id =3D PCI_DEVICE_ID_INTEL_82801I_UHCI5, .revision =3D 0x03, .irq_pin =3D 1, .unplug =3D false, },{ - .name =3D "ich9-usb-uhci6", /* 00:1a.2 */ + .name =3D TYPE_ICH9_USB_UHCI(6), /* 00:1a.2 */ .vendor_id =3D PCI_VENDOR_ID_INTEL, .device_id =3D PCI_DEVICE_ID_INTEL_82801I_UHCI6, .revision =3D 0x03, --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow , Mark Cave-Ayland Subject: [PATCH v6 09/33] hw/intc/i8259: Make using the isa_pic singleton more type-safe Date: Mon, 9 Jan 2023 18:23:22 +0100 Message-Id: <20230109172347.1830-10-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=shentey@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285807114100001 Content-Type: text/plain; charset="utf-8" This even spares some casts in hot code paths along the way. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Reviewed-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Note: The next patch will introduce a class "isa-pic", which is shall not be confused with the isa_pic singleton. --- include/hw/intc/i8259.h | 6 +++--- include/qemu/typedefs.h | 1 + hw/intc/i8259.c | 11 ++++------- 3 files changed, 8 insertions(+), 10 deletions(-) diff --git a/include/hw/intc/i8259.h b/include/hw/intc/i8259.h index e2b1e8c59a..a0e34dd990 100644 --- a/include/hw/intc/i8259.h +++ b/include/hw/intc/i8259.h @@ -3,10 +3,10 @@ =20 /* i8259.c */ =20 -extern DeviceState *isa_pic; +extern PICCommonState *isa_pic; qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq); qemu_irq *kvm_i8259_init(ISABus *bus); -int pic_get_output(DeviceState *d); -int pic_read_irq(DeviceState *d); +int pic_get_output(PICCommonState *s); +int pic_read_irq(PICCommonState *s); =20 #endif diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 073abab998..fba04875c2 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -99,6 +99,7 @@ typedef struct PCIExpressDevice PCIExpressDevice; typedef struct PCIExpressHost PCIExpressHost; typedef struct PCIHostDeviceAddress PCIHostDeviceAddress; typedef struct PCIHostState PCIHostState; +typedef struct PICCommonState PICCommonState; typedef struct PostcopyDiscardState PostcopyDiscardState; typedef struct Property Property; typedef struct PropertyInfo PropertyInfo; diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index cc4e21ffec..0261f087b2 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -55,7 +55,7 @@ struct PICClass { #ifdef DEBUG_IRQ_LATENCY static int64_t irq_time[16]; #endif -DeviceState *isa_pic; +PICCommonState *isa_pic; static PICCommonState *slave_pic; =20 /* return the highest priority found in mask (highest =3D smallest @@ -173,9 +173,8 @@ static void pic_intack(PICCommonState *s, int irq) pic_update_irq(s); } =20 -int pic_read_irq(DeviceState *d) +int pic_read_irq(PICCommonState *s) { - PICCommonState *s =3D PIC_COMMON(d); int irq, intno; =20 irq =3D pic_get_irq(s); @@ -354,10 +353,8 @@ static uint64_t pic_ioport_read(void *opaque, hwaddr a= ddr, return ret; } =20 -int pic_get_output(DeviceState *d) +int pic_get_output(PICCommonState *s) { - PICCommonState *s =3D PIC_COMMON(d); - return (pic_get_irq(s) >=3D 0); } =20 @@ -426,7 +423,7 @@ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq) irq_set[i] =3D qdev_get_gpio_in(dev, i); } =20 - isa_pic =3D dev; + isa_pic =3D PIC_COMMON(dev); =20 isadev =3D i8259_init_chip(TYPE_I8259, bus, false); dev =3D DEVICE(isadev); --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673285818; cv=none; d=zohomail.com; s=zohoarc; b=TlHbnKsKhxqsZIjnQngnypDcFzM3Wc/fqmi/keNdxJnuN/1G6f0OOjb+0vFG9JvbCvgrZs5UQ7vCHEIVhmVK/Xw9qp1/oANGwVEZAbQ5BP++DC7ep8m/wOti7pXMMl1PNPqdjvyiARumIQOFqG0tL+R1vSmDIAa5wZCRp1V3JfE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673285818; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mgtdEHCrqZkKeHSwNr7rmdJndX3/1+NtuZOqm1NlxBM=; b=Fk8O6npY/3k4OWfW/us/yCfPJHhETGJEaSAKdt10J8mcnGjcI3Lug5f6j5Kmmekt6javtfj8tDGah4vsWDw+3It5fHxjpGDk10UuCGWjpu6RWA0zeKIZHTNLgl1TO2Tl9EQt90aVgOP17/HDF3FVKukIvK2o2w7XbMpcCRHl9YY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673285818540972.7957663507598; Mon, 9 Jan 2023 09:36:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEvtW-0002dX-RQ; Mon, 09 Jan 2023 12:25:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEvtU-0002aO-B6; Mon, 09 Jan 2023 12:25:08 -0500 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEvtS-00018g-Dx; Mon, 09 Jan 2023 12:25:08 -0500 Received: by mail-ej1-x636.google.com with SMTP id tz12so21912191ejc.9; Mon, 09 Jan 2023 09:25:04 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow , Mark Cave-Ayland Subject: [PATCH v6 10/33] hw/intc/i8259: Introduce i8259 proxy TYPE_ISA_PIC Date: Mon, 9 Jan 2023 18:23:23 +0100 Message-Id: <20230109172347.1830-11-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=shentey@gmail.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285819105100001 Content-Type: text/plain; charset="utf-8" Having an i8259 proxy allows for ISA PICs to be created and wired up in southbridges. This is especially interesting for PIIX3 for two reasons: First, the southbridge doesn't need to care about the virtualization technology used (KVM, TCG, Xen) due to in-IRQs (where devices get attached) and out-IRQs (which will trigger the IRQs of the respective virtualization technology) are separated. Second, since the in-IRQs are populated with fully initialized qemu_irq's, they can already be wired up inside PIIX3. Cc: Mark Cave-Ayland Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Reviewed-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/intc/i8259.h | 18 ++++++++++++++++++ hw/intc/i8259.c | 27 +++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/include/hw/intc/i8259.h b/include/hw/intc/i8259.h index a0e34dd990..7fb403971c 100644 --- a/include/hw/intc/i8259.h +++ b/include/hw/intc/i8259.h @@ -1,6 +1,24 @@ #ifndef HW_I8259_H #define HW_I8259_H =20 +#include "qom/object.h" +#include "hw/isa/isa.h" +#include "qemu/typedefs.h" + +#define TYPE_ISA_PIC "isa-pic" +OBJECT_DECLARE_SIMPLE_TYPE(ISAPICState, ISA_PIC) + +/* + * TYPE_ISA_PIC is currently a PIC proxy which allows for interrupt wiring= in + * a virtualization technology agnostic way. + */ +struct ISAPICState { + DeviceState parent_obj; + + qemu_irq in_irqs[ISA_NUM_IRQS]; + qemu_irq out_irqs[ISA_NUM_IRQS]; +}; + /* i8259.c */ =20 extern PICCommonState *isa_pic; diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index 0261f087b2..e99d02136d 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -455,9 +455,36 @@ static const TypeInfo i8259_info =3D { .class_size =3D sizeof(PICClass), }; =20 +static void isapic_set_irq(void *opaque, int irq, int level) +{ + ISAPICState *s =3D opaque; + + qemu_set_irq(s->out_irqs[irq], level); +} + +static void isapic_init(Object *obj) +{ + ISAPICState *s =3D ISA_PIC(obj); + + qdev_init_gpio_in(DEVICE(s), isapic_set_irq, ISA_NUM_IRQS); + qdev_init_gpio_out(DEVICE(s), s->out_irqs, ISA_NUM_IRQS); + + for (int i =3D 0; i < ISA_NUM_IRQS; ++i) { + s->in_irqs[i] =3D qdev_get_gpio_in(DEVICE(s), i); + } +} + +static const TypeInfo isapic_info =3D { + .name =3D TYPE_ISA_PIC, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(ISAPICState), + .instance_init =3D isapic_init, +}; + static void pic_register_types(void) { type_register_static(&i8259_info); + type_register_static(&isapic_info); } =20 type_init(pic_register_types) --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673285189; cv=none; d=zohomail.com; s=zohoarc; b=a+VvwwV/waB1HlOxjul8kG7MFNHC6+hHwKYE7qg8zSCgfIVtV4s7iAP0GZ4a93E6mEh+CLkeg/8n8NFXqzmgO3IwUGSyzuPxa1v+o+xk2CrW9fe3fGU9RCUM+Sn2R+FWAaNzPjWXE6Ffiw3v8Lws+b5Sgv0z4PVZ1TR5f79GXQc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673285189; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5p7sgEdtKfggSOTX5nCZYcfDZwg+qbuLkjdlk4PFRss=; b=d2vTNigFDWoLtEKAxiymBPzUiKx47noN4fL1VZ+QaM9nHXhLj8a43YQBAorXG5Z6JHoWF8WsHQW9zeuC8bdGMN3clHZpvE2djDKZ3JRu02Mcymfj/mk+wwK0SxnsI4n8a1DoPNEPZ52G7YYaO+YYaltdtbJg9BxHlePHnUYgn4w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167328518907977.70667310489739; Mon, 9 Jan 2023 09:26:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEvuB-0002xA-9l; Mon, 09 Jan 2023 12:25:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEvtW-0002cT-2d; Mon, 09 Jan 2023 12:25:10 -0500 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEvtT-0001Ey-H5; Mon, 09 Jan 2023 12:25:09 -0500 Received: by mail-ej1-x631.google.com with SMTP id tz12so21912361ejc.9; Mon, 09 Jan 2023 09:25:05 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow , Thomas Huth Subject: [PATCH v6 11/33] hw/i386/pc: Create RTC controllers in south bridges Date: Mon, 9 Jan 2023 18:23:24 +0100 Message-Id: <20230109172347.1830-12-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=shentey@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285190181100001 Content-Type: text/plain; charset="utf-8" Just like in the real hardware (and in PIIX4), create the RTC controllers in the south bridges. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Reviewed-by: Thomas Huth Message-Id: <20221022150508.26830-11-shentey@gmail.com> --- include/hw/i386/ich9.h | 2 ++ include/hw/southbridge/piix.h | 4 ++++ hw/i386/pc.c | 12 +++++++++++- hw/i386/pc_piix.c | 8 ++++++++ hw/i386/pc_q35.c | 1 + hw/isa/lpc_ich9.c | 8 ++++++++ hw/isa/piix3.c | 15 +++++++++++++++ hw/isa/Kconfig | 2 ++ 8 files changed, 51 insertions(+), 1 deletion(-) diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index 222781e8b9..dab309d5e3 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -7,6 +7,7 @@ #include "hw/isa/apm.h" #include "hw/acpi/acpi.h" #include "hw/acpi/ich9.h" +#include "hw/rtc/mc146818rtc.h" #include "qom/object.h" =20 void ich9_lpc_set_irq(void *opaque, int irq_num, int level); @@ -35,6 +36,7 @@ struct ICH9LPCState { */ uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; =20 + RTCState rtc; APMState apm; ICH9LPCPMRegs pm; uint32_t sci_level; /* track sci level */ diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 0bf48e936d..b06d26fa11 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -13,6 +13,8 @@ #define HW_SOUTHBRIDGE_PIIX_H =20 #include "hw/pci/pci_device.h" +#include "qom/object.h" +#include "hw/rtc/mc146818rtc.h" =20 /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 @@ -51,6 +53,8 @@ struct PIIXState { /* This member isn't used. Just for save/load compatibility */ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; =20 + RTCState rtc; + /* Reset Control Register contents */ uint8_t rcr; =20 diff --git a/hw/i386/pc.c b/hw/i386/pc.c index d489ecc0d1..448557333b 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1304,7 +1304,17 @@ void pc_basic_device_init(struct PCMachineState *pcm= s, pit_alt_irq =3D qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); rtc_irq =3D qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); } - *rtc_state =3D mc146818_rtc_init(isa_bus, 2000, rtc_irq); + + if (rtc_irq) { + qdev_connect_gpio_out(DEVICE(*rtc_state), 0, rtc_irq); + } else { + uint32_t irq =3D object_property_get_uint(OBJECT(*rtc_state), + "irq", + &error_fatal); + isa_connect_gpio_out(*rtc_state, 0, irq); + } + object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(*rtc_state), + "date"); =20 qemu_register_boot_set(pc_boot_set, *rtc_state); =20 diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index df64dd8dcc..8f894714e5 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -32,6 +32,7 @@ #include "hw/i386/pc.h" #include "hw/i386/apic.h" #include "hw/pci-host/i440fx.h" +#include "hw/rtc/mc146818rtc.h" #include "hw/southbridge/piix.h" #include "hw/display/ramfb.h" #include "hw/firmware/smbios.h" @@ -239,10 +240,17 @@ static void pc_init1(MachineState *machine, piix3->pic =3D x86ms->gsi; piix3_devfn =3D piix3->dev.devfn; isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); + rtc_state =3D ISA_DEVICE(object_resolve_path_component(OBJECT(pci_= dev), + "rtc")); } else { pci_bus =3D NULL; isa_bus =3D isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); + + rtc_state =3D isa_new(TYPE_MC146818_RTC); + qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000); + isa_realize_and_unref(rtc_state, isa_bus, &error_fatal); + i8257_dma_init(isa_bus, 0); pcms->hpet_enabled =3D false; } diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 83c57c6eb1..da97df69f7 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -239,6 +239,7 @@ static void pc_q35_init(MachineState *machine) lpc =3D pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_D= EV, ICH9_LPC_FUNC), true, TYPE_ICH9_LPC_DEVICE); + rtc_state =3D ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "r= tc")); =20 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, TYPE_HOTPLUG_HANDLER, diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 8d541e2b54..498175c1cc 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -663,6 +663,8 @@ static void ich9_lpc_initfn(Object *obj) static const uint8_t acpi_enable_cmd =3D ICH9_APM_ACPI_ENABLE; static const uint8_t acpi_disable_cmd =3D ICH9_APM_ACPI_DISABLE; =20 + object_initialize_child(obj, "rtc", &lpc->rtc, TYPE_MC146818_RTC); + object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT, &lpc->sci_gsi, OBJ_PROP_FLAG_READ); object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CM= D, @@ -728,6 +730,12 @@ static void ich9_lpc_realize(PCIDevice *d, Error **err= p) isa_bus_irqs(isa_bus, lpc->gsi); =20 i8257_dma_init(isa_bus, 0); + + /* RTC */ + qdev_prop_set_int32(DEVICE(&lpc->rtc), "base_year", 2000); + if (!qdev_realize(DEVICE(&lpc->rtc), BUS(isa_bus), errp)) { + return; + } } =20 static bool ich9_rst_cnt_needed(void *opaque) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 283b971ec4..e8ddb6a602 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -28,6 +28,7 @@ #include "hw/dma/i8257.h" #include "hw/southbridge/piix.h" #include "hw/irq.h" +#include "hw/qdev-properties.h" #include "hw/isa/isa.h" #include "hw/xen/xen.h" #include "sysemu/runstate.h" @@ -301,6 +302,12 @@ static void pci_piix3_realize(PCIDevice *dev, Error **= errp) PIIX_RCR_IOPORT, &d->rcr_mem, 1); =20 i8257_dma_init(isa_bus, 0); + + /* RTC */ + qdev_prop_set_int32(DEVICE(&d->rtc), "base_year", 2000); + if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) { + return; + } } =20 static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -327,6 +334,13 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml = *scope) } } =20 +static void pci_piix3_init(Object *obj) +{ + PIIX3State *d =3D PIIX3_PCI_DEVICE(obj); + + object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); +} + static void pci_piix3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -353,6 +367,7 @@ static const TypeInfo piix3_pci_type_info =3D { .name =3D TYPE_PIIX3_PCI_DEVICE, .parent =3D TYPE_PCI_DEVICE, .instance_size =3D sizeof(PIIX3State), + .instance_init =3D pci_piix3_init, .abstract =3D true, .class_init =3D pci_piix3_class_init, .interfaces =3D (InterfaceInfo[]) { diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 0156a66889..c10cbc5fc1 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -35,6 +35,7 @@ config PIIX3 bool select I8257 select ISA_BUS + select MC146818RTC =20 config PIIX4 bool @@ -79,3 +80,4 @@ config LPC_ICH9 select I8257 select ISA_BUS select ACPI_ICH9 + select MC146818RTC --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow , Thomas Huth Subject: [PATCH v6 12/33] hw/i386/pc: No need for rtc_state to be an out-parameter Date: Mon, 9 Jan 2023 18:23:25 +0100 Message-Id: <20230109172347.1830-13-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=shentey@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285994138100003 Now that the RTC is created as part of the southbridges it doesn't need to be an out-parameter any longer. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell Reviewed-by: Michael S. Tsirkin Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20221022150508.26830-12-shentey@gmail.com> --- include/hw/i386/pc.h | 2 +- hw/i386/pc.c | 12 ++++++------ hw/i386/pc_piix.c | 2 +- hw/i386/pc_q35.c | 2 +- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 991f905f5d..dd059e8667 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -169,7 +169,7 @@ uint64_t pc_pci_hole64_start(void); DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); void pc_basic_device_init(struct PCMachineState *pcms, ISABus *isa_bus, qemu_irq *gsi, - ISADevice **rtc_state, + ISADevice *rtc_state, bool create_fdctrl, uint32_t hpet_irqs); void pc_cmos_init(PCMachineState *pcms, diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 448557333b..53a5443e09 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1251,7 +1251,7 @@ static void pc_superio_init(ISABus *isa_bus, bool cre= ate_fdctrl, =20 void pc_basic_device_init(struct PCMachineState *pcms, ISABus *isa_bus, qemu_irq *gsi, - ISADevice **rtc_state, + ISADevice *rtc_state, bool create_fdctrl, uint32_t hpet_irqs) { @@ -1306,17 +1306,17 @@ void pc_basic_device_init(struct PCMachineState *pc= ms, } =20 if (rtc_irq) { - qdev_connect_gpio_out(DEVICE(*rtc_state), 0, rtc_irq); + qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); } else { - uint32_t irq =3D object_property_get_uint(OBJECT(*rtc_state), + uint32_t irq =3D object_property_get_uint(OBJECT(rtc_state), "irq", &error_fatal); - isa_connect_gpio_out(*rtc_state, 0, irq); + isa_connect_gpio_out(rtc_state, 0, irq); } - object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(*rtc_state), + object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), "date"); =20 - qemu_register_boot_set(pc_boot_set, *rtc_state); + qemu_register_boot_set(pc_boot_set, rtc_state); =20 if (!xen_enabled() && (x86ms->pit =3D=3D ON_OFF_AUTO_AUTO || x86ms->pit =3D=3D ON_OFF_AU= TO_ON)) { diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 8f894714e5..a577ea2f4e 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -276,7 +276,7 @@ static void pc_init1(MachineState *machine, } =20 /* init basic PC hardware */ - pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, true, + pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, true, 0x4); =20 pc_nic_init(pcmc, isa_bus, pci_bus); diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index da97df69f7..58c51fbd9e 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -293,7 +293,7 @@ static void pc_q35_init(MachineState *machine) } =20 /* init basic PC hardware */ - pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_fl= oppy, + pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, !mc->no_flo= ppy, 0xff0104); =20 /* connect pm stuff to lpc */ --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673285411; cv=none; d=zohomail.com; s=zohoarc; b=LuPw7P8xTO2QE86sEHKNIStM2AvYWEsmUHZ1WLEFW3a8CSPENj+XEFEIgyhaoyy41tXAOcDKdOMd9+pGBiGfPRm/+ijfUGxX+0GIW0nohIblBltD9JHtFVEf8OEvoT1wBPjgXmWtGuXmt9AgR2Jw+XnG4X02LUcnthQK2srVf64= ARC-Message-Signature: i=1; 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 13/33] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge Date: Mon, 9 Jan 2023 18:23:26 +0100 Message-Id: <20230109172347.1830-14-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=shentey@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285413213100003 Content-Type: text/plain; charset="utf-8" The next patches will need to take advantage of it. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-3-shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/i386/pc_piix.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index a577ea2f4e..37afc01d30 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -235,7 +235,8 @@ static void pc_init1(MachineState *machine, : pc_pci_slot_get_pirq); pcms->bus =3D pci_bus; =20 - pci_dev =3D pci_create_simple_multifunction(pci_bus, -1, true, typ= e); + pci_dev =3D pci_new_multifunction(-1, true, type); + pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); piix3 =3D PIIX3_PCI_DEVICE(pci_dev); piix3->pic =3D x86ms->gsi; piix3_devfn =3D piix3->dev.devfn; --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673286118; cv=none; d=zohomail.com; s=zohoarc; b=mV9bB8IM0KIaRU/7upLQXBv4EM9tm23ZBuuB5ghCrTUjUVlTcctgTkZmnPzlsKpEDLWdxPdDAms/0v8qHX8MVG2vAtx7X+bIwq+zMUQ7e9sEPSc2HIE2GAffBTfFS92A0MIRAj/hiw8XgUnDGeAhvej1qFasQnus4oOaMI+c6lY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673286118; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iEfe8DszwIoCvxSU0reKf5l+UfAr8tT4LsXbGha4/uw=; b=YxUaxYvFCQJyzWXFypqMgdarIqPZezYTBFL5GET7ZctcQdTRiy2+oJk4tINsdqYflMDLNDxkMoDRX5dvWVGvrADVPMTufg+rTNCzhJPq6Y6IjrBOzLPeTaA+uhinGo+sDNVDJMPNKjmdkWaPQjbapwqMVsH8k9hO5yC65H3fMt0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673286118867760.6483664689746; Mon, 9 Jan 2023 09:41:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEvto-0002mX-2k; Mon, 09 Jan 2023 12:25:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEvtY-0002fa-KT; Mon, 09 Jan 2023 12:25:12 -0500 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEvtW-00010R-NP; Mon, 09 Jan 2023 12:25:12 -0500 Received: by mail-ej1-x634.google.com with SMTP id cf18so15590617ejb.5; Mon, 09 Jan 2023 09:25:09 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id 18-20020a170906201200b00846734faa9asm3925625ejo.164.2023.01.09.09.25.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 09:25:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iEfe8DszwIoCvxSU0reKf5l+UfAr8tT4LsXbGha4/uw=; b=q7auXqbaxFTU0U0zqmVmLx47mkNJiYaj1V/bU2uj5BLvNBgGvUmxtyvzNfqgNalOVs puCc+LJf27Kujk9HIHNzkHHbJnlknetTOmvxLbRovpRStTV/rRJc8ucMwjGfYeejemfq LXFXzDhPqFTNslMVZEH5XtbAiZn3zaYtGQEhL1Ql3foDGxFILsuHW5UbiGgxx8NeVSck t6kMqX+m1a6FT4iY3TtgcifxzXRqalsXtq9HGLjQDh4ZW+Ro56jU3PVSPrzMWqwTypV7 mDE+r1QNduPfE78zPKLS3ulapPu1s7ZbOd0jZC2yfLJcRnk1sfoKX1fOMrIIfp3xuWDV O3dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iEfe8DszwIoCvxSU0reKf5l+UfAr8tT4LsXbGha4/uw=; b=EsmSkCp1VZ7ZUhPOwEFgj4OhUD1SuAn9pMlZXMvqKCrnu8AzogHPezBDjkGEe2Tme6 hzVj2tWU3FWCzBnTey+c5mRXdnuiYaFTYzc4MeJAZCqPlVrcSK9rgXswKXbuXKo3ZPUv 3vhVq9BWg2/MPdfnuyfzaqGpIBi9CBBbqJr4QrWmUX2mbJVy698HNz8yoStivkClbLTd cSoBlllaTbuUwSzM6M3iIfCgymjYu50o3HuaH45QJ3YKA7q98es4Q3dg3OZYnT02gsH3 G+5e2/71q7BEh8sDONMdXpXzSTPrtah2avH/5Tc4/mfOdVhbbhvVLNB72JiCYqcweAUq /EbA== X-Gm-Message-State: AFqh2koVvEmhIuU6vrIBYB3b2TpTS+OfU7ROmNsGcfCM4GtWEqTV4KT8 cG/jrq01lLFOtdASbAmkNtZhkDvCdY+k8Q== X-Google-Smtp-Source: AMrXdXtN/apqJjHI16o4dfREGHyfDXrn6HpkGdRy0/bd8GWMCHfU+visPPZH0HcYmQ8MjOMA/7Yjug== X-Received: by 2002:a17:906:1ccc:b0:7c0:d88b:4323 with SMTP id i12-20020a1709061ccc00b007c0d88b4323mr50299546ejh.61.1673285108472; Mon, 09 Jan 2023 09:25:08 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: John G Johnson , Richard Henderson , Igor Mammedov , Elena Ufimtseva , Ani Sinha , Eduardo Habkost , Gerd Hoffmann , Jagannathan Raman , "Michael S. Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 14/33] hw/isa/piix3: Create USB controller in host device Date: Mon, 9 Jan 2023 18:23:27 +0100 Message-Id: <20230109172347.1830-15-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=shentey@gmail.com; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673286121131100001 Content-Type: text/plain; charset="utf-8" The USB controller is an integral part of PIIX3 (function 2). So create it as part of the south bridge. Note that the USB function is optional in QEMU. This is why it gets object_initialize_child()'ed in realize rather than in instance_init. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-13-shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/southbridge/piix.h | 4 ++++ hw/i386/pc_piix.c | 7 ++----- hw/isa/piix3.c | 17 +++++++++++++++++ hw/isa/Kconfig | 1 + 4 files changed, 24 insertions(+), 5 deletions(-) diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index b06d26fa11..762709f2fd 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci_device.h" #include "qom/object.h" #include "hw/rtc/mc146818rtc.h" +#include "hw/usb/hcd-uhci.h" =20 /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 @@ -54,12 +55,15 @@ struct PIIXState { int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; =20 RTCState rtc; + UHCIState uhci; =20 /* Reset Control Register contents */ uint8_t rcr; =20 /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ MemoryRegion rcr_mem; + + bool has_usb; }; typedef struct PIIXState PIIX3State; =20 diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 37afc01d30..61d8152078 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -52,7 +52,6 @@ #include "exec/memory.h" #include "hw/acpi/acpi.h" #include "hw/acpi/piix4.h" -#include "hw/usb/hcd-uhci.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/xen.h" @@ -236,6 +235,8 @@ static void pc_init1(MachineState *machine, pcms->bus =3D pci_bus; =20 pci_dev =3D pci_new_multifunction(-1, true, type); + object_property_set_bool(OBJECT(pci_dev), "has-usb", + machine_usb(machine), &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); piix3 =3D PIIX3_PCI_DEVICE(pci_dev); piix3->pic =3D x86ms->gsi; @@ -314,10 +315,6 @@ static void pc_init1(MachineState *machine, } #endif =20 - if (pcmc->pci_enabled && machine_usb(machine)) { - pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI); - } - if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms)= )) { PCIDevice *piix4_pm; =20 diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index e8ddb6a602..45c20dea17 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -288,6 +288,7 @@ static const MemoryRegionOps rcr_ops =3D { static void pci_piix3_realize(PCIDevice *dev, Error **errp) { PIIX3State *d =3D PIIX3_PCI_DEVICE(dev); + PCIBus *pci_bus =3D pci_get_bus(dev); ISABus *isa_bus; =20 isa_bus =3D isa_bus_new(DEVICE(d), pci_address_space(dev), @@ -308,6 +309,16 @@ static void pci_piix3_realize(PCIDevice *dev, Error **= errp) if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) { return; } + + /* USB */ + if (d->has_usb) { + object_initialize_child(OBJECT(dev), "uhci", &d->uhci, + TYPE_PIIX3_USB_UHCI); + qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2); + if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) { + return; + } + } } =20 static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -341,6 +352,11 @@ static void pci_piix3_init(Object *obj) object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); } =20 +static Property pci_piix3_props[] =3D { + DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), + DEFINE_PROP_END_OF_LIST(), +}; + static void pci_piix3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -360,6 +376,7 @@ static void pci_piix3_class_init(ObjectClass *klass, vo= id *data) * pc_piix.c's pc_init1() */ dc->user_creatable =3D false; + device_class_set_props(dc, pci_piix3_props); adevc->build_dev_aml =3D build_pci_isa_aml; } =20 diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index c10cbc5fc1..f01bc0dff3 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -36,6 +36,7 @@ config PIIX3 select I8257 select ISA_BUS select MC146818RTC + select USB_UHCI =20 config PIIX4 bool --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 15/33] hw/isa/piix3: Create power management controller in host device Date: Mon, 9 Jan 2023 18:23:28 +0100 Message-Id: <20230109172347.1830-16-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=shentey@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673286159219100001 Content-Type: text/plain; charset="utf-8" The power management controller is an integral part of PIIX3 (function 3). So create it as part of the south bridge. Note that the ACPI function is optional in QEMU. This is why it gets object_initialize_child()'ed in realize rather than in instance_init. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-14-shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/southbridge/piix.h | 6 ++++++ hw/i386/pc_piix.c | 24 ++++++++++++++---------- hw/isa/piix3.c | 14 ++++++++++++++ hw/isa/Kconfig | 1 + 4 files changed, 35 insertions(+), 10 deletions(-) diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 762709f2fd..b1eaab1d95 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -14,6 +14,7 @@ =20 #include "hw/pci/pci_device.h" #include "qom/object.h" +#include "hw/acpi/piix4.h" #include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" =20 @@ -56,6 +57,9 @@ struct PIIXState { =20 RTCState rtc; UHCIState uhci; + PIIX4PMState pm; + + uint32_t smb_io_base; =20 /* Reset Control Register contents */ uint8_t rcr; @@ -63,7 +67,9 @@ struct PIIXState { /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ MemoryRegion rcr_mem; =20 + bool has_acpi; bool has_usb; + bool smm_enabled; }; typedef struct PIIXState PIIX3State; =20 diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 61d8152078..5ea8d4a585 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -46,12 +46,12 @@ #include "sysemu/kvm.h" #include "hw/kvm/clock.h" #include "hw/sysbus.h" +#include "hw/i2c/i2c.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/xen/xen-x86.h" #include "hw/xen/xen.h" #include "exec/memory.h" #include "hw/acpi/acpi.h" -#include "hw/acpi/piix4.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/xen.h" @@ -97,6 +97,7 @@ static void pc_init1(MachineState *machine, MemoryRegion *system_io =3D get_system_io(); PCIBus *pci_bus; ISABus *isa_bus; + Object *piix4_pm; int piix3_devfn =3D -1; qemu_irq smi_irq; GSIState *gsi_state; @@ -237,15 +238,25 @@ static void pc_init1(MachineState *machine, pci_dev =3D pci_new_multifunction(-1, true, type); object_property_set_bool(OBJECT(pci_dev), "has-usb", machine_usb(machine), &error_abort); + object_property_set_bool(OBJECT(pci_dev), "has-acpi", + x86_machine_is_acpi_enabled(x86ms), + &error_abort); + qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100); + object_property_set_bool(OBJECT(pci_dev), "smm-enabled", + x86_machine_is_smm_enabled(x86ms), + &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); + piix3 =3D PIIX3_PCI_DEVICE(pci_dev); piix3->pic =3D x86ms->gsi; piix3_devfn =3D piix3->dev.devfn; isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); rtc_state =3D ISA_DEVICE(object_resolve_path_component(OBJECT(pci_= dev), "rtc")); + piix4_pm =3D object_resolve_path_component(OBJECT(pci_dev), "pm"); } else { pci_bus =3D NULL; + piix4_pm =3D NULL; isa_bus =3D isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); =20 @@ -315,15 +326,8 @@ static void pc_init1(MachineState *machine, } #endif =20 - if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms)= )) { - PCIDevice *piix4_pm; - + if (piix4_pm) { smi_irq =3D qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); - piix4_pm =3D pci_new(piix3_devfn + 3, TYPE_PIIX4_PM); - qdev_prop_set_uint32(DEVICE(piix4_pm), "smb_io_base", 0xb100); - qdev_prop_set_bit(DEVICE(piix4_pm), "smm-enabled", - x86_machine_is_smm_enabled(x86ms)); - pci_realize_and_unref(piix4_pm, pci_bus, &error_fatal); =20 qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]); qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_ir= q); @@ -337,7 +341,7 @@ static void pc_init1(MachineState *machine, object_property_allow_set_link, OBJ_PROP_LINK_STRONG); object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_P= ROP, - OBJECT(piix4_pm), &error_abort); + piix4_pm, &error_abort); } =20 if (machine->nvdimms_state->is_enabled) { diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 45c20dea17..ed7d58bc98 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -319,6 +319,17 @@ static void pci_piix3_realize(PCIDevice *dev, Error **= errp) return; } } + + /* Power Management */ + if (d->has_acpi) { + object_initialize_child(OBJECT(d), "pm", &d->pm, TYPE_PIIX4_PM); + qdev_prop_set_int32(DEVICE(&d->pm), "addr", dev->devfn + 3); + qdev_prop_set_uint32(DEVICE(&d->pm), "smb_io_base", d->smb_io_base= ); + qdev_prop_set_bit(DEVICE(&d->pm), "smm-enabled", d->smm_enabled); + if (!qdev_realize(DEVICE(&d->pm), BUS(pci_bus), errp)) { + return; + } + } } =20 static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -353,7 +364,10 @@ static void pci_piix3_init(Object *obj) } =20 static Property pci_piix3_props[] =3D { + DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), + DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index f01bc0dff3..cf79580384 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -33,6 +33,7 @@ config PC87312 =20 config PIIX3 bool + select ACPI_PIIX4 select I8257 select ISA_BUS select MC146818RTC --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 16/33] hw/isa/piix3: Create TYPE_ISA_PIC in host device Date: Mon, 9 Jan 2023 18:23:29 +0100 Message-Id: <20230109172347.1830-17-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=shentey@gmail.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285204155100001 Content-Type: text/plain; charset="utf-8" The newly introduced TYPE_ISA_PIC allows for wiring up devices in the southbridge where the virtualization technology used (KVM, TCG, Xen) is not yet known. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-16-shentey@gmail.com> --- include/hw/southbridge/piix.h | 4 ++-- hw/i386/pc_piix.c | 15 +++++++++------ hw/isa/piix3.c | 10 +++++++++- hw/i386/Kconfig | 1 + hw/isa/Kconfig | 1 + 5 files changed, 22 insertions(+), 9 deletions(-) diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index b1eaab1d95..514ccdb7fd 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci_device.h" #include "qom/object.h" #include "hw/acpi/piix4.h" +#include "hw/intc/i8259.h" #include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" =20 @@ -50,11 +51,10 @@ struct PIIXState { #endif uint64_t pic_levels; =20 - qemu_irq *pic; - /* This member isn't used. Just for save/load compatibility */ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; =20 + ISAPICState pic; RTCState rtc; UHCIState uhci; PIIX4PMState pm; diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 5ea8d4a585..df8e2e389b 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -219,10 +219,11 @@ static void pc_init1(MachineState *machine, gsi_state =3D pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); =20 if (pcmc->pci_enabled) { - PIIX3State *piix3; + DeviceState *dev; PCIDevice *pci_dev; const char *type =3D xen_enabled() ? TYPE_PIIX3_XEN_DEVICE : TYPE_PIIX3_DEVICE; + int i; =20 pci_bus =3D i440fx_init(pci_type, i440fx_host, @@ -247,10 +248,12 @@ static void pc_init1(MachineState *machine, &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); =20 - piix3 =3D PIIX3_PCI_DEVICE(pci_dev); - piix3->pic =3D x86ms->gsi; - piix3_devfn =3D piix3->dev.devfn; - isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); + dev =3D DEVICE(object_resolve_path_component(OBJECT(pci_dev), "pic= ")); + for (i =3D 0; i < ISA_NUM_IRQS; i++) { + qdev_connect_gpio_out(dev, i, x86ms->gsi[i]); + } + piix3_devfn =3D pci_dev->devfn; + isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); rtc_state =3D ISA_DEVICE(object_resolve_path_component(OBJECT(pci_= dev), "rtc")); piix4_pm =3D object_resolve_path_component(OBJECT(pci_dev), "pm"); @@ -259,6 +262,7 @@ static void pc_init1(MachineState *machine, piix4_pm =3D NULL; isa_bus =3D isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); + isa_bus_irqs(isa_bus, x86ms->gsi); =20 rtc_state =3D isa_new(TYPE_MC146818_RTC); qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000); @@ -267,7 +271,6 @@ static void pc_init1(MachineState *machine, i8257_dma_init(isa_bus, 0); pcms->hpet_enabled =3D false; } - isa_bus_irqs(isa_bus, x86ms->gsi); =20 if (x86ms->pic =3D=3D ON_OFF_AUTO_ON || x86ms->pic =3D=3D ON_OFF_AUTO_= AUTO) { pc_i8259_create(isa_bus, gsi_state->i8259_irq); diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index ed7d58bc98..88a6bf28ea 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -39,7 +39,7 @@ =20 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) { - qemu_set_irq(piix3->pic[pic_irq], + qemu_set_irq(piix3->pic.in_irqs[pic_irq], !!(piix3->pic_levels & (((1ULL << PIIX_NUM_PIRQS) - 1) << (pic_irq * PIIX_NUM_PIRQS)))); @@ -297,6 +297,13 @@ static void pci_piix3_realize(PCIDevice *dev, Error **= errp) return; } =20 + /* PIC */ + if (!qdev_realize(DEVICE(&d->pic), NULL, errp)) { + return; + } + + isa_bus_irqs(isa_bus, d->pic.in_irqs); + memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, "piix3-reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), @@ -360,6 +367,7 @@ static void pci_piix3_init(Object *obj) { PIIX3State *d =3D PIIX3_PCI_DEVICE(obj); =20 + object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); } =20 diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index c4fb5b49bd..1291f59896 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -71,6 +71,7 @@ config I440FX select ACPI_PIIX4 select PC_PCI select PC_ACPI + select I8259 select PCI_I440FX select PIIX3 select IDE_PIIX diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index cf79580384..fccf095d07 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -35,6 +35,7 @@ config PIIX3 bool select ACPI_PIIX4 select I8257 + select I8259 select ISA_BUS select MC146818RTC select USB_UHCI --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 17/33] hw/isa/piix3: Create IDE controller in host device Date: Mon, 9 Jan 2023 18:23:30 +0100 Message-Id: <20230109172347.1830-18-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=shentey@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673286078658100003 Content-Type: text/plain; charset="utf-8" Now that PIIX3 contains the new TYPE_ISA_PIC, it is possible to instantiate PIIX3 IDE in the PIIX3 southbridge. PIIX3 IDE wires up its interrupts to the ISA bus in its realize method which requires the interrupt controller to provide fully populated qemu_irqs. This is the case for TYPE_ISA_PIC even though the virtualization technology isn't known yet. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-17-shentey@gmail.com> --- include/hw/southbridge/piix.h | 2 ++ hw/i386/pc_piix.c | 15 ++++++--------- hw/isa/piix3.c | 8 ++++++++ hw/i386/Kconfig | 1 - hw/isa/Kconfig | 1 + 5 files changed, 17 insertions(+), 10 deletions(-) diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 514ccdb7fd..e3c35ca16f 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci_device.h" #include "qom/object.h" #include "hw/acpi/piix4.h" +#include "hw/ide/pci.h" #include "hw/intc/i8259.h" #include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" @@ -56,6 +57,7 @@ struct PIIXState { =20 ISAPICState pic; RTCState rtc; + PCIIDEState ide; UHCIState uhci; PIIX4PMState pm; =20 diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index df8e2e389b..4675981021 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -41,7 +41,6 @@ #include "hw/usb.h" #include "net/net.h" #include "hw/ide/pci.h" -#include "hw/ide/piix.h" #include "hw/irq.h" #include "sysemu/kvm.h" #include "hw/kvm/clock.h" @@ -98,7 +97,6 @@ static void pc_init1(MachineState *machine, PCIBus *pci_bus; ISABus *isa_bus; Object *piix4_pm; - int piix3_devfn =3D -1; qemu_irq smi_irq; GSIState *gsi_state; BusState *idebus[MAX_IDE_BUS]; @@ -252,11 +250,14 @@ static void pc_init1(MachineState *machine, for (i =3D 0; i < ISA_NUM_IRQS; i++) { qdev_connect_gpio_out(dev, i, x86ms->gsi[i]); } - piix3_devfn =3D pci_dev->devfn; isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); rtc_state =3D ISA_DEVICE(object_resolve_path_component(OBJECT(pci_= dev), "rtc")); piix4_pm =3D object_resolve_path_component(OBJECT(pci_dev), "pm"); + dev =3D DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide= ")); + pci_ide_create_devs(PCI_DEVICE(dev)); + idebus[0] =3D qdev_get_child_bus(dev, "ide.0"); + idebus[1] =3D qdev_get_child_bus(dev, "ide.1"); } else { pci_bus =3D NULL; piix4_pm =3D NULL; @@ -270,6 +271,8 @@ static void pc_init1(MachineState *machine, =20 i8257_dma_init(isa_bus, 0); pcms->hpet_enabled =3D false; + idebus[0] =3D NULL; + idebus[1] =3D NULL; } =20 if (x86ms->pic =3D=3D ON_OFF_AUTO_ON || x86ms->pic =3D=3D ON_OFF_AUTO_= AUTO) { @@ -298,12 +301,6 @@ static void pc_init1(MachineState *machine, pc_nic_init(pcmc, isa_bus, pci_bus); =20 if (pcmc->pci_enabled) { - PCIDevice *dev; - - dev =3D pci_create_simple(pci_bus, piix3_devfn + 1, TYPE_PIIX3_IDE= ); - pci_ide_create_devs(dev); - idebus[0] =3D qdev_get_child_bus(&dev->qdev, "ide.0"); - idebus[1] =3D qdev_get_child_bus(&dev->qdev, "ide.1"); pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); } #ifdef CONFIG_IDE_ISA diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 88a6bf28ea..a549b1a8a5 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -29,6 +29,7 @@ #include "hw/southbridge/piix.h" #include "hw/irq.h" #include "hw/qdev-properties.h" +#include "hw/ide/piix.h" #include "hw/isa/isa.h" #include "hw/xen/xen.h" #include "sysemu/runstate.h" @@ -317,6 +318,12 @@ static void pci_piix3_realize(PCIDevice *dev, Error **= errp) return; } =20 + /* IDE */ + qdev_prop_set_int32(DEVICE(&d->ide), "addr", dev->devfn + 1); + if (!qdev_realize(DEVICE(&d->ide), BUS(pci_bus), errp)) { + return; + } + /* USB */ if (d->has_usb) { object_initialize_child(OBJECT(dev), "uhci", &d->uhci, @@ -369,6 +376,7 @@ static void pci_piix3_init(Object *obj) =20 object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); + object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); } =20 static Property pci_piix3_props[] =3D { diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index 1291f59896..7e53dc8f82 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -74,7 +74,6 @@ config I440FX select I8259 select PCI_I440FX select PIIX3 - select IDE_PIIX select DIMM select SMBIOS select FW_CFG_DMA diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index fccf095d07..b911306909 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -36,6 +36,7 @@ config PIIX3 select ACPI_PIIX4 select I8257 select I8259 + select IDE_PIIX select ISA_BUS select MC146818RTC select USB_UHCI --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 18/33] hw/isa/piix3: Wire up ACPI interrupt internally Date: Mon, 9 Jan 2023 18:23:31 +0100 Message-Id: <20230109172347.1830-19-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=shentey@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673286308088100001 Content-Type: text/plain; charset="utf-8" Now that PIIX3 has the PIC integrated, the ACPI controller can be wired up internally. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-18-shentey@gmail.com> --- hw/i386/pc_piix.c | 1 - hw/isa/piix3.c | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 4675981021..92d9dd1ae2 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -329,7 +329,6 @@ static void pc_init1(MachineState *machine, if (piix4_pm) { smi_irq =3D qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); =20 - qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]); qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_ir= q); pcms->smbus =3D I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c"= )); /* TODO: Populate SPD eeprom data. */ diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index a549b1a8a5..6d2ffd449c 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -343,6 +343,8 @@ static void pci_piix3_realize(PCIDevice *dev, Error **e= rrp) if (!qdev_realize(DEVICE(&d->pm), BUS(pci_bus), errp)) { return; } + qdev_connect_gpio_out(DEVICE(&d->pm), 0, + qdev_get_gpio_in(DEVICE(&d->pic), 9)); } } =20 --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673285958; cv=none; d=zohomail.com; s=zohoarc; b=Urb4YMP/jWXVIEeQBm+5norrw3nl3vTTCdPv93z4eExgOfLZ8aGBsASV9XzEDXl3LaRyuD4bSA4Z9WtUQjdCdi5RoA9S/2ROLinox3KugbWM4ptSelKHQPu6N3xlUpIkrVBOO+qiZcs0GULEZ+z95yRquQv21PXWvNxpC1X4COk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673285958; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZTrYIrNaAOJ10ynaGMpgu6wEYURWdVAhdTXgUormHxM=; b=Q8/zgqcavXFJwzny1CiWFnRpOAYYxGmGGcBeNs4Q5Unr29QcElyweY6Ek9m3wzcBQ0ylcToLUdRF1p8MMJMOazBHgwkKTZEnjIu8kE56qK+AGoX2zMCNydqRIoO2GOBmnOv7yIC40c2Uc7wQi6GpiOUeUrRUUH59EeyAZjKbW4s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167328595869779.84250599298753; Mon, 9 Jan 2023 09:39:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEvuH-0003Fr-4T; Mon, 09 Jan 2023 12:25:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEvtf-0002jI-C3; Mon, 09 Jan 2023 12:25:19 -0500 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEvtd-0001Jo-Gc; Mon, 09 Jan 2023 12:25:19 -0500 Received: by mail-ej1-x62b.google.com with SMTP id fc4so21870599ejc.12; Mon, 09 Jan 2023 09:25:15 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 19/33] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS Date: Mon, 9 Jan 2023 18:23:32 +0100 Message-Id: <20230109172347.1830-20-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=shentey@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285959942100003 Content-Type: text/plain; charset="utf-8" PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise inconsistencies can occur. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-21-shentey@gmail.com> --- include/hw/southbridge/piix.h | 5 ++--- hw/isa/piix3.c | 8 ++++---- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index e3c35ca16f..f48cfd7936 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -32,7 +32,6 @@ */ #define PIIX_RCR_IOPORT 0xcf9 =20 -#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ =20 struct PIIXState { @@ -44,10 +43,10 @@ struct PIIXState { * So one PIC level is tracked by PIIX_NUM_PIRQS bits. * * PIRQ is mapped to PIC pins, we track it by - * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS =3D 64 bits with + * PIIX_NUM_PIRQS * ISA_NUM_IRQS =3D 64 bits with * pic_irq * PIIX_NUM_PIRQS + pirq */ -#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 +#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64 #error "unable to encode pic state in 64bit in pic_levels." #endif uint64_t pic_levels; diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 6d2ffd449c..e813e20639 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -52,7 +52,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix= 3, int pirq, int level) uint64_t mask; =20 pic_irq =3D piix3->dev.config[PIIX_PIRQCA + pirq]; - if (pic_irq >=3D PIIX_NUM_PIC_IRQS) { + if (pic_irq >=3D ISA_NUM_IRQS) { return; } =20 @@ -66,7 +66,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pi= rq, int level) int pic_irq; =20 pic_irq =3D piix3->dev.config[PIIX_PIRQCA + pirq]; - if (pic_irq >=3D PIIX_NUM_PIC_IRQS) { + if (pic_irq >=3D ISA_NUM_IRQS) { return; } =20 @@ -87,7 +87,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opa= que, int pin) int irq =3D piix3->dev.config[PIIX_PIRQCA + pin]; PCIINTxRoute route; =20 - if (irq < PIIX_NUM_PIC_IRQS) { + if (irq < ISA_NUM_IRQS) { route.mode =3D PCI_INTX_ENABLED; route.irq =3D irq; } else { @@ -119,7 +119,7 @@ static void piix3_write_config(PCIDevice *dev, =20 pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); piix3_update_irq_levels(piix3); - for (pic_irq =3D 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { + for (pic_irq =3D 0; pic_irq < ISA_NUM_IRQS; pic_irq++) { piix3_set_irq_pic(piix3, pic_irq); } } --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673286524; cv=none; d=zohomail.com; s=zohoarc; b=JpSp77hDLzogeXHaO8oATQN/dUEX9TE/yEDqJsSFnAhCO8uR6AS/9Y16J8NykyGvKASpof6q86hg65FNg0y3INUVarmgGgXSHFnl8OKtCOp2hWH+gsiXClsxQk19vW/GtwV7QKrNvAq50Khx7pg8c4A+CljTiPNMHupYjxpLw9s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673286524; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ROZS9DAh1LyOJO5f9sd5J7Flg4V9+Kkad/7x0aYqgvc=; b=gCExoQqQISvISHeXQ+RDlFamUdC+trCdJyTFy8edPtcO2skAANXs7Cmtv7d4YWLCSRMFYqYmWBCoVN1u+viAV2myQNSAKg//iSXe/bWyUVctPySH4ZWj32++6OIgecceHqqNxICMzY+Y1lt3lje1IW+iWgVF0eY6IKxGg7/tk5Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673286524770175.9804733318398; Mon, 9 Jan 2023 09:48:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEvuN-0003Yt-Ca; Mon, 09 Jan 2023 12:26:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEvtg-0002jz-CP; Mon, 09 Jan 2023 12:25:21 -0500 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEvte-0000yV-BV; Mon, 09 Jan 2023 12:25:19 -0500 Received: by mail-ej1-x630.google.com with SMTP id ud5so21943252ejc.4; Mon, 09 Jan 2023 09:25:16 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 20/33] hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 Date: Mon, 9 Jan 2023 18:23:33 +0100 Message-Id: <20230109172347.1830-21-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=shentey@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673286526958100001 Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-22-shentey@gmail.com> --- hw/isa/piix3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index e813e20639..c6659bbfda 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -381,7 +381,7 @@ static void pci_piix3_init(Object *obj) object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); } =20 -static Property pci_piix3_props[] =3D { +static Property pci_piix_props[] =3D { DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), @@ -408,7 +408,7 @@ static void pci_piix3_class_init(ObjectClass *klass, vo= id *data) * pc_piix.c's pc_init1() */ dc->user_creatable =3D false; - device_class_set_props(dc, pci_piix3_props); + device_class_set_props(dc, pci_piix_props); adevc->build_dev_aml =3D build_pci_isa_aml; } =20 --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673286014; cv=none; d=zohomail.com; s=zohoarc; b=IMcOUK/dT/X7gECaqwWm1YRQbRA8kLHbF4V9Yr2XIog3lwha+w5lLOEEDSGwN+s3A6skWjUI/G2N4tPiumeUnG0A+qpb59jfHbhdBj1wdMoXWPCuiZo4RTtbwEFZDzFGiwjxt1lFsUBCV0K6i+l6pftLAFbsdgK6+uBk8bK1cYk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673286014; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oNVX7gPoz1BSpxO3xGWjfBNYIjlgV62/Ccs00KSMxZU=; b=NkoubwAwVBUG4wh4NoVPGJP8Suu0sfV/Vt/PiEJWKi1T9XTu3MpQmyYarkpL0yhpZq/CIwDuQCeVgkAf14he4k4TUHEbCeuSG4H3B02Fc42GvvosNJQr+uGrd+Brd0GrXoRDEUNANtr97o0y1dShT11o5/e47w1/0JlwdpuHCVE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673286014028615.1752517969417; Mon, 9 Jan 2023 09:40:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEvtr-0002tk-00; Mon, 09 Jan 2023 12:25:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEvth-0002k9-Ck; Mon, 09 Jan 2023 12:25:21 -0500 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEvte-00011P-Ni; Mon, 09 Jan 2023 12:25:20 -0500 Received: by mail-ej1-x62a.google.com with SMTP id az20so2854306ejc.1; Mon, 09 Jan 2023 09:25:17 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id 18-20020a170906201200b00846734faa9asm3925625ejo.164.2023.01.09.09.25.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 09:25:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oNVX7gPoz1BSpxO3xGWjfBNYIjlgV62/Ccs00KSMxZU=; b=F5aSgXNN0oOJKV/MVixZWxW+C4IYabRCb3346L3M4RydAHJ9wTFaWJxRd7ehJwlbXh XeOA+4tI3n69Dw+N4f3A7GA9VUkVp0gYnYo6z5anWVSl5HJQqZOs+3tXwbqitr9ZDC78 qUbYYff8BjppJhR+JlT7yqUKMHJgpfqPa0ZsoCbKvxmbN5EfRIwmYFnSfEQO1VtNc8VJ Fb+ORvqd2LVNHRMh2NqTjb1EN3Yi3P07HX3uvjvRFe49doSeXw72LVK8xA/TZHBwli7v 6JEV/hZhrRDY/m9Aqp0/e/EsWH/ib2Dv1O+21w3+w9K2h1oQqABYvtgKJpImke0SSfCC 1LzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oNVX7gPoz1BSpxO3xGWjfBNYIjlgV62/Ccs00KSMxZU=; b=SQNVlkSNtDmI8NFpWB5sAh5BKDDEE/D9ZyJIx/coHcGvlqL+KFd9nt6e4Ql/H6gPQZ laQWCOdi9YeVHpJUEce5fYOZGq2OF0x/lGbGw+F31gF9FdnHkKZUqwSZFCgmIePDQjMS JWMS7c12tGzpoiSFwd/gp6W4KPvhKBNKmeg3pG/U0HIKOwkJxGG8ZK7MRw0ejE8Ivios 4kCl+qM4DkRuUb/qULJDKv7kU9WyiyrbHGrgXHqUvoVSH9qM1daIMvonOnzrQHe8KlpO c0NJ+HVwTV3TN0GnlNy6DaG5DG6u+9CvjZe3UfWAOtRNiNzyqyNxU+BO/Gwp8YyJRzXN uIcw== X-Gm-Message-State: AFqh2ko4Tp7XXHKz7MDh9Hx4rPhSnXJs+cvaqKEeaqiH/gS6W5eT98WR 1JtR7ZQ4cG6e/udWQQV6nrCv41L3PE1Ayg== X-Google-Smtp-Source: AMrXdXsrhwz/Lhuqex+/saHNSuT0/XGsUp/1rP8+H7rPzmOosomuHDqvZ00siHwekSw22N12hAxA5w== X-Received: by 2002:a17:907:a585:b0:7b4:edca:739 with SMTP id vs5-20020a170907a58500b007b4edca0739mr50904502ejc.5.1673285116630; Mon, 09 Jan 2023 09:25:16 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: John G Johnson , Richard Henderson , Igor Mammedov , Elena Ufimtseva , Ani Sinha , Eduardo Habkost , Gerd Hoffmann , Jagannathan Raman , "Michael S. Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 21/33] hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 Date: Mon, 9 Jan 2023 18:23:34 +0100 Message-Id: <20230109172347.1830-22-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=shentey@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673286014345100001 Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-23-shentey@gmail.com> --- hw/isa/piix3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index c6659bbfda..d674130fc9 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -145,7 +145,7 @@ static void piix3_write_config_xen(PCIDevice *dev, piix3_write_config(dev, address, val, len); } =20 -static void piix3_reset(DeviceState *dev) +static void piix_reset(DeviceState *dev) { PIIX3State *d =3D PIIX3_PCI_DEVICE(dev); uint8_t *pci_conf =3D d->dev.config; @@ -395,7 +395,7 @@ static void pci_piix3_class_init(ObjectClass *klass, vo= id *data) PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); AcpiDevAmlIfClass *adevc =3D ACPI_DEV_AML_IF_CLASS(klass); =20 - dc->reset =3D piix3_reset; + dc->reset =3D piix_reset; dc->desc =3D "ISA bridge"; dc->vmsd =3D &vmstate_piix3; dc->hotpluggable =3D false; --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673286333; cv=none; d=zohomail.com; s=zohoarc; b=eBf64EqgsvwINDHN7MdedZe2Iij2nkJtOhKlSBKdc1EFTqzq9BI84Mhz93ZPfq8QrYiUkpCWsk+mXTBthqwJOWgbiu6P/6Hh50zxQTgWBiREONCIKoXXBx8/0Aqp5kozywPgmqVQppqtCQeGrWRbrC+h0JLHfEgESi12RyqRL+Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673286333; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CxUcKaThBl8AYC0m74VCf/oU271ubQWNI8NJL87KmlU=; b=ZvUkSMxz/Dk7weosunOOvC3IL7EIZX/OeFCzg845nwq11ZEdEidKtjjqB56HM7nj4BeMrQxLxdYKdWXxIekEpdJPQ5f955ajVF+q7L10RRSx+Bn2+tm7G0dsVRNj8DmYhVlv2OJ3CMec0c2nPSw/yzoM71F5VC7YX67HRfuX1hM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673286333825808.1998715222558; Mon, 9 Jan 2023 09:45:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEvuM-0003Vk-CD; Mon, 09 Jan 2023 12:26:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEvtj-0002l8-5W; Mon, 09 Jan 2023 12:25:23 -0500 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEvtg-000131-8P; Mon, 09 Jan 2023 12:25:22 -0500 Received: by mail-ej1-x635.google.com with SMTP id u19so21852749ejm.8; Mon, 09 Jan 2023 09:25:18 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 22/33] hw/isa/piix3: Drop the "3" from PIIX base class Date: Mon, 9 Jan 2023 18:23:35 +0100 Message-Id: <20230109172347.1830-23-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=shentey@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673286334167100001 Content-Type: text/plain; charset="utf-8" This commit marks the finalization of the PIIX3 preparations to be merged with PIIX4. In particular, PIIXState is prepared to be reused in piix4.c. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-25-shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/southbridge/piix.h | 6 ++-- hw/isa/piix3.c | 60 +++++++++++++++++------------------ 2 files changed, 32 insertions(+), 34 deletions(-) diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index f48cfd7936..907c3568b6 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -72,11 +72,9 @@ struct PIIXState { bool has_usb; bool smm_enabled; }; -typedef struct PIIXState PIIX3State; =20 -#define TYPE_PIIX3_PCI_DEVICE "pci-piix3" -DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, - TYPE_PIIX3_PCI_DEVICE) +#define TYPE_PIIX_PCI_DEVICE "pci-piix" +OBJECT_DECLARE_SIMPLE_TYPE(PIIXState, PIIX_PCI_DEVICE) =20 #define TYPE_PIIX3_DEVICE "PIIX3" #define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen" diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index d674130fc9..4ce1653406 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -38,7 +38,7 @@ =20 #define XEN_PIIX_NUM_PIRQS 128ULL =20 -static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) +static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq) { qemu_set_irq(piix3->pic.in_irqs[pic_irq], !!(piix3->pic_levels & @@ -46,7 +46,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_= irq) (pic_irq * PIIX_NUM_PIRQS)))); } =20 -static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int = level) +static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int l= evel) { int pic_irq; uint64_t mask; @@ -61,7 +61,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix= 3, int pirq, int level) piix3->pic_levels |=3D mask * !!level; } =20 -static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) +static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level) { int pic_irq; =20 @@ -77,13 +77,13 @@ static void piix3_set_irq_level(PIIX3State *piix3, int = pirq, int level) =20 static void piix3_set_irq(void *opaque, int pirq, int level) { - PIIX3State *piix3 =3D opaque; + PIIXState *piix3 =3D opaque; piix3_set_irq_level(piix3, pirq, level); } =20 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { - PIIX3State *piix3 =3D opaque; + PIIXState *piix3 =3D opaque; int irq =3D piix3->dev.config[PIIX_PIRQCA + pin]; PCIINTxRoute route; =20 @@ -98,7 +98,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opa= que, int pin) } =20 /* irq routing is changed. so rebuild bitmap */ -static void piix3_update_irq_levels(PIIX3State *piix3) +static void piix3_update_irq_levels(PIIXState *piix3) { PCIBus *bus =3D pci_get_bus(&piix3->dev); int pirq; @@ -114,7 +114,7 @@ static void piix3_write_config(PCIDevice *dev, { pci_default_write_config(dev, address, val, len); if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { - PIIX3State *piix3 =3D PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 =3D PIIX_PCI_DEVICE(dev); int pic_irq; =20 pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); @@ -147,7 +147,7 @@ static void piix3_write_config_xen(PCIDevice *dev, =20 static void piix_reset(DeviceState *dev) { - PIIX3State *d =3D PIIX3_PCI_DEVICE(dev); + PIIXState *d =3D PIIX_PCI_DEVICE(dev); uint8_t *pci_conf =3D d->dev.config; =20 pci_conf[0x04] =3D 0x07; /* master, memory and I/O */ @@ -188,7 +188,7 @@ static void piix_reset(DeviceState *dev) =20 static int piix3_post_load(void *opaque, int version_id) { - PIIX3State *piix3 =3D opaque; + PIIXState *piix3 =3D opaque; int pirq; =20 /* @@ -211,7 +211,7 @@ static int piix3_post_load(void *opaque, int version_id) static int piix3_pre_save(void *opaque) { int i; - PIIX3State *piix3 =3D opaque; + PIIXState *piix3 =3D opaque; =20 for (i =3D 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { piix3->pci_irq_levels_vmstate[i] =3D @@ -223,7 +223,7 @@ static int piix3_pre_save(void *opaque) =20 static bool piix3_rcr_needed(void *opaque) { - PIIX3State *piix3 =3D opaque; + PIIXState *piix3 =3D opaque; =20 return (piix3->rcr !=3D 0); } @@ -234,7 +234,7 @@ static const VMStateDescription vmstate_piix3_rcr =3D { .minimum_version_id =3D 1, .needed =3D piix3_rcr_needed, .fields =3D (VMStateField[]) { - VMSTATE_UINT8(rcr, PIIX3State), + VMSTATE_UINT8(rcr, PIIXState), VMSTATE_END_OF_LIST() } }; @@ -246,8 +246,8 @@ static const VMStateDescription vmstate_piix3 =3D { .post_load =3D piix3_post_load, .pre_save =3D piix3_pre_save, .fields =3D (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIX3State), - VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, + VMSTATE_PCI_DEVICE(dev, PIIXState), + VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIXState, PIIX_NUM_PIRQS, 3), VMSTATE_END_OF_LIST() }, @@ -260,7 +260,7 @@ static const VMStateDescription vmstate_piix3 =3D { =20 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned le= n) { - PIIX3State *d =3D opaque; + PIIXState *d =3D opaque; =20 if (val & 4) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); @@ -271,7 +271,7 @@ static void rcr_write(void *opaque, hwaddr addr, uint64= _t val, unsigned len) =20 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) { - PIIX3State *d =3D opaque; + PIIXState *d =3D opaque; =20 return d->rcr; } @@ -288,7 +288,7 @@ static const MemoryRegionOps rcr_ops =3D { =20 static void pci_piix3_realize(PCIDevice *dev, Error **errp) { - PIIX3State *d =3D PIIX3_PCI_DEVICE(dev); + PIIXState *d =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); ISABus *isa_bus; =20 @@ -374,7 +374,7 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *= scope) =20 static void pci_piix3_init(Object *obj) { - PIIX3State *d =3D PIIX3_PCI_DEVICE(obj); + PIIXState *d =3D PIIX_PCI_DEVICE(obj); =20 object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); @@ -382,10 +382,10 @@ static void pci_piix3_init(Object *obj) } =20 static Property pci_piix_props[] =3D { - DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), - DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), - DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), - DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false), + DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0), + DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true), + DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -412,10 +412,10 @@ static void pci_piix3_class_init(ObjectClass *klass, = void *data) adevc->build_dev_aml =3D build_pci_isa_aml; } =20 -static const TypeInfo piix3_pci_type_info =3D { - .name =3D TYPE_PIIX3_PCI_DEVICE, +static const TypeInfo piix_pci_type_info =3D { + .name =3D TYPE_PIIX_PCI_DEVICE, .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PIIX3State), + .instance_size =3D sizeof(PIIXState), .instance_init =3D pci_piix3_init, .abstract =3D true, .class_init =3D pci_piix3_class_init, @@ -429,7 +429,7 @@ static const TypeInfo piix3_pci_type_info =3D { static void piix3_realize(PCIDevice *dev, Error **errp) { ERRP_GUARD(); - PIIX3State *piix3 =3D PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); =20 pci_piix3_realize(dev, errp); @@ -451,14 +451,14 @@ static void piix3_class_init(ObjectClass *klass, void= *data) =20 static const TypeInfo piix3_info =3D { .name =3D TYPE_PIIX3_DEVICE, - .parent =3D TYPE_PIIX3_PCI_DEVICE, + .parent =3D TYPE_PIIX_PCI_DEVICE, .class_init =3D piix3_class_init, }; =20 static void piix3_xen_realize(PCIDevice *dev, Error **errp) { ERRP_GUARD(); - PIIX3State *piix3 =3D PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); =20 pci_piix3_realize(dev, errp); @@ -485,13 +485,13 @@ static void piix3_xen_class_init(ObjectClass *klass, = void *data) =20 static const TypeInfo piix3_xen_info =3D { .name =3D TYPE_PIIX3_XEN_DEVICE, - .parent =3D TYPE_PIIX3_PCI_DEVICE, + .parent =3D TYPE_PIIX_PCI_DEVICE, .class_init =3D piix3_xen_class_init, }; =20 static void piix3_register_types(void) { - type_register_static(&piix3_pci_type_info); + type_register_static(&piix_pci_type_info); type_register_static(&piix3_info); type_register_static(&piix3_xen_info); } --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 23/33] hw/isa/piix4: Make PIIX4's ACPI and USB functions optional Date: Mon, 9 Jan 2023 18:23:36 +0100 Message-Id: <20230109172347.1830-24-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=shentey@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285705992100001 Content-Type: text/plain; charset="utf-8" This aligns PIIX4 with PIIX3. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-30-shentey@gmail.com> --- hw/isa/piix4.c | 44 ++++++++++++++++++++++++++++++++------------ hw/mips/malta.c | 6 ++++-- 2 files changed, 36 insertions(+), 14 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index de60ceef73..de4133f573 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -51,9 +51,16 @@ struct PIIX4State { PCIIDEState ide; UHCIState uhci; PIIX4PMState pm; + + uint32_t smb_io_base; + /* Reset Control Register */ MemoryRegion rcr_mem; uint8_t rcr; + + bool has_acpi; + bool has_usb; + bool smm_enabled; }; =20 OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE) @@ -234,17 +241,26 @@ static void piix4_realize(PCIDevice *dev, Error **err= p) } =20 /* USB */ - qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); - if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { - return; + if (s->has_usb) { + object_initialize_child(OBJECT(dev), "uhci", &s->uhci, + TYPE_PIIX4_USB_UHCI); + qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); + if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { + return; + } } =20 /* ACPI controller */ - qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); - if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { - return; + if (s->has_acpi) { + object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); + qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); + qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base= ); + qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); + if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { + return; + } + qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]); } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]); =20 pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); } @@ -255,13 +271,16 @@ static void piix4_init(Object *obj) =20 object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); - object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI); - - object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM); - qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", 0x1100); - qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", 0); } =20 +static Property piix4_props[] =3D { + DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0), + DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true), + DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false), + DEFINE_PROP_END_OF_LIST(), +}; + static void piix4_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -280,6 +299,7 @@ static void piix4_class_init(ObjectClass *klass, void *= data) */ dc->user_creatable =3D false; dc->hotpluggable =3D false; + device_class_set_props(dc, piix4_props); } =20 static const TypeInfo piix4_info =3D { diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 94d4c49bf5..4a2e0edd98 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1449,8 +1449,10 @@ void mips_malta_init(MachineState *machine) empty_slot_init("GT64120", 0, 0x20000000); =20 /* Southbridge */ - piix4 =3D pci_create_simple_multifunction(pci_bus, PIIX4_PCI_DEVFN, tr= ue, - TYPE_PIIX4_PCI_DEVICE); + piix4 =3D pci_new_multifunction(PIIX4_PCI_DEVFN, true, + TYPE_PIIX4_PCI_DEVICE); + qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100); + pci_realize_and_unref(piix4, pci_bus, &error_fatal); isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); =20 dev =3D DEVICE(object_resolve_path_component(OBJECT(piix4), "ide")); --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673285489; cv=none; d=zohomail.com; s=zohoarc; b=HaMv5lPKf8b/Yog4KOBk+dpFCmy5/NTgz4jlYC1nnKaG1MtOJiYMwEQNjmTKA06AWoh1TBgVZASl/OhxNA5zO2oA2Gnnqdq2NXJp2jhvx1n+pqVPx3wNuW3wBPm5mFZ7GmRaurgr4fd65fmsoAtMMwwfheInHEHttwc+DRIoWNE= ARC-Message-Signature: i=1; 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 24/33] hw/isa/piix4: Remove unused inbound ISA interrupt lines Date: Mon, 9 Jan 2023 18:23:37 +0100 Message-Id: <20230109172347.1830-25-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=shentey@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285491551100001 Content-Type: text/plain; charset="utf-8" The Malta board, which is the only user of PIIX4, doesn't connect to the exported interrupt lines. PIIX3 doesn't expose such interrupt lines either, so remove them for PIIX4 for simplicity and consistency. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-32-shentey@gmail.com> --- hw/isa/piix4.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index de4133f573..9edaa5de3e 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -155,12 +155,6 @@ static void piix4_request_i8259_irq(void *opaque, int = irq, int level) qemu_set_irq(s->cpu_intr, level); } =20 -static void piix4_set_i8259_irq(void *opaque, int irq, int level) -{ - PIIX4State *s =3D opaque; - qemu_set_irq(s->isa[irq], level); -} - static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { @@ -204,8 +198,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } =20 - qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq, - "isa", ISA_NUM_IRQS); qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr, "intr", 1); =20 --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673285453; cv=none; d=zohomail.com; s=zohoarc; b=gw25P+cD9hKIxq3WHCez3nIMLPykk2iFQlZKUpe4WCDRj5toRq9xt35oJ+dHw6KH+lvWTKDsO/p01YO83GLJ4T8HIGZ/1MsKMqq7S8coR0LlAEMalGJH18mlhNVyfHl3lhkY1gc9Fzb/n95YHw7fGttzXYoeaLRZteRy5GTnPSU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673285453; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IMdn1pWnXwwaTdih9emYCZADk1B97e7zAw/7nMQYL5E=; b=PLIukfyEA/IwkPAG2kmgZ5qZjWtg8WJ3ew/J5h8WD3wRakoSZ0DW86IfMKkps0Smt7GbqOn/fH3vKVAQ4wdY34wx9ys/C40FYskQZbeSafvlBCs5X89/QnvuTZ0WDhVg9FgTrQqk0bssBECT4g5pY9NES20GKp//YVzom3aE1/M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167328545354227.14615212903584; Mon, 9 Jan 2023 09:30:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEvuG-0003Eb-2J; Mon, 09 Jan 2023 12:25:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEvtn-0002mk-5u; Mon, 09 Jan 2023 12:25:27 -0500 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEvtj-0000yV-UY; Mon, 09 Jan 2023 12:25:25 -0500 Received: by mail-ej1-x630.google.com with SMTP id ud5so21943913ejc.4; Mon, 09 Jan 2023 09:25:22 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id 18-20020a170906201200b00846734faa9asm3925625ejo.164.2023.01.09.09.25.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 09:25:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IMdn1pWnXwwaTdih9emYCZADk1B97e7zAw/7nMQYL5E=; b=RSRPwX1sAgWcXr8fKGZHpY5BnMO7NdW5CR7eZHLX7HT1BxsbQf2j6r1obCUK2RzIuG Rr734INhE4fqwibDAH+XpffWN3sNdQRvyfrGDLKZ7CT6Zl8rJONF+ZkYIigK465e+821 FjaV9Sg+wMzY+Os5tVJoabJy9OynchUBzqQ8zhjZy8T+ysY24s0gsCMcsp6YpgG9K24S q4LUVyFrK7GEOa9LEt3HKopOFErdSugWr0KFINj1zcnVgp9IdOFvhkXwEiaucjWIAqvM OpuO3K4F5mMjPJk8MLCUNENk5rO86yqgo0MP3ACerBaMS4H7Xw/QDGYrVAOuFqnh+Rql VYDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IMdn1pWnXwwaTdih9emYCZADk1B97e7zAw/7nMQYL5E=; b=hrs52ueJEIDbGk4Om1FRwN0jUHxxErnq5DPJWBUm46qN8OBJeA0SNGF7m1CKXw4fXF z+yLUjqMTNccMpmCVjnOEzfP8XPFcGA0e7QbtzI6AhlGTDtwIAKK+eOMH9P1rM6pBito tJFvuGpPg0RVW7Se6/FN45bGzt/FancFzf2rBVO74T8ANCopThzqMYFd+pT9Lxwkehd5 newQFgAA8Gx9s6kEq0o3yAr4rNZSstwMBrgOWmTrKL8X9IQVnB4YTMbaOw0dlypBIx0i QtjC4OT+NaNQvF4yLqm8bWA7JQIImGCL992K0Ns5Jeiis7HeGavKA2gO/UyyulAI0A3Q zp1Q== X-Gm-Message-State: AFqh2koUZFAkHX05cx48hcPFUyhs9vmxeHC15F5zNGU6dQkkYVH3hjlb 2omWBG4b3nByce0recqXDcUvQ9s02Bffzw== X-Google-Smtp-Source: AMrXdXucGL0GNW71e0acYeSHdPkuN4mUXNEsp2IN2yJD9G9teMMcUDBiC9nxtYoY7ckhVmsBXLhcmw== X-Received: by 2002:a17:906:30c9:b0:78d:f457:1052 with SMTP id b9-20020a17090630c900b0078df4571052mr53566286ejb.15.1673285121595; Mon, 09 Jan 2023 09:25:21 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: John G Johnson , Richard Henderson , Igor Mammedov , Elena Ufimtseva , Ani Sinha , Eduardo Habkost , Gerd Hoffmann , Jagannathan Raman , "Michael S. Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 25/33] hw/isa/piix4: Use TYPE_ISA_PIC device Date: Mon, 9 Jan 2023 18:23:38 +0100 Message-Id: <20230109172347.1830-26-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=shentey@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285455596100003 Content-Type: text/plain; charset="utf-8" Aligns the code with PIIX3 such that PIIXState can be used in PIIX4, too. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-33-shentey@gmail.com> --- hw/isa/piix4.c | 28 ++++++++++------------------ hw/mips/malta.c | 11 +++++++++-- hw/mips/Kconfig | 1 + 3 files changed, 20 insertions(+), 20 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 9edaa5de3e..eae4db0182 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -44,9 +44,8 @@ =20 struct PIIX4State { PCIDevice dev; - qemu_irq cpu_intr; - qemu_irq *isa; =20 + ISAPICState pic; RTCState rtc; PCIIDEState ide; UHCIState uhci; @@ -82,7 +81,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int = level) pic_level |=3D pci_bus_get_irq_level(bus, i); } } - qemu_set_irq(s->isa[pic_irq], pic_level); + qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); } } =20 @@ -149,12 +148,6 @@ static const VMStateDescription vmstate_piix4 =3D { } }; =20 -static void piix4_request_i8259_irq(void *opaque, int irq, int level) -{ - PIIX4State *s =3D opaque; - qemu_set_irq(s->cpu_intr, level); -} - static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { @@ -190,7 +183,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) PIIX4State *s =3D PIIX4_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); ISABus *isa_bus; - qemu_irq *i8259_out_irq; =20 isa_bus =3D isa_bus_new(DEVICE(dev), pci_address_space(dev), pci_address_space_io(dev), errp); @@ -198,20 +190,18 @@ static void piix4_realize(PCIDevice *dev, Error **err= p) return; } =20 - qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr, - "intr", 1); - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, "reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &s->rcr_mem, 1); =20 /* initialize i8259 pic */ - i8259_out_irq =3D qemu_allocate_irqs(piix4_request_i8259_irq, s, 1); - s->isa =3D i8259_init(isa_bus, *i8259_out_irq); + if (!qdev_realize(DEVICE(&s->pic), NULL, errp)) { + return; + } =20 /* initialize ISA irqs */ - isa_bus_irqs(isa_bus, s->isa); + isa_bus_irqs(isa_bus, s->pic.in_irqs); =20 /* initialize pit */ i8254_pit_init(isa_bus, 0x40, 0, NULL); @@ -224,7 +214,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { return; } - s->rtc.irq =3D isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq); + s->rtc.irq =3D qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); =20 /* IDE */ qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); @@ -251,7 +241,8 @@ static void piix4_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { return; } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]); + qdev_connect_gpio_out(DEVICE(&s->pm), 0, + qdev_get_gpio_in(DEVICE(&s->pic), 9)); } =20 pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); @@ -261,6 +252,7 @@ static void piix4_init(Object *obj) { PIIX4State *s =3D PIIX4_PCI_DEVICE(obj); =20 + object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); } diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 4a2e0edd98..55f3e0c54a 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -29,6 +29,7 @@ #include "qemu/guest-random.h" #include "hw/clock.h" #include "hw/southbridge/piix.h" +#include "hw/intc/i8259.h" #include "hw/isa/superio.h" #include "hw/char/serial.h" #include "net/net.h" @@ -1280,10 +1281,11 @@ void mips_malta_init(MachineState *machine) PCIBus *pci_bus; ISABus *isa_bus; qemu_irq cbus_irq, i8259_irq; + qemu_irq *i8259; I2CBus *smbus; DriveInfo *dinfo; int fl_idx =3D 0; - int be; + int be, i; MaltaState *s; PCIDevice *piix4; DeviceState *dev; @@ -1459,7 +1461,12 @@ void mips_malta_init(MachineState *machine) pci_ide_create_devs(PCI_DEVICE(dev)); =20 /* Interrupt controller */ - qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq); + dev =3D DEVICE(object_resolve_path_component(OBJECT(piix4), "pic")); + i8259 =3D i8259_init(isa_bus, i8259_irq); + for (i =3D 0; i < ISA_NUM_IRQS; i++) { + qdev_connect_gpio_out(dev, i, i8259[i]); + } + g_free(i8259); =20 /* generate SPD EEPROM data */ dev =3D DEVICE(object_resolve_path_component(OBJECT(piix4), "pm")); diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index 4e7042f03d..d156de812c 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -1,5 +1,6 @@ config MALTA bool + select I8259 select ISA_SUPERIO select PIIX4 =20 --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 26/33] hw/isa/piix4: Reuse struct PIIXState from PIIX3 Date: Mon, 9 Jan 2023 18:23:39 +0100 Message-Id: <20230109172347.1830-27-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=shentey@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285515656100003 Content-Type: text/plain; charset="utf-8" Now that PIIX4 also uses TYPE_ISA_PIC, both implementations can share the same struct. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-34-shentey@gmail.com> --- hw/isa/piix4.c | 51 +++++++++++++++----------------------------------- 1 file changed, 15 insertions(+), 36 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index eae4db0182..ce88377630 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -42,32 +42,10 @@ #include "sysemu/runstate.h" #include "qom/object.h" =20 -struct PIIX4State { - PCIDevice dev; - - ISAPICState pic; - RTCState rtc; - PCIIDEState ide; - UHCIState uhci; - PIIX4PMState pm; - - uint32_t smb_io_base; - - /* Reset Control Register */ - MemoryRegion rcr_mem; - uint8_t rcr; - - bool has_acpi; - bool has_usb; - bool smm_enabled; -}; - -OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE) - static void piix4_set_irq(void *opaque, int irq_num, int level) { int i, pic_irq, pic_level; - PIIX4State *s =3D opaque; + PIIXState *s =3D opaque; PCIBus *bus =3D pci_get_bus(&s->dev); =20 /* now we change the pic irq level according to the piix irq mappings = */ @@ -87,7 +65,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int = level) =20 static void piix4_isa_reset(DeviceState *dev) { - PIIX4State *d =3D PIIX4_PCI_DEVICE(dev); + PIIXState *d =3D PIIX_PCI_DEVICE(dev); uint8_t *pci_conf =3D d->dev.config; =20 pci_conf[0x04] =3D 0x07; // master, memory and I/O @@ -122,12 +100,13 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0xac] =3D 0x00; pci_conf[0xae] =3D 0x00; =20 + d->pic_levels =3D 0; /* not used in PIIX4 */ d->rcr =3D 0; } =20 static int piix4_post_load(void *opaque, int version_id) { - PIIX4State *s =3D opaque; + PIIXState *s =3D opaque; =20 if (version_id =3D=3D 2) { s->rcr =3D 0; @@ -142,8 +121,8 @@ static const VMStateDescription vmstate_piix4 =3D { .minimum_version_id =3D 2, .post_load =3D piix4_post_load, .fields =3D (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIX4State), - VMSTATE_UINT8_V(rcr, PIIX4State, 3), + VMSTATE_PCI_DEVICE(dev, PIIXState), + VMSTATE_UINT8_V(rcr, PIIXState, 3), VMSTATE_END_OF_LIST() } }; @@ -151,7 +130,7 @@ static const VMStateDescription vmstate_piix4 =3D { static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { - PIIX4State *s =3D opaque; + PIIXState *s =3D opaque; =20 if (val & 4) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); @@ -163,7 +142,7 @@ static void piix4_rcr_write(void *opaque, hwaddr addr, = uint64_t val, =20 static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) { - PIIX4State *s =3D opaque; + PIIXState *s =3D opaque; =20 return s->rcr; } @@ -180,7 +159,7 @@ static const MemoryRegionOps piix4_rcr_ops =3D { =20 static void piix4_realize(PCIDevice *dev, Error **errp) { - PIIX4State *s =3D PIIX4_PCI_DEVICE(dev); + PIIXState *s =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); ISABus *isa_bus; =20 @@ -250,7 +229,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) =20 static void piix4_init(Object *obj) { - PIIX4State *s =3D PIIX4_PCI_DEVICE(obj); + PIIXState *s =3D PIIX_PCI_DEVICE(obj); =20 object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); @@ -258,10 +237,10 @@ static void piix4_init(Object *obj) } =20 static Property piix4_props[] =3D { - DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0), - DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true), - DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true), - DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false), + DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0), + DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true), + DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -289,7 +268,7 @@ static void piix4_class_init(ObjectClass *klass, void *= data) static const TypeInfo piix4_info =3D { .name =3D TYPE_PIIX4_PCI_DEVICE, .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PIIX4State), + .instance_size =3D sizeof(PIIXState), .instance_init =3D piix4_init, .class_init =3D piix4_class_init, .interfaces =3D (InterfaceInfo[]) { --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673285884; cv=none; d=zohomail.com; s=zohoarc; b=lRa0jZZVWsA5iflFENyVxIMpu6CYMxDSV5EiXTH43Q8HajdMJYEGEGU7n7lP/UtxNTYVMHVWnfXavZGbIPYteeyP78ZTQ/W3irg5sXmoys4l08iMbf8E5AhPvZvaGu8aqKnQXtDg1j/GYPm/mPbf4A1JBvSfjS5UEB56GaEASds= ARC-Message-Signature: i=1; a=rsa-sha256; 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 27/33] hw/isa/piix4: Rename reset control operations to match PIIX3 Date: Mon, 9 Jan 2023 18:23:40 +0100 Message-Id: <20230109172347.1830-28-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=shentey@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285885387100001 Both implementations are the same and will be shared upon merging. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-35-shentey@gmail.com> --- hw/isa/piix4.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index ce88377630..de7cde192f 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -127,7 +127,7 @@ static const VMStateDescription vmstate_piix4 =3D { } }; =20 -static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, +static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { PIIXState *s =3D opaque; @@ -140,16 +140,16 @@ static void piix4_rcr_write(void *opaque, hwaddr addr= , uint64_t val, s->rcr =3D val & 2; /* keep System Reset type only */ } =20 -static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) +static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned int len) { PIIXState *s =3D opaque; =20 return s->rcr; } =20 -static const MemoryRegionOps piix4_rcr_ops =3D { - .read =3D piix4_rcr_read, - .write =3D piix4_rcr_write, +static const MemoryRegionOps rcr_ops =3D { + .read =3D rcr_read, + .write =3D rcr_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .impl =3D { .min_access_size =3D 1, @@ -169,7 +169,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } =20 - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, "reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &s->rcr_mem, 1); --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673286181; cv=none; d=zohomail.com; s=zohoarc; b=dI+xHqW3L8izqIQSqjpL3pzr9x32Blz/NpGDJTqdmGcVs5VfCL+UQf/szkAWm4ysxnb2ysthfKAtAgImUV8ZJ8D9dasWxZmOv2CWRbrWhReAPLLHu+hT8ctXFoFfq+P0iW3bBG1NzC+ZTDKUDsfA3yR6GafxFsnVynqCGOv8D7Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673286181; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7h+EaidJYN1PMOh81KPeY+UFEpWpDpjeC/UX+BKgWDM=; b=ROfGMy/8pU2CvklOIsH6TNdNl7eT4PkgqD8SQ8J6F7dyKD6Cd057ZSVT0VpdBQ/ZKPu6xvnTHvcYsR2AUrA/i1IDGpFX9sOsm1eyFqauu2uQndciiufQW7kJA+vu6fPOlfaDITE1WDQTKWbmQpGBWPU0kITkv5SK5QE+9S7LJ1U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673286181565764.2836165931461; Mon, 9 Jan 2023 09:43:01 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEvuV-0004C5-S1; Mon, 09 Jan 2023 12:26:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEvtq-0002tM-Jv; Mon, 09 Jan 2023 12:25:30 -0500 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEvtn-00011P-Tk; Mon, 09 Jan 2023 12:25:30 -0500 Received: by mail-ej1-x62a.google.com with SMTP id az20so2855390ejc.1; Mon, 09 Jan 2023 09:25:26 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 28/33] hw/isa/piix3: Merge hw/isa/piix4.c Date: Mon, 9 Jan 2023 18:23:41 +0100 Message-Id: <20230109172347.1830-29-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=shentey@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673286183316100011 Now that the PIIX3 and PIIX4 device models are sufficiently consolidated, their implementations can be merged into one file for further consolidation. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-37-shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/isa/{piix3.c =3D> piix.c} | 158 ++++++++++++++++++++ hw/isa/piix4.c | 285 ------------------------------------- MAINTAINERS | 6 +- hw/i386/Kconfig | 2 +- hw/isa/Kconfig | 12 +- hw/isa/meson.build | 3 +- hw/mips/Kconfig | 2 +- 7 files changed, 165 insertions(+), 303 deletions(-) rename hw/isa/{piix3.c =3D> piix.c} (75%) delete mode 100644 hw/isa/piix4.c diff --git a/hw/isa/piix3.c b/hw/isa/piix.c similarity index 75% rename from hw/isa/piix3.c rename to hw/isa/piix.c index 4ce1653406..81cb4e64ab 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix.c @@ -2,6 +2,7 @@ * QEMU PIIX PCI ISA Bridge Emulation * * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2018 Herv=C3=A9 Poussineau * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal @@ -27,6 +28,7 @@ #include "qapi/error.h" #include "hw/dma/i8257.h" #include "hw/southbridge/piix.h" +#include "hw/timer/i8254.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/ide/piix.h" @@ -81,6 +83,27 @@ static void piix3_set_irq(void *opaque, int pirq, int le= vel) piix3_set_irq_level(piix3, pirq, level); } =20 +static void piix4_set_irq(void *opaque, int irq_num, int level) +{ + int i, pic_irq, pic_level; + PIIXState *s =3D opaque; + PCIBus *bus =3D pci_get_bus(&s->dev); + + /* now we change the pic irq level according to the piix irq mappings = */ + /* XXX: optimize */ + pic_irq =3D s->dev.config[PIIX_PIRQCA + irq_num]; + if (pic_irq < ISA_NUM_IRQS) { + /* The pic level is the logical OR of all the PCI irqs mapped to i= t. */ + pic_level =3D 0; + for (i =3D 0; i < PIIX_NUM_PIRQS; i++) { + if (pic_irq =3D=3D s->dev.config[PIIX_PIRQCA + i]) { + pic_level |=3D pci_bus_get_irq_level(bus, i); + } + } + qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); + } +} + static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { PIIXState *piix3 =3D opaque; @@ -208,6 +231,17 @@ static int piix3_post_load(void *opaque, int version_i= d) return 0; } =20 +static int piix4_post_load(void *opaque, int version_id) +{ + PIIXState *s =3D opaque; + + if (version_id =3D=3D 2) { + s->rcr =3D 0; + } + + return 0; +} + static int piix3_pre_save(void *opaque) { int i; @@ -257,6 +291,17 @@ static const VMStateDescription vmstate_piix3 =3D { } }; =20 +static const VMStateDescription vmstate_piix4 =3D { + .name =3D "PIIX4", + .version_id =3D 3, + .minimum_version_id =3D 2, + .post_load =3D piix4_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_PCI_DEVICE(dev, PIIXState), + VMSTATE_UINT8_V(rcr, PIIXState, 3), + VMSTATE_END_OF_LIST() + } +}; =20 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned le= n) { @@ -489,11 +534,124 @@ static const TypeInfo piix3_xen_info =3D { .class_init =3D piix3_xen_class_init, }; =20 +static void piix4_realize(PCIDevice *dev, Error **errp) +{ + PIIXState *s =3D PIIX_PCI_DEVICE(dev); + PCIBus *pci_bus =3D pci_get_bus(dev); + ISABus *isa_bus; + + isa_bus =3D isa_bus_new(DEVICE(dev), pci_address_space(dev), + pci_address_space_io(dev), errp); + if (!isa_bus) { + return; + } + + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, + "reset-control", 1); + memory_region_add_subregion_overlap(pci_address_space_io(dev), + PIIX_RCR_IOPORT, &s->rcr_mem, 1); + + /* initialize i8259 pic */ + if (!qdev_realize(DEVICE(&s->pic), NULL, errp)) { + return; + } + + /* initialize ISA irqs */ + isa_bus_irqs(isa_bus, s->pic.in_irqs); + + /* initialize pit */ + i8254_pit_init(isa_bus, 0x40, 0, NULL); + + /* DMA */ + i8257_dma_init(isa_bus, 0); + + /* RTC */ + qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); + if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { + return; + } + s->rtc.irq =3D qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); + + /* IDE */ + qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); + if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { + return; + } + + /* USB */ + if (s->has_usb) { + object_initialize_child(OBJECT(dev), "uhci", &s->uhci, + TYPE_PIIX4_USB_UHCI); + qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); + if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { + return; + } + } + + /* ACPI controller */ + if (s->has_acpi) { + object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); + qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); + qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base= ); + qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); + if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { + return; + } + qdev_connect_gpio_out(DEVICE(&s->pm), 0, + qdev_get_gpio_in(DEVICE(&s->pic), 9)); + } + + pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); +} + +static void piix4_init(Object *obj) +{ + PIIXState *s =3D PIIX_PCI_DEVICE(obj); + + object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); + object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); + object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); +} + +static void piix4_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->realize =3D piix4_realize; + k->vendor_id =3D PCI_VENDOR_ID_INTEL; + k->device_id =3D PCI_DEVICE_ID_INTEL_82371AB_0; + k->class_id =3D PCI_CLASS_BRIDGE_ISA; + dc->reset =3D piix_reset; + dc->desc =3D "ISA bridge"; + dc->vmsd =3D &vmstate_piix4; + /* + * Reason: part of PIIX4 southbridge, needs to be wired up, + * e.g. by mips_malta_init() + */ + dc->user_creatable =3D false; + dc->hotpluggable =3D false; + device_class_set_props(dc, pci_piix_props); +} + +static const TypeInfo piix4_info =3D { + .name =3D TYPE_PIIX4_PCI_DEVICE, + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(PIIXState), + .instance_init =3D piix4_init, + .class_init =3D piix4_class_init, + .interfaces =3D (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, +}; + static void piix3_register_types(void) { type_register_static(&piix_pci_type_info); type_register_static(&piix3_info); type_register_static(&piix3_xen_info); + type_register_static(&piix4_info); } =20 type_init(piix3_register_types) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c deleted file mode 100644 index de7cde192f..0000000000 --- a/hw/isa/piix4.c +++ /dev/null @@ -1,285 +0,0 @@ -/* - * QEMU PIIX4 PCI Bridge Emulation - * - * Copyright (c) 2006 Fabrice Bellard - * Copyright (c) 2018 Herv=C3=A9 Poussineau - * - * Permission is hereby granted, free of charge, to any person obtaining a= copy - * of this software and associated documentation files (the "Software"), t= o deal - * in the Software without restriction, including without limitation the r= ights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included= in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN - * THE SOFTWARE. - */ - -#include "qemu/osdep.h" -#include "qapi/error.h" -#include "hw/irq.h" -#include "hw/southbridge/piix.h" -#include "hw/pci/pci.h" -#include "hw/ide/piix.h" -#include "hw/isa/isa.h" -#include "hw/intc/i8259.h" -#include "hw/dma/i8257.h" -#include "hw/timer/i8254.h" -#include "hw/rtc/mc146818rtc.h" -#include "hw/ide/pci.h" -#include "hw/acpi/piix4.h" -#include "hw/usb/hcd-uhci.h" -#include "migration/vmstate.h" -#include "sysemu/reset.h" -#include "sysemu/runstate.h" -#include "qom/object.h" - -static void piix4_set_irq(void *opaque, int irq_num, int level) -{ - int i, pic_irq, pic_level; - PIIXState *s =3D opaque; - PCIBus *bus =3D pci_get_bus(&s->dev); - - /* now we change the pic irq level according to the piix irq mappings = */ - /* XXX: optimize */ - pic_irq =3D s->dev.config[PIIX_PIRQCA + irq_num]; - if (pic_irq < ISA_NUM_IRQS) { - /* The pic level is the logical OR of all the PCI irqs mapped to i= t. */ - pic_level =3D 0; - for (i =3D 0; i < PIIX_NUM_PIRQS; i++) { - if (pic_irq =3D=3D s->dev.config[PIIX_PIRQCA + i]) { - pic_level |=3D pci_bus_get_irq_level(bus, i); - } - } - qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); - } -} - -static void piix4_isa_reset(DeviceState *dev) -{ - PIIXState *d =3D PIIX_PCI_DEVICE(dev); - uint8_t *pci_conf =3D d->dev.config; - - pci_conf[0x04] =3D 0x07; // master, memory and I/O - pci_conf[0x05] =3D 0x00; - pci_conf[0x06] =3D 0x00; - pci_conf[0x07] =3D 0x02; // PCI_status_devsel_medium - pci_conf[0x4c] =3D 0x4d; - pci_conf[0x4e] =3D 0x03; - pci_conf[0x4f] =3D 0x00; - pci_conf[0x60] =3D 0x80; - pci_conf[0x61] =3D 0x80; - pci_conf[0x62] =3D 0x80; - pci_conf[0x63] =3D 0x80; - pci_conf[0x69] =3D 0x02; - pci_conf[0x70] =3D 0x80; - pci_conf[0x76] =3D 0x0c; - pci_conf[0x77] =3D 0x0c; - pci_conf[0x78] =3D 0x02; - pci_conf[0x79] =3D 0x00; - pci_conf[0x80] =3D 0x00; - pci_conf[0x82] =3D 0x00; - pci_conf[0xa0] =3D 0x08; - pci_conf[0xa2] =3D 0x00; - pci_conf[0xa3] =3D 0x00; - pci_conf[0xa4] =3D 0x00; - pci_conf[0xa5] =3D 0x00; - pci_conf[0xa6] =3D 0x00; - pci_conf[0xa7] =3D 0x00; - pci_conf[0xa8] =3D 0x0f; - pci_conf[0xaa] =3D 0x00; - pci_conf[0xab] =3D 0x00; - pci_conf[0xac] =3D 0x00; - pci_conf[0xae] =3D 0x00; - - d->pic_levels =3D 0; /* not used in PIIX4 */ - d->rcr =3D 0; -} - -static int piix4_post_load(void *opaque, int version_id) -{ - PIIXState *s =3D opaque; - - if (version_id =3D=3D 2) { - s->rcr =3D 0; - } - - return 0; -} - -static const VMStateDescription vmstate_piix4 =3D { - .name =3D "PIIX4", - .version_id =3D 3, - .minimum_version_id =3D 2, - .post_load =3D piix4_post_load, - .fields =3D (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIXState), - VMSTATE_UINT8_V(rcr, PIIXState, 3), - VMSTATE_END_OF_LIST() - } -}; - -static void rcr_write(void *opaque, hwaddr addr, uint64_t val, - unsigned int len) -{ - PIIXState *s =3D opaque; - - if (val & 4) { - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); - return; - } - - s->rcr =3D val & 2; /* keep System Reset type only */ -} - -static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned int len) -{ - PIIXState *s =3D opaque; - - return s->rcr; -} - -static const MemoryRegionOps rcr_ops =3D { - .read =3D rcr_read, - .write =3D rcr_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, - .impl =3D { - .min_access_size =3D 1, - .max_access_size =3D 1, - }, -}; - -static void piix4_realize(PCIDevice *dev, Error **errp) -{ - PIIXState *s =3D PIIX_PCI_DEVICE(dev); - PCIBus *pci_bus =3D pci_get_bus(dev); - ISABus *isa_bus; - - isa_bus =3D isa_bus_new(DEVICE(dev), pci_address_space(dev), - pci_address_space_io(dev), errp); - if (!isa_bus) { - return; - } - - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, - "reset-control", 1); - memory_region_add_subregion_overlap(pci_address_space_io(dev), - PIIX_RCR_IOPORT, &s->rcr_mem, 1); - - /* initialize i8259 pic */ - if (!qdev_realize(DEVICE(&s->pic), NULL, errp)) { - return; - } - - /* initialize ISA irqs */ - isa_bus_irqs(isa_bus, s->pic.in_irqs); - - /* initialize pit */ - i8254_pit_init(isa_bus, 0x40, 0, NULL); - - /* DMA */ - i8257_dma_init(isa_bus, 0); - - /* RTC */ - qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); - if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { - return; - } - s->rtc.irq =3D qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); - - /* IDE */ - qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); - if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { - return; - } - - /* USB */ - if (s->has_usb) { - object_initialize_child(OBJECT(dev), "uhci", &s->uhci, - TYPE_PIIX4_USB_UHCI); - qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); - if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { - return; - } - } - - /* ACPI controller */ - if (s->has_acpi) { - object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); - qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); - qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base= ); - qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); - if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { - return; - } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, - qdev_get_gpio_in(DEVICE(&s->pic), 9)); - } - - pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); -} - -static void piix4_init(Object *obj) -{ - PIIXState *s =3D PIIX_PCI_DEVICE(obj); - - object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); - object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); - object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); -} - -static Property piix4_props[] =3D { - DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0), - DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true), - DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), - DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), - DEFINE_PROP_END_OF_LIST(), -}; - -static void piix4_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); - - k->realize =3D piix4_realize; - k->vendor_id =3D PCI_VENDOR_ID_INTEL; - k->device_id =3D PCI_DEVICE_ID_INTEL_82371AB_0; - k->class_id =3D PCI_CLASS_BRIDGE_ISA; - dc->reset =3D piix4_isa_reset; - dc->desc =3D "ISA bridge"; - dc->vmsd =3D &vmstate_piix4; - /* - * Reason: part of PIIX4 southbridge, needs to be wired up, - * e.g. by mips_malta_init() - */ - dc->user_creatable =3D false; - dc->hotpluggable =3D false; - device_class_set_props(dc, piix4_props); -} - -static const TypeInfo piix4_info =3D { - .name =3D TYPE_PIIX4_PCI_DEVICE, - .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PIIXState), - .instance_init =3D piix4_init, - .class_init =3D piix4_class_init, - .interfaces =3D (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, -}; - -static void piix4_register_types(void) -{ - type_register_static(&piix4_info); -} - -type_init(piix4_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index 7a40d4d865..569042c3a1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1236,7 +1236,7 @@ Malta M: Philippe Mathieu-Daud=C3=A9 R: Aurelien Jarno S: Odd Fixes -F: hw/isa/piix4.c +F: hw/isa/piix.c F: hw/acpi/piix4.c F: hw/mips/malta.c F: hw/mips/gt64xxx_pci.c @@ -1654,7 +1654,7 @@ F: hw/pci-host/pam.c F: include/hw/pci-host/i440fx.h F: include/hw/pci-host/q35.h F: include/hw/pci-host/pam.h -F: hw/isa/piix3.c +F: hw/isa/piix.c F: hw/isa/lpc_ich9.c F: hw/i2c/smbus_ich9.c F: hw/acpi/piix4.c @@ -2344,7 +2344,7 @@ PIIX4 South Bridge (i82371AB) M: Herv=C3=A9 Poussineau M: Philippe Mathieu-Daud=C3=A9 S: Maintained -F: hw/isa/piix4.c +F: hw/isa/piix.c F: include/hw/southbridge/piix.h =20 Firmware configuration (fw_cfg) diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index 7e53dc8f82..5e04e07758 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -73,7 +73,7 @@ config I440FX select PC_ACPI select I8259 select PCI_I440FX - select PIIX3 + select PIIX select DIMM select SMBIOS select FW_CFG_DMA diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index b911306909..040a18c070 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -31,17 +31,7 @@ config PC87312 select FDC_ISA select IDE_ISA =20 -config PIIX3 - bool - select ACPI_PIIX4 - select I8257 - select I8259 - select IDE_PIIX - select ISA_BUS - select MC146818RTC - select USB_UHCI - -config PIIX4 +config PIIX bool # For historical reasons, SuperIO devices are created in the board # for PIIX4. diff --git a/hw/isa/meson.build b/hw/isa/meson.build index 8bf678ca0a..314bbd0860 100644 --- a/hw/isa/meson.build +++ b/hw/isa/meson.build @@ -3,8 +3,7 @@ softmmu_ss.add(when: 'CONFIG_I82378', if_true: files('i8237= 8.c')) softmmu_ss.add(when: 'CONFIG_ISA_BUS', if_true: files('isa-bus.c')) softmmu_ss.add(when: 'CONFIG_ISA_SUPERIO', if_true: files('isa-superio.c')) softmmu_ss.add(when: 'CONFIG_PC87312', if_true: files('pc87312.c')) -softmmu_ss.add(when: 'CONFIG_PIIX3', if_true: files('piix3.c')) -softmmu_ss.add(when: 'CONFIG_PIIX4', if_true: files('piix4.c')) +softmmu_ss.add(when: 'CONFIG_PIIX', if_true: files('piix.c')) softmmu_ss.add(when: 'CONFIG_SMC37C669', if_true: files('smc37c669-superio= .c')) softmmu_ss.add(when: 'CONFIG_VT82C686', if_true: files('vt82c686.c')) =20 diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index d156de812c..5b16ff4ed2 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -2,7 +2,7 @@ config MALTA bool select I8259 select ISA_SUPERIO - select PIIX4 + select PIIX =20 config MIPSSIM bool --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 29/33] hw/isa/piix: Harmonize names of reset control memory regions Date: Mon, 9 Jan 2023 18:23:42 +0100 Message-Id: <20230109172347.1830-30-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=shentey@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673286181370100007 There is no need for having different names here. Having the same name further allows code to be shared between PIIX3 and PIIX4. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-38-shentey@gmail.com> --- hw/isa/piix.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 81cb4e64ab..d8cd80e859 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -351,7 +351,7 @@ static void pci_piix3_realize(PCIDevice *dev, Error **e= rrp) isa_bus_irqs(isa_bus, d->pic.in_irqs); =20 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, - "piix3-reset-control", 1); + "piix-reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &d->rcr_mem, 1); =20 @@ -547,7 +547,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) } =20 memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, - "reset-control", 1); + "piix-reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &s->rcr_mem, 1); =20 --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673285402; cv=none; d=zohomail.com; s=zohoarc; b=MFVVboJsdkOqLQEAUZHKpfRZIUqhKVbB4qQawdro76ZxxIursRIYi9ATyD2rsFrWRDO/MkOwtpITp8iZwHofAJPUbSII/gOce6KhSerLcEDKIzz8Wbe7+GiZnpuoXUlPUyH07m8kTSbg9Ewp/44ejkg3g0oI4QPvylLiJTCRaus= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673285402; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OKI3pQf10L0CafJmgzqflOFdUTw3VE2jrgkDejTMPzM=; b=DWqFQ4fp6JVoyGrXTPBSrQ1KTXH3V4mo+sjyndsloGkXUq7im4I1Q2qSKZW6vF3DCIIV+1NVt55rYDzcM5CuJV/b4hhn8oTWbdv27QZHPkYE6S5IumfaqujrnriXqpRww6mfQiD3eBaFIqJl4BeKBZ48M2SPhXdtDf4Gwq/RnSg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673285402509700.0590997866514; Mon, 9 Jan 2023 09:30:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEvuK-0003TM-TH; Mon, 09 Jan 2023 12:26:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEvts-0002vo-Dd; Mon, 09 Jan 2023 12:25:34 -0500 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEvtq-00018g-I0; Mon, 09 Jan 2023 12:25:32 -0500 Received: by mail-ej1-x636.google.com with SMTP id tz12so21915150ejc.9; Mon, 09 Jan 2023 09:25:28 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 30/33] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 Date: Mon, 9 Jan 2023 18:23:43 +0100 Message-Id: <20230109172347.1830-31-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=shentey@gmail.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285403240100001 Content-Type: text/plain; charset="utf-8" Resolves duplicate code. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-39-shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/isa/piix.c | 65 +++++++-------------------------------------------- 1 file changed, 9 insertions(+), 56 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index d8cd80e859..0132f6e70a 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -331,7 +331,8 @@ static const MemoryRegionOps rcr_ops =3D { }, }; =20 -static void pci_piix3_realize(PCIDevice *dev, Error **errp) +static void pci_piix_realize(PCIDevice *dev, const char *uhci_type, + Error **errp) { PIIXState *d =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); @@ -371,8 +372,7 @@ static void pci_piix3_realize(PCIDevice *dev, Error **e= rrp) =20 /* USB */ if (d->has_usb) { - object_initialize_child(OBJECT(dev), "uhci", &d->uhci, - TYPE_PIIX3_USB_UHCI); + object_initialize_child(OBJECT(dev), "uhci", &d->uhci, uhci_type); qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2); if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) { return; @@ -477,7 +477,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp) PIIXState *piix3 =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); =20 - pci_piix3_realize(dev, errp); + pci_piix_realize(dev, TYPE_PIIX3_USB_UHCI, errp); if (*errp) { return; } @@ -506,7 +506,7 @@ static void piix3_xen_realize(PCIDevice *dev, Error **e= rrp) PIIXState *piix3 =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); =20 - pci_piix3_realize(dev, errp); + pci_piix_realize(dev, TYPE_PIIX3_USB_UHCI, errp); if (*errp) { return; } @@ -536,71 +536,24 @@ static const TypeInfo piix3_xen_info =3D { =20 static void piix4_realize(PCIDevice *dev, Error **errp) { + ERRP_GUARD(); PIIXState *s =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); ISABus *isa_bus; =20 - isa_bus =3D isa_bus_new(DEVICE(dev), pci_address_space(dev), - pci_address_space_io(dev), errp); - if (!isa_bus) { - return; - } - - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, - "piix-reset-control", 1); - memory_region_add_subregion_overlap(pci_address_space_io(dev), - PIIX_RCR_IOPORT, &s->rcr_mem, 1); - - /* initialize i8259 pic */ - if (!qdev_realize(DEVICE(&s->pic), NULL, errp)) { + pci_piix_realize(dev, TYPE_PIIX4_USB_UHCI, errp); + if (*errp) { return; } =20 - /* initialize ISA irqs */ - isa_bus_irqs(isa_bus, s->pic.in_irqs); + isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(dev), "isa.0")); =20 /* initialize pit */ i8254_pit_init(isa_bus, 0x40, 0, NULL); =20 - /* DMA */ - i8257_dma_init(isa_bus, 0); - /* RTC */ - qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); - if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { - return; - } s->rtc.irq =3D qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); =20 - /* IDE */ - qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); - if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { - return; - } - - /* USB */ - if (s->has_usb) { - object_initialize_child(OBJECT(dev), "uhci", &s->uhci, - TYPE_PIIX4_USB_UHCI); - qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); - if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { - return; - } - } - - /* ACPI controller */ - if (s->has_acpi) { - object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); - qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); - qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base= ); - qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); - if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { - return; - } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, - qdev_get_gpio_in(DEVICE(&s->pic), 9)); - } - pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); } =20 --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673285301; 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 31/33] hw/isa/piix: Rename functions to be shared for interrupt triggering Date: Mon, 9 Jan 2023 18:23:44 +0100 Message-Id: <20230109172347.1830-32-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=shentey@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673285302766100001 Content-Type: text/plain; charset="utf-8" PIIX4 will get the same optimizations which are already implemented for PIIX3. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-40-shentey@gmail.com> --- hw/isa/piix.c | 56 +++++++++++++++++++++++++-------------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 0132f6e70a..33ea5275ec 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -40,47 +40,47 @@ =20 #define XEN_PIIX_NUM_PIRQS 128ULL =20 -static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq) +static void piix_set_irq_pic(PIIXState *piix, int pic_irq) { - qemu_set_irq(piix3->pic.in_irqs[pic_irq], - !!(piix3->pic_levels & + qemu_set_irq(piix->pic.in_irqs[pic_irq], + !!(piix->pic_levels & (((1ULL << PIIX_NUM_PIRQS) - 1) << (pic_irq * PIIX_NUM_PIRQS)))); } =20 -static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int l= evel) +static void piix_set_irq_level_internal(PIIXState *piix, int pirq, int lev= el) { int pic_irq; uint64_t mask; =20 - pic_irq =3D piix3->dev.config[PIIX_PIRQCA + pirq]; + pic_irq =3D piix->dev.config[PIIX_PIRQCA + pirq]; if (pic_irq >=3D ISA_NUM_IRQS) { return; } =20 mask =3D 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); - piix3->pic_levels &=3D ~mask; - piix3->pic_levels |=3D mask * !!level; + piix->pic_levels &=3D ~mask; + piix->pic_levels |=3D mask * !!level; } =20 -static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level) +static void piix_set_irq_level(PIIXState *piix, int pirq, int level) { int pic_irq; =20 - pic_irq =3D piix3->dev.config[PIIX_PIRQCA + pirq]; + pic_irq =3D piix->dev.config[PIIX_PIRQCA + pirq]; if (pic_irq >=3D ISA_NUM_IRQS) { return; } =20 - piix3_set_irq_level_internal(piix3, pirq, level); + piix_set_irq_level_internal(piix, pirq, level); =20 - piix3_set_irq_pic(piix3, pic_irq); + piix_set_irq_pic(piix, pic_irq); } =20 -static void piix3_set_irq(void *opaque, int pirq, int level) +static void piix_set_irq(void *opaque, int pirq, int level) { - PIIXState *piix3 =3D opaque; - piix3_set_irq_level(piix3, pirq, level); + PIIXState *piix =3D opaque; + piix_set_irq_level(piix, pirq, level); } =20 static void piix4_set_irq(void *opaque, int irq_num, int level) @@ -121,29 +121,29 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void = *opaque, int pin) } =20 /* irq routing is changed. so rebuild bitmap */ -static void piix3_update_irq_levels(PIIXState *piix3) +static void piix_update_irq_levels(PIIXState *piix) { - PCIBus *bus =3D pci_get_bus(&piix3->dev); + PCIBus *bus =3D pci_get_bus(&piix->dev); int pirq; =20 - piix3->pic_levels =3D 0; + piix->pic_levels =3D 0; for (pirq =3D 0; pirq < PIIX_NUM_PIRQS; pirq++) { - piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq)); + piix_set_irq_level(piix, pirq, pci_bus_get_irq_level(bus, pirq)); } } =20 -static void piix3_write_config(PCIDevice *dev, - uint32_t address, uint32_t val, int len) +static void piix_write_config(PCIDevice *dev, uint32_t address, uint32_t v= al, + int len) { pci_default_write_config(dev, address, val, len); if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { - PIIXState *piix3 =3D PIIX_PCI_DEVICE(dev); + PIIXState *piix =3D PIIX_PCI_DEVICE(dev); int pic_irq; =20 - pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); - piix3_update_irq_levels(piix3); + pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix->dev)); + piix_update_irq_levels(piix); for (pic_irq =3D 0; pic_irq < ISA_NUM_IRQS; pic_irq++) { - piix3_set_irq_pic(piix3, pic_irq); + piix_set_irq_pic(piix, pic_irq); } } } @@ -165,7 +165,7 @@ static void piix3_write_config_xen(PCIDevice *dev, } } =20 - piix3_write_config(dev, address, val, len); + piix_write_config(dev, address, val, len); } =20 static void piix_reset(DeviceState *dev) @@ -225,7 +225,7 @@ static int piix3_post_load(void *opaque, int version_id) */ piix3->pic_levels =3D 0; for (pirq =3D 0; pirq < PIIX_NUM_PIRQS; pirq++) { - piix3_set_irq_level_internal(piix3, pirq, + piix_set_irq_level_internal(piix3, pirq, pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq)); } return 0; @@ -482,7 +482,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp) return; } =20 - pci_bus_irqs(pci_bus, piix3_set_irq, piix3, PIIX_NUM_PIRQS); + pci_bus_irqs(pci_bus, piix_set_irq, piix3, PIIX_NUM_PIRQS); pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); } =20 @@ -490,7 +490,7 @@ static void piix3_class_init(ObjectClass *klass, void *= data) { PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 - k->config_write =3D piix3_write_config; + k->config_write =3D piix_write_config; k->realize =3D piix3_realize; } =20 --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673286166; cv=none; d=zohomail.com; s=zohoarc; b=G5xwoLcrjKI1Z9sI/AVNmBz8rIiP8RfIBr7dq47jbiVYXVYCXR+qRxyBnliDesmDitn8BdVrmpGitGHpf+l/UywS/N4H2n/PHN8A3qSS2LFYpVavYvWUtjwA8upDQduVda62gq68k1YJLot95fVMTHpUflVMvIeL2sm4JmJSsds= ARC-Message-Signature: i=1; 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 32/33] hw/isa/piix: Consolidate IRQ triggering Date: Mon, 9 Jan 2023 18:23:45 +0100 Message-Id: <20230109172347.1830-33-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=shentey@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673286167217100002 Content-Type: text/plain; charset="utf-8" Speeds up PIIX4 which resolves an old TODO. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-41-shentey@gmail.com> --- hw/isa/piix.c | 26 +++----------------------- 1 file changed, 3 insertions(+), 23 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 33ea5275ec..f125a6175f 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -83,27 +83,6 @@ static void piix_set_irq(void *opaque, int pirq, int lev= el) piix_set_irq_level(piix, pirq, level); } =20 -static void piix4_set_irq(void *opaque, int irq_num, int level) -{ - int i, pic_irq, pic_level; - PIIXState *s =3D opaque; - PCIBus *bus =3D pci_get_bus(&s->dev); - - /* now we change the pic irq level according to the piix irq mappings = */ - /* XXX: optimize */ - pic_irq =3D s->dev.config[PIIX_PIRQCA + irq_num]; - if (pic_irq < ISA_NUM_IRQS) { - /* The pic level is the logical OR of all the PCI irqs mapped to i= t. */ - pic_level =3D 0; - for (i =3D 0; i < PIIX_NUM_PIRQS; i++) { - if (pic_irq =3D=3D s->dev.config[PIIX_PIRQCA + i]) { - pic_level |=3D pci_bus_get_irq_level(bus, i); - } - } - qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); - } -} - static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { PIIXState *piix3 =3D opaque; @@ -239,7 +218,7 @@ static int piix4_post_load(void *opaque, int version_id) s->rcr =3D 0; } =20 - return 0; + return piix3_post_load(opaque, version_id); } =20 static int piix3_pre_save(void *opaque) @@ -554,7 +533,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) /* RTC */ s->rtc.irq =3D qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); =20 - pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); + pci_bus_irqs(pci_bus, piix_set_irq, s, PIIX_NUM_PIRQS); } =20 static void piix4_init(Object *obj) @@ -571,6 +550,7 @@ static void piix4_class_init(ObjectClass *klass, void *= data) DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 + k->config_write =3D piix_write_config; k->realize =3D piix4_realize; k->vendor_id =3D PCI_VENDOR_ID_INTEL; k->device_id =3D PCI_DEVICE_ID_INTEL_82371AB_0; --=20 2.39.0 From nobody Sun May 19 05:00:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673286544; cv=none; d=zohomail.com; s=zohoarc; b=E9FUUEL30Qt3dSo+J3yo7DEQ2EJnKe2CucvS1d/Ryo9JJk2MraFth24P09vjSEoDp0UB++u1tiSBSsTVxfoe/p4JIEifneTzU5aZuDHOjZIGTuKy4pPap/VMkcMRW3oKj4dVbDtBBwbrUIuSDQItuPBHmOu07WGVQ/k89I82p1Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673286544; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=y67kMzKEA5zvZj3DM2r1UaT4WdFS43+t3Pu/sLLfnF0=; b=iSYPgsH0/LR4p0edC2YNwT/qVqMe2UR2V9OoMzArw6+BTVYcMtgVZA19DAdD4Brcigv2KQ9X7ki7bWx20yX2IIF041fJiK4915miEzCdgUHr4n7gx+Vgk2ApHCVyeqrB75WkAz4o+GHNf12axHckQiqw8Hmxz9oi8c99f3NiIJ0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673286544073218.59849777446425; Mon, 9 Jan 2023 09:49:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEvuN-0003a8-OF; Mon, 09 Jan 2023 12:26:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEvtz-0002wm-Mj; Mon, 09 Jan 2023 12:25:40 -0500 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEvtu-0001XM-41; Mon, 09 Jan 2023 12:25:36 -0500 Received: by mail-ej1-x635.google.com with SMTP id gh17so21952344ejb.6; Mon, 09 Jan 2023 09:25:32 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , Paolo Bonzini , John Snow , Aurelien Jarno , qemu-ppc@nongnu.org, Jiaxun Yang , qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow Subject: [PATCH v6 33/33] hw/isa/piix: Share PIIX3's base class with PIIX4 Date: Mon, 9 Jan 2023 18:23:46 +0100 Message-Id: <20230109172347.1830-34-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230109172347.1830-1-shentey@gmail.com> References: <20230109172347.1830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=shentey@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1673286544864100001 Content-Type: text/plain; charset="utf-8" Having a common base class will allow for substituting PIIX3 with PIIX4 and vice versa. Moreover, it makes PIIX4 implement the acpi-dev-aml-interface. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-42-shentey@gmail.com> --- hw/isa/piix.c | 49 ++++++++++++++++++++++--------------------------- 1 file changed, 22 insertions(+), 27 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index f125a6175f..54a1246a9d 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -396,13 +396,12 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml= *scope) } } =20 -static void pci_piix3_init(Object *obj) +static void pci_piix_init(Object *obj) { PIIXState *d =3D PIIX_PCI_DEVICE(obj); =20 object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); - object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); } =20 static Property pci_piix_props[] =3D { @@ -413,7 +412,7 @@ static Property pci_piix_props[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -static void pci_piix3_class_init(ObjectClass *klass, void *data) +static void pci_piix_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); @@ -421,11 +420,8 @@ static void pci_piix3_class_init(ObjectClass *klass, v= oid *data) =20 dc->reset =3D piix_reset; dc->desc =3D "ISA bridge"; - dc->vmsd =3D &vmstate_piix3; dc->hotpluggable =3D false; k->vendor_id =3D PCI_VENDOR_ID_INTEL; - /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ - k->device_id =3D PCI_DEVICE_ID_INTEL_82371SB_0; k->class_id =3D PCI_CLASS_BRIDGE_ISA; /* * Reason: part of PIIX3 southbridge, needs to be wired up by @@ -440,9 +436,9 @@ static const TypeInfo piix_pci_type_info =3D { .name =3D TYPE_PIIX_PCI_DEVICE, .parent =3D TYPE_PCI_DEVICE, .instance_size =3D sizeof(PIIXState), - .instance_init =3D pci_piix3_init, + .instance_init =3D pci_piix_init, .abstract =3D true, - .class_init =3D pci_piix3_class_init, + .class_init =3D pci_piix_class_init, .interfaces =3D (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, { TYPE_ACPI_DEV_AML_IF }, @@ -465,17 +461,29 @@ static void piix3_realize(PCIDevice *dev, Error **err= p) pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); } =20 +static void piix3_init(Object *obj) +{ + PIIXState *d =3D PIIX_PCI_DEVICE(obj); + + object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); +} + static void piix3_class_init(ObjectClass *klass, void *data) { + DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 k->config_write =3D piix_write_config; k->realize =3D piix3_realize; + /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ + k->device_id =3D PCI_DEVICE_ID_INTEL_82371SB_0; + dc->vmsd =3D &vmstate_piix3; } =20 static const TypeInfo piix3_info =3D { .name =3D TYPE_PIIX3_DEVICE, .parent =3D TYPE_PIIX_PCI_DEVICE, + .instance_init =3D piix3_init, .class_init =3D piix3_class_init, }; =20 @@ -501,15 +509,20 @@ static void piix3_xen_realize(PCIDevice *dev, Error *= *errp) =20 static void piix3_xen_class_init(ObjectClass *klass, void *data) { + DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 k->config_write =3D piix3_write_config_xen; k->realize =3D piix3_xen_realize; + /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ + k->device_id =3D PCI_DEVICE_ID_INTEL_82371SB_0; + dc->vmsd =3D &vmstate_piix3; } =20 static const TypeInfo piix3_xen_info =3D { .name =3D TYPE_PIIX3_XEN_DEVICE, .parent =3D TYPE_PIIX_PCI_DEVICE, + .instance_init =3D piix3_init, .class_init =3D piix3_xen_class_init, }; =20 @@ -540,8 +553,6 @@ static void piix4_init(Object *obj) { PIIXState *s =3D PIIX_PCI_DEVICE(obj); =20 - object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); - object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); } =20 @@ -552,31 +563,15 @@ static void piix4_class_init(ObjectClass *klass, void= *data) =20 k->config_write =3D piix_write_config; k->realize =3D piix4_realize; - k->vendor_id =3D PCI_VENDOR_ID_INTEL; k->device_id =3D PCI_DEVICE_ID_INTEL_82371AB_0; - k->class_id =3D PCI_CLASS_BRIDGE_ISA; - dc->reset =3D piix_reset; - dc->desc =3D "ISA bridge"; dc->vmsd =3D &vmstate_piix4; - /* - * Reason: part of PIIX4 southbridge, needs to be wired up, - * e.g. by mips_malta_init() - */ - dc->user_creatable =3D false; - dc->hotpluggable =3D false; - device_class_set_props(dc, pci_piix_props); } =20 static const TypeInfo piix4_info =3D { .name =3D TYPE_PIIX4_PCI_DEVICE, - .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PIIXState), + .parent =3D TYPE_PIIX_PCI_DEVICE, .instance_init =3D piix4_init, .class_init =3D piix4_class_init, - .interfaces =3D (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, }; =20 static void piix3_register_types(void) --=20 2.39.0