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([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.42.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:42:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CqxByOMVMdC4CXnPg+/kztWxcoqpr3Xu2ZWLOOcXjkI=; b=Lm44J9ifzkzsi4OiX/5YiVz9znpUnfrqz/YXBXng0/t/lBqEWJzEHhD1ejBW8mOrGE uxrOJmsaiAHbl6UZ721edLJ9HvW3cDKMFnXP1KuLOxZXxb0fWbyTDvYoduXJd4rPAySB sjBrXjhWxeslosK2b4Ij8KwhVouqOJFq8gLdP25J6hM0aNeFn9rrn5kj7vNYCEalBMFk C5vrOBkpZflwYmJcpFmrAPtu6rFDidyreOD9g1CtIbVO5CSYalL4ioLfthYMhnorYNoF y7J3WFqFVSN/GOcxVq9hFW/NF4VA/Qi8mX86Q66hGzqCg9rIs+D+Ljo234iAbm6mdGv3 Mi1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CqxByOMVMdC4CXnPg+/kztWxcoqpr3Xu2ZWLOOcXjkI=; b=nf2yFss7vrSy+cnhq7PkiStBASH6ITKNhJERhaNj1thiZigR/uvzzf6MnMZQ3xl4Zt plK7kS1LdtCZ47BYyPukN7OdjiQcSJzi9Rez9Txp/HHTPHoiCawdXPkSB6kf9TQykS8+ +RN1/xPLzGA+KwNFyHSZn03ngK0o6S24oU9eJB7gXu1rWIztXbYS4u5JMe9VuSp2eS4S /HfQuvKoeuJu0YUVQ3lrnRAK/+Kz0RwRUEuN08hkMj+Vnil2gJcaU1w6olaTIuoerFQm 6wOTPgaUp9vawFQCiMA+kftEEKJjfXWcaKmn3/zlcDoTnAIEsbQguPCI+kvBxmU9Bvbc +oaw== X-Gm-Message-State: AFqh2kqIeqP2uxZic8TQKewKNZZflSITRjGDKCYBH4IeGWutvy95a+0Y sekpW/A0d94Yf0n3f2Qh8BiQ3OIT5QbXiO2N X-Google-Smtp-Source: AMrXdXtcU3RClbpknS9LapTpipSvUdnFUrOqb7Lro2m9VbexrqzZzQGDQfO2qDtzPoSSTSQWAtmSig== X-Received: by 2002:a17:902:ed8b:b0:193:1f23:2966 with SMTP id e11-20020a170902ed8b00b001931f232966mr5818910plj.59.1673228571579; Sun, 08 Jan 2023 17:42:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 01/22] tcg: Split out tcg_out_exit_tb Date: Sun, 8 Jan 2023 17:42:27 -0800 Message-Id: <20230109014248.2894281-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109014248.2894281-1-richard.henderson@linaro.org> References: <20230109014248.2894281-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673228961081100005 The INDEX_op_exit_tb opcode needs no register allocation. Split out a dedicated helper function for it. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tcg.c | 4 ++++ tcg/aarch64/tcg-target.c.inc | 22 ++++++++++-------- tcg/arm/tcg-target.c.inc | 11 +++++---- tcg/i386/tcg-target.c.inc | 21 +++++++++-------- tcg/loongarch64/tcg-target.c.inc | 22 ++++++++++-------- tcg/mips/tcg-target.c.inc | 33 +++++++++++++-------------- tcg/ppc/tcg-target.c.inc | 11 +++++---- tcg/riscv/tcg-target.c.inc | 22 ++++++++++-------- tcg/s390x/tcg-target.c.inc | 23 ++++++++++--------- tcg/sparc64/tcg-target.c.inc | 39 +++++++++++++++++--------------- tcg/tci/tcg-target.c.inc | 10 ++++---- 11 files changed, 121 insertions(+), 97 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index da91779890..fa1c7fdacd 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -103,6 +103,7 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCG= Reg ret, TCGReg arg1, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); +static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]); @@ -4716,6 +4717,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= target_ulong pc_start) case INDEX_op_call: tcg_reg_alloc_call(s, op); break; + case INDEX_op_exit_tb: + tcg_out_exit_tb(s, op->args[0]); + break; case INDEX_op_dup2_vec: if (tcg_reg_alloc_dup2(s, op)) { break; diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index ad1816e32d..501b77c215 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1887,6 +1887,17 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg da= ta_reg, TCGReg addr_reg, =20 static const tcg_insn_unit *tb_ret_addr; =20 +static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) +{ + /* Reuse the zeroing that exists for goto_ptr. */ + if (a0 =3D=3D 0) { + tcg_out_goto_long(s, tcg_code_gen_epilogue); + } else { + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0); + tcg_out_goto_long(s, tb_ret_addr); + } +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -1906,16 +1917,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, #define REG0(I) (const_args[I] ? TCG_REG_XZR : (TCGReg)args[I]) =20 switch (opc) { - case INDEX_op_exit_tb: - /* Reuse the zeroing that exists for goto_ptr. */ - if (a0 =3D=3D 0) { - tcg_out_goto_long(s, tcg_code_gen_epilogue); - } else { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0); - tcg_out_goto_long(s, tb_ret_addr); - } - break; - case INDEX_op_goto_tb: tcg_debug_assert(s->tb_jmp_insn_offset !=3D NULL); /* @@ -2305,6 +2306,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ + case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ default: g_assert_not_reached(); } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 9245ea86d0..799cf13536 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1933,6 +1933,12 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is64) =20 static void tcg_out_epilogue(TCGContext *s); =20 +static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) +{ + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, arg); + tcg_out_epilogue(s); +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -1941,10 +1947,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, int c; =20 switch (opc) { - case INDEX_op_exit_tb: - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, args[0]); - tcg_out_epilogue(s); - break; case INDEX_op_goto_tb: { /* Indirect jump method */ @@ -2256,6 +2258,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_call: /* Always emitted via tcg_out_call. */ + case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ default: tcg_abort(); } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 58bd5873f5..feb257db01 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2347,6 +2347,17 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is64) #endif } =20 +static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) +{ + /* Reuse the zeroing that exists for goto_ptr. */ + if (a0 =3D=3D 0) { + tcg_out_jmp(s, tcg_code_gen_epilogue); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_EAX, a0); + tcg_out_jmp(s, tb_ret_addr); + } +} + static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -2371,15 +2382,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, const_a2 =3D const_args[2]; =20 switch (opc) { - case INDEX_op_exit_tb: - /* Reuse the zeroing that exists for goto_ptr. */ - if (a0 =3D=3D 0) { - tcg_out_jmp(s, tcg_code_gen_epilogue); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_EAX, a0); - tcg_out_jmp(s, tb_ret_addr); - } - break; case INDEX_op_goto_tb: if (s->tb_jmp_insn_offset) { /* direct jump method */ @@ -2794,6 +2796,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ + case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ default: tcg_abort(); } diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index c9e99e8ec3..29e4bfcb49 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1068,6 +1068,17 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uint= ptr_t jmp_rx, =20 static const tcg_insn_unit *tb_ret_addr; =20 +static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) +{ + /* Reuse the zeroing that exists for goto_ptr. */ + if (a0 =3D=3D 0) { + tcg_out_call_int(s, tcg_code_gen_epilogue, true); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); + tcg_out_call_int(s, tb_ret_addr, true); + } +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -1078,16 +1089,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, int c2 =3D const_args[2]; =20 switch (opc) { - case INDEX_op_exit_tb: - /* Reuse the zeroing that exists for goto_ptr. */ - if (a0 =3D=3D 0) { - tcg_out_call_int(s, tcg_code_gen_epilogue, true); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); - tcg_out_call_int(s, tb_ret_addr, true); - } - break; - case INDEX_op_goto_tb: tcg_debug_assert(s->tb_jmp_insn_offset !=3D NULL); /* @@ -1500,6 +1501,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ + case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ default: g_assert_not_reached(); } diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 292e490b5c..52881abd35 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1951,6 +1951,21 @@ static void tcg_out_clz(TCGContext *s, MIPSInsn opcv= 2, MIPSInsn opcv6, } } =20 +static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) +{ + TCGReg b0 =3D TCG_REG_ZERO; + + if (a0 & ~0xffff) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff); + b0 =3D TCG_REG_V0; + } + if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); + tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); + } + tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff); +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -1970,23 +1985,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c2 =3D const_args[2]; =20 switch (opc) { - case INDEX_op_exit_tb: - { - TCGReg b0 =3D TCG_REG_ZERO; - - a0 =3D (intptr_t)a0; - if (a0 & ~0xffff) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff); - b0 =3D TCG_REG_V0; - } - if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, - (uintptr_t)tb_ret_addr); - tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); - } - tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff); - } - break; case INDEX_op_goto_tb: /* indirect jump method */ tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); @@ -2403,6 +2401,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ + case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ default: tcg_abort(); } diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index e0621463f6..a95e4001d3 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2616,6 +2616,12 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out32(s, BCLR | BO_ALWAYS); } =20 +static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) +{ + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, arg); + tcg_out_b(s, 0, tcg_code_gen_epilogue); +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -2623,10 +2629,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGArg a0, a1, a2; =20 switch (opc) { - case INDEX_op_exit_tb: - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]); - tcg_out_b(s, 0, tcg_code_gen_epilogue); - break; case INDEX_op_goto_tb: if (s->tb_jmp_insn_offset) { /* Direct jump. */ @@ -3185,6 +3187,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ + case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ default: tcg_abort(); } diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index f741e0582d..9b42cb4b2e 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1289,6 +1289,17 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is_64) =20 static const tcg_insn_unit *tb_ret_addr; =20 +static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) +{ + /* Reuse the zeroing that exists for goto_ptr. */ + if (a0 =3D=3D 0) { + tcg_out_call_int(s, tcg_code_gen_epilogue, true); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); + tcg_out_call_int(s, tb_ret_addr, true); + } +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -1299,16 +1310,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, int c2 =3D const_args[2]; =20 switch (opc) { - case INDEX_op_exit_tb: - /* Reuse the zeroing that exists for goto_ptr. */ - if (a0 =3D=3D 0) { - tcg_out_call_int(s, tcg_code_gen_epilogue, true); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); - tcg_out_call_int(s, tb_ret_addr, true); - } - break; - case INDEX_op_goto_tb: assert(s->tb_jmp_insn_offset =3D=3D 0); /* indirect jump method */ @@ -1617,6 +1618,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ + case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ default: g_assert_not_reached(); } diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 2b38fd991d..48a0c3e3c0 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1944,6 +1944,17 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg da= ta_reg, TCGReg addr_reg, #endif } =20 +static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) +{ + /* Reuse the zeroing that exists for goto_ptr. */ + if (a0 =3D=3D 0) { + tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0); + tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr); + } +} + # define OP_32_64(x) \ case glue(glue(INDEX_op_,x),_i32): \ case glue(glue(INDEX_op_,x),_i64) @@ -1956,17 +1967,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, TCGArg a0, a1, a2; =20 switch (opc) { - case INDEX_op_exit_tb: - /* Reuse the zeroing that exists for goto_ptr. */ - a0 =3D args[0]; - if (a0 =3D=3D 0) { - tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0); - tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr); - } - break; - case INDEX_op_goto_tb: a0 =3D args[0]; /* @@ -2619,6 +2619,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ + case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ default: tcg_abort(); } diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index eb913f33c8..d2d8b46815 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1428,6 +1428,26 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg da= ta, TCGReg addr, #endif /* CONFIG_SOFTMMU */ } =20 +static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) +{ + if (check_fit_ptr(a0, 13)) { + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); + tcg_out_movi_imm13(s, TCG_REG_O0, a0); + return; + } else if (USE_REG_TB) { + intptr_t tb_diff =3D tcg_tbrel_diff(s, (void *)a0); + if (check_fit_ptr(tb_diff, 13)) { + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); + /* Note that TCG_REG_TB has been unwound to O1. */ + tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O1, tb_diff, ARITH_ADD); + return; + } + } + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff); + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); + tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR); +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -1442,24 +1462,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c2 =3D const_args[2]; =20 switch (opc) { - case INDEX_op_exit_tb: - if (check_fit_ptr(a0, 13)) { - tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); - tcg_out_movi_imm13(s, TCG_REG_O0, a0); - break; - } else if (USE_REG_TB) { - intptr_t tb_diff =3D tcg_tbrel_diff(s, (void *)a0); - if (check_fit_ptr(tb_diff, 13)) { - tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); - /* Note that TCG_REG_TB has been unwound to O1. */ - tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O1, tb_diff, ARITH_A= DD); - break; - } - } - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff); - tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); - tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR); - break; case INDEX_op_goto_tb: if (s->tb_jmp_insn_offset) { /* direct jump method */ @@ -1716,6 +1718,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ + case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ default: tcg_abort(); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index d36a7ebdd1..2f3bcce3a7 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -590,6 +590,11 @@ static void tcg_out_call(TCGContext *s, const tcg_insn= _unit *func, # define CASE_64(x) #endif =20 +static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) +{ + tcg_out_op_p(s, INDEX_op_exit_tb, (void *)arg); +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -597,10 +602,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGOpcode exts; =20 switch (opc) { - case INDEX_op_exit_tb: - tcg_out_op_p(s, opc, (void *)args[0]); - break; - case INDEX_op_goto_tb: tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); /* indirect jump method. */ @@ -779,6 +780,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ + case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ default: tcg_abort(); } --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673229087514100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/i386/tcg-target.c.inc | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index feb257db01..c4ff59e9ee 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2383,23 +2383,19 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, =20 switch (opc) { case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset) { - /* direct jump method */ - int gap; - /* jump displacement must be aligned for atomic patching; + qemu_build_assert(TCG_TARGET_HAS_direct_jump); + { + /* + * Jump displacement must be aligned for atomic patching; * see if we need to add extra nops before jump */ - gap =3D QEMU_ALIGN_PTR_UP(s->code_ptr + 1, 4) - s->code_ptr; + int gap =3D QEMU_ALIGN_PTR_UP(s->code_ptr + 1, 4) - s->code_pt= r; if (gap !=3D 1) { tcg_out_nopn(s, gap - 1); } tcg_out8(s, OPC_JMP_long); /* jmp im */ s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); tcg_out32(s, 0); - } else { - /* indirect jump method */ - tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, -1, - (intptr_t)(s->tb_jmp_target_addr + a0)); } set_jmp_reset_offset(s, a0); break; --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.42.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:42:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=XzwUZnyRNwzrgTXbl3ZOKS8AhOqGhEQmhJu+6+SsqQQ=; b=jeYoNc5jBiI8f7dIkdMlZJdP6bT8b+41TmKQ6r0iIIPR8g+9yZt7rOoYxPShyMP1Hy 7xnYwACXffbsMk+zwZOr4qHG9WFBHTBNUCqpoIaLz4fo6Nqr3Aw4hSHYCZuPei4+b5Yg BLyzikHztYIQxbaDgKuYEbm+PghGlBAgVRjXh6xYli+tGQIov9BG8By6ik6IeAsVgq69 AdE0knaxFYNMhGOahbAYZlewHI5eUxinS0iOqof1xyGtjRIfIMaB8ZpsiJIgr71X2vwy Bq+oldyfx2VzEB9ZUOSLyAvDS4t8+Pu8RUGnWBqjhMN/ROdkScit+lLqlTpcdIdRp+v+ IaCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XzwUZnyRNwzrgTXbl3ZOKS8AhOqGhEQmhJu+6+SsqQQ=; b=FajnX2lGITo6+2f1ZLX7t0meDkHIK1uF+zfPDzGJHeqpDB9WMHWhcdqNYPw5glkIWH uZjyPJcB02QLjNptqMiKuPcd0p0XpaBU2fLMz5mMHlI4+V6IiZA6rr2FbrGGKCsy6lPF pURJHo0wQJUsQQ1TnFhKkoxqK5q0OjeoVTPTkcwpVCLBuzJuxbVBpwRUbp2VX0o8XtzW qH8p8OrDzrC4HJ7KI8E04ISDL9WFx3t+72ytEgGy+hDVEfKyQ+uSJVMU3KvD0bQUxtJ5 SFxTc6cfyReso+6gvi6jzJ4pbv/I19KoHTJcUbty0RsmZ0LSB6lb4Jrpsh/eXQXDV65z 84IA== X-Gm-Message-State: AFqh2koavfGEv50vofwR3aDz2v7BKXc2RWY33LQANBPylCz1CuEmReU6 WumAf266/RF3cD+jlirudVur1vfhT9D74jrR X-Google-Smtp-Source: AMrXdXuA6QJUkp4yPTXXP65otWr/XGJ0ElzGzP6X3VBWehFjXqoHlbKm+iGsPXz8RMT5v8rGpTsj/Q== X-Received: by 2002:a17:902:d4ca:b0:191:1f16:efa3 with SMTP id o10-20020a170902d4ca00b001911f16efa3mr69451943plg.65.1673228573150; Sun, 08 Jan 2023 17:42:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 03/22] tcg/ppc: Remove unused goto_tb code for indirect jump Date: Sun, 8 Jan 2023 17:42:29 -0800 Message-Id: <20230109014248.2894281-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109014248.2894281-1-richard.henderson@linaro.org> References: <20230109014248.2894281-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673228995216100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/ppc/tcg-target.c.inc | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index a95e4001d3..b72e266990 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2630,27 +2630,21 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 switch (opc) { case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset) { - /* Direct jump. */ - if (TCG_TARGET_REG_BITS =3D=3D 64) { - /* Ensure the next insns are 8 or 16-byte aligned. */ - while ((uintptr_t)s->code_ptr & (have_isa_2_07 ? 15 : 7)) { - tcg_out32(s, NOP); - } - s->tb_jmp_insn_offset[args[0]] =3D tcg_current_code_size(s= ); - tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0)); - tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0)); - } else { - s->tb_jmp_insn_offset[args[0]] =3D tcg_current_code_size(s= ); - tcg_out32(s, B); - s->tb_jmp_reset_offset[args[0]] =3D tcg_current_code_size(= s); - break; + qemu_build_assert(TCG_TARGET_HAS_direct_jump); + /* Direct jump. */ + if (TCG_TARGET_REG_BITS =3D=3D 64) { + /* Ensure the next insns are 8 or 16-byte aligned. */ + while ((uintptr_t)s->code_ptr & (have_isa_2_07 ? 15 : 7)) { + tcg_out32(s, NOP); } + s->tb_jmp_insn_offset[args[0]] =3D tcg_current_code_size(s); + tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0)); + tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0)); } else { - /* Indirect jump. */ - tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D NULL); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0, - (intptr_t)(s->tb_jmp_insn_offset + args[0])); + s->tb_jmp_insn_offset[args[0]] =3D tcg_current_code_size(s); + tcg_out32(s, B); + s->tb_jmp_reset_offset[args[0]] =3D tcg_current_code_size(s); + break; } tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); tcg_out32(s, BCCTR | BO_ALWAYS); --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673228951; cv=none; d=zohomail.com; s=zohoarc; b=IhvqFaZQZKIhzEhad2x+xk+LXd6rweqPXgpRM20rMArL7NiLUh/j6eHpi5+x7VKLnQN5KpniwUMj0x1j1Nm7LLcseozBa3pLOmtHI3hD3m1EbNhMH1hsISlUNietAhbBN8XYYzuuwBsrGR3eHyQfWKPuPG17H7RyTcygLcPYlBI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673228951; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Xbt+7EtsDJRuy41qlehYVSoIBF1LmYyXp3uFG/l4kE4=; b=Yy7PjCHuAn26v8ZIVp0gzpQrUPB5KK5togAKOQX5/PspmQz+EjkWHmxb1uGQHglx2QTDVKcEhyqWkStyOV/qIw9s46//fHEhGguONZ37ELINOnMz6d4e2DWUqTXXtsVlMTxO2mbS2xjZYHP5EKvoASbzYCnZqYRK67tGxiqnM9c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673228951945751.2962084086132; Sun, 8 Jan 2023 17:49:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEhBi-0000lD-Js; Sun, 08 Jan 2023 20:42:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEhBg-0000kI-T9 for qemu-devel@nongnu.org; Sun, 08 Jan 2023 20:42:56 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEhBf-0001W3-6k for qemu-devel@nongnu.org; Sun, 08 Jan 2023 20:42:56 -0500 Received: by mail-pl1-x633.google.com with SMTP id d3so7940344plr.10 for ; Sun, 08 Jan 2023 17:42:54 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.42.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:42:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Xbt+7EtsDJRuy41qlehYVSoIBF1LmYyXp3uFG/l4kE4=; b=qjY15oW4U3FzdamCR1S87cyR/FSaQM2uF4zrcQ+8GwenhbaSOCpVerZjHYdZFZRvjm ixqMlD5We4n3RIuYQ2WrD1vNVCordDdLiKhgny0tlMOJRZqqMWfSFbz3ZFms5keNHqy0 FH/CE4WiHQIvs5z9mFd3oyt9OohbIxJISyHNSFmJDPtxom5UG83XsHcBh50m4fSLE7ho NnPa9i/Aeuqe2GxNrLAjLdmA2aDTwsi6uV7JHV01X3lDtJkzMpVlL7HbYkvp3qctpy7j wN8Z3Tu9/YDpJu6TtwLzbz8NH+AztfnnfjrvpvlwBqFkY7Wa3Qujm5ylmyquwycwRb1O lmkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673228952966100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/sparc64/tcg-target.c.inc | 41 +++++++++++------------------------- 1 file changed, 12 insertions(+), 29 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index d2d8b46815..26b00d1638 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -537,17 +537,6 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, T= CGArg val, return false; } =20 -static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, const void *arg) -{ - intptr_t diff =3D tcg_tbrel_diff(s, arg); - if (USE_REG_TB && check_fit_ptr(diff, 13)) { - tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff); - return; - } - tcg_out_movi(s, TCG_TYPE_PTR, ret, (uintptr_t)arg & ~0x3ff); - tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, (uintptr_t)arg & 0x3ff); -} - static void tcg_out_sety(TCGContext *s, TCGReg rs) { tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs)); @@ -1463,27 +1452,21 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 switch (opc) { case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset) { - /* direct jump method */ - if (USE_REG_TB) { - /* make sure the patch is 8-byte aligned. */ - if ((intptr_t)s->code_ptr & 4) { - tcg_out_nop(s); - } - s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); - tcg_out_sethi(s, TCG_REG_T1, 0); - tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 0, ARITH_OR); - tcg_out_arith(s, TCG_REG_G0, TCG_REG_TB, TCG_REG_T1, JMPL); - tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH= _ADD); - } else { - s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); - tcg_out32(s, CALL); + qemu_build_assert(TCG_TARGET_HAS_direct_jump); + /* Direct jump. */ + if (USE_REG_TB) { + /* make sure the patch is 8-byte aligned. */ + if ((intptr_t)s->code_ptr & 4) { tcg_out_nop(s); } + s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); + tcg_out_sethi(s, TCG_REG_T1, 0); + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 0, ARITH_OR); + tcg_out_arith(s, TCG_REG_G0, TCG_REG_TB, TCG_REG_T1, JMPL); + tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD= ); } else { - /* indirect jump method */ - tcg_out_ld_ptr(s, TCG_REG_TB, s->tb_jmp_target_addr + a0); - tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); + s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); + tcg_out32(s, CALL); tcg_out_nop(s); } set_jmp_reset_offset(s, a0); --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.42.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:42:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=grVx4B5QIXEtO36ehyBBMBW63QQU1Dpe8dKQILJNBJI=; b=SdZSjTlqnS4ZYbEYB/E6hmAepm36ot9Au2m7krN4H8o51uPvB6b9YIz+bDkSu18r9N +/RoAC98SCKwNGdum0DUXbzyqmIuGe+fCo5C94UnnQBz5dv5jowJFEU3hY3++AGkwqaH J+w9lteCl/EiENdRId6DHgxVMlBMXxw/Gc0ydMB6a34xsdjpubmRGFknf+HE7Lc7CFCV nrAhBpnfns6ZArfOer5pQDF2SY8iQ3wcdqcsJmIDJVRryLlpOVu8m/+1/i/HE+WtCjV8 /4LlH64s+IndX4XLoNc7o5Oy9CpFDbB0E+hcz6It6VN1EzTy45e+5fNcI3evY5MQo/EW UIiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=grVx4B5QIXEtO36ehyBBMBW63QQU1Dpe8dKQILJNBJI=; b=4sqaQZiDdoFKAqXji8Lr/HctpD+rrgY2/xyXhz1v1fPx2Co9KoAoRO+JQgqJ7WID8m jxZOfoHjBcjVRhPUH83f5UjNMs+nmUozHXhLUTND1gQZrk/gNG8e3WauNssvtTzslcBi TrSquFo6oD+1U6fsi4VUwWTESzPkeWn/EeJjg9QqGU9c4FT+tMgJjMjIrI4YfZaGocvE /TDUAbxEzyAw0nVDn2F2voT/H8nT7eL/ZuRuB1+DFsEOLkVdUOyUb4j8nO3xNap2FIlJ udi6AzCEC6jGXkRhhk3ZH5cg1HAILZuT/rbRXsPye8w9ItA7OkVpm8zZasJS51efTVRa kTEQ== X-Gm-Message-State: AFqh2kp1fZxGjylNomD6PkChOus4VLa12VABpK7Gzm8H+0ebn10zTwAl QtgyB8B1EQ3slkVvk7UdVHVKbbsNYCQ8FkEV X-Google-Smtp-Source: AMrXdXuneIDhqmcwLUCzmgslTJGJ2jkV2nNfZRBIRD1uzENkwbOhedMNu3LJUOd5CAhjQRqYLfNPcg== X-Received: by 2002:a17:903:328c:b0:193:37c2:89d7 with SMTP id jh12-20020a170903328c00b0019337c289d7mr377617plb.17.1673228574760; Sun, 08 Jan 2023 17:42:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 05/22] tcg: Replace asserts on tcg_jmp_insn_offset Date: Sun, 8 Jan 2023 17:42:31 -0800 Message-Id: <20230109014248.2894281-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109014248.2894281-1-richard.henderson@linaro.org> References: <20230109014248.2894281-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673228675879100001 Test TCG_TARGET_HAS_direct_jump instead of testing an implementation pointer. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/arm/tcg-target.c.inc | 2 +- tcg/loongarch64/tcg-target.c.inc | 2 +- tcg/mips/tcg-target.c.inc | 2 +- tcg/riscv/tcg-target.c.inc | 2 +- tcg/tci/tcg-target.c.inc | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 501b77c215..90af096c11 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1918,7 +1918,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 switch (opc) { case INDEX_op_goto_tb: - tcg_debug_assert(s->tb_jmp_insn_offset !=3D NULL); + qemu_build_assert(TCG_TARGET_HAS_direct_jump); /* * Ensure that ADRP+ADD are 8-byte aligned so that an atomic * write can be used to patch the target address. diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 799cf13536..033ff90daa 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1953,7 +1953,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, intptr_t ptr, dif, dil; TCGReg base =3D TCG_REG_PC; =20 - tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); + qemu_build_assert(!TCG_TARGET_HAS_direct_jump); ptr =3D (intptr_t)tcg_splitwx_to_rx(s->tb_jmp_target_addr + ar= gs[0]); dif =3D tcg_pcrel_diff(s, (void *)ptr) - 8; dil =3D sextract32(dif, 0, 12); diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 29e4bfcb49..5dd645fd17 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1090,7 +1090,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 switch (opc) { case INDEX_op_goto_tb: - tcg_debug_assert(s->tb_jmp_insn_offset !=3D NULL); + qemu_build_assert(TCG_TARGET_HAS_direct_jump); /* * Ensure that patch area is 8-byte aligned so that an * atomic write can be used to patch the target address. diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 52881abd35..02887d7cb1 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1987,7 +1987,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, switch (opc) { case INDEX_op_goto_tb: /* indirect jump method */ - tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); + qemu_build_assert(!TCG_TARGET_HAS_direct_jump); tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, (uintptr_t)(s->tb_jmp_target_addr + a0)); tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 9b42cb4b2e..b977c8025d 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1311,7 +1311,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 switch (opc) { case INDEX_op_goto_tb: - assert(s->tb_jmp_insn_offset =3D=3D 0); + qemu_build_assert(!TCG_TARGET_HAS_direct_jump); /* indirect jump method */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO, (uintptr_t)(s->tb_jmp_target_addr + a0)); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 2f3bcce3a7..ad356f1875 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -603,7 +603,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 switch (opc) { case INDEX_op_goto_tb: - tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); + qemu_build_assert(!TCG_TARGET_HAS_direct_jump); /* indirect jump method. */ tcg_out_op_p(s, opc, s->tb_jmp_target_addr + args[0]); set_jmp_reset_offset(s, args[0]); --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673228951; cv=none; d=zohomail.com; s=zohoarc; b=NaV4IYxbGSJ7a4phHUgUTrEy/7Xg22oksStfSMtcXLVuSuLJaY8WkXUVaQfiHBfhOPBqtvj2RYPj2yyx6NICIZLz/s2/aD+sbOd0wqz6BxEZgrv+/xbRpBwRNhLqukLjQ6t6N7vtoi4GIIi6LMTRPq+PPdahTTpPZ5axpdkdfnk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673228951; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.42.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:42:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Nl2kpg0vOAep8cFecUh2Ws75UWdU6NCW3Ikfwhvzzgs=; b=oAyNEWui15nTH2JnOhySKGyd5qO2DVV8MhyFWDcop6Q958/BhNor0ZDBdZor8iPU9Y 4kb8Jhlo4ewMixfk9dR9q5uIvGJ8xZiXsGvZ0Z//Xl425dmhdkSjJLDla6CSAadWWVvY gPybvYARx5E7MEAVFJmVPI6yIy9/BxQaF3qurwcOjiKGkeRTHA0Xx21KG7SIK/7yH+vK hWIM3EjVwbrhh4Kh3ypIGNWDSVoSwsT9Kq2a7kRyiXshJBY4KK5omD4d0KxXvaYKR/4B rpiq5fplvUsJYZ1NsEj354d2xtOVdsP1QUJUWyAvUuZpXwqEMwJKAGeQ2uqwPgwopS8t 050w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Nl2kpg0vOAep8cFecUh2Ws75UWdU6NCW3Ikfwhvzzgs=; b=53qhl8C2m+1cHEUI/EkrTtbLM4KFITrX/aifWyOF+Dy7yfD3MpW8fGb1NKbUvh8u0w SgZp/PU5pLGoo+ZVQGhlRZhIvKuAO7RVbz02tgsDi70MW0yyyTvbT1+riGIJWCVZ+xWw vktHSQM7+Cw3PopMGuuAsp9I0/eOyYCrbGjBJNhsZwxhMuuzU9LfgDAllfdaLkg0AVkQ GAoga8Epn1h/A2v+xTlKqhiJpoMJGtSyDsb0VHvoKPPX+kXibMlWa7WouA02g0307DfJ itI7a0GI5g+pqyXg6A6UOJDUhYtXvXDglXAnx/X0unHaxQ3IbH+dYC5X+PJXnDgu1Mvw BQFQ== X-Gm-Message-State: AFqh2krIHQ6yqcmDzFec6Lj0KSOHbeTrMWA+Fw4WwUzmDbuPdvof1uQi RJKOiUwglsoEIYvzzhXcDIbhi/HYO31QYvpC X-Google-Smtp-Source: AMrXdXs/IYqEfadX6errUjAlUSYL9fSsmSksX5a2Tv5GHCol1qr2KbtoXCIyQJWnWc6UVRPfo62WFg== X-Received: by 2002:a17:902:f68b:b0:192:751c:6e8d with SMTP id l11-20020a170902f68b00b00192751c6e8dmr75455953plg.58.1673228575531; Sun, 08 Jan 2023 17:42:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 06/22] tcg: Introduce set_jmp_insn_offset Date: Sun, 8 Jan 2023 17:42:32 -0800 Message-Id: <20230109014248.2894281-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109014248.2894281-1-richard.henderson@linaro.org> References: <20230109014248.2894281-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673228953079100005 Content-Type: text/plain; charset="utf-8" Similar to the existing set_jmp_reset_offset. Move any assert for TCG_TARGET_HAS_direct_jump into the new function (which now cannot be build-time). Will be unused if TCG_TARGET_HAS_direct_jump is constant 0, but we can't test for constant in the preprocessor, so just mark it G_GNUC_UNUSED. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tcg.c | 10 ++++++++++ tcg/aarch64/tcg-target.c.inc | 3 +-- tcg/i386/tcg-target.c.inc | 3 +-- tcg/loongarch64/tcg-target.c.inc | 3 +-- tcg/ppc/tcg-target.c.inc | 7 +++---- tcg/s390x/tcg-target.c.inc | 2 +- tcg/sparc64/tcg-target.c.inc | 5 ++--- 7 files changed, 19 insertions(+), 14 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index fa1c7fdacd..edd86d6a59 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -312,6 +312,16 @@ static void set_jmp_reset_offset(TCGContext *s, int wh= ich) s->tb_jmp_reset_offset[which] =3D tcg_current_code_size(s); } =20 +static void G_GNUC_UNUSED set_jmp_insn_offset(TCGContext *s, int which) +{ + /* + * We will check for overflow at the end of the opcode loop in + * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX. + */ + tcg_debug_assert(TCG_TARGET_HAS_direct_jump); + s->tb_jmp_insn_offset[which] =3D tcg_current_code_size(s); +} + /* Signal overflow, starting over with fewer guest insns. */ static G_NORETURN void tcg_raise_tb_overflow(TCGContext *s) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 90af096c11..59e6a08e93 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1918,7 +1918,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 switch (opc) { case INDEX_op_goto_tb: - qemu_build_assert(TCG_TARGET_HAS_direct_jump); /* * Ensure that ADRP+ADD are 8-byte aligned so that an atomic * write can be used to patch the target address. @@ -1926,7 +1925,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, if ((uintptr_t)s->code_ptr & 7) { tcg_out32(s, NOP); } - s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); + set_jmp_insn_offset(s, a0); /* * actual branch destination will be patched by * tb_target_set_jmp_target later diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index c4ff59e9ee..6fb40fe8ba 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2383,7 +2383,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, =20 switch (opc) { case INDEX_op_goto_tb: - qemu_build_assert(TCG_TARGET_HAS_direct_jump); { /* * Jump displacement must be aligned for atomic patching; @@ -2394,7 +2393,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, tcg_out_nopn(s, gap - 1); } tcg_out8(s, OPC_JMP_long); /* jmp im */ - s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); + set_jmp_insn_offset(s, a0); tcg_out32(s, 0); } set_jmp_reset_offset(s, a0); diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 5dd645fd17..bce7340604 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1090,7 +1090,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 switch (opc) { case INDEX_op_goto_tb: - qemu_build_assert(TCG_TARGET_HAS_direct_jump); /* * Ensure that patch area is 8-byte aligned so that an * atomic write can be used to patch the target address. @@ -1098,7 +1097,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, if ((uintptr_t)s->code_ptr & 7) { tcg_out_nop(s); } - s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); + set_jmp_insn_offset(s, a0); /* * actual branch destination will be patched by * tb_target_set_jmp_target later diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index b72e266990..dbe8ccd353 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2630,20 +2630,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 switch (opc) { case INDEX_op_goto_tb: - qemu_build_assert(TCG_TARGET_HAS_direct_jump); /* Direct jump. */ if (TCG_TARGET_REG_BITS =3D=3D 64) { /* Ensure the next insns are 8 or 16-byte aligned. */ while ((uintptr_t)s->code_ptr & (have_isa_2_07 ? 15 : 7)) { tcg_out32(s, NOP); } - s->tb_jmp_insn_offset[args[0]] =3D tcg_current_code_size(s); + set_jmp_insn_offset(s, args[0]); tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0)); tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0)); } else { - s->tb_jmp_insn_offset[args[0]] =3D tcg_current_code_size(s); + set_jmp_insn_offset(s, args[0]); tcg_out32(s, B); - s->tb_jmp_reset_offset[args[0]] =3D tcg_current_code_size(s); + set_jmp_reset_offset(s, args[0]); break; } tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 48a0c3e3c0..c234347d6a 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1977,7 +1977,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, tcg_out16(s, NOP); } tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); - s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); + set_jmp_insn_offset(s, a0); s->code_ptr +=3D 2; set_jmp_reset_offset(s, a0); break; diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 26b00d1638..c3109fe51b 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1452,20 +1452,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 switch (opc) { case INDEX_op_goto_tb: - qemu_build_assert(TCG_TARGET_HAS_direct_jump); /* Direct jump. */ if (USE_REG_TB) { /* make sure the patch is 8-byte aligned. */ if ((intptr_t)s->code_ptr & 4) { tcg_out_nop(s); } - s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); + set_jmp_insn_offset(s, a0); tcg_out_sethi(s, TCG_REG_T1, 0); tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 0, ARITH_OR); tcg_out_arith(s, TCG_REG_G0, TCG_REG_TB, TCG_REG_T1, JMPL); tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD= ); } else { - s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); + set_jmp_insn_offset(s, a0); tcg_out32(s, CALL); tcg_out_nop(s); } --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673228721; cv=none; d=zohomail.com; s=zohoarc; b=dzivLge3TfN04Wy+YYrtvPWFM1zYY2ZIwXTs5ad7ca+mF4+RYS/jYuf/teI505kmI1iFl6Y8M1Cq4Dp6GHrbzVmXeIe4zblMIBjwWT1DTUmMdXV0Owk63DtfHFWO5fC+0bTjpjUhb2RAs22Sdvrr2FirpaBnjN87zFgoIrCvJYY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673228721; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=l1XkOrURQbEjzKpNCT5axppzb0ADc0C5+daoVD38V04=; b=YAZagDswyCP8A+8TucZpuJfzb6XbCtxAErkrrExXry67JG7rCwL8yZOLU7xWs5A6DFMhEu3vbdtXLjjpRuU6OlgvM5quFhwSgHN3nodvY40CTSMPCnEhhkcf9XrcVBO1Dr5m2GeNI/mxHeWqNMHzmQBq8qm+qRC4S3Rkt7ItcCE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673228721160977.1955936195734; Sun, 8 Jan 2023 17:45:21 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEhBl-0000mj-Am; Sun, 08 Jan 2023 20:43:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEhBj-0000lV-Hs for qemu-devel@nongnu.org; Sun, 08 Jan 2023 20:42:59 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEhBh-0001X4-QO for qemu-devel@nongnu.org; Sun, 08 Jan 2023 20:42:59 -0500 Received: by mail-pj1-x1029.google.com with SMTP id o8-20020a17090a9f8800b00223de0364beso11214721pjp.4 for ; Sun, 08 Jan 2023 17:42:57 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.42.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:42:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l1XkOrURQbEjzKpNCT5axppzb0ADc0C5+daoVD38V04=; b=zJr2KtTfNmKXeUCwZVwwI6H/awS6AH63LmlptNMa5JJdpaFvgz+Z5n0nLY3IlbYxoJ 7wiBRRUGYUvjRew3CQz+N5JcjSZpnBBDerpmXLjlI59P8xC8XgqRRPaflhf8kDYJDPTF NLb9NDKLXjTSBUQkN0Qd3rA/gzBKDFb9Hfmu/BiwlVZbGAuL8XK1KmVThfzimtHwzFk/ cTiswneICXb8/tAKNz1vQRHQ/Ibk96r2IaCgJ0G0rnWFnKVG9hUGecdk0beNCZHc/Y5g 0sTCoIBVfuDJTxMg0/vqMvPMbp9zxyVZNnbrE+UlXsb/dK+7M7IDFdu/NOLMUSDUYrhJ W4xA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l1XkOrURQbEjzKpNCT5axppzb0ADc0C5+daoVD38V04=; b=uDyYs4asm4sQ5y1lnj7Wh1tmK1oVqcDPmZT//rVafU/+vkpmvrHdTvvj6KQ2XGsXA7 ODWGoaM/fglXsWQQDmvI9WRBlivy5f+8YK7TN/dfd8CjYbxuVtt1JmvB1iMpmB4ZX1T0 Abw+I0docguJUza+WJqwwARNYuTCZsMCG4fNY6S+Pnloz74fzPWdOLXrnBk0L2cXNkMz U/yl7oeTDeULGLlvrz0HOlQ4F6GrDotKNwqUwYwlgUPMjY8dF9xmduf9SMPgVXSxqaJZ D5mRz+nRwLuI2Z6SoElHQtD5W0wK8c0o8xcLHnkXSgI+i60b8JN+hiQBP2lpP3Mkrmtf EQsg== X-Gm-Message-State: AFqh2kp6j42QtD/pg2HcQ7o+CI6d2k3s5wXqeQlrs30RMoPFo9e7jmne elzKGRN207xSEuM8J8mPUbdXB+/jmTrwiVnt X-Google-Smtp-Source: AMrXdXuo0bqKQDpb0/O8s0zDh01bCeYiKMtAXsT4Hi/iPtus35uTPABMMtszyinNjiPEgWIaBrAfng== X-Received: by 2002:a17:902:b493:b0:189:cb73:75f0 with SMTP id y19-20020a170902b49300b00189cb7375f0mr58055220plr.8.1673228576479; Sun, 08 Jan 2023 17:42:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 07/22] tcg: Introduce get_jmp_target_addr Date: Sun, 8 Jan 2023 17:42:33 -0800 Message-Id: <20230109014248.2894281-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109014248.2894281-1-richard.henderson@linaro.org> References: <20230109014248.2894281-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673228722054100003 Similar to the existing set_jmp_reset_offset. Include the rw->rx address space conversion done by arm and s390x, and forgotten by mips and riscv. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tcg.c | 9 +++++++++ tcg/arm/tcg-target.c.inc | 2 +- tcg/mips/tcg-target.c.inc | 2 +- tcg/riscv/tcg-target.c.inc | 2 +- tcg/tci/tcg-target.c.inc | 2 +- 5 files changed, 13 insertions(+), 4 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index edd86d6a59..f59f0bfe39 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -322,6 +322,15 @@ static void G_GNUC_UNUSED set_jmp_insn_offset(TCGConte= xt *s, int which) s->tb_jmp_insn_offset[which] =3D tcg_current_code_size(s); } =20 +static uintptr_t G_GNUC_UNUSED get_jmp_target_addr(TCGContext *s, int whic= h) +{ + /* + * Return the read-execute version of the pointer, for the benefit + * of any pc-relative addressing mode. + */ + return (uintptr_t)tcg_splitwx_to_rx(s->tb_jmp_target_addr + which); +} + /* Signal overflow, starting over with fewer guest insns. */ static G_NORETURN void tcg_raise_tb_overflow(TCGContext *s) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 033ff90daa..83b6d77e2e 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1954,7 +1954,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGReg base =3D TCG_REG_PC; =20 qemu_build_assert(!TCG_TARGET_HAS_direct_jump); - ptr =3D (intptr_t)tcg_splitwx_to_rx(s->tb_jmp_target_addr + ar= gs[0]); + ptr =3D get_jmp_target_addr(s, args[0]); dif =3D tcg_pcrel_diff(s, (void *)ptr) - 8; dil =3D sextract32(dif, 0, 12); if (dif !=3D dil) { diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 02887d7cb1..c30173ab64 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1989,7 +1989,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, /* indirect jump method */ qemu_build_assert(!TCG_TARGET_HAS_direct_jump); tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, - (uintptr_t)(s->tb_jmp_target_addr + a0)); + get_jmp_target_addr(s, a0)); tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); tcg_out_nop(s); set_jmp_reset_offset(s, a0); diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index b977c8025d..5b2eac6ab8 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1314,7 +1314,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, qemu_build_assert(!TCG_TARGET_HAS_direct_jump); /* indirect jump method */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO, - (uintptr_t)(s->tb_jmp_target_addr + a0)); + get_jmp_target_addr(s, a0)); tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0); set_jmp_reset_offset(s, a0); break; diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index ad356f1875..59daffc0a0 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -605,7 +605,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: qemu_build_assert(!TCG_TARGET_HAS_direct_jump); /* indirect jump method. */ - tcg_out_op_p(s, opc, s->tb_jmp_target_addr + args[0]); + tcg_out_op_p(s, opc, (void *)get_jmp_target_addr(s, args[0])); set_jmp_reset_offset(s, args[0]); break; =20 --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.42.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:42:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l4TcKh31DNw4WagwpYMOY3ScxJfjNPX31WmXPY4VoCM=; b=e6k3n2XLgQYO3VrWuKN3JdBkkM8xtzZtY9mk+F/E6HiNS+T4qUjumz3dBFqganXDiT K43Gy6zelUWkAANJ7VLt3fTw6TkwlEgmQwc0wX72JWDhH5y1O+J4o4LUg5OANICXAdjX SoV3Qe8gTL9AHHlKzz+7caXT50ylXHW413DiU4/gi0BspUTj2w6G0Je3d8ch5K1PErcM wyxDsZjCF6D05YXH5YjS/Mz2+9SJ8FdYENIutmEZrgDEMy7XdIPJzkPPLFdRVnhbNrEi LBG2H75zTm8H72IWtAvKqe1YWSfJKMFq3ZjEgR5neCGc2wfiyWuMCdVoyGjKrdGaifh6 9zIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l4TcKh31DNw4WagwpYMOY3ScxJfjNPX31WmXPY4VoCM=; b=CDiPlmyBFsk5PkuFKYfQbmKQjcrhfgMd5pW92XbtTH2Ud8z3SatAT2LO9uRLt/W6kx 2igaqx9gPCt8Ajyfnda5+KDVgzx/xlgttJk3DshlnfeYRgbL+7A8+ShN2K0kAwkAdMdk xr9to4+ojBWdQ5LZrzbeeXyqKd0/fmmzOm3YYBF06vJAkWGThFPDAkpBaQYz2hx0I/1p gpTDfjhFIaFm+vWqmOnsz4R4ZD1Co7opquC7KPkskz9+CnU+Y46cPdNH7FFmKvn/sTlR IBMRIlEjJPVriKywyKxjLz36Tr6zAxNt64Pv4ne5Fg3teaFAYGjuYwRuP4/ga8ARdn5D r3/Q== X-Gm-Message-State: AFqh2kosnky3EbkWYExGMdl2nhGZLsSzLCAsVi1P0fcAJ7S7Hx19w5ou s5k9rHWZ103M6eaa7VPIPFKzKQkWu4qpClW2 X-Google-Smtp-Source: AMrXdXvKZZH69F8MM/wt7dbNTr5e0YqMX1I/qB5H7bBOFgieKZ1RoEzUnhe11/xrD8CL+UEBdlgo6g== X-Received: by 2002:a17:902:d386:b0:192:68e8:c60c with SMTP id e6-20020a170902d38600b0019268e8c60cmr55743745pld.31.1673228577273; Sun, 08 Jan 2023 17:42:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 08/22] tcg: Split out tcg_out_goto_tb Date: Sun, 8 Jan 2023 17:42:34 -0800 Message-Id: <20230109014248.2894281-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109014248.2894281-1-richard.henderson@linaro.org> References: <20230109014248.2894281-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673228802372100003 The INDEX_op_goto_tb opcode needs no register allocation. Split out a dedicated helper function for it. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tcg.c | 4 ++ tcg/aarch64/tcg-target.c.inc | 40 ++++++++++--------- tcg/arm/tcg-target.c.inc | 49 ++++++++++++----------- tcg/i386/tcg-target.c.inc | 33 ++++++++-------- tcg/loongarch64/tcg-target.c.inc | 38 +++++++++--------- tcg/mips/tcg-target.c.inc | 21 +++++----- tcg/ppc/tcg-target.c.inc | 52 ++++++++++++------------ tcg/riscv/tcg-target.c.inc | 20 +++++----- tcg/s390x/tcg-target.c.inc | 31 ++++++++------- tcg/sparc64/tcg-target.c.inc | 68 +++++++++++++++++--------------- tcg/tci/tcg-target.c.inc | 16 ++++---- 11 files changed, 199 insertions(+), 173 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index f59f0bfe39..467604efa3 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -104,6 +104,7 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); +static void tcg_out_goto_tb(TCGContext *s, int which); static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]); @@ -4739,6 +4740,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= target_ulong pc_start) case INDEX_op_exit_tb: tcg_out_exit_tb(s, op->args[0]); break; + case INDEX_op_goto_tb: + tcg_out_goto_tb(s, op->args[0]); + break; case INDEX_op_dup2_vec: if (tcg_reg_alloc_dup2(s, op)) { break; diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 59e6a08e93..ad35bee8af 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1898,6 +1898,26 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t= a0) } } =20 +static void tcg_out_goto_tb(TCGContext *s, int which) +{ + /* + * Ensure that ADRP+ADD are 8-byte aligned so that an atomic + * write can be used to patch the target address. + */ + if ((uintptr_t)s->code_ptr & 7) { + tcg_out32(s, NOP); + } + set_jmp_insn_offset(s, which); + /* + * actual branch destination will be patched by + * tb_target_set_jmp_target later + */ + tcg_out_insn(s, 3406, ADRP, TCG_REG_TMP, 0); + tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_TMP, TCG_REG_TMP, 0); + tcg_out_insn(s, 3207, BR, TCG_REG_TMP); + set_jmp_reset_offset(s, which); +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -1917,25 +1937,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, #define REG0(I) (const_args[I] ? TCG_REG_XZR : (TCGReg)args[I]) =20 switch (opc) { - case INDEX_op_goto_tb: - /* - * Ensure that ADRP+ADD are 8-byte aligned so that an atomic - * write can be used to patch the target address. - */ - if ((uintptr_t)s->code_ptr & 7) { - tcg_out32(s, NOP); - } - set_jmp_insn_offset(s, a0); - /* - * actual branch destination will be patched by - * tb_target_set_jmp_target later - */ - tcg_out_insn(s, 3406, ADRP, TCG_REG_TMP, 0); - tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_TMP, TCG_REG_TMP= , 0); - tcg_out_insn(s, 3207, BR, TCG_REG_TMP); - set_jmp_reset_offset(s, a0); - break; - case INDEX_op_goto_ptr: tcg_out_insn(s, 3207, BR, a0); break; @@ -2306,6 +2307,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ + case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ default: g_assert_not_reached(); } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 83b6d77e2e..b8f3b0c634 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1939,6 +1939,31 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t= arg) tcg_out_epilogue(s); } =20 +static void tcg_out_goto_tb(TCGContext *s, int which) +{ + /* Indirect jump method */ + intptr_t ptr, dif, dil; + TCGReg base =3D TCG_REG_PC; + + qemu_build_assert(!TCG_TARGET_HAS_direct_jump); + ptr =3D get_jmp_target_addr(s, which); + dif =3D tcg_pcrel_diff(s, (void *)ptr) - 8; + dil =3D sextract32(dif, 0, 12); + if (dif !=3D dil) { + /* + * The TB is close, but outside the 12 bits addressable by + * the load. We can extend this to 20 bits with a sub of a + * shifted immediate from pc. In the vastly unlikely event + * the code requires more than 1MB, we'll use 2 insns and + * be no worse off. + */ + base =3D TCG_REG_R0; + tcg_out_movi32(s, COND_AL, base, ptr - dil); + } + tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, base, dil); + set_jmp_reset_offset(s, which); +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -1947,29 +1972,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, int c; =20 switch (opc) { - case INDEX_op_goto_tb: - { - /* Indirect jump method */ - intptr_t ptr, dif, dil; - TCGReg base =3D TCG_REG_PC; - - qemu_build_assert(!TCG_TARGET_HAS_direct_jump); - ptr =3D get_jmp_target_addr(s, args[0]); - dif =3D tcg_pcrel_diff(s, (void *)ptr) - 8; - dil =3D sextract32(dif, 0, 12); - if (dif !=3D dil) { - /* The TB is close, but outside the 12 bits addressable by - the load. We can extend this to 20 bits with a sub of a - shifted immediate from pc. In the vastly unlikely event - the code requires more than 1MB, we'll use 2 insns and - be no worse off. */ - base =3D TCG_REG_R0; - tcg_out_movi32(s, COND_AL, base, ptr - dil); - } - tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, base, dil); - set_jmp_reset_offset(s, args[0]); - } - break; case INDEX_op_goto_ptr: tcg_out_b_reg(s, COND_AL, args[0]); break; @@ -2259,6 +2261,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ + case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ default: tcg_abort(); } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 6fb40fe8ba..33c4139730 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2358,6 +2358,22 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t= a0) } } =20 +static void tcg_out_goto_tb(TCGContext *s, int which) +{ + /* + * Jump displacement must be aligned for atomic patching; + * see if we need to add extra nops before jump + */ + int gap =3D QEMU_ALIGN_PTR_UP(s->code_ptr + 1, 4) - s->code_ptr; + if (gap !=3D 1) { + tcg_out_nopn(s, gap - 1); + } + tcg_out8(s, OPC_JMP_long); /* jmp im */ + set_jmp_insn_offset(s, which); + tcg_out32(s, 0); + set_jmp_reset_offset(s, which); +} + static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -2382,22 +2398,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, const_a2 =3D const_args[2]; =20 switch (opc) { - case INDEX_op_goto_tb: - { - /* - * Jump displacement must be aligned for atomic patching; - * see if we need to add extra nops before jump - */ - int gap =3D QEMU_ALIGN_PTR_UP(s->code_ptr + 1, 4) - s->code_pt= r; - if (gap !=3D 1) { - tcg_out_nopn(s, gap - 1); - } - tcg_out8(s, OPC_JMP_long); /* jmp im */ - set_jmp_insn_offset(s, a0); - tcg_out32(s, 0); - } - set_jmp_reset_offset(s, a0); - break; case INDEX_op_goto_ptr: /* jmp to the given host address (could be epilogue) */ tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, a0); @@ -2792,6 +2792,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ + case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ default: tcg_abort(); } diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index bce7340604..25de7a9ee0 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1079,6 +1079,25 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t= a0) } } =20 +static void tcg_out_goto_tb(TCGContext *s, int which) +{ + /* + * Ensure that patch area is 8-byte aligned so that an + * atomic write can be used to patch the target address. + */ + if ((uintptr_t)s->code_ptr & 7) { + tcg_out_nop(s); + } + set_jmp_insn_offset(s, which); + /* + * actual branch destination will be patched by + * tb_target_set_jmp_target later + */ + tcg_out_opc_pcaddu18i(s, TCG_REG_TMP0, 0); + tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_TMP0, 0); + set_jmp_reset_offset(s, which); +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -1089,24 +1108,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, int c2 =3D const_args[2]; =20 switch (opc) { - case INDEX_op_goto_tb: - /* - * Ensure that patch area is 8-byte aligned so that an - * atomic write can be used to patch the target address. - */ - if ((uintptr_t)s->code_ptr & 7) { - tcg_out_nop(s); - } - set_jmp_insn_offset(s, a0); - /* - * actual branch destination will be patched by - * tb_target_set_jmp_target later - */ - tcg_out_opc_pcaddu18i(s, TCG_REG_TMP0, 0); - tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_TMP0, 0); - set_jmp_reset_offset(s, a0); - break; - case INDEX_op_mb: tcg_out_mb(s, a0); break; @@ -1501,6 +1502,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ + case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ default: g_assert_not_reached(); } diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index c30173ab64..e54df4128b 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1966,6 +1966,17 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t= a0) tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff); } =20 +static void tcg_out_goto_tb(TCGContext *s, int which) +{ + /* indirect jump method */ + qemu_build_assert(!TCG_TARGET_HAS_direct_jump); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, + get_jmp_target_addr(s, which)); + tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); + tcg_out_nop(s); + set_jmp_reset_offset(s, which); +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -1985,15 +1996,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c2 =3D const_args[2]; =20 switch (opc) { - case INDEX_op_goto_tb: - /* indirect jump method */ - qemu_build_assert(!TCG_TARGET_HAS_direct_jump); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, - get_jmp_target_addr(s, a0)); - tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); - tcg_out_nop(s); - set_jmp_reset_offset(s, a0); - break; case INDEX_op_goto_ptr: /* jmp to the given host address (could be epilogue) */ tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); @@ -2402,6 +2404,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ + case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ default: tcg_abort(); } diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index dbe8ccd353..e56f86c613 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2622,6 +2622,32 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t= arg) tcg_out_b(s, 0, tcg_code_gen_epilogue); } =20 +static void tcg_out_goto_tb(TCGContext *s, int which) +{ + /* Direct jump. */ + if (TCG_TARGET_REG_BITS =3D=3D 64) { + /* Ensure the next insns are 8 or 16-byte aligned. */ + while ((uintptr_t)s->code_ptr & (have_isa_2_07 ? 15 : 7)) { + tcg_out32(s, NOP); + } + set_jmp_insn_offset(s, which); + tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0)); + tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0)); + tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); + tcg_out32(s, BCCTR | BO_ALWAYS); + set_jmp_reset_offset(s, which); + if (USE_REG_TB) { + /* For the unlinked case, need to reset TCG_REG_TB. */ + tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB, + -tcg_current_code_size(s)); + } + } else { + set_jmp_insn_offset(s, which); + tcg_out32(s, B); + set_jmp_reset_offset(s, which); + } +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -2629,31 +2655,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGArg a0, a1, a2; =20 switch (opc) { - case INDEX_op_goto_tb: - /* Direct jump. */ - if (TCG_TARGET_REG_BITS =3D=3D 64) { - /* Ensure the next insns are 8 or 16-byte aligned. */ - while ((uintptr_t)s->code_ptr & (have_isa_2_07 ? 15 : 7)) { - tcg_out32(s, NOP); - } - set_jmp_insn_offset(s, args[0]); - tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0)); - tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0)); - } else { - set_jmp_insn_offset(s, args[0]); - tcg_out32(s, B); - set_jmp_reset_offset(s, args[0]); - break; - } - tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); - tcg_out32(s, BCCTR | BO_ALWAYS); - set_jmp_reset_offset(s, args[0]); - if (USE_REG_TB) { - /* For the unlinked case, need to reset TCG_REG_TB. */ - tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB, - -tcg_current_code_size(s)); - } - break; case INDEX_op_goto_ptr: tcg_out32(s, MTSPR | RS(args[0]) | CTR); if (USE_REG_TB) { @@ -3181,6 +3182,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ + case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ default: tcg_abort(); } diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 5b2eac6ab8..ee6759f787 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1300,6 +1300,16 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t= a0) } } =20 +static void tcg_out_goto_tb(TCGContext *s, int which) +{ + qemu_build_assert(!TCG_TARGET_HAS_direct_jump); + /* indirect jump method */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO, + get_jmp_target_addr(s, which)); + tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0); + set_jmp_reset_offset(s, which); +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -1310,15 +1320,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, int c2 =3D const_args[2]; =20 switch (opc) { - case INDEX_op_goto_tb: - qemu_build_assert(!TCG_TARGET_HAS_direct_jump); - /* indirect jump method */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO, - get_jmp_target_addr(s, a0)); - tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0); - set_jmp_reset_offset(s, a0); - break; - case INDEX_op_goto_ptr: tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0); break; @@ -1619,6 +1620,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ + case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ default: g_assert_not_reached(); } diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index c234347d6a..e008f0efcc 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1955,6 +1955,21 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t= a0) } } =20 +static void tcg_out_goto_tb(TCGContext *s, int which) +{ + /* + * Branch displacement must be aligned for atomic patching; + * see if we need to add extra nop before branch + */ + if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { + tcg_out16(s, NOP); + } + tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); + set_jmp_insn_offset(s, which); + s->code_ptr +=3D 2; + set_jmp_reset_offset(s, which); +} + # define OP_32_64(x) \ case glue(glue(INDEX_op_,x),_i32): \ case glue(glue(INDEX_op_,x),_i64) @@ -1967,21 +1982,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, TCGArg a0, a1, a2; =20 switch (opc) { - case INDEX_op_goto_tb: - a0 =3D args[0]; - /* - * branch displacement must be aligned for atomic patching; - * see if we need to add extra nop before branch - */ - if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { - tcg_out16(s, NOP); - } - tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); - set_jmp_insn_offset(s, a0); - s->code_ptr +=3D 2; - set_jmp_reset_offset(s, a0); - break; - case INDEX_op_goto_ptr: a0 =3D args[0]; tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0); @@ -2620,6 +2620,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ + case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ default: tcg_abort(); } diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index c3109fe51b..594767ded8 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1437,6 +1437,41 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t= a0) tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR); } =20 +static void tcg_out_goto_tb(TCGContext *s, int which) +{ + /* Direct jump. */ + if (USE_REG_TB) { + /* make sure the patch is 8-byte aligned. */ + if ((intptr_t)s->code_ptr & 4) { + tcg_out_nop(s); + } + set_jmp_insn_offset(s, which); + tcg_out_sethi(s, TCG_REG_T1, 0); + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 0, ARITH_OR); + tcg_out_arith(s, TCG_REG_G0, TCG_REG_TB, TCG_REG_T1, JMPL); + tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); + } else { + set_jmp_insn_offset(s, which); + tcg_out32(s, CALL); + tcg_out_nop(s); + } + set_jmp_reset_offset(s, which); + + /* + * For the unlinked path of goto_tb, we need to reset TCG_REG_TB + * to the beginning of this TB. + */ + if (USE_REG_TB) { + int c =3D -tcg_current_code_size(s); + if (check_fit_i32(c, 13)) { + tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, c); + tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD= ); + } + } +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -1451,38 +1486,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c2 =3D const_args[2]; =20 switch (opc) { - case INDEX_op_goto_tb: - /* Direct jump. */ - if (USE_REG_TB) { - /* make sure the patch is 8-byte aligned. */ - if ((intptr_t)s->code_ptr & 4) { - tcg_out_nop(s); - } - set_jmp_insn_offset(s, a0); - tcg_out_sethi(s, TCG_REG_T1, 0); - tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 0, ARITH_OR); - tcg_out_arith(s, TCG_REG_G0, TCG_REG_TB, TCG_REG_T1, JMPL); - tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD= ); - } else { - set_jmp_insn_offset(s, a0); - tcg_out32(s, CALL); - tcg_out_nop(s); - } - set_jmp_reset_offset(s, a0); - - /* For the unlinked path of goto_tb, we need to reset - TCG_REG_TB to the beginning of this TB. */ - if (USE_REG_TB) { - c =3D -tcg_current_code_size(s); - if (check_fit_i32(c, 13)) { - tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, c); - tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, - TCG_REG_T1, ARITH_ADD); - } - } - break; case INDEX_op_goto_ptr: tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL); if (USE_REG_TB) { @@ -1701,6 +1704,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ + case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ default: tcg_abort(); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 59daffc0a0..f2ac356900 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -595,6 +595,14 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t a= rg) tcg_out_op_p(s, INDEX_op_exit_tb, (void *)arg); } =20 +static void tcg_out_goto_tb(TCGContext *s, int which) +{ + qemu_build_assert(!TCG_TARGET_HAS_direct_jump); + /* indirect jump method. */ + tcg_out_op_p(s, INDEX_op_goto_tb, (void *)get_jmp_target_addr(s, which= )); + set_jmp_reset_offset(s, which); +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -602,13 +610,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGOpcode exts; =20 switch (opc) { - case INDEX_op_goto_tb: - qemu_build_assert(!TCG_TARGET_HAS_direct_jump); - /* indirect jump method. */ - tcg_out_op_p(s, opc, (void *)get_jmp_target_addr(s, args[0])); - set_jmp_reset_offset(s, args[0]); - break; - case INDEX_op_goto_ptr: tcg_out_op_r(s, opc, args[0]); break; @@ -781,6 +782,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ + case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ default: tcg_abort(); } --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673228881; cv=none; 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([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.42.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:42:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NWiFXNj6R/76TLM7GNYc4jJNs/0+KnaQLuUilm2f5p4=; b=HFprXzECG0BGuFPIJO+kfDkINr6KVgS2QisMXH6QfikJGIIbf5bmWQCF/GuOwG2+Ss K2pNT6nJmvnp/2qNyDG8wb2gc3qyBjTkto79caN/a5QkozOTt4PpbtQj3EDyjIs5Dmzd ld5y3X+/6cz9BrEdomFsvZ8mgZs/g5c8yi4Kn1lzsJUV2YzrdMeDHWlcFT5f3fmGIim+ 2VeD6we9DDx0aBnfKFhwzAugefFuGVzB95miObLyt4+FYXwr/bz/0X4zBemN2sdCIobE Csw0ERJaHjJsEqR5n7EYV9a5HcrCh6YKl4fSWWLbNI1y4R+oM5uguDPTsAeMyN7cGHbA iB4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NWiFXNj6R/76TLM7GNYc4jJNs/0+KnaQLuUilm2f5p4=; b=j+nI7Yd4lqPR/9Hh2gBec8c6XMHuqdgHaEXnHuQUfsrxtb9Fek3jKm/ClA5QVpqtME /80xcSLREYskDPwcs/EkfiQf1HwHkRsrbKcGNsbGe1YXTLYRn7H3QkCXccci9pphG5YY ohaIR08IN1y+KdPGT/rM2h0nsYlwT74RjSyoTOI5mQw6vWw3oOJXPlmi5YtXDgu1pRJ9 95zH9pUs/vpXFe7HLSwNJvxBin9A1zA/y3VEPKKCP+uhLCo8uzBWVRvpDFwh4ouu91/G FXdqMRMe/Nu6L1aAsxExwScDFZhYP0zSDGbVHhbDnqACu/KRM42I+r+41UT4y1lnST12 z+8Q== X-Gm-Message-State: AFqh2kppviLvdRlsUfjwr14K7jfoNweAL7yxAdsDOxfm6F2CygJL4QNj E5veAxgHppdwNhSALpyaekIVbVST9HIvV+fA X-Google-Smtp-Source: AMrXdXtWkLrUYjZdldxwntLqI6DEnHH/F6Kfw5BraB740B5I6ABbl8mLsx3ekDmEWvHw2QC7k6uJqw== X-Received: by 2002:a17:902:c1c9:b0:192:6544:18b0 with SMTP id c9-20020a170902c1c900b00192654418b0mr57161669plc.63.1673228578071; Sun, 08 Jan 2023 17:42:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 09/22] tcg: Rename TB_JMP_RESET_OFFSET_INVALID to TB_JMP_OFFSET_INVALID Date: Sun, 8 Jan 2023 17:42:35 -0800 Message-Id: <20230109014248.2894281-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109014248.2894281-1-richard.henderson@linaro.org> References: <20230109014248.2894281-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673228882779100003 This will shortly be used for more than reset. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/exec/exec-all.h | 2 +- accel/tcg/translate-all.c | 8 ++++---- tcg/tcg.c | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 25e11b0a8d..b4d09c89ab 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -585,8 +585,8 @@ struct TranslationBlock { * setting one of the jump targets (or patching the jump instruction).= Only * two of such jumps are supported. */ +#define TB_JMP_OFFSET_INVALID 0xffff /* indicates no jump generated */ uint16_t jmp_reset_offset[2]; /* offset of original jump target */ -#define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated = */ uintptr_t jmp_target_arg[2]; /* target address or offset */ =20 /* diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 51ac1f6c84..99c81e9691 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -501,10 +501,10 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->jmp_dest[1] =3D (uintptr_t)NULL; =20 /* init original jump addresses which have been set during tcg_gen_cod= e() */ - if (tb->jmp_reset_offset[0] !=3D TB_JMP_RESET_OFFSET_INVALID) { + if (tb->jmp_reset_offset[0] !=3D TB_JMP_OFFSET_INVALID) { tb_reset_jump(tb, 0); } - if (tb->jmp_reset_offset[1] !=3D TB_JMP_RESET_OFFSET_INVALID) { + if (tb->jmp_reset_offset[1] !=3D TB_JMP_OFFSET_INVALID) { tb_reset_jump(tb, 1); } =20 @@ -686,9 +686,9 @@ static gboolean tb_tree_stats_iter(gpointer key, gpoint= er value, gpointer data) if (tb_page_addr1(tb) !=3D -1) { tst->cross_page++; } - if (tb->jmp_reset_offset[0] !=3D TB_JMP_RESET_OFFSET_INVALID) { + if (tb->jmp_reset_offset[0] !=3D TB_JMP_OFFSET_INVALID) { tst->direct_jmp_count++; - if (tb->jmp_reset_offset[1] !=3D TB_JMP_RESET_OFFSET_INVALID) { + if (tb->jmp_reset_offset[1] !=3D TB_JMP_OFFSET_INVALID) { tst->direct_jmp2_count++; } } diff --git a/tcg/tcg.c b/tcg/tcg.c index 467604efa3..8c35a40eb3 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -4664,8 +4664,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= target_ulong pc_start) #endif =20 /* Initialize goto_tb jump offsets. */ - tb->jmp_reset_offset[0] =3D TB_JMP_RESET_OFFSET_INVALID; - tb->jmp_reset_offset[1] =3D TB_JMP_RESET_OFFSET_INVALID; + tb->jmp_reset_offset[0] =3D TB_JMP_OFFSET_INVALID; + tb->jmp_reset_offset[1] =3D TB_JMP_OFFSET_INVALID; tcg_ctx->tb_jmp_reset_offset =3D tb->jmp_reset_offset; if (TCG_TARGET_HAS_direct_jump) { tcg_ctx->tb_jmp_insn_offset =3D tb->jmp_target_arg; --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673228704; cv=none; d=zohomail.com; s=zohoarc; b=QRXxRSbFqDKRzE4tHyyrYNnoSJoafAjBusOXS1sQ+Y+RdHAktq6jUW+RyduNggF1JM2oUoscfyYdpi/CEDCB1wGSrz80zkq2Q+4rBE8M5QW7r7r7UGbHEJFYLFarfm2FbOt0/n0fcBo6mXMNktAfq3Lo9fPbjvFlNDVoqQrtKDE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673228704; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=A4OwvWQkwAWr6AsGpUBHBcNHseT39GUsYtHIf8rJKUY=; b=eJK5rnMwovut4jf3jGV1H0IxeAbILZGlPo4HJDTRD9nlKdYg7Cy9euNE94mfDZsnYGbdgh7sLODboI4hl7QFkAsaCWDaL8zEytVQ6UjxWgegwpzJIADA1XcpUiFhPilFqgWeFv509Z6PTY6N40DwfEjD327refSN9ZIj3f1a1E8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673228704819415.0740663231642; Sun, 8 Jan 2023 17:45:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEhBn-0000nV-5w; Sun, 08 Jan 2023 20:43:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEhBl-0000mk-Dg for qemu-devel@nongnu.org; Sun, 08 Jan 2023 20:43:01 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEhBj-0001W3-LV for qemu-devel@nongnu.org; Sun, 08 Jan 2023 20:43:01 -0500 Received: by mail-pl1-x633.google.com with SMTP id d3so7940473plr.10 for ; Sun, 08 Jan 2023 17:42:59 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.42.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:42:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=A4OwvWQkwAWr6AsGpUBHBcNHseT39GUsYtHIf8rJKUY=; b=kM6Xb5LE5pIzEzMrC+my5EpjN14TgVFt+lVot9tcMhPd6xq89v1KipiiYyGKuPzC78 ZaTq8TT6YSg6OmTIhcbpWRhp550WLxmjkoZbUPHUX+CXQqEenvXDQzVc4hhvW689qwgK gU9yh04I4DFNPzMvFOAM3WGwjOT0FqigGOi0fxQ4tWJKgWPWNeZ+zJUZ+LMrinxliaGz Okb6SUG5sxWh1bxwOLQ+pmiSEWh9yqQBseZU/cQd4flh7bwWTnOb1okbZDXXc3/7eeT2 udhaORjCRoHK6csylZISidVT/BXj8g5jZDob54dM2zRW2sJLz4aNFwWd7So3kInne4cd 2njA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A4OwvWQkwAWr6AsGpUBHBcNHseT39GUsYtHIf8rJKUY=; b=4b6C4nwZCf57fCQw9XDFMX9HnsTIt2XIaUO6NqskMfWDVCBflahs2E39X4aJ1vEFfp +GHsKut6ZGkBXNsOdM9//j68vgLLSOP/452nqGnnzT0GJKWNSlLS6d4EsNPcAvEUX7hy tXERys3FhJoUNOBKxLU4a75QsJ1f7K4Sq5aiKh3AkDp8JrluZslJLyeVgKzj9buOyM1D LpY26RMs17T4dQ3N+8YasgopRR/AHM9GgDdt3oBtN9qgzOhYMouaVMDNPBdiEhXkphXs 85ORrJ17J5yc0OZkI86ujCzrCFB25fMRXmzEw8XAUttwNR0eYEoWCKkj+YbMhMgo5VcU 6DPg== X-Gm-Message-State: AFqh2koturdfgACoBRyp0rchzeeEY4B4F0eGsm90DENDbL4Tt061ywX2 nuLZDFKHhM7gr/m9/Y1P4nDSEECxCsDVen2T X-Google-Smtp-Source: AMrXdXviazQyNSfAz5Y/zZN/WSrsFNGbNiLizSgK/v9Hcgn3wMnznoZ/esPgH7Nm0M+KiPuKrE+1wA== X-Received: by 2002:a17:902:ce04:b0:189:b4d0:aee with SMTP id k4-20020a170902ce0400b00189b4d00aeemr82128700plg.67.1673228578833; Sun, 08 Jan 2023 17:42:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 10/22] tcg: Add gen_tb to TCGContext Date: Sun, 8 Jan 2023 17:42:36 -0800 Message-Id: <20230109014248.2894281-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109014248.2894281-1-richard.henderson@linaro.org> References: <20230109014248.2894281-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673228706013100003 Content-Type: text/plain; charset="utf-8" This can replace four other variables that are references into the TranslationBlock structure. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/tcg/tcg.h | 11 +++-------- accel/tcg/translate-all.c | 2 +- tcg/tcg-op.c | 14 +++++++------- tcg/tcg.c | 14 +++----------- 4 files changed, 14 insertions(+), 27 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index b949d75fdd..c2d5430b5a 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -552,20 +552,15 @@ struct TCGContext { int nb_indirects; int nb_ops; =20 - /* goto_tb support */ - tcg_insn_unit *code_buf; - uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */ - uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */ - uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */ - TCGRegSet reserved_regs; - uint32_t tb_cflags; /* cflags of the current TB */ intptr_t current_frame_offset; intptr_t frame_start; intptr_t frame_end; TCGTemp *frame_temp; =20 - tcg_insn_unit *code_ptr; + TranslationBlock *gen_tb; /* tb for which code is being generated = */ + tcg_insn_unit *code_buf; /* pointer for start of tb */ + tcg_insn_unit *code_ptr; /* pointer for running end of tb */ =20 #ifdef CONFIG_PROFILER TCGProfile prof; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 99c81e9691..e6a70d795e 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -349,7 +349,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->trace_vcpu_dstate =3D *cpu->trace_dstate; tb_set_page_addr0(tb, phys_pc); tb_set_page_addr1(tb, -1); - tcg_ctx->tb_cflags =3D cflags; + tcg_ctx->gen_tb =3D tb; tb_overflow: =20 #ifdef CONFIG_PROFILER diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index cd1cd4e736..9fa9f1b0fd 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -86,7 +86,7 @@ void tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2, TCG= Arg a3, =20 void tcg_gen_mb(TCGBar mb_type) { - if (tcg_ctx->tb_cflags & CF_PARALLEL) { + if (tcg_ctx->gen_tb->cflags & CF_PARALLEL) { tcg_gen_op1(INDEX_op_mb, mb_type); } } @@ -2782,7 +2782,7 @@ void tcg_gen_exit_tb(const TranslationBlock *tb, unsi= gned idx) void tcg_gen_goto_tb(unsigned idx) { /* We tested CF_NO_GOTO_TB in translator_use_goto_tb. */ - tcg_debug_assert(!(tcg_ctx->tb_cflags & CF_NO_GOTO_TB)); + tcg_debug_assert(!(tcg_ctx->gen_tb->cflags & CF_NO_GOTO_TB)); /* We only support two chained exits. */ tcg_debug_assert(idx <=3D TB_EXIT_IDXMAX); #ifdef CONFIG_DEBUG_TCG @@ -2798,7 +2798,7 @@ void tcg_gen_lookup_and_goto_ptr(void) { TCGv_ptr ptr; =20 - if (tcg_ctx->tb_cflags & CF_NO_GOTO_PTR) { + if (tcg_ctx->gen_tb->cflags & CF_NO_GOTO_PTR) { tcg_gen_exit_tb(NULL, 0); return; } @@ -3165,7 +3165,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv a= ddr, TCGv_i32 cmpv, { memop =3D tcg_canonicalize_memop(memop, 0, 0); =20 - if (!(tcg_ctx->tb_cflags & CF_PARALLEL)) { + if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { TCGv_i32 t1 =3D tcg_temp_new_i32(); TCGv_i32 t2 =3D tcg_temp_new_i32(); =20 @@ -3203,7 +3203,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv a= ddr, TCGv_i64 cmpv, { memop =3D tcg_canonicalize_memop(memop, 1, 0); =20 - if (!(tcg_ctx->tb_cflags & CF_PARALLEL)) { + if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); =20 @@ -3364,7 +3364,7 @@ static void * const table_##NAME[(MO_SIZE | MO_BSWAP)= + 1] =3D { \ void tcg_gen_atomic_##NAME##_i32 \ (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, MemOp memop) \ { \ - if (tcg_ctx->tb_cflags & CF_PARALLEL) { \ + if (tcg_ctx->gen_tb->cflags & CF_PARALLEL) { \ do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \ @@ -3374,7 +3374,7 @@ void tcg_gen_atomic_##NAME##_i32 = \ void tcg_gen_atomic_##NAME##_i64 \ (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, MemOp memop) \ { \ - if (tcg_ctx->tb_cflags & CF_PARALLEL) { \ + if (tcg_ctx->gen_tb->cflags & CF_PARALLEL) { \ do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \ diff --git a/tcg/tcg.c b/tcg/tcg.c index 8c35a40eb3..c1f77f4392 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -310,7 +310,7 @@ static void set_jmp_reset_offset(TCGContext *s, int whi= ch) * We will check for overflow at the end of the opcode loop in * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX. */ - s->tb_jmp_reset_offset[which] =3D tcg_current_code_size(s); + s->gen_tb->jmp_reset_offset[which] =3D tcg_current_code_size(s); } =20 static void G_GNUC_UNUSED set_jmp_insn_offset(TCGContext *s, int which) @@ -320,7 +320,7 @@ static void G_GNUC_UNUSED set_jmp_insn_offset(TCGContex= t *s, int which) * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX. */ tcg_debug_assert(TCG_TARGET_HAS_direct_jump); - s->tb_jmp_insn_offset[which] =3D tcg_current_code_size(s); + s->gen_tb->jmp_target_arg[which] =3D tcg_current_code_size(s); } =20 static uintptr_t G_GNUC_UNUSED get_jmp_target_addr(TCGContext *s, int whic= h) @@ -329,7 +329,7 @@ static uintptr_t G_GNUC_UNUSED get_jmp_target_addr(TCGC= ontext *s, int which) * Return the read-execute version of the pointer, for the benefit * of any pc-relative addressing mode. */ - return (uintptr_t)tcg_splitwx_to_rx(s->tb_jmp_target_addr + which); + return (uintptr_t)tcg_splitwx_to_rx(s->gen_tb->jmp_target_arg + which); } =20 /* Signal overflow, starting over with fewer guest insns. */ @@ -4666,14 +4666,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb= , target_ulong pc_start) /* Initialize goto_tb jump offsets. */ tb->jmp_reset_offset[0] =3D TB_JMP_OFFSET_INVALID; tb->jmp_reset_offset[1] =3D TB_JMP_OFFSET_INVALID; - tcg_ctx->tb_jmp_reset_offset =3D tb->jmp_reset_offset; - if (TCG_TARGET_HAS_direct_jump) { - tcg_ctx->tb_jmp_insn_offset =3D tb->jmp_target_arg; - tcg_ctx->tb_jmp_target_addr =3D NULL; - } else { - tcg_ctx->tb_jmp_insn_offset =3D NULL; - tcg_ctx->tb_jmp_target_addr =3D tb->jmp_target_arg; - } =20 tcg_reg_alloc_start(s); =20 --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673228725; cv=none; d=zohomail.com; s=zohoarc; b=Fwm1aCfjnjW5HZgxTdYFe818Ng1LFGk6VDt2ImW/YgHWRqSfTAooIpMUiU8Se3mCd41mSTzXoDP1mADM6vAhLnA3AU+vYDXDtnj6abXmUkgaF8s1YhM0n5KooB0uFHPtKJhGWYPcNgUGn+67e9Nxt6VyEs2L139yJ7WUSyLFXt0= ARC-Message-Signature: i=1; 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([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.42.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:42:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=NEPoewYIYUX4/fFFzLfNsZVv8UqWZ3zn3T6sHH/Cx9k=; b=cqZY7Kfg+UCDjpxz9N6rHgaUUQ+ojPM7AAmXCfO53VZ3UVsRztL7W3VDhPFE/efpaK BNbvRtIWpU/4UMoyMuerb1zbV7a7aMQksBVX7cgbf6wwtZ7MJll22M2lBJDWutznpuaR C3fnJ2lHTmHGaj1WCxK61RwO1Auk+/BGyBguHwSkECdHfR0GwKRugkCxKIbjhqjAFx1s ggkMyz28GPeM5ay8b/mA3qvke343vmb7mztUlqv/lgK2UgdN0eCcVtinIxldjuMJF4Ty AmVnB6RZ9PYv2BaKKLNdJWkdnP8HXE/mOiJzyZp+OAJP/tvRlDnWp216RKLSrlgnG3Gn AyPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NEPoewYIYUX4/fFFzLfNsZVv8UqWZ3zn3T6sHH/Cx9k=; b=6G1ro4eARcQk5UwlqrqzvOvDOjSUaYwsSrktfU5d933KK2+15rHZgaIprgmNsJET1/ kf0tijnZQpxXl4MqVOqhZd3GnOgO+abbiwnYMgD+vZ7A/rs+wZynFJ6/PJ3UCpD5ZEqE fsGNo6SZDomw0DCMmqN+mY+7Q9WaRbfHnt9jxKT/RLHRkr9Z45UfwK4Y1lL0c3rlXu1n u36phK+k70HU2PRDXUnHrymZ3IacWkjm00cbx8hnxINXqyzWFnjf+Z1bPnGgeZiXPfg3 1OndkQ28BWOp0jP3AE1erT50NJ6Budi/ym3CySSC72oQz5bSyQEv4BzlOOOLk8DKrho5 hGQg== X-Gm-Message-State: AFqh2koRedvq6i5K/nXZU4lLVaEteg/MyySuYO/TOFuZLCkoMfnJjHB2 7O6O8blY+SHBWbO830STWdPYjggc5ofZR3/j X-Google-Smtp-Source: AMrXdXvvm9WUGR6ruAjfTZP4l4h7IJbVCd9oANkTopbJzDsV5bUHpuefAU53isfQ4vw1WqZWS1yUHw== X-Received: by 2002:a17:902:cad5:b0:193:12fd:a2e3 with SMTP id y21-20020a170902cad500b0019312fda2e3mr7718168pld.55.1673228579598; Sun, 08 Jan 2023 17:42:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 11/22] tcg: Add TranslationBlock.jmp_insn_offset Date: Sun, 8 Jan 2023 17:42:37 -0800 Message-Id: <20230109014248.2894281-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109014248.2894281-1-richard.henderson@linaro.org> References: <20230109014248.2894281-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673228726098100001 Content-Type: text/plain; charset="utf-8" Stop overloading jmp_target_arg for both offset and address, depending on TCG_TARGET_HAS_direct_jump. Instead, add a new field to hold the jump insn offset and always set the target address in jmp_target_addr[]. This will allow a tcg backend to use either direct or indirect depending on displacement. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/exec/exec-all.h | 3 ++- accel/tcg/cpu-exec.c | 5 ++--- tcg/tcg.c | 6 ++++-- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index b4d09c89ab..54585a9954 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -587,7 +587,8 @@ struct TranslationBlock { */ #define TB_JMP_OFFSET_INVALID 0xffff /* indicates no jump generated */ uint16_t jmp_reset_offset[2]; /* offset of original jump target */ - uintptr_t jmp_target_arg[2]; /* target address or offset */ + uint16_t jmp_insn_offset[2]; /* offset of direct jump insn */ + uintptr_t jmp_target_addr[2]; /* target address */ =20 /* * Each TB has a NULL-terminated list (jmp_list_head) of incoming jump= s. diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 356fe348de..a87fbf74f4 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -572,14 +572,13 @@ void cpu_exec_step_atomic(CPUState *cpu) =20 void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr) { + tb->jmp_target_addr[n] =3D addr; if (TCG_TARGET_HAS_direct_jump) { - uintptr_t offset =3D tb->jmp_target_arg[n]; + uintptr_t offset =3D tb->jmp_insn_offset[n]; uintptr_t tc_ptr =3D (uintptr_t)tb->tc.ptr; uintptr_t jmp_rx =3D tc_ptr + offset; uintptr_t jmp_rw =3D jmp_rx - tcg_splitwx_diff; tb_target_set_jmp_target(tc_ptr, jmp_rx, jmp_rw, addr); - } else { - tb->jmp_target_arg[n] =3D addr; } } =20 diff --git a/tcg/tcg.c b/tcg/tcg.c index c1f77f4392..7b16af17da 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -320,7 +320,7 @@ static void G_GNUC_UNUSED set_jmp_insn_offset(TCGContex= t *s, int which) * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX. */ tcg_debug_assert(TCG_TARGET_HAS_direct_jump); - s->gen_tb->jmp_target_arg[which] =3D tcg_current_code_size(s); + s->gen_tb->jmp_insn_offset[which] =3D tcg_current_code_size(s); } =20 static uintptr_t G_GNUC_UNUSED get_jmp_target_addr(TCGContext *s, int whic= h) @@ -329,7 +329,7 @@ static uintptr_t G_GNUC_UNUSED get_jmp_target_addr(TCGC= ontext *s, int which) * Return the read-execute version of the pointer, for the benefit * of any pc-relative addressing mode. */ - return (uintptr_t)tcg_splitwx_to_rx(s->gen_tb->jmp_target_arg + which); + return (uintptr_t)tcg_splitwx_to_rx(&s->gen_tb->jmp_target_addr[which]= ); } =20 /* Signal overflow, starting over with fewer guest insns. */ @@ -4666,6 +4666,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= target_ulong pc_start) /* Initialize goto_tb jump offsets. */ tb->jmp_reset_offset[0] =3D TB_JMP_OFFSET_INVALID; tb->jmp_reset_offset[1] =3D TB_JMP_OFFSET_INVALID; + tb->jmp_insn_offset[0] =3D TB_JMP_OFFSET_INVALID; + tb->jmp_insn_offset[1] =3D TB_JMP_OFFSET_INVALID; =20 tcg_reg_alloc_start(s); =20 --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673229008; cv=none; d=zohomail.com; s=zohoarc; b=UGHmtlqnRKFJZOIMShayLGenoPYUg6Qyu6UCSp2cDNDXMl3ESbFJY86AJsaIpou5lPQIxpIOSnnpM1lO+tmGFk3TVwmDIGXkNo91I5Z5c1/2kMWInewUMzp5NQZcNoD+bKI5tADQzNhXaX5xlkMb66LGG663rAW8VCUF3KTyV4A= ARC-Message-Signature: i=1; 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([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.42.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:43:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=k6OR+XG0IEsD8via1R4K6HtmWQxfco7OVq+cQ8c/hag=; b=PyFZSsMKpDsHNidmfnRTmQ3BVPfxN6XiTb6mYhxqUp9DPhl0TXVnFr1FbbxhhTLjuH cowhSzcv++i6Bs8AMgMchB7ZWJ+24Y7AesYCtGNaQ8lMkNdpd86LbFlj16QWqmUxRLd/ daVzImGAo7julO8L1/L5nGh8EMkL6z9MnNhstoxLMY3FMiJ94dVVpBa+XdQvKzBbF/3r Y/CfWXRzz8nPN2672Apr59aAht+uoB3wHRZys/WsPg2zBCyHJXVlYtEqWUGWv4uB9nZk XSbSpiDC+nmyX9z7FAg4TRDf1S0WJkZZZqZq6dEo6aOAizQT11jTdLev06lnVsvroaIP dg/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k6OR+XG0IEsD8via1R4K6HtmWQxfco7OVq+cQ8c/hag=; b=vKblGwweMoGyIdRm3/lhbfoCEQf7aqGrpkXmIdJni8VQJozvFzYh803HFDwA9ixVUv PILvu3hCqpI+6e2ZRvFs/pnj5qy4o69RPf284b0uB7k0PO2TqcdMIbI7X0gKv932kqdb Q4ZJIOtZ/94viCATPDuYF5wexO28NsX6n2DEros2UCCnL7b9SbTfhhXgnLdrbIqgAGk5 k4D/PfwZGpk8gVNwM87lp7fwpaOY5ZuK98BR9q+sQtge+GrE5T0lRtcvSpwy0bu7fmhU mAFs31AZ8a3hf/Uq/8wGteQ8r9iheSCbTNomUfG3F23NPP0lRJaTpeC0pm2EpaT4z2Em mK1g== X-Gm-Message-State: AFqh2krCJRkgTH4iiZnmzzVqDMztTmvScm49km40fx0ompPMBUBC/dPu PmGSkYxi16f0LUgRzSRH2zbpi2UQT3xi8btE X-Google-Smtp-Source: AMrXdXuA7X9FGpItGSkXkgFDzbI/CjmVik8v4K+WQgAPFUdyVFWfEP1ltnsC75yD5duBbFfzQIIQ6g== X-Received: by 2002:a17:903:50e:b0:189:bda4:4a39 with SMTP id jn14-20020a170903050e00b00189bda44a39mr61422791plb.49.1673228580590; Sun, 08 Jan 2023 17:43:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 12/22] tcg: Change tb_target_set_jmp_target arguments Date: Sun, 8 Jan 2023 17:42:38 -0800 Message-Id: <20230109014248.2894281-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109014248.2894281-1-richard.henderson@linaro.org> References: <20230109014248.2894281-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673229009386100001 Content-Type: text/plain; charset="utf-8" Replace 'tc_ptr' and 'addr' with 'tb' and 'n'. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/aarch64/tcg-target.h | 3 ++- tcg/arm/tcg-target.h | 3 ++- tcg/i386/tcg-target.h | 9 ++------- tcg/loongarch64/tcg-target.h | 3 ++- tcg/mips/tcg-target.h | 3 ++- tcg/ppc/tcg-target.h | 3 ++- tcg/riscv/tcg-target.h | 3 ++- tcg/s390x/tcg-target.h | 10 ++-------- tcg/sparc64/tcg-target.h | 3 ++- tcg/tci/tcg-target.h | 3 ++- accel/tcg/cpu-exec.c | 6 +++--- tcg/aarch64/tcg-target.c.inc | 5 +++-- tcg/i386/tcg-target.c.inc | 9 +++++++++ tcg/loongarch64/tcg-target.c.inc | 5 +++-- tcg/ppc/tcg-target.c.inc | 7 ++++--- tcg/s390x/tcg-target.c.inc | 10 ++++++++++ tcg/sparc64/tcg-target.c.inc | 7 ++++--- 17 files changed, 56 insertions(+), 36 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 413a5410c5..d491c198da 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -152,7 +152,8 @@ typedef enum { #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 0 =20 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(const TranslationBlock *, int, + uintptr_t, uintptr_t); =20 #define TCG_TARGET_NEED_LDST_LABELS #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index b7843d2d54..4c1433093c 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -152,7 +152,8 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_MEMORY_BSWAP 0 =20 /* not defined -- call should be eliminated at compile time */ -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t, uintptr_t); =20 #define TCG_TARGET_NEED_LDST_LABELS #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7edb7f1d9a..7500ceaab9 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -220,13 +220,8 @@ extern bool have_movbe; #define TCG_TARGET_extract_i64_valid(ofs, len) \ (((ofs) =3D=3D 8 && (len) =3D=3D 8) || ((ofs) + (len)) =3D=3D 32) =20 -static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jm= p_rx, - uintptr_t jmp_rw, uintptr_t ad= dr) -{ - /* patch the branch destination */ - qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4)); - /* no need to flush icache explicitly */ -} +void tb_target_set_jmp_target(const TranslationBlock *, int, + uintptr_t, uintptr_t); =20 /* This defines the natural memory order supported by this * architecture before guarantees made by various barrier diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index e5f7a1f09d..a150c3c7b2 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -171,7 +171,8 @@ typedef enum { #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 =20 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t, uintptr_t); =20 #define TCG_TARGET_DEFAULT_MO (0) =20 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 15721c3e42..d1adf3e326 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -206,7 +206,8 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 /* not defined -- call should be eliminated at compile time */ -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t) +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t, uintptr_t) QEMU_ERROR("code path is reachable"); =20 #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index b5cd225cfa..02764c3331 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -180,7 +180,8 @@ extern bool have_vsx; #define TCG_TARGET_HAS_bitsel_vec have_vsx #define TCG_TARGET_HAS_cmpsel_vec 0 =20 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t, uintptr_t); =20 #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 232537ccea..bce164fde2 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -166,7 +166,8 @@ typedef enum { #endif =20 /* not defined -- call should be eliminated at compile time */ -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t, uintptr_t); =20 #define TCG_TARGET_DEFAULT_MO (0) =20 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 68dcbc6645..57ba165800 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -175,14 +175,8 @@ extern uint64_t s390_facilities[3]; =20 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 -static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jm= p_rx, - uintptr_t jmp_rw, uintptr_t ad= dr) -{ - /* patch the branch destination */ - intptr_t disp =3D addr - (jmp_rx - 2); - qatomic_set((int32_t *)jmp_rw, disp / 2); - /* no need to flush icache explicitly */ -} +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t jmp_rx, uintptr_t jmp_rw); =20 #define TCG_TARGET_NEED_LDST_LABELS #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index 0044ac8d78..282833bd8d 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -155,7 +155,8 @@ extern bool use_vis3_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t, uintptr_t); =20 #define TCG_TARGET_NEED_POOL_LABELS =20 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 94ec541b4e..f9ee83d751 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -177,6 +177,7 @@ typedef enum { #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 /* not defined -- call should be eliminated at compile time */ -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t, uintptr_t); =20 #endif /* TCG_TARGET_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index a87fbf74f4..ac5b581e52 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -574,11 +574,11 @@ void tb_set_jmp_target(TranslationBlock *tb, int n, u= intptr_t addr) { tb->jmp_target_addr[n] =3D addr; if (TCG_TARGET_HAS_direct_jump) { + const TranslationBlock *c_tb =3D tcg_splitwx_to_rx(tb); uintptr_t offset =3D tb->jmp_insn_offset[n]; - uintptr_t tc_ptr =3D (uintptr_t)tb->tc.ptr; - uintptr_t jmp_rx =3D tc_ptr + offset; + uintptr_t jmp_rx =3D (uintptr_t)tb->tc.ptr + offset; uintptr_t jmp_rw =3D jmp_rx - tcg_splitwx_diff; - tb_target_set_jmp_target(tc_ptr, jmp_rx, jmp_rw, addr); + tb_target_set_jmp_target(c_tb, n, jmp_rx, jmp_rw); } } =20 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index ad35bee8af..0b65f2cac1 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1353,9 +1353,10 @@ static void tcg_out_call(TCGContext *s, const tcg_in= sn_unit *target, tcg_out_call_int(s, target); } =20 -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, - uintptr_t jmp_rw, uintptr_t addr) +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t jmp_rx, uintptr_t jmp_rw) { + uintptr_t addr =3D tb->jmp_target_addr[n]; tcg_insn_unit i1, i2; TCGType rt =3D TCG_TYPE_I64; TCGReg rd =3D TCG_REG_TMP; diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 33c4139730..c71c3e664d 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2374,6 +2374,15 @@ static void tcg_out_goto_tb(TCGContext *s, int which) set_jmp_reset_offset(s, which); } =20 +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t jmp_rx, uintptr_t jmp_rw) +{ + /* patch the branch destination */ + uintptr_t addr =3D tb->jmp_target_addr[n]; + qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4)); + /* no need to flush icache explicitly */ +} + static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 25de7a9ee0..3174557ce3 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1039,11 +1039,12 @@ static void tcg_out_nop(TCGContext *s) tcg_out32(s, NOP); } =20 -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, - uintptr_t jmp_rw, uintptr_t addr) +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t jmp_rx, uintptr_t jmp_rw) { tcg_insn_unit i1, i2; ptrdiff_t upper, lower; + uintptr_t addr =3D tb->jmp_target_addr[n]; ptrdiff_t offset =3D (ptrdiff_t)(addr - jmp_rx) >> 2; =20 if (offset =3D=3D sextreg(offset, 0, 26)) { diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index e56f86c613..6f2c8faea6 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1893,11 +1893,12 @@ static inline void ppc64_replace4(uintptr_t rx, uin= tptr_t rw, flush_idcache_range(rx, rw, 16); } =20 -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, - uintptr_t jmp_rw, uintptr_t addr) +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t jmp_rx, uintptr_t jmp_rw) { tcg_insn_unit i0, i1, i2, i3; - intptr_t tb_diff =3D addr - tc_ptr; + uintptr_t addr =3D tb->jmp_target_addr[n]; + intptr_t tb_diff =3D addr - (uintptr_t)tb->tc.ptr; intptr_t br_diff =3D addr - (jmp_rx + 4); intptr_t lo, hi; =20 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index e008f0efcc..2d049a4cc7 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1970,6 +1970,16 @@ static void tcg_out_goto_tb(TCGContext *s, int which) set_jmp_reset_offset(s, which); } =20 +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t jmp_rx, uintptr_t jmp_rw) +{ + /* patch the branch destination */ + uintptr_t addr =3D tb->jmp_target_addr[n]; + intptr_t disp =3D addr - (jmp_rx - 2); + qatomic_set((int32_t *)jmp_rw, disp / 2); + /* no need to flush icache explicitly */ +} + # define OP_32_64(x) \ case glue(glue(INDEX_op_,x),_i32): \ case glue(glue(INDEX_op_,x),_i64) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 594767ded8..fdb711bdf6 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1885,10 +1885,11 @@ void tcg_register_jit(const void *buf, size_t buf_s= ize) tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } =20 -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, - uintptr_t jmp_rw, uintptr_t addr) +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t jmp_rx, uintptr_t jmp_rw) { - intptr_t tb_disp =3D addr - tc_ptr; + uintptr_t addr =3D tb->jmp_target_addr[n]; + intptr_t tb_disp =3D addr - (uintptr_t)tb->tc.ptr; intptr_t br_disp =3D addr - jmp_rx; tcg_insn_unit i1, i2; =20 --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673229010; cv=none; d=zohomail.com; s=zohoarc; b=U+RDeOz7S7GiclMPEK4KAp/hP6gnCaWZhE2aaYktgNvkt2bpLgu/d6qTW1SypA4zwSIiKNzPWhyZ6lc+AcqPxmE00cWnWrbjupICXz6p5RdLTMK6sjSUCRo9GOSrPKs3rZvxshflhBp4dTPc9lM+DMEwdJv+AG5mumyjNcXUQ7I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673229010; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673229011199100007 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/tcg/tcg.h | 3 +++ tcg/aarch64/tcg-target.h | 4 ---- tcg/arm/tcg-target.h | 5 ----- tcg/i386/tcg-target.h | 3 --- tcg/loongarch64/tcg-target.h | 3 --- tcg/mips/tcg-target.h | 5 ----- tcg/ppc/tcg-target.h | 4 ---- tcg/riscv/tcg-target.h | 4 ---- tcg/s390x/tcg-target.h | 4 ---- tcg/sparc64/tcg-target.h | 4 ---- tcg/tci/tcg-target.h | 4 ---- 11 files changed, 3 insertions(+), 40 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index c2d5430b5a..6f497172f8 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -833,6 +833,9 @@ void tcg_func_start(TCGContext *s); =20 int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_star= t); =20 +void tb_target_set_jmp_target(const TranslationBlock *, int, + uintptr_t, uintptr_t); + void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t siz= e); =20 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index d491c198da..a585d035d9 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -151,10 +151,6 @@ typedef enum { =20 #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 0 - -void tb_target_set_jmp_target(const TranslationBlock *, int, - uintptr_t, uintptr_t); - #define TCG_TARGET_NEED_LDST_LABELS #define TCG_TARGET_NEED_POOL_LABELS =20 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 4c1433093c..d347a5dc53 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -150,11 +150,6 @@ extern bool use_neon_instructions; =20 #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 0 - -/* not defined -- call should be eliminated at compile time */ -void tb_target_set_jmp_target(const TranslationBlock *tb, int n, - uintptr_t, uintptr_t); - #define TCG_TARGET_NEED_LDST_LABELS #define TCG_TARGET_NEED_POOL_LABELS =20 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7500ceaab9..d3705da2ed 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -220,9 +220,6 @@ extern bool have_movbe; #define TCG_TARGET_extract_i64_valid(ofs, len) \ (((ofs) =3D=3D 8 && (len) =3D=3D 8) || ((ofs) + (len)) =3D=3D 32) =20 -void tb_target_set_jmp_target(const TranslationBlock *, int, - uintptr_t, uintptr_t); - /* This defines the natural memory order supported by this * architecture before guarantees made by various barrier * instructions. diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index a150c3c7b2..5782c6887c 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -171,9 +171,6 @@ typedef enum { #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 =20 -void tb_target_set_jmp_target(const TranslationBlock *tb, int n, - uintptr_t, uintptr_t); - #define TCG_TARGET_DEFAULT_MO (0) =20 #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index d1adf3e326..82b40100cf 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -205,11 +205,6 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 -/* not defined -- call should be eliminated at compile time */ -void tb_target_set_jmp_target(const TranslationBlock *tb, int n, - uintptr_t, uintptr_t) - QEMU_ERROR("code path is reachable"); - #define TCG_TARGET_NEED_LDST_LABELS =20 #endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 02764c3331..5ffb41fb57 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -180,12 +180,8 @@ extern bool have_vsx; #define TCG_TARGET_HAS_bitsel_vec have_vsx #define TCG_TARGET_HAS_cmpsel_vec 0 =20 -void tb_target_set_jmp_target(const TranslationBlock *tb, int n, - uintptr_t, uintptr_t); - #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 - #define TCG_TARGET_NEED_LDST_LABELS #define TCG_TARGET_NEED_POOL_LABELS =20 diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index bce164fde2..c9af6d592f 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -165,10 +165,6 @@ typedef enum { #define TCG_TARGET_HAS_mulsh_i64 1 #endif =20 -/* not defined -- call should be eliminated at compile time */ -void tb_target_set_jmp_target(const TranslationBlock *tb, int n, - uintptr_t, uintptr_t); - #define TCG_TARGET_DEFAULT_MO (0) =20 #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 57ba165800..9f5d1cf1c7 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -174,10 +174,6 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) - -void tb_target_set_jmp_target(const TranslationBlock *tb, int n, - uintptr_t jmp_rx, uintptr_t jmp_rw); - #define TCG_TARGET_NEED_LDST_LABELS #define TCG_TARGET_NEED_POOL_LABELS =20 diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index 282833bd8d..b78a545581 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -154,10 +154,6 @@ extern bool use_vis3_instructions; =20 #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 - -void tb_target_set_jmp_target(const TranslationBlock *tb, int n, - uintptr_t, uintptr_t); - #define TCG_TARGET_NEED_POOL_LABELS =20 #endif diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index f9ee83d751..359d62c2f3 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -176,8 +176,4 @@ typedef enum { =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 -/* not defined -- call should be eliminated at compile time */ -void tb_target_set_jmp_target(const TranslationBlock *tb, int n, - uintptr_t, uintptr_t); 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([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.43.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:43:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dS32zfSBu/kF12OtOcGjeLh3cT3wgUbDUauEFguZfiU=; b=Ln7q9+BC/VMn01rCztqz8ipqrvE2JcnUmu9wup0BzXje5QjcGrZjk1ha8lwpdxbo8Y QDOOWlooXT8/rgHTdSTDp8dqGg7Bmw1AWTDWUSUMUhi3ynVAPlvVpVZFSecl2LdMUHmx j/mh1HITIe6SZxFBsaPYMUchoNQCmOhZQMf8H2+cgvPNP2GEsQ+byIww9gSdSgzoiHDK wXCG/0HFsl4+s5wfU8/vcy5HoI/Aboj2avZHXkQcR29TTz9UYxNYqiHj9POHwtvmTB80 5GhF3XUKCDAbyC3kyA8JyK6A7473Q+VlqmY/hXKaRP6jc6ptpOCCg3lo3tBTK+1wpd7A GBbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dS32zfSBu/kF12OtOcGjeLh3cT3wgUbDUauEFguZfiU=; b=MWgJ8NbH7RH5YXWfs5S9iQpyZrnar7FdNKsMHMpU7zupJ75xXaBakwRt4Ah1pFS8+D zeOHHCba0SSPfVQVEIJslxPQ5KOYgRrChN5QFxhpBZrDWEVgc6ip91YrLcW6dopMC6p3 yQjjbTR9kISyJNZzeAInpzI6edrjNW7JldyZ85n3WXgtJMD84zpoQYS0s+U7oO6kDfWX ULjqSrbLFMskzq2ApKHVCD11alc7Ukv6jJdbQu3NCuwiEz678ef2/5buauHKrmBHCgMg 7BDGwy/BRBVfZ1wD8DkLHnBI7bH+nA0EL5gXT3Dvp7iq4TEdnDKcS87bR4ke7VJZTL/h m6dw== X-Gm-Message-State: AFqh2kroVRv4zlk9RgL9Mlp+pKFBSFOTTlmlGQPeNJHp6Nlyqu1CFEcC zN57SVZ37qCDYatgBy/d9geH/OU1llHNXFRn X-Google-Smtp-Source: AMrXdXu/6TIQYz4r6qNGSXKY/wL0D7TPnVlv7HBDokjyFx42XbI29F4ZSJvh05xlMrGVWVQJs70Bmw== X-Received: by 2002:a17:902:b413:b0:189:6ab3:9e64 with SMTP id x19-20020a170902b41300b001896ab39e64mr62154821plr.34.1673228582266; Sun, 08 Jan 2023 17:43:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 14/22] tcg: Always define tb_target_set_jmp_target Date: Sun, 8 Jan 2023 17:42:40 -0800 Message-Id: <20230109014248.2894281-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109014248.2894281-1-richard.henderson@linaro.org> References: <20230109014248.2894281-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673228979101100003 Install empty versions for !TCG_TARGET_HAS_direct_jump hosts. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 6 ++++++ tcg/mips/tcg-target.c.inc | 6 ++++++ tcg/riscv/tcg-target.c.inc | 6 ++++++ tcg/tci/tcg-target.c.inc | 6 ++++++ 4 files changed, 24 insertions(+) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index b8f3b0c634..b21dd561fa 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1964,6 +1964,12 @@ static void tcg_out_goto_tb(TCGContext *s, int which) set_jmp_reset_offset(s, which); } =20 +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t jmp_rx, uintptr_t jmp_rw) +{ + /* Always indirect, nothing to do */ +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index e54df4128b..0b5e100cb1 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1977,6 +1977,12 @@ static void tcg_out_goto_tb(TCGContext *s, int which) set_jmp_reset_offset(s, which); } =20 +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t jmp_rx, uintptr_t jmp_rw) +{ + /* Always indirect, nothing to do */ +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index ee6759f787..e6a3915859 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1310,6 +1310,12 @@ static void tcg_out_goto_tb(TCGContext *s, int which) set_jmp_reset_offset(s, which); } =20 +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t jmp_rx, uintptr_t jmp_rw) +{ + /* Always indirect, nothing to do */ +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f2ac356900..54779d86d9 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -603,6 +603,12 @@ static void tcg_out_goto_tb(TCGContext *s, int which) set_jmp_reset_offset(s, which); } =20 +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t jmp_rx, uintptr_t jmp_rw) +{ + /* Always indirect, nothing to do */ +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673228670; cv=none; d=zohomail.com; s=zohoarc; b=KM/cbwCMMiQ+vSPN7LsnVIY+NtoIA9TQm8SDqCjAwJ0ED6ojzcpgOhurJKxhAA4ntl63wSefBrPFZzqUOrTO8chKBXl5aO25LEENd/W4XYbQlCth+sbp1AeAB+meXiRZgVppqtflwGmP89cmSuwJbG+tGPhBl/c95nT90rhBYiY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673228670; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=n+ZQDFURp2kFPKT/uUbD+HNlENA4zxdL8rMBOWsImJ4=; b=Z6rNQagwIqJY3phvsE2dkc8Sv01nxf9UfdvIzR9fAxuyoe4RrKZea00s7OO/0aWtbnAgzgKx94ukVS/X4WTVwvLrhDcmNV7PlvGl41ONK6Esxj+6TEQPYsf/NO6sTJSfWBTNRNADkxbvUZjDwdjT6HNAVgpsZF0vzCGiLrK5ubE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673228669992728.8645584694611; Sun, 8 Jan 2023 17:44:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEhBs-0000qR-UZ; Sun, 08 Jan 2023 20:43:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEhBq-0000p1-LB for qemu-devel@nongnu.org; Sun, 08 Jan 2023 20:43:06 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEhBo-0001Z1-Ji for qemu-devel@nongnu.org; Sun, 08 Jan 2023 20:43:06 -0500 Received: by mail-pl1-x62d.google.com with SMTP id g16so7931894plq.12 for ; Sun, 08 Jan 2023 17:43:04 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.43.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:43:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=n+ZQDFURp2kFPKT/uUbD+HNlENA4zxdL8rMBOWsImJ4=; b=l9kccrmUnt2GuiEATZbSnjF7Eal3KFVu1FVlmJbaJDqzjzmrntv94wOjv+CniILOXY Egg4hoZpEIZmQMhHtizWjX7YKU+/XCCXZG0szvxJb92sxeODkBPkwR55C3pr7PIIEhRp PUOtK1sXJXRJrZ11pGsimQpoXGOCWuUMa5I5PYU3fy6s+V/fX5HW/LmFO1aaTknb90xc rfIjOMypNfJ7BC6MHraUtbR0xaeNScT5DzTVN8b86hs4kgVG1t8RdGf8UJeeXPTVE7Jo oq7smHcr2mWGU9Ldt3XPn0Cf+8njNnsG9jJfAQKMCx7RmeSAUAjBZo2uBxi4hBsIMNJ4 tTzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n+ZQDFURp2kFPKT/uUbD+HNlENA4zxdL8rMBOWsImJ4=; b=KjCH7jWgmJeLJflyLkiji6HEN5QUbOyaUUu7yACJ5JDp6GWOYbLf7aVIfxa1mlwhbe aDRGSXUDN6iGjYsUfcEFEsFuT4Z/vjfMPoZe+S7HlcNvkrXpXssGTn1ZSHAkZ68lHyud iRrlHaOBqPWAPqDcWuYNyONv4tkfF0VZMxyuBIteKspj9hO+YseqNdJwQOl8iNJ0jh22 KuhRgJE0DP4R/JmtaNUdrl27BMJZil2x4J0UHbgnqzc7LS/9ryt+X9W4T4GvhVxdNSnG WLbfuYji7gXIZMUJjzAhwX9Xtdfd0/6pTX0HoOIibdGJxjgkwklfn0/hEzQ1HnAyhqYQ hWBg== X-Gm-Message-State: AFqh2koOV7DiD6vwXiCy4PXV47KsntanhnHWA33hXnpvRZmtEK3nVJf1 q5hUiQ0cbeavUld3LK3XFdM5QjdX8fjRdO6n X-Google-Smtp-Source: AMrXdXvUd2pOfv9xs3RadCSAoLP018tGQ9YcdsGO+5NoEbVHw1Ys2//vrEpDBl0MHpzaoByu3g/abw== X-Received: by 2002:a17:902:e291:b0:192:fc7b:2bc0 with SMTP id o17-20020a170902e29100b00192fc7b2bc0mr12056365plc.13.1673228583253; Sun, 08 Jan 2023 17:43:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 15/22] tcg: Remove TCG_TARGET_HAS_direct_jump Date: Sun, 8 Jan 2023 17:42:41 -0800 Message-Id: <20230109014248.2894281-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109014248.2894281-1-richard.henderson@linaro.org> References: <20230109014248.2894281-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673228671875100011 Content-Type: text/plain; charset="utf-8" We now have the option to generate direct or indirect goto_tb depending on the dynamic displacement, thus the define is no longer necessary or completely accurate. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/aarch64/tcg-target.h | 1 - tcg/arm/tcg-target.h | 1 - tcg/i386/tcg-target.h | 1 - tcg/loongarch64/tcg-target.h | 1 - tcg/mips/tcg-target.h | 1 - tcg/ppc/tcg-target.h | 1 - tcg/riscv/tcg-target.h | 1 - tcg/s390x/tcg-target.h | 1 - tcg/sparc64/tcg-target.h | 1 - tcg/tci/tcg-target.h | 1 - accel/tcg/cpu-exec.c | 13 ++++++------- tcg/tcg.c | 1 - tcg/arm/tcg-target.c.inc | 1 - tcg/mips/tcg-target.c.inc | 1 - tcg/riscv/tcg-target.c.inc | 1 - tcg/s390x/tcg-target.c.inc | 3 +++ tcg/tci/tcg-target.c.inc | 1 - 17 files changed, 9 insertions(+), 22 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index a585d035d9..6067446b03 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -123,7 +123,6 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 -#define TCG_TARGET_HAS_direct_jump 1 =20 #define TCG_TARGET_HAS_v64 1 #define TCG_TARGET_HAS_v128 1 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index d347a5dc53..91b8954804 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -121,7 +121,6 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_div_i32 use_idiv_instructions #define TCG_TARGET_HAS_rem_i32 0 -#define TCG_TARGET_HAS_direct_jump 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 #define TCG_TARGET_HAS_v64 use_neon_instructions diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index d3705da2ed..5797a55ea0 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -141,7 +141,6 @@ extern bool have_movbe; #define TCG_TARGET_HAS_muls2_i32 1 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 -#define TCG_TARGET_HAS_direct_jump 1 =20 #if TCG_TARGET_REG_BITS =3D=3D 64 /* Keep target addresses zero-extended in a register. */ diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index 5782c6887c..1c3e48d662 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -128,7 +128,6 @@ typedef enum { #define TCG_TARGET_HAS_clz_i32 1 #define TCG_TARGET_HAS_ctz_i32 1 #define TCG_TARGET_HAS_ctpop_i32 0 -#define TCG_TARGET_HAS_direct_jump 1 #define TCG_TARGET_HAS_brcond2 0 #define TCG_TARGET_HAS_setcond2 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 82b40100cf..7bc8e15293 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -134,7 +134,6 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_muluh_i32 1 #define TCG_TARGET_HAS_mulsh_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 -#define TCG_TARGET_HAS_direct_jump 0 =20 #if TCG_TARGET_REG_BITS =3D=3D 64 #define TCG_TARGET_HAS_add2_i32 0 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 5ffb41fb57..f253184915 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -108,7 +108,6 @@ extern bool have_vsx; #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 1 #define TCG_TARGET_HAS_mulsh_i32 1 -#define TCG_TARGET_HAS_direct_jump 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 #if TCG_TARGET_REG_BITS =3D=3D 64 diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index c9af6d592f..1337bc1f1e 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -121,7 +121,6 @@ typedef enum { #define TCG_TARGET_HAS_clz_i32 0 #define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_ctpop_i32 0 -#define TCG_TARGET_HAS_direct_jump 0 #define TCG_TARGET_HAS_brcond2 1 #define TCG_TARGET_HAS_setcond2 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 9f5d1cf1c7..e597e47e60 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -105,7 +105,6 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_extrl_i64_i32 0 #define TCG_TARGET_HAS_extrh_i64_i32 0 -#define TCG_TARGET_HAS_direct_jump 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 #define TCG_TARGET_HAS_div2_i64 1 diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index b78a545581..1d6a5c8b07 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -111,7 +111,6 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_muls2_i32 1 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 -#define TCG_TARGET_HAS_direct_jump 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 #define TCG_TARGET_HAS_extrl_i64_i32 1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 359d62c2f3..1414ab4d5b 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -82,7 +82,6 @@ #define TCG_TARGET_HAS_muls2_i32 1 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 -#define TCG_TARGET_HAS_direct_jump 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 #if TCG_TARGET_REG_BITS =3D=3D 64 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ac5b581e52..0892c6534a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -572,14 +572,13 @@ void cpu_exec_step_atomic(CPUState *cpu) =20 void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr) { + const TranslationBlock *c_tb =3D tcg_splitwx_to_rx(tb); + uintptr_t offset =3D tb->jmp_insn_offset[n]; + uintptr_t jmp_rx =3D (uintptr_t)tb->tc.ptr + offset; + uintptr_t jmp_rw =3D jmp_rx - tcg_splitwx_diff; + tb->jmp_target_addr[n] =3D addr; - if (TCG_TARGET_HAS_direct_jump) { - const TranslationBlock *c_tb =3D tcg_splitwx_to_rx(tb); - uintptr_t offset =3D tb->jmp_insn_offset[n]; - uintptr_t jmp_rx =3D (uintptr_t)tb->tc.ptr + offset; - uintptr_t jmp_rw =3D jmp_rx - tcg_splitwx_diff; - tb_target_set_jmp_target(c_tb, n, jmp_rx, jmp_rw); - } + tb_target_set_jmp_target(c_tb, n, jmp_rx, jmp_rw); } =20 static inline void tb_add_jump(TranslationBlock *tb, int n, diff --git a/tcg/tcg.c b/tcg/tcg.c index 7b16af17da..9d7e2b1f1b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -319,7 +319,6 @@ static void G_GNUC_UNUSED set_jmp_insn_offset(TCGContex= t *s, int which) * We will check for overflow at the end of the opcode loop in * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX. */ - tcg_debug_assert(TCG_TARGET_HAS_direct_jump); s->gen_tb->jmp_insn_offset[which] =3D tcg_current_code_size(s); } =20 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index b21dd561fa..e1e1c2620d 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1945,7 +1945,6 @@ static void tcg_out_goto_tb(TCGContext *s, int which) intptr_t ptr, dif, dil; TCGReg base =3D TCG_REG_PC; =20 - qemu_build_assert(!TCG_TARGET_HAS_direct_jump); ptr =3D get_jmp_target_addr(s, which); dif =3D tcg_pcrel_diff(s, (void *)ptr) - 8; dil =3D sextract32(dif, 0, 12); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 0b5e100cb1..6e000d8e69 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1969,7 +1969,6 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t = a0) static void tcg_out_goto_tb(TCGContext *s, int which) { /* indirect jump method */ - qemu_build_assert(!TCG_TARGET_HAS_direct_jump); tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, get_jmp_target_addr(s, which)); tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index e6a3915859..136fe54d4b 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1302,7 +1302,6 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t = a0) =20 static void tcg_out_goto_tb(TCGContext *s, int which) { - qemu_build_assert(!TCG_TARGET_HAS_direct_jump); /* indirect jump method */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO, get_jmp_target_addr(s, which)); diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 2d049a4cc7..218318feb2 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1973,6 +1973,9 @@ static void tcg_out_goto_tb(TCGContext *s, int which) void tb_target_set_jmp_target(const TranslationBlock *tb, int n, uintptr_t jmp_rx, uintptr_t jmp_rw) { + if (!HAVE_FACILITY(GEN_INST_EXT)) { + return; + } /* patch the branch destination */ uintptr_t addr =3D tb->jmp_target_addr[n]; intptr_t disp =3D addr - (jmp_rx - 2); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 54779d86d9..bc452007c6 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -597,7 +597,6 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t ar= g) =20 static void tcg_out_goto_tb(TCGContext *s, int which) { - qemu_build_assert(!TCG_TARGET_HAS_direct_jump); /* indirect jump method. */ tcg_out_op_p(s, INDEX_op_goto_tb, (void *)get_jmp_target_addr(s, which= )); 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([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.43.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:43:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UN6kyNTXi7JMI1hLJ0Bnvri+VQ42kzdG+Um81HCiobc=; b=tvnkN6QW1WRGQDGj2nyWlLOcvymMKHlyVVGpP4eYYz4c1uKUBPsWvJ7IRWn1cKd680 u2CwnB+QcN6bjtXqm54n2kYWXA3hliFGF+Hl/Cw3Lgsw23+2OhDD7MRTSnq07LpaMKK0 vNCT0gSuDBUf13b0nZVgXVGEuX0veupZpv7Rml84W1bzdKIvm/gee2lbYqkRawh0Ockv atOXDhjqgpUqgQ1yGOG87hfHrsuj5QVTFcYcyMT59Gg/T6EUxSa1uXDjj4q3IRZMKh0A DiTfGnQZTcg5aJihlJJd2557KhNvIl6RUbXY9qlzX8e2eOwX4e3v6+jgOcfkUxO8ShMv qsQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UN6kyNTXi7JMI1hLJ0Bnvri+VQ42kzdG+Um81HCiobc=; b=O+YYeZTmHn97cHfVROOHV1o0pWMXvrlfyeG1ccGoyiPkOzCnibaKgV5WBWBeRVE/l1 TvDGKQ3PjM2zBSBS/QbFncLY/DA80sFgBsRutDnqDRX8+qW4KMi1MIFf8cxviIc3FkUt 8xJOdPZc79Jq6RvMjoQy1gbP2AcKg2oBccfRMR36HjW2JA1abOcrVa1RUH9twN7zIvYs tiafNGmRWp2WTCLM5+J/Y06rgbsR+fLjIgq7eGcCu3Syi+F0qBeHyStdWOTbfQccmLu1 sqMr7Sxpi08HCmXRJJfgmgyim8k+jzV5Q0aG6w4jmwt/4Fh3jeXTio/3pr2vkw2/+m4z a1Vg== X-Gm-Message-State: AFqh2kpZjVv63Vv2NPuTsDnJhfJpU8mHhKRiALknqv3ovfaTGUYS9dvE 1PwJ/UxuDmLQJ41/y9TFwI0OxS+Up34HdISH X-Google-Smtp-Source: AMrXdXtzSwrG1q4XbSLA7gotzisnaBOlD5IyKgML5YvhwLYvatD9xVnPsz6FECfyJsJIXssWDv9MZw== X-Received: by 2002:a17:902:8309:b0:189:469c:dc0 with SMTP id bd9-20020a170902830900b00189469c0dc0mr31770448plb.7.1673228584164; Sun, 08 Jan 2023 17:43:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: hev Subject: [PATCH v2 16/22] tcg/aarch64: Reorg goto_tb implementation Date: Sun, 8 Jan 2023 17:42:42 -0800 Message-Id: <20230109014248.2894281-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109014248.2894281-1-richard.henderson@linaro.org> References: <20230109014248.2894281-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673228961020100003 Content-Type: text/plain; charset="utf-8" The old implementation replaces two insns, swapping between b nop br x30 and adrp x30, addi x30, x30, lo12: br x30 There is a race condition in which a thread could be stopped at the PC of the second insn, and when restarted does not see the complete address computation and branches to nowhere. The new implemetation replaces only one insn, swapping between b br tmp and ldr tmp, br tmp Reported-by: hev Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/aarch64/tcg-target.h | 3 +- tcg/aarch64/tcg-target.c.inc | 64 +++++++++++++++--------------------- 2 files changed, 28 insertions(+), 39 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 6067446b03..0ba2298ea6 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -15,7 +15,8 @@ =20 #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 24 -#define MAX_CODE_GEN_BUFFER_SIZE (2 * GiB) +#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) +#undef TCG_TARGET_STACK_GROWSUP =20 typedef enum { TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 0b65f2cac1..1d0ebf01a5 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1353,33 +1353,6 @@ static void tcg_out_call(TCGContext *s, const tcg_in= sn_unit *target, tcg_out_call_int(s, target); } =20 -void tb_target_set_jmp_target(const TranslationBlock *tb, int n, - uintptr_t jmp_rx, uintptr_t jmp_rw) -{ - uintptr_t addr =3D tb->jmp_target_addr[n]; - tcg_insn_unit i1, i2; - TCGType rt =3D TCG_TYPE_I64; - TCGReg rd =3D TCG_REG_TMP; - uint64_t pair; - - ptrdiff_t offset =3D addr - jmp_rx; - - if (offset =3D=3D sextract64(offset, 0, 26)) { - i1 =3D I3206_B | ((offset >> 2) & 0x3ffffff); - i2 =3D NOP; - } else { - offset =3D (addr >> 12) - (jmp_rx >> 12); - - /* patch ADRP */ - i1 =3D I3406_ADRP | (offset & 3) << 29 | (offset & 0x1ffffc) << (5= - 2) | rd; - /* patch ADDI */ - i2 =3D I3401_ADDI | rt << 31 | (addr & 0xfff) << 10 | rd << 5 | rd; - } - pair =3D (uint64_t)i2 << 32 | i1; - qatomic_set((uint64_t *)jmp_rw, pair); - flush_idcache_range(jmp_rx, jmp_rw, 8); -} - static inline void tcg_out_goto_label(TCGContext *s, TCGLabel *l) { if (!l->has_value) { @@ -1902,23 +1875,38 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_= t a0) static void tcg_out_goto_tb(TCGContext *s, int which) { /* - * Ensure that ADRP+ADD are 8-byte aligned so that an atomic - * write can be used to patch the target address. + * Direct branch, or indirect address load, will be patched + * by tb_target_set_jmp_target. Assert indirect load offset + * in range early, regardless of direct branch distance. */ - if ((uintptr_t)s->code_ptr & 7) { - tcg_out32(s, NOP); - } + intptr_t i_off =3D tcg_pcrel_diff(s, (void *)get_jmp_target_addr(s, wh= ich)); + tcg_debug_assert(i_off =3D=3D sextract64(i_off, 0, 21)); + set_jmp_insn_offset(s, which); - /* - * actual branch destination will be patched by - * tb_target_set_jmp_target later - */ - tcg_out_insn(s, 3406, ADRP, TCG_REG_TMP, 0); - tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_TMP, TCG_REG_TMP, 0); + tcg_out32(s, I3206_B); tcg_out_insn(s, 3207, BR, TCG_REG_TMP); set_jmp_reset_offset(s, which); } =20 +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t jmp_rx, uintptr_t jmp_rw) +{ + uintptr_t d_addr =3D tb->jmp_target_addr[n]; + uintptr_t i_addr =3D (uintptr_t)&tb->jmp_target_addr[n]; + ptrdiff_t d_offset =3D d_addr - jmp_rx; + ptrdiff_t i_offset =3D i_addr - jmp_rx; + tcg_insn_unit insn; + + /* Either directly branch, or indirect branch load. */ + if (d_offset =3D=3D sextract64(d_offset, 0, 26)) { + insn =3D I3206_B | ((d_offset >> 2) & 0x3ffffff); + } else { + insn =3D I3305_LDR | TCG_REG_TMP | (((i_offset >> 2) & 0x7ffff) <<= 5); + } + qatomic_set((uint32_t *)jmp_rw, insn); + flush_idcache_range(jmp_rx, jmp_rw, 4); +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673229151; cv=none; d=zohomail.com; s=zohoarc; b=WGormOAv3KbNDhxNqg6F7SgL5eZfUM1nrObxbGkuOKiGJgVyy1rPosda3ycdENz7X/Bq35vaoiZQfp0JFjtwdNEZmmYkdun9OhxyU5mAF2xT00GfgzzHhmJ6fUfNFNjHEvDzuijst8UDr9U/S10hRqvvrnzyfJS1j9KwcGl+xB8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673229151; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ybxe5BnWNBxH6uN6QcJsd3eJUNtW1iUptSAvC+pL/8o=; b=FynWMnEY8dFGYVNjwyL8mTooCXVqG3q1csKwb+C8lbdiCeagOulfwoaRPG09UX69vhh5W+D3eoTVJhHhEeDWyl8+SGL91ugeWnfGQXmMd3P7GXQQh77q1UTM1B/VQKxoKrJP1pwWl0zURaXcHH49OEWGyJstKp6IBa/XY53xGlY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673229151377984.7255757787935; Sun, 8 Jan 2023 17:52:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEhBu-0000rX-Jc; Sun, 08 Jan 2023 20:43:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEhBr-0000pY-On for qemu-devel@nongnu.org; Sun, 08 Jan 2023 20:43:07 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEhBp-0001Wt-Pg for qemu-devel@nongnu.org; Sun, 08 Jan 2023 20:43:07 -0500 Received: by mail-pj1-x1033.google.com with SMTP id o7-20020a17090a0a0700b00226c9b82c3aso7810363pjo.3 for ; Sun, 08 Jan 2023 17:43:05 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.43.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:43:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ybxe5BnWNBxH6uN6QcJsd3eJUNtW1iUptSAvC+pL/8o=; b=LHtIZ5WaIa8eCac+p7u/LlAiTfT2YhcGbhss+QuyKuNFE/n7y80Wig0V0yLtL/NYDH j8akzZ17xwpSeakdmVFcgbODJVzKcyxrRGQY3JT7qt6E8Q5lp5bcXsGYXApnlrY72B1W 4gURPSHD48joJMUiOHqC/qW0yN+Hikq538J+ZcMy85YLm5wrOol1Yp2DNzRa2xf5ucKE YZKTlpUAIQ1asn8x8hDg0zUk4V8Yh5Pi3FLpIVuMEOUjOkdUh3Bh8WTXE5nyVNIZaRb/ JZyWOL7J2imjI8TOv+i+GmjWGVIaGw+9Np7+Tvqnt/KC0JLd8EAVhUV531Hy08Ae+fZm Ji/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ybxe5BnWNBxH6uN6QcJsd3eJUNtW1iUptSAvC+pL/8o=; b=bErZArQxQECNyFasgEj6o7aH3q12aEchXoFK25roSJbLI80HveuKzgf3D8vQxu9ILW pbHf+pb+cgfJ/gQZj7m1ZIOcPkrvk1Pi8911wBTQYSVqrNv6MD2GRxzk9lcijcIIWDkQ 6rocrjApypUAIzvIRyYDwGdTigZOO80KldhbmL0aM7fcvALRc41Kh4dq+yTqztKWKiju 5rIkrbbefpF0ZA99LOftIkWnCJF9P+Qpyx4UuKnYwAoWIysQT4FNt2Rpedb6Fa0MISLK 1HrTdD7b+6XWwG/MjPcC59X4tK49zy1aRH4xqMOFNutRx8UXW19glc4xpDVGrojdGG72 17wg== X-Gm-Message-State: AFqh2kqJj2p+1mXtzIzKowb+j+loSjkwnyn8ebjiFCLaOOQLp7wz8rF8 0t1zY2m2nIOgZGRBy5QN3v3/6gIws8MqY7Qj X-Google-Smtp-Source: AMrXdXv6IIRTjo4cwBlpUr0g4Kzj5jR+fNMPKhvcNgZqc1CbZTO8ggKZcOeBC7o8/lDfVmpU8XcV4w== X-Received: by 2002:a17:902:e884:b0:192:c014:f6ba with SMTP id w4-20020a170902e88400b00192c014f6bamr41486076plg.33.1673228584953; Sun, 08 Jan 2023 17:43:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 17/22] tcg/ppc: Reorg goto_tb implementation Date: Sun, 8 Jan 2023 17:42:43 -0800 Message-Id: <20230109014248.2894281-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109014248.2894281-1-richard.henderson@linaro.org> References: <20230109014248.2894281-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673229151802100002 Content-Type: text/plain; charset="utf-8" The old ppc64 implementation replaces 2 or 4 insns, which leaves a race condition in which a thread could be stopped at a PC in the middle of the sequence, and when restarted does not see the complete address computation and branches to nowhere. The new implemetation replaces only one insn, swapping between b and mtctr r31 falling through to a general-case indirect branch. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/ppc/tcg-target.h | 3 +- tcg/ppc/tcg-target.c.inc | 158 +++++++++++---------------------------- 2 files changed, 44 insertions(+), 117 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index f253184915..af81c5a57f 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -27,11 +27,10 @@ =20 #ifdef _ARCH_PPC64 # define TCG_TARGET_REG_BITS 64 -# define MAX_CODE_GEN_BUFFER_SIZE (2 * GiB) #else # define TCG_TARGET_REG_BITS 32 -# define MAX_CODE_GEN_BUFFER_SIZE (32 * MiB) #endif +#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) =20 #define TCG_TARGET_NB_REGS 64 #define TCG_TARGET_INSN_UNIT_SIZE 4 diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 6f2c8faea6..8d6899cf40 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1854,104 +1854,6 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) tcg_out32(s, insn); } =20 -static inline uint64_t make_pair(tcg_insn_unit i1, tcg_insn_unit i2) -{ - if (HOST_BIG_ENDIAN) { - return (uint64_t)i1 << 32 | i2; - } - return (uint64_t)i2 << 32 | i1; -} - -static inline void ppc64_replace2(uintptr_t rx, uintptr_t rw, - tcg_insn_unit i0, tcg_insn_unit i1) -{ -#if TCG_TARGET_REG_BITS =3D=3D 64 - qatomic_set((uint64_t *)rw, make_pair(i0, i1)); - flush_idcache_range(rx, rw, 8); -#else - qemu_build_not_reached(); -#endif -} - -static inline void ppc64_replace4(uintptr_t rx, uintptr_t rw, - tcg_insn_unit i0, tcg_insn_unit i1, - tcg_insn_unit i2, tcg_insn_unit i3) -{ - uint64_t p[2]; - - p[!HOST_BIG_ENDIAN] =3D make_pair(i0, i1); - p[HOST_BIG_ENDIAN] =3D make_pair(i2, i3); - - /* - * There's no convenient way to get the compiler to allocate a pair - * of registers at an even index, so copy into r6/r7 and clobber. - */ - asm("mr %%r6, %1\n\t" - "mr %%r7, %2\n\t" - "stq %%r6, %0" - : "=3DQ"(*(__int128 *)rw) : "r"(p[0]), "r"(p[1]) : "r6", "r7"); - flush_idcache_range(rx, rw, 16); -} - -void tb_target_set_jmp_target(const TranslationBlock *tb, int n, - uintptr_t jmp_rx, uintptr_t jmp_rw) -{ - tcg_insn_unit i0, i1, i2, i3; - uintptr_t addr =3D tb->jmp_target_addr[n]; - intptr_t tb_diff =3D addr - (uintptr_t)tb->tc.ptr; - intptr_t br_diff =3D addr - (jmp_rx + 4); - intptr_t lo, hi; - - if (TCG_TARGET_REG_BITS =3D=3D 32) { - intptr_t diff =3D addr - jmp_rx; - tcg_debug_assert(in_range_b(diff)); - qatomic_set((uint32_t *)jmp_rw, B | (diff & 0x3fffffc)); - flush_idcache_range(jmp_rx, jmp_rw, 4); - return; - } - - /* - * For 16-bit displacements, we can use a single add + branch. - * This happens quite often. - */ - if (tb_diff =3D=3D (int16_t)tb_diff) { - i0 =3D ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff); - i1 =3D B | (br_diff & 0x3fffffc); - ppc64_replace2(jmp_rx, jmp_rw, i0, i1); - return; - } - - lo =3D (int16_t)tb_diff; - hi =3D (int32_t)(tb_diff - lo); - assert(tb_diff =3D=3D hi + lo); - i0 =3D ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16); - i1 =3D ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo); - - /* - * Without stq from 2.07, we can only update two insns, - * and those must be the ones that load the target address. - */ - if (!have_isa_2_07) { - ppc64_replace2(jmp_rx, jmp_rw, i0, i1); - return; - } - - /* - * For 26-bit displacements, we can use a direct branch. - * Otherwise we still need the indirect branch, which we - * must restore after a potential direct branch write. - */ - br_diff -=3D 4; - if (in_range_b(br_diff)) { - i2 =3D B | (br_diff & 0x3fffffc); - i3 =3D NOP; - } else { - i2 =3D MTSPR | RS(TCG_REG_TB) | CTR; - i3 =3D BCCTR | BO_ALWAYS; - } - ppc64_replace4(jmp_rx, jmp_rw, i0, i1, i2, i3); -} - static void tcg_out_call_int(TCGContext *s, int lk, const tcg_insn_unit *target) { @@ -2625,30 +2527,56 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_= t arg) =20 static void tcg_out_goto_tb(TCGContext *s, int which) { - /* Direct jump. */ - if (TCG_TARGET_REG_BITS =3D=3D 64) { - /* Ensure the next insns are 8 or 16-byte aligned. */ - while ((uintptr_t)s->code_ptr & (have_isa_2_07 ? 15 : 7)) { - tcg_out32(s, NOP); - } + uintptr_t ptr =3D get_jmp_target_addr(s, which); + + if (USE_REG_TB) { + ptrdiff_t offset =3D tcg_tbrel_diff(s, (void *)ptr); + tcg_out_mem_long(s, LD, LDX, TCG_REG_TB, TCG_REG_TB, offset); + =20 + /* Direct branch will be patched by tb_target_set_jmp_target. */ set_jmp_insn_offset(s, which); - tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0)); - tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0)); tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); + + /* When branch is out of range, fall through to indirect. */ + tcg_out32(s, BCCTR | BO_ALWAYS); + + /* For the unlinked case, need to reset TCG_REG_TB. */ + set_jmp_reset_offset(s, which); + tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB, + -tcg_current_code_size(s)); + } else { + /* Direct branch will be patched by tb_target_set_jmp_target. */ + set_jmp_insn_offset(s, which); + tcg_out32(s, NOP); + + /* When branch is out of range, fall through to indirect. */ + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, ptr - (int16_t)ptr); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, (int16_t)p= tr); + tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR); tcg_out32(s, BCCTR | BO_ALWAYS); set_jmp_reset_offset(s, which); - if (USE_REG_TB) { - /* For the unlinked case, need to reset TCG_REG_TB. */ - tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB, - -tcg_current_code_size(s)); - } - } else { - set_jmp_insn_offset(s, which); - tcg_out32(s, B); - set_jmp_reset_offset(s, which); } } =20 +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t jmp_rx, uintptr_t jmp_rw) +{ + uintptr_t addr =3D tb->jmp_target_addr[n]; + intptr_t diff =3D addr - jmp_rx; + tcg_insn_unit insn; + + if (in_range_b(diff)) { + insn =3D B | (diff & 0x3fffffc); + } else if (USE_REG_TB) { + insn =3D MTSPR | RS(TCG_REG_TB) | CTR; + } else { + insn =3D NOP; + } + + qatomic_set((uint32_t *)jmp_rw, insn); + flush_idcache_range(jmp_rx, jmp_rw, 4); +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673229027; cv=none; d=zohomail.com; s=zohoarc; b=S55PSD5gyQHNsoVpPOvC2TnS6XvmdkH/LMiAbX0acZWZys3w3lgf1Xxuri7pCZI53v0XJ78s/fY96c66y+cE4UHwRHx9dd1sRwQ4xZuKGh196t2Cl+iptm8y/GL2Nr3qCUTkTU5gMdXD8ySLML6hHmJHonwkr1QZl9tcC3OePa0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673229027; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KSp22loacyuOjJO3M7+ZxWFYwNHKL7tMHgm5GLt2Nj4=; b=YHlv9wVnvPzc7soi6V9u6yHYEKy2D+hCN+ucENOdSl2XS9sSYmimC+Ygll7N8osjUpDGraLT8D1Lkajj82ckl6Ul93SrhvA6tOP3lCLZ5Zs5lylqn2FFfhLo86d+uvn8wHt4YXbk8q1A2+sKhQ1AOGsO96Tuc5e1Pwa0MYA/M8E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673229027571539.8169148446198; Sun, 8 Jan 2023 17:50:27 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEhBv-0000sI-C2; Sun, 08 Jan 2023 20:43:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEhBt-0000qh-2H for qemu-devel@nongnu.org; Sun, 08 Jan 2023 20:43:09 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEhBr-0001Zh-7l for qemu-devel@nongnu.org; Sun, 08 Jan 2023 20:43:08 -0500 Received: by mail-pl1-x634.google.com with SMTP id 17so8004360pll.0 for ; Sun, 08 Jan 2023 17:43:06 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.43.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:43:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KSp22loacyuOjJO3M7+ZxWFYwNHKL7tMHgm5GLt2Nj4=; b=lH35ryC5/4oPMmWm6b3ZiBbksR31kblEChr9megPpfZaB2Ow4qQDBaPU8WDM4GTEti Zg4WuAwnM/pDjTdO5zV9gAZlXE4ANvf5wVJ8d/xUkyFXgeLeCN7NwG5EEi6MDbliHxJS AV1nS9/T8m8r0OFJe7SCBExm2SkgO+K1TWfAAYl7vvQ1lDEQswnK9AN7UmcO7wJn/rLu jIJU2oGh9y7CXOwDv6zV/l6oTryPNNTD07XHMkasRBfY5CIZ9veMSxMnW2QSA7yzK7+L GCMvQtL/aBThGdZlvJfzAn5FJMlpelpDprgzigR7YCuLqXli8sGwgZI8bSiHzKoz8laS rA6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KSp22loacyuOjJO3M7+ZxWFYwNHKL7tMHgm5GLt2Nj4=; b=wA8dy8n+KMr9kXmiY3Jc2sE31siMJsLHFQzAEZLMP5WLYhM3wjTAPA2lVstRLGga0q gtrXKLk6OZe4gfb4c1/zPtR3mqj2pZuAwzfDZCD7fxXWMddnTPe8N3JEmB7fp+57xmrl 5uWXIFGd+79E13f6ZM3YvEIqppippdHQko9K60yo+DDmMdvNH0ihHdOTKqvVqdSXN/cC q2xZJWC3zwQx83jzagflO0OMt3dHdn1xe/KpEgqJ5wAorTbjypjnMQCj6CmPx2p7g+8s vREDUKOTyJMIY0LHsrZWf+3frzAU9WrftwS1xy4rdab4wOlpFbW3Gg+DTQuS/Jm0Vc3E MDJA== X-Gm-Message-State: AFqh2kpozsv2Q/bV1OlXQB32iydcv5np1oeTk/rQ03oPxMuXoWpbR6Gm 7ahAA+1x9VDkRF5u+I6QnWfIDp9DQy9SrrHw X-Google-Smtp-Source: AMrXdXuDYp1D/tl4ImmHdQKmCDHg/8IclGgGpO6oDeTExAWGiViKoCvSuhePn6f2DJ7Q8n3l49iXKg== X-Received: by 2002:a05:6a20:7d95:b0:b0:1051:30a0 with SMTP id v21-20020a056a207d9500b000b0105130a0mr98408325pzj.51.1673228585820; Sun, 08 Jan 2023 17:43:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 18/22] tcg/sparc64: Remove USE_REG_TB Date: Sun, 8 Jan 2023 17:42:44 -0800 Message-Id: <20230109014248.2894281-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109014248.2894281-1-richard.henderson@linaro.org> References: <20230109014248.2894281-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673229029314100003 This is always true for sparc64, so this is dead since 3a5f6805c7ca. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/sparc64/tcg-target.c.inc | 62 ++++++++++++------------------------ 1 file changed, 21 insertions(+), 41 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index fdb711bdf6..e0b3957149 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -92,7 +92,6 @@ static const char * const tcg_target_reg_names[TCG_TARGET= _NB_REGS] =3D { #endif =20 #define TCG_REG_TB TCG_REG_I1 -#define USE_REG_TB (sizeof(void *) > 4) =20 static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_L0, @@ -439,7 +438,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, } =20 /* A 13-bit constant relative to the TB. */ - if (!in_prologue && USE_REG_TB) { + if (!in_prologue) { test =3D tcg_tbrel_diff(s, (void *)arg); if (check_fit_ptr(test, 13)) { tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD); @@ -468,7 +467,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, } =20 /* Use the constant pool, if possible. */ - if (!in_prologue && USE_REG_TB) { + if (!in_prologue) { new_pool_label(s, arg, R_SPARC_13, s->code_ptr, tcg_tbrel_diff(s, NULL)); tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(TCG_REG_TB)); @@ -1015,10 +1014,8 @@ static void tcg_target_qemu_prologue(TCGContext *s) #endif =20 /* We choose TCG_REG_TB such that no move is required. */ - if (USE_REG_TB) { - QEMU_BUILD_BUG_ON(TCG_REG_TB !=3D TCG_REG_I1); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); - } + QEMU_BUILD_BUG_ON(TCG_REG_TB !=3D TCG_REG_I1); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); =20 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL); /* delay slot */ @@ -1423,7 +1420,7 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t = a0) tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); tcg_out_movi_imm13(s, TCG_REG_O0, a0); return; - } else if (USE_REG_TB) { + } else { intptr_t tb_diff =3D tcg_tbrel_diff(s, (void *)a0); if (check_fit_ptr(tb_diff, 13)) { tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); @@ -1439,36 +1436,30 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_= t a0) =20 static void tcg_out_goto_tb(TCGContext *s, int which) { + int c; + /* Direct jump. */ - if (USE_REG_TB) { - /* make sure the patch is 8-byte aligned. */ - if ((intptr_t)s->code_ptr & 4) { - tcg_out_nop(s); - } - set_jmp_insn_offset(s, which); - tcg_out_sethi(s, TCG_REG_T1, 0); - tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 0, ARITH_OR); - tcg_out_arith(s, TCG_REG_G0, TCG_REG_TB, TCG_REG_T1, JMPL); - tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); - } else { - set_jmp_insn_offset(s, which); - tcg_out32(s, CALL); + /* make sure the patch is 8-byte aligned. */ + if ((intptr_t)s->code_ptr & 4) { tcg_out_nop(s); } + set_jmp_insn_offset(s, which); + tcg_out_sethi(s, TCG_REG_T1, 0); + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 0, ARITH_OR); + tcg_out_arith(s, TCG_REG_G0, TCG_REG_TB, TCG_REG_T1, JMPL); + tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); set_jmp_reset_offset(s, which); =20 /* * For the unlinked path of goto_tb, we need to reset TCG_REG_TB * to the beginning of this TB. */ - if (USE_REG_TB) { - int c =3D -tcg_current_code_size(s); - if (check_fit_i32(c, 13)) { - tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, c); - tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD= ); - } + c =3D -tcg_current_code_size(s); + if (check_fit_i32(c, 13)) { + tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, c); + tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); } } =20 @@ -1488,11 +1479,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, switch (opc) { case INDEX_op_goto_ptr: tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL); - if (USE_REG_TB) { - tcg_out_mov_delay(s, TCG_REG_TB, a0); - } else { - tcg_out_nop(s); - } + tcg_out_mov_delay(s, TCG_REG_TB, a0); break; case INDEX_op_br: tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0)); @@ -1898,13 +1885,6 @@ void tb_target_set_jmp_target(const TranslationBlock= *tb, int n, tcg_debug_assert(tb_disp =3D=3D (int32_t)tb_disp); tcg_debug_assert(br_disp =3D=3D (int32_t)br_disp); =20 - if (!USE_REG_TB) { - qatomic_set((uint32_t *)jmp_rw, - deposit32(CALL, 0, 30, br_disp >> 2)); - flush_idcache_range(jmp_rx, jmp_rw, 4); - return; - } - /* This does not exercise the range of the branch, but we do still need to be able to load the new value of TCG_REG_TB. But this does still happen quite often. */ --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673228986; cv=none; d=zohomail.com; s=zohoarc; b=X16ExPUvg58Z1nBzjM2xEbaw+PWK9EKpfHfwTGrP98o/GvVzEWFCfRRSQnKt/msJ1tsxd2h/XVLIbKf19aln16ot2r+3JKqCD/WWupk+n1bZi/XoASq57yxib1iMulrHRCrcxnlC1cmXm4yrJAIlIJEckybvuWkYAW5uE8UQdCc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673228986; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Do4aEWMqG+Ov79EmLqFR2DzW1DBnRUUmODHZM3QbOyY=; b=FfnhAmyntM0jmEGWZ7TYOg2ZUgTD6Aga9Y0m3cNh3GMRdkSIAhmkF6gZ3tSI/DQLH8gQdSMEeqr877D10YDJcAm3aFlqAyLjamB+757aGIPnaIYVSDOy66lsd3/fCcF3okFiW5KDd+fbBEP2nARAmgd+pPwMu5/Etsyii5US90A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673228986082897.5311652547919; Sun, 8 Jan 2023 17:49:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEhBv-0000sK-Rr; Sun, 08 Jan 2023 20:43:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEhBt-0000rJ-Vg for qemu-devel@nongnu.org; Sun, 08 Jan 2023 20:43:09 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEhBs-0001aF-4f for qemu-devel@nongnu.org; Sun, 08 Jan 2023 20:43:09 -0500 Received: by mail-pj1-x102b.google.com with SMTP id w4-20020a17090ac98400b002186f5d7a4cso11290503pjt.0 for ; Sun, 08 Jan 2023 17:43:07 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.43.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:43:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Do4aEWMqG+Ov79EmLqFR2DzW1DBnRUUmODHZM3QbOyY=; b=Vok9Tv8ySnizXNuNZTkXprj6oA4OUhM0sTmwZDwBESDFy6XspgtZcfW/ljybJfq+kV ccT8IEFgfqWXA7I/XnE2WCo6Y1JIF9eg5HkcVC+mKe0oDlbzmBgPZJra+Vmy3MOm9ofC pP1ezkc2CDG6nTrM/uuRREinEakp2UB8cegmwZpOjnL/lTnU9VwWqG0vEQC3dhmB9KT1 7S7RIT+NH447KSCpPuTy9O6eSpN6kgmSQlgkSV7DGQbThq02LnzNGh75SYB6bE/a6RQT DJqps1lv3NlbojgjtGzoQWyOcZuLou/krvMzCOatqtpuXkuC6Q8W9jRPuJiVqlIklF8d SpsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Do4aEWMqG+Ov79EmLqFR2DzW1DBnRUUmODHZM3QbOyY=; b=sQasUNQDjEagazIkWEHEhaS5Hto+4QVWoUMkftYrT8AgLf9qvXOYBhJmNmq7zplgW6 p6fgHcIRubGxAYyqkpZIF6BfcA7splaX4iCyzZcZicFldJ2uzZyjbDAudHaYGfqnJCD1 SZGltVzhoDN6fuTyoeGyYU8UZzYld0Xfx22cvSyUzM71H3KnGqdY0lzpt4pCXjo7rycY 8vJn5Qv54pZBT4xR08ZZhMN1bhX/98E58dz7QQ9jMUvmvjWjCsIYHQs7Wa8xxn3mrjZ0 soWLPng01T5SjDsPdoaQnlrEuOsJsy5sLafkWhc+/7ioa41+uxU0jNSwvxHSmBoGIMhV u3jg== X-Gm-Message-State: AFqh2kqj1px6qon/EnZFESP1c2FHmeBcM4deF6gSSPgt+bN7REABi5+Q wMLMpzNYr04OWJgN7jnEfbCzAuk1Cp4AGrxf X-Google-Smtp-Source: AMrXdXuCbkId92BHddcKG+OIFD2aOSObIudMJww3OUQRHAkN8Y8xhbWbLk8g/9MMFKiVhPgByuOcTQ== X-Received: by 2002:a17:902:7404:b0:189:b0fe:d70f with SMTP id g4-20020a170902740400b00189b0fed70fmr64743627pll.60.1673228586790; Sun, 08 Jan 2023 17:43:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 19/22] tcg/sparc64: Reorg goto_tb implementation Date: Sun, 8 Jan 2023 17:42:45 -0800 Message-Id: <20230109014248.2894281-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109014248.2894281-1-richard.henderson@linaro.org> References: <20230109014248.2894281-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673228987173100001 Content-Type: text/plain; charset="utf-8" The old sparc64 implementation may replace two insns, which leaves a race condition in which a thread could be stopped at a PC in the middle of the sequence, and when restarted does not see the complete address computation and branches to nowhere. The new implemetation replaces only one insn, swapping between a direct branch and a direct call. The TCG_REG_TB register is loaded from tb->jmp_target_addr[] in the delay slot. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/sparc64/tcg-target.c.inc | 87 +++++++++++++++--------------------- 1 file changed, 37 insertions(+), 50 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index e0b3957149..dd406bc065 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1436,33 +1436,56 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_= t a0) =20 static void tcg_out_goto_tb(TCGContext *s, int which) { - int c; + ptrdiff_t off =3D tcg_tbrel_diff(s, (void *)get_jmp_target_addr(s, whi= ch)); =20 - /* Direct jump. */ - /* make sure the patch is 8-byte aligned. */ - if ((intptr_t)s->code_ptr & 4) { - tcg_out_nop(s); - } + /* Direct branch will be patched by tb_target_set_jmp_target. */ set_jmp_insn_offset(s, which); - tcg_out_sethi(s, TCG_REG_T1, 0); - tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 0, ARITH_OR); - tcg_out_arith(s, TCG_REG_G0, TCG_REG_TB, TCG_REG_T1, JMPL); - tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); + tcg_out32(s, CALL); + /* delay slot */ + tcg_debug_assert(check_fit_ptr(off, 13)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, TCG_REG_TB, off); set_jmp_reset_offset(s, which); =20 /* * For the unlinked path of goto_tb, we need to reset TCG_REG_TB * to the beginning of this TB. */ - c =3D -tcg_current_code_size(s); - if (check_fit_i32(c, 13)) { - tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD); + off =3D -tcg_current_code_size(s); + if (check_fit_i32(off, 13)) { + tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, off, ARITH_ADD); } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, c); + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, off); tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); } } =20 +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t jmp_rx, uintptr_t jmp_rw) +{ + uintptr_t addr =3D tb->jmp_target_addr[n]; + intptr_t br_disp =3D (intptr_t)(addr - jmp_rx) >> 2; + tcg_insn_unit insn; + + br_disp >>=3D 2; + if (check_fit_ptr(br_disp, 19)) { + /* ba,pt %icc, addr */ + insn =3D deposit32(INSN_OP(0) | INSN_OP2(1) | INSN_COND(COND_A) + | BPCC_ICC | BPCC_PT, 0, 19, br_disp); + } else if (check_fit_ptr(br_disp, 22)) { + /* ba addr */ + insn =3D deposit32(INSN_OP(0) | INSN_OP2(2) | INSN_COND(COND_A), + 0, 22, br_disp); + } else { + /* The code_gen_buffer can't be larger than 2GB. */ + tcg_debug_assert(check_fit_ptr(br_disp, 30)); + /* call addr */ + insn =3D deposit32(CALL, 0, 30, br_disp); + } + + qatomic_set((uint32_t *)jmp_rw, insn); + flush_idcache_range(jmp_rx, jmp_rw, 4); +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -1871,39 +1894,3 @@ void tcg_register_jit(const void *buf, size_t buf_si= ze) { tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } - -void tb_target_set_jmp_target(const TranslationBlock *tb, int n, - uintptr_t jmp_rx, uintptr_t jmp_rw) -{ - uintptr_t addr =3D tb->jmp_target_addr[n]; - intptr_t tb_disp =3D addr - (uintptr_t)tb->tc.ptr; - intptr_t br_disp =3D addr - jmp_rx; - tcg_insn_unit i1, i2; - - /* We can reach the entire address space for ILP32. - For LP64, the code_gen_buffer can't be larger than 2GB. */ - tcg_debug_assert(tb_disp =3D=3D (int32_t)tb_disp); - tcg_debug_assert(br_disp =3D=3D (int32_t)br_disp); - - /* This does not exercise the range of the branch, but we do - still need to be able to load the new value of TCG_REG_TB. - But this does still happen quite often. */ - if (check_fit_ptr(tb_disp, 13)) { - /* ba,pt %icc, addr */ - i1 =3D (INSN_OP(0) | INSN_OP2(1) | INSN_COND(COND_A) - | BPCC_ICC | BPCC_PT | INSN_OFF19(br_disp)); - i2 =3D (ARITH_ADD | INSN_RD(TCG_REG_TB) | INSN_RS1(TCG_REG_TB) - | INSN_IMM13(tb_disp)); - } else if (tb_disp >=3D 0) { - i1 =3D SETHI | INSN_RD(TCG_REG_T1) | ((tb_disp & 0xfffffc00) >> 10= ); - i2 =3D (ARITH_OR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1) - | INSN_IMM13(tb_disp & 0x3ff)); - } else { - i1 =3D SETHI | INSN_RD(TCG_REG_T1) | ((~tb_disp & 0xfffffc00) >> 1= 0); - i2 =3D (ARITH_XOR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1) - | INSN_IMM13((tb_disp & 0x3ff) | -0x400)); - } - - qatomic_set((uint64_t *)jmp_rw, deposit64(i2, 32, 32, i1)); - flush_idcache_range(jmp_rx, jmp_rw, 8); -} --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.43.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:43:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8WPefftrPh8ywQzSPRJOZ0Nm9rSwT8iGc5lkhLzE1qM=; b=GcfA34gmR5tftba4rxwt7FuyJTd2iN7cGxITh1wTGwH8Wg4Z1tvgByfD4fnYgCQMvi z7rAbthlniSGd/XrKUJnVgYRh+dZZymsqmbselU3FrQ6xC4zMIJ1Ytsyx4n8Chg6TGOV w71KNVOjtQgb3OmJ0U24l8J0BRNF11zxhxTckecKhC5IrPNt6ASUPji9s7vidQgIukXc 9aYs76MdulcG7uX/62nIWW9n734IwgVYLLH7mFDyBxVJq/zGRlqcmSrO/HLsUYaKK115 Uebl8MUgjlmIlexDBN8FO9nT1ed+NBhUBCr5p4qE7kxn/hEhj/1utttF+9MdE8Wt3wmY CVnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8WPefftrPh8ywQzSPRJOZ0Nm9rSwT8iGc5lkhLzE1qM=; b=CA6y/SibrijpNG82ycHMJdRPhmNrSd5LK6JM3L+UEbw69Aa11dHRowX5dnl2VK/FES wY8TsX2JIoGxQLegg8zTFWKotdSBcL+02t5RqW7yeA3M+W0X4AYaKfsyQPKtKbMH4Gex n9ykAceLNjb72VyEGGIbmEmFQg4VZnvTFBSzDjtckRsIdwgPi0KsboYe/+vFsiBjJVqY kJfudpFig0dJJE3H4aJHVgDs65txAoQIjuc3XKNLof0shJK2nn8cyEXO0a6GCegxU85m mLdWjWZuVAGUfO739yMCnglv3p4hriXY0BHwY5S3YqRTt8OUf7Z+F5dbp4F8RKTa3ozL O/IA== X-Gm-Message-State: AFqh2kpjaW5W8+MEDKfndEpjtiVz1RRNd2yuyzpkCcoO1eYROkhMnjNP cH48NYPh8VV8hdsIkPjUDE2ciacJYpg1dYMY X-Google-Smtp-Source: AMrXdXsA+L9kSDbPdlwcgxKvNAVfJMecUmI2Yo2u72ckmhwSKnMpKDz2WtKCwuGHCKsDSAYVxob+JQ== X-Received: by 2002:a17:902:848d:b0:189:5f5c:da1d with SMTP id c13-20020a170902848d00b001895f5cda1dmr61162230plo.18.1673228587626; Sun, 08 Jan 2023 17:43:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 20/22] tcg/arm: Implement direct branch for goto_tb Date: Sun, 8 Jan 2023 17:42:46 -0800 Message-Id: <20230109014248.2894281-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109014248.2894281-1-richard.henderson@linaro.org> References: <20230109014248.2894281-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673228669925100004 Content-Type: text/plain; charset="utf-8" Now that tcg can handle direct and indirect goto_tb simultaneously, we can optimistically leave space for a direct branch and fall back to loading the pointer from the TB for an indirect branch. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/arm/tcg-target.c.inc | 52 ++++++++++++++++++++++++++++------------ 1 file changed, 37 insertions(+), 15 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index e1e1c2620d..794ed8c3a2 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -135,6 +135,8 @@ typedef enum { ARITH_BIC =3D 0xe << 21, ARITH_MVN =3D 0xf << 21, =20 + INSN_B =3D 0x0a000000, + INSN_CLZ =3D 0x016f0f10, INSN_RBIT =3D 0x06ff0f30, =20 @@ -546,7 +548,7 @@ static bool tcg_target_const_match(int64_t val, TCGType= type, int ct) =20 static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) { - tcg_out32(s, (cond << 28) | 0x0a000000 | + tcg_out32(s, (cond << 28) | INSN_B | (((offset - 8) >> 2) & 0x00ffffff)); } =20 @@ -1941,32 +1943,52 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_= t arg) =20 static void tcg_out_goto_tb(TCGContext *s, int which) { - /* Indirect jump method */ - intptr_t ptr, dif, dil; - TCGReg base =3D TCG_REG_PC; + uintptr_t i_addr; + intptr_t i_disp; =20 - ptr =3D get_jmp_target_addr(s, which); - dif =3D tcg_pcrel_diff(s, (void *)ptr) - 8; - dil =3D sextract32(dif, 0, 12); - if (dif !=3D dil) { + /* Direct branch will be patched by tb_target_set_jmp_target. */ + set_jmp_insn_offset(s, which); + tcg_out32(s, INSN_NOP); + + /* When branch is out of range, fall through to indirect. */ + i_addr =3D get_jmp_target_addr(s, which); + i_disp =3D tcg_pcrel_diff(s, (void *)i_addr) - 8; + tcg_debug_assert(i_disp < 0); + if (i_disp >=3D -0xfff) { + tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, i_disp); + } else { /* * The TB is close, but outside the 12 bits addressable by * the load. We can extend this to 20 bits with a sub of a - * shifted immediate from pc. In the vastly unlikely event - * the code requires more than 1MB, we'll use 2 insns and - * be no worse off. + * shifted immediate from pc. */ - base =3D TCG_REG_R0; - tcg_out_movi32(s, COND_AL, base, ptr - dil); + int h =3D -i_disp; + int l =3D h & 0xfff; + + h =3D encode_imm_nofail(h - l); + tcg_out_dat_imm(s, COND_AL, ARITH_SUB, TCG_REG_R0, TCG_REG_PC, h); + tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, l); } - tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, base, dil); set_jmp_reset_offset(s, which); } =20 void tb_target_set_jmp_target(const TranslationBlock *tb, int n, uintptr_t jmp_rx, uintptr_t jmp_rw) { - /* Always indirect, nothing to do */ + uintptr_t addr =3D tb->jmp_target_addr[n]; + ptrdiff_t offset =3D addr - (jmp_rx + 8); + tcg_insn_unit insn; + + /* Either directly branch, or fall through to indirect branch. */ + if (offset =3D=3D sextract64(offset, 0, 26)) { + /* B */ + insn =3D (COND_AL << 28) | INSN_B | ((offset >> 2) & 0x00ffffff); + } else { + insn =3D INSN_NOP; + } + + qatomic_set((uint32_t *)jmp_rw, insn); + flush_idcache_range(jmp_rx, jmp_rw, 4); } =20 static void tcg_out_op(TCGContext *s, TCGOpcode opc, --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673228668; cv=none; d=zohomail.com; s=zohoarc; b=CcMBnHfqcoE0UH1sN4AZYeqKwC2PAGzNP2HnCS8kG6P1bJLjr/Ob/e/6zRjqL+3qUPQOBtiT8/YOH5/MA0K8oT6CFY22+9NoVs8utmRum5VYMwZbqdiNhVESiu3Spw0KyKKyZmKcjR0lZEhTxT9/3IEnVeOue6KyDVRdpsIAL6o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673228668; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=op0Rf4OXX9B+XJCysG6bOjZLlZA6usVvQUy5OnNEk0M=; b=RFAQRo8MWkhRoysFv42iyHm15PEZH+GOgg90V1qMQVKbLfSn0X5mfD9RTlLuRU20c30e7CxNKii8ui6hmpKgFpmBr9gW9NxVp2TnvcsxbH+Gg76EDvvHX6lu3J7J8CzWfDvJDQpXQbspoMQw2GM2m37prikf8GUKmbunfcfvUjM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673228668538878.9464454208755; Sun, 8 Jan 2023 17:44:28 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pEhBw-0000sj-TH; Sun, 08 Jan 2023 20:43:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEhBv-0000s6-4E for qemu-devel@nongnu.org; Sun, 08 Jan 2023 20:43:11 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEhBt-0001aU-LZ for qemu-devel@nongnu.org; Sun, 08 Jan 2023 20:43:10 -0500 Received: by mail-pj1-x1032.google.com with SMTP id o13so3761222pjg.2 for ; Sun, 08 Jan 2023 17:43:09 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.43.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:43:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=op0Rf4OXX9B+XJCysG6bOjZLlZA6usVvQUy5OnNEk0M=; b=obpYe50VjzdOvjlEFglcIoQJbuSpHUVNSPDAklEgvDunzjudmVywZtztfnASePXamn k8fRqpSbHCgZcBbLy/EbqXB4qu4J/QQBOErEXCsKvUsxVsaBJa/+P9XQnGxLCwtIg6Le uEScZataojyfD4WFutLHZkGIwyMCdr6p37cjZA1n8HoM34oKfny1fksYA63TzvWqjcaD Gr2F6q4lW/mW4WcljPWo9DoKDdXIQvSYxEetRuaLCNnFNP1GYBD78FgqAPuK75Y4F9RN E9DazRtqsD6NyPY70UKDPvPC7oX/aJO8dHNU5kbuc8aE2I6RKQS/pANCFSyEp4WsrLoS OwTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673228669869100003 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/riscv/tcg-target.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 136fe54d4b..82ca86431e 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -267,6 +267,7 @@ typedef enum { #endif =20 OPC_FENCE =3D 0x0000000f, + OPC_NOP =3D OPC_ADDI, /* nop =3D addi r0,r0,0 */ } RISCVInsn; =20 /* @@ -403,7 +404,7 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int coun= t) { int i; for (i =3D 0; i < count; ++i) { - p[i] =3D encode_i(OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); + p[i] =3D OPC_NOP; } } =20 --=20 2.34.1 From nobody Sat May 18 00:00:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673229199; cv=none; d=zohomail.com; s=zohoarc; b=UfLCAw35wNpmnOC3nL9bAkKA7wYdvQhZpvwJXDp7qIFUqkB5ttHGv1E3qzNTnsn5n3JeKQtR34QE7rkAJu/7ODlqavhI/F4Sh5edUseVBniApYVjwf+S5/ajPvl0gNwuH5JE6ADvj9/BWnxpR4qKxpgPJEQaG7GVriqYw1oesQg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673229199; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902ca0d00b00178b77b7e71sm4743617pld.188.2023.01.08.17.43.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 17:43:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+h7RCn1T3BLlChRBESm2AUKCCLXsKfuBBeFApIcrDxY=; b=wT5yyM6zUtVSQbCKL2TDavKToH9e8JA9+hT1i1OxFgH/ju8yO/ZtL8kNn8SZct9cd3 g8BTi8HtM0oMCBdWlUk7WeYtMx0EWg1fRwI2EXqcfEL+eLWmEsEXa3xuT3uxUEWC1Oq+ olz+v5s3akkt8dlEjES2Od8iV6WSMQCI5f16FIqb2y2IlyjO0boehZUorJoM2wT5jYFe /Fsmvz8KVbLIntREquCtzf5Vr3A9ep4kyh1qkWArDRZ6aKiRBRbpgbjvKtqQ4OGpebZi ZYyD2980sVUFeEEqg7NJsDLXGrrZrNERmep3O6qccaehMeYNfQCl8rICjpKr+4CByf4T OLxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+h7RCn1T3BLlChRBESm2AUKCCLXsKfuBBeFApIcrDxY=; b=RL2r5IfT7jDYbrlwnNsqEwUcs3tJ3cdkD1QjmxBfGxu1GeAzCqwMF4VNU5gAWLrsb+ eklX7FUSmvrwDFA8gAjA333ThACgSfopeBAyLYyaxluxXa1C63awCRaVzLj1TCMpaQ66 m1U+3d5KYGf1gNg9pXxlAnhtnlp05bm/a+vR8GZokjbdtRalYKt3S2GPZvoD1MJttyX8 kxqvyqpfqkvoids8OvnQWW6RxQ5SoRI4CR1HKUbp9vbTkFzKFObv2hoX+SmJcHa0RHiK T1X6qJUtplaQcY3MfjmKQoE3OTGHZnKdnRDdH1RiWYT9LhtTqmh9ca915RQRrMjo+r98 I/jQ== X-Gm-Message-State: AFqh2kr2+4tY08yeuImVSHXD79YY3lsH8BlLslo+cZInvicpyUb7ACc1 8ARMZ5EQRbyejyD1AV9w35NmjI50wLXQhKBH X-Google-Smtp-Source: AMrXdXs1XSpJY09O/o7ZgeVFSMs3fHou25EthMRo5FEUfCJ+odrofa6afsa4vK/WlTOoprrBsaagFg== X-Received: by 2002:a17:903:240b:b0:192:8bee:3e29 with SMTP id e11-20020a170903240b00b001928bee3e29mr53786136plo.2.1673228589290; Sun, 08 Jan 2023 17:43:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 22/22] tcg/riscv: Implement direct branch for goto_tb Date: Sun, 8 Jan 2023 17:42:48 -0800 Message-Id: <20230109014248.2894281-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109014248.2894281-1-richard.henderson@linaro.org> References: <20230109014248.2894281-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673229199963100001 Content-Type: text/plain; charset="utf-8" Now that tcg can handle direct and indirect goto_tb simultaneously, we can optimistically leave space for a direct branch and fall back to loading the pointer from the TB for an indirect branch. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/riscv/tcg-target.c.inc | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 82ca86431e..f0b0a98e2c 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1303,7 +1303,11 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t= a0) =20 static void tcg_out_goto_tb(TCGContext *s, int which) { - /* indirect jump method */ + /* Direct branch will be patched by tb_target_set_jmp_target. */ + set_jmp_insn_offset(s, which); + tcg_out32(s, OPC_NOP); + + /* When branch is out of range, fall through to indirect. */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO, get_jmp_target_addr(s, which)); tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0); @@ -1313,7 +1317,18 @@ static void tcg_out_goto_tb(TCGContext *s, int which) void tb_target_set_jmp_target(const TranslationBlock *tb, int n, uintptr_t jmp_rx, uintptr_t jmp_rw) { - /* Always indirect, nothing to do */ + uintptr_t addr =3D tb->jmp_target_addr[n]; + ptrdiff_t offset =3D addr - jmp_rx; + tcg_insn_unit insn; + + /* Either directly branch, or fall through to indirect branch. */ + if (offset =3D=3D sextreg(offset, 0, 20)) { + insn =3D encode_uj(OPC_JAL, TCG_REG_ZERO, offset); + } else { + insn =3D OPC_NOP; + } + qatomic_set((uint32_t *)jmp_rw, insn); + flush_idcache_range(jmp_rx, jmp_rw, 4); } =20 static void tcg_out_op(TCGContext *s, TCGOpcode opc, --=20 2.34.1