From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929271; cv=none; d=zohomail.com; s=zohoarc; b=dS+RxU4xkVz6TmVCR3O+DcOmFJH5j77g89JCxnt8vTDry8yICwU7p0l6CG2uiwSkE2vJEizGkUQNBbcJOjOSvCrNkdATwzwPkiYQu5jOHauZ3/PFww2tnyGpRysdYaBRg9hGsDacNGiczRr+xvWVOHt4IwXwUYho+Itj+rpjNv0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672929271; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5Gf+reKwkE6jXOJI2HiIZEfL9A4187k5o28S5UxntFc=; b=m0AM0eNDpbcthLu+hcWni1R2cXC0vXZvjlrnOZVtQFTent/EcOKYple/Y5MzCtY3/aOzVqZaPRaBsJxAeZXVyAPoZE1oK5WIJfXgIrgkcyXRc7yD2WudfrjBJIRAHkwXLvRTExlFpAwIateUsTGTbaV5Gtlx2AczqQLMPwmmBeU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672929271924898.1454367012462; Thu, 5 Jan 2023 06:34:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDRJF-0002pE-6C; Thu, 05 Jan 2023 09:33:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDRIu-0002ju-UX; Thu, 05 Jan 2023 09:33:26 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDRIs-0006tD-Aq; Thu, 05 Jan 2023 09:33:12 -0500 Received: by mail-wr1-x42d.google.com with SMTP id d17so16572247wrs.2; Thu, 05 Jan 2023 06:33:08 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 01/31] hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition Date: Thu, 5 Jan 2023 15:31:58 +0100 Message-Id: <20230105143228.244965-2-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=shentey@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929365172100001 From: Philippe Mathieu-Daud=C3=A9 The PIIX4 PCI-ISA bridge function is always located at 10:0. Since we want to re-use its address, add the PIIX4_PCI_DEVFN definition. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20221027204720.33611-2-philmd@linaro.org> Reviewed-by: Michael S. Tsirkin --- hw/mips/malta.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index e435f80973..2e175741ff 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -72,6 +72,8 @@ =20 #define FLASH_SIZE 0x400000 =20 +#define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0) + typedef struct { MemoryRegion iomem; MemoryRegion iomem_lo; /* 0 - 0x900 */ @@ -1427,7 +1429,7 @@ void mips_malta_init(MachineState *machine) empty_slot_init("GT64120", 0, 0x20000000); =20 /* Southbridge */ - piix4 =3D pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), t= rue, + piix4 =3D pci_create_simple_multifunction(pci_bus, PIIX4_PCI_DEVFN, tr= ue, TYPE_PIIX4_PCI_DEVICE); isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); =20 --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929250; cv=none; d=zohomail.com; s=zohoarc; b=ZVKpWOzMfWyFIYs87G6lMShMVrHzwWAG1Yf/7fut3LsHfXTqvPG+vNmbS1Ir2NUyUVNqobg/LIjBglgbuijrVAp5Hrc1p8T8BVozvcIuI7dkyCTxL9OyznBcaQ81sZO2zSZ0qgy/AyIEZ1p7X0FHbR8DUZhUKsI9DgjDkzAmB/4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672929250; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ncw5nnPVK/uF8+rX+LoiYH3+/VQ+iJInXM5uQBXVtuY=; b=bNGOdHVIKIXsSWPSQh21gQsJy8NrqI9jl24WXBu48mmfLTQhzpTig/7Bu7VIl/lYU2olQWMLnp8vYVEwLzufZvLLfCBR4qXU1Ps0lHDF6lpiKeQb71B1ZpYKlBrFnOtcDHKpKJoeD0Whxdf39LVAsGLWx8WT++yaRGPvLyezxGM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672929250716812.3638123390036; Thu, 5 Jan 2023 06:34:10 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDRJF-0002pp-TG; Thu, 05 Jan 2023 09:33:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDRJ8-0002kk-Ht; Thu, 05 Jan 2023 09:33:26 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDRIs-0006tS-ED; Thu, 05 Jan 2023 09:33:13 -0500 Received: by mail-wr1-x434.google.com with SMTP id co23so36341866wrb.4; Thu, 05 Jan 2023 06:33:09 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id bt15-20020a056000080f00b00297dcfdc90fsm12260447wrb.24.2023.01.05.06.33.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 06:33:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ncw5nnPVK/uF8+rX+LoiYH3+/VQ+iJInXM5uQBXVtuY=; b=RNX1JKz3q/4t+luafx4cuFcZmg3YaPBe4lkGOzfk2MTTFF+n7wO6FfDCKj31vmJQEn OtYa4o8cmx4j278C6ezrlYrxfSXRzVXFpM4Lrtt8jJO8FVstG/GauXDNUqobSYUVuriL FUYOpM5qvx0sKlnspEaJLlmGborKqwic0yeub4U65imMCanSMQnOrPh04+D/P22QEqb8 OODSZJCQtSLi9MJMKYNUN3tBXsN1klyjQ9NRDT/hAl96A/M4RXhh8iYhmY5QcimzXRXA mdGZzBll+wQ25grgMx9XRN9YfmefGDW1q3kvmOxWBYZZ2m13QXF3oPv7NPo/K8+FE2zz PMwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ncw5nnPVK/uF8+rX+LoiYH3+/VQ+iJInXM5uQBXVtuY=; b=NQiXYFfBnbxOKDmNQmLUuf2IABKobVwOk/9SiLmPZ1MUYsKyCZ+eProURGu/eUIMcJ DiMBs3qAylEsp+M6wP9xkUuQ3ULtwomGeg07GdsSu8DMITyh5nr/9Hyz4YqGKPNRXmi1 cvshnGNSaGMULcnvmVh4CmzwjVAqzmV1VWwFYgOeiUg2vZQYlFBvxTJ5PSEsyOVAXPnl 97h7HMuafs7YifJzIM1XXpaZ82V1bBa124SAU3aBdgrSECC1AMb3b8fb++I3bPzP8rk/ G5FhD8CXK47vUlBg7XszpM03W+4IdhKkQlPMPfmyoaumZMsQRn7YZb/EG1949fYb7k/Q gLPQ== X-Gm-Message-State: AFqh2krwg9SREue4Pzpo9/Bs+paLSBgstKFHoNOWk30TNIOqX+wEm0uO e5PwrQX7U6A06Er+6R9fHZgzbkTH4vwo2A== X-Google-Smtp-Source: AMrXdXuPLv690JBT8uxgyB/BFUC53+jyeFKb35Pmq+MQWuV41mzgtbe+ALht/IYcnZdpP6h9fm5dlA== X-Received: by 2002:a05:6000:18a6:b0:280:4a9:c8dd with SMTP id b6-20020a05600018a600b0028004a9c8ddmr40208330wri.18.1672929188361; Thu, 05 Jan 2023 06:33:08 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , qemu-block@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Ani Sinha , Richard Henderson , Jiaxun Yang , Aurelien Jarno , "Michael S. Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 02/31] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader Date: Thu, 5 Jan 2023 15:31:59 +0100 Message-Id: <20230105143228.244965-3-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=shentey@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929326985100001 From: Philippe Mathieu-Daud=C3=A9 Linux kernel expects the northbridge & southbridge chipsets configured by the BIOS firmware. We emulate that by writing a tiny bootloader code in write_bootloader(). Upon introduction in commit 5c2b87e34d ("PIIX4 support"), the PIIX4 configuration space included values specific to the Malta board. Set the Malta-specific IRQ routing values in the embedded bootloader, so the next commit can remove the Malta specific bits from the PIIX4 PCI-ISA bridge and make it generic (matching the real hardware). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20221027204720.33611-3-philmd@linaro.org> Reviewed-by: Michael S. Tsirkin --- hw/mips/malta.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 2e175741ff..ef3e10dc4d 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -804,6 +804,8 @@ static void write_bootloader_nanomips(uint8_t *base, ui= nt64_t run_addr, stw_p(p++, 0x8422); stw_p(p++, 0x9088); /* sw t0, 0x88(t1) */ =20 + /* TODO set PIIX IRQC[A:D] routing values! */ + stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); =20 stw_p(p++, NM_HI2(kernel_entry)); @@ -841,6 +843,9 @@ static void write_bootloader_nanomips(uint8_t *base, ui= nt64_t run_addr, static void write_bootloader(uint8_t *base, uint64_t run_addr, uint64_t kernel_entry) { + const char pci_pins_cfg[PCI_NUM_PINS] =3D { + 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ + }; uint32_t *p; =20 /* Small bootloader */ @@ -915,6 +920,20 @@ static void write_bootloader(uint8_t *base, uint64_t r= un_addr, =20 #undef cpu_to_gt32 =20 + /* + * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0. + * Load the PIIX IRQC[A:D] routing config address, then + * write routing configuration to the config data register. + */ + bl_gen_write_u32(&p, /* GT_PCI0_CFGADDR */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), + tswap32((1 << 31) /* ConfigEn */ + | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 + | PIIX_PIRQCA)); + bl_gen_write_u32(&p, /* GT_PCI0_CFGDATA */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), + tswap32(ldl_be_p(pci_pins_cfg))); + bl_gen_jump_kernel(&p, true, ENVP_VADDR - 64, /* --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929926; cv=none; d=zohomail.com; s=zohoarc; b=DcFCzKe5Vcgpa3YW5g1FFU8inEchqtgy6il77rv5f64ltVhAJAioz+2Stsp2rJeDz8vX+j35jyX3eQw1l0R37uVgGgYOmEOhtsrtKt8BIAkvkUBoyr1GPwZmbyYt2FZpsO08b6uJnmg641KZDxHzEJSFtiVBVLFYTzSKV7remZ0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672929926; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YHtHVYo4NVUXU56/alQ0bH+UtHEiwYpVK/P9pel6Axs=; b=PUApO6t8EYo/FgpwspwmxDBt91cgnI3WTxfdt6Ly1OOGq6ZZiOM3pX2302tmFu4O24y0LlamK8U8fLAs0TJ6P8CZ0upAd/YGHKD/ezM7WEVEBRaWJCRi4vO5ViPbreCKI1A9vgRb4uM1Li8GHzTVUJ9lGolQxQQT7mMu5yfs7Fk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672929926740879.7454697916863; Thu, 5 Jan 2023 06:45:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDRJG-0002q8-KA; Thu, 05 Jan 2023 09:33:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDRJ8-0002kh-Gf; Thu, 05 Jan 2023 09:33:26 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDRIt-0006tZ-QQ; Thu, 05 Jan 2023 09:33:13 -0500 Received: by mail-wr1-x42a.google.com with SMTP id s9so4301256wru.13; Thu, 05 Jan 2023 06:33:11 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 03/31] hw/isa/piix4: Correct IRQRC[A:D] reset values Date: Thu, 5 Jan 2023 15:32:00 +0100 Message-Id: <20230105143228.244965-4-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=shentey@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929927988100003 From: Philippe Mathieu-Daud=C3=A9 IRQRC[A:D] registers reset value is 0x80. We were forcing the MIPS Malta machine routing to be able to boot a Linux kernel without any bootloader. We now have these registers initialized in the Malta machine write_bootloader(), so we can use the correct reset values. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20221027204720.33611-4-philmd@linaro.org> Reviewed-by: Michael S. Tsirkin --- hw/isa/piix4.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index eca96fb8f0..6e9434129d 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -91,10 +91,10 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0x4c] =3D 0x4d; pci_conf[0x4e] =3D 0x03; pci_conf[0x4f] =3D 0x00; - pci_conf[0x60] =3D 0x0a; // PCI A -> IRQ 10 - pci_conf[0x61] =3D 0x0a; // PCI B -> IRQ 10 - pci_conf[0x62] =3D 0x0b; // PCI C -> IRQ 11 - pci_conf[0x63] =3D 0x0b; // PCI D -> IRQ 11 + pci_conf[0x60] =3D 0x80; + pci_conf[0x61] =3D 0x80; + pci_conf[0x62] =3D 0x80; + pci_conf[0x63] =3D 0x80; pci_conf[0x69] =3D 0x02; pci_conf[0x70] =3D 0x80; pci_conf[0x76] =3D 0x0c; --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929301; cv=none; d=zohomail.com; s=zohoarc; b=bMor2LzsacZ5r/4DiQSWWEmWS57je9eJbrhZnkfCsyyLlwAkj1wSdo2mP+7Ru/B2MTLMOAPjR+tbq53PDzpZtqdeJrZgF4Xkd52Nggj5wbamupLqrh8Qty7lBtI6ndgr9r+h3LibWvbpdyToVgbixyHHwm8Ob9dzEp6iPLGZQ7Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672929301; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0n/SCpv5aiBm+X16I26hh3ltLrnYFlTaexw96i1C/dI=; b=Y2n6Rqt5j1Svksjbos+XaeGlreLfZUexceOlvVCO0tfCNJUpXSYZSC+nAGE2irC3eC5bizfc691HNNmKzjqSmYfflPxw9kBTmybfeKZKSLikzkVGOUKEUNb4abVxXzrznJK7/tofJKMdBoDZOYjpE7JhM0XXqMyYPcnt+YY76uY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672929301823144.95135636391365; Thu, 5 Jan 2023 06:35:01 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDRJF-0002pt-V0; Thu, 05 Jan 2023 09:33:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDRJ8-0002ki-Hr; Thu, 05 Jan 2023 09:33:26 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDRIu-0006tk-1M; Thu, 05 Jan 2023 09:33:13 -0500 Received: by mail-wr1-x42d.google.com with SMTP id r2so1493199wrv.7; Thu, 05 Jan 2023 06:33:11 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id bt15-20020a056000080f00b00297dcfdc90fsm12260447wrb.24.2023.01.05.06.33.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 06:33:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0n/SCpv5aiBm+X16I26hh3ltLrnYFlTaexw96i1C/dI=; b=Sg54jycdG9d4dHVSOGE3L3NgT2pGvcQIjqy5XJ7GjXZgFig0GYpvuN5XyoqfYtiBna 93F0Noa+lqoOPVzPWHdXDm2Yp18o6XE0QdFLboxbyySCgDtxalpjczRHVWQUSPeu4XpG 3pjL5KdH80bjRqm1l6h7z4D0XW7RC8eI5myb/YsX6YRFHXMEWjoVNhJrlFNQznKJ0FSY 3PXSYggcl9w7rtmLl0T5bQVPoOllp4v7Rk3xcr1OviLHq40Ft+X7GEqp/WlCOz1VwsJ1 nYjDV4L1Q+cvvuzgeNbukeEbNcSXYXc5JH69Gjha5YBVCTBKm/1WrC2JfrkjmBVdeEIS mb7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0n/SCpv5aiBm+X16I26hh3ltLrnYFlTaexw96i1C/dI=; b=37cE1KfMwQYHkhmfnDdHeaMu73o/MGw4msmvYftxok0K8fT8Yk9yIvt2bnkjqa17Ab nilxvOjUs8OHuGST5I7CbI6PybqXf4UuAWoxeZ+hzOAo5upwEVKXFaA2AKmTRG0EC8IW YTl54qbemvE9hxhLANet5/vkpEKc5Tv+BLt4fzocwOnFjPwHsQLtX8YNNEydNAWchqpp uZ5jKMBmu8Wv7jS5HeZ7Rczf837masvXVElTglaauU2mS34uo+0h1IOvXYNmbQjHZMjz CMv6zhFOaCCz3qK0bdABGIEwqAe0KS60kEgA4+IdWPTuHuSxJuJABHKfGZ8IFxTryImA QJoQ== X-Gm-Message-State: AFqh2krZJXtmCiYhvgQOSH+JdwD+W2mks2abTvKEQl0FEq5xpX4fM5K9 rYVgkcApzUztVtHn3AZffI4Q4WyetSL/Ow== X-Google-Smtp-Source: AMrXdXtuO1JLTiJ1KXMgjtMV3qTQXthYD0Dpx7do4CaA5bl5cXNuUa3b8t5paV5uRGni0RgSyURSoQ== X-Received: by 2002:a5d:51c7:0:b0:29d:7fe4:b70e with SMTP id n7-20020a5d51c7000000b0029d7fe4b70emr6667961wrv.7.1672929190301; Thu, 05 Jan 2023 06:33:10 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , qemu-block@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Ani Sinha , Richard Henderson , Jiaxun Yang , Aurelien Jarno , "Michael S. Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 04/31] hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig Date: Thu, 5 Jan 2023 15:32:01 +0100 Message-Id: <20230105143228.244965-5-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=shentey@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929371838100005 Tracking dependencies via Kconfig seems much cleaner. Note that PIIX4 already depends on ACPI_PIIX4. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Michael S. Tsirkin --- configs/devices/mips-softmmu/common.mak | 2 -- hw/mips/Kconfig | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/configs/devices/mips-softmmu/common.mak b/configs/devices/mips= -softmmu/common.mak index 416161f833..7813fd1b41 100644 --- a/configs/devices/mips-softmmu/common.mak +++ b/configs/devices/mips-softmmu/common.mak @@ -18,10 +18,8 @@ CONFIG_PCSPK=3Dy CONFIG_PCKBD=3Dy CONFIG_FDC=3Dy CONFIG_ACPI=3Dy -CONFIG_ACPI_PIIX4=3Dy CONFIG_APM=3Dy CONFIG_I8257=3Dy -CONFIG_PIIX4=3Dy CONFIG_IDE_ISA=3Dy CONFIG_PFLASH_CFI01=3Dy CONFIG_I8259=3Dy diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index 725525358d..4e7042f03d 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -1,6 +1,7 @@ config MALTA bool select ISA_SUPERIO + select PIIX4 =20 config MIPSSIM bool --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929867; cv=none; d=zohomail.com; s=zohoarc; b=Xlq58zmsQwBmnQSLL6X7zThEA8yDeYHYT9xQNY10HF/YVxBtF3+9FR+aLjHojk5551CO1s3vMwXHoqXLq2DSADYvJA37/4B2SoYdRC90CElTvYEq0t2xWqYuERgfOqf19yb96WDibGe0o1owQQq4pxzxUsgW5Rn44ideEw6+uIY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672929867; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hHk6ePf0VRd2q38GwoD9GjFLpVvV6YZeT24HsIu9nQs=; b=Sp/3qbOTgzS5id9nvo8HGdBy0W/X6RccUlpCD1PkZ8DrLrstau95Zj5Oi5TNLwUkYqlt8hLyk/NpuyK4XiMNe9qcYuvePHouI368SJiOCSNpC+kIUdRSY4s5o1TzMK3OMpjfSBUakBy3OXbC1/BV+NPSB9iCH4WDjZJN3ZVyg/8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672929867580911.8435501324971; Thu, 5 Jan 2023 06:44:27 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDRJG-0002q9-Kv; Thu, 05 Jan 2023 09:33:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDRJ8-0002kn-Hl; Thu, 05 Jan 2023 09:33:26 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDRIw-0006u3-Iu; Thu, 05 Jan 2023 09:33:17 -0500 Received: by mail-wr1-x42d.google.com with SMTP id m7so1872171wrn.10; Thu, 05 Jan 2023 06:33:12 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow , Mark Cave-Ayland Subject: [PATCH v5 05/31] hw/usb/hcd-uhci: Introduce TYPE_ defines for device models Date: Thu, 5 Jan 2023 15:32:02 +0100 Message-Id: <20230105143228.244965-6-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=shentey@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929869798100003 Suggested-by: Mark Cave-Ayland Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-10-shentey@gmail.com> --- hw/usb/hcd-uhci.h | 4 ++++ hw/i386/pc_piix.c | 3 ++- hw/i386/pc_q35.c | 13 +++++++------ hw/isa/piix4.c | 2 +- hw/usb/hcd-uhci.c | 16 ++++++++-------- 5 files changed, 22 insertions(+), 16 deletions(-) diff --git a/hw/usb/hcd-uhci.h b/hw/usb/hcd-uhci.h index c85ab7868e..83e6f548b1 100644 --- a/hw/usb/hcd-uhci.h +++ b/hw/usb/hcd-uhci.h @@ -91,4 +91,8 @@ typedef struct UHCIInfo { void uhci_data_class_init(ObjectClass *klass, void *data); void usb_uhci_common_realize(PCIDevice *dev, Error **errp); =20 +#define TYPE_PIIX3_USB_UHCI "piix3-usb-uhci" +#define TYPE_PIIX4_USB_UHCI "piix4-usb-uhci" +#define TYPE_ICH9_USB_UHCI(fn) "ich9-usb-uhci" #fn + #endif diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index c743122c52..edc0ac8cf1 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -51,6 +51,7 @@ #include "exec/memory.h" #include "hw/acpi/acpi.h" #include "hw/acpi/piix4.h" +#include "hw/usb/hcd-uhci.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/xen.h" @@ -306,7 +307,7 @@ static void pc_init1(MachineState *machine, #endif =20 if (pcmc->pci_enabled && machine_usb(machine)) { - pci_create_simple(pci_bus, piix3_devfn + 2, "piix3-usb-uhci"); + pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI); } =20 if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms)= )) { diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 65ea226211..83c57c6eb1 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -48,6 +48,7 @@ #include "hw/ide/pci.h" #include "hw/ide/ahci.h" #include "hw/usb.h" +#include "hw/usb/hcd-uhci.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/numa.h" @@ -65,15 +66,15 @@ struct ehci_companions { }; =20 static const struct ehci_companions ich9_1d[] =3D { - { .name =3D "ich9-usb-uhci1", .func =3D 0, .port =3D 0 }, - { .name =3D "ich9-usb-uhci2", .func =3D 1, .port =3D 2 }, - { .name =3D "ich9-usb-uhci3", .func =3D 2, .port =3D 4 }, + { .name =3D TYPE_ICH9_USB_UHCI(1), .func =3D 0, .port =3D 0 }, + { .name =3D TYPE_ICH9_USB_UHCI(2), .func =3D 1, .port =3D 2 }, + { .name =3D TYPE_ICH9_USB_UHCI(3), .func =3D 2, .port =3D 4 }, }; =20 static const struct ehci_companions ich9_1a[] =3D { - { .name =3D "ich9-usb-uhci4", .func =3D 0, .port =3D 0 }, - { .name =3D "ich9-usb-uhci5", .func =3D 1, .port =3D 2 }, - { .name =3D "ich9-usb-uhci6", .func =3D 2, .port =3D 4 }, + { .name =3D TYPE_ICH9_USB_UHCI(4), .func =3D 0, .port =3D 0 }, + { .name =3D TYPE_ICH9_USB_UHCI(5), .func =3D 1, .port =3D 2 }, + { .name =3D TYPE_ICH9_USB_UHCI(6), .func =3D 2, .port =3D 4 }, }; =20 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 6e9434129d..de60ceef73 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -255,7 +255,7 @@ static void piix4_init(Object *obj) =20 object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); - object_initialize_child(obj, "uhci", &s->uhci, "piix4-usb-uhci"); + object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI); =20 object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM); qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", 0x1100); diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c index d1b5657d72..30ae0104bb 100644 --- a/hw/usb/hcd-uhci.c +++ b/hw/usb/hcd-uhci.c @@ -1292,56 +1292,56 @@ void uhci_data_class_init(ObjectClass *klass, void = *data) =20 static UHCIInfo uhci_info[] =3D { { - .name =3D "piix3-usb-uhci", + .name =3D TYPE_PIIX3_USB_UHCI, .vendor_id =3D PCI_VENDOR_ID_INTEL, .device_id =3D PCI_DEVICE_ID_INTEL_82371SB_2, .revision =3D 0x01, .irq_pin =3D 3, .unplug =3D true, },{ - .name =3D "piix4-usb-uhci", + .name =3D TYPE_PIIX4_USB_UHCI, .vendor_id =3D PCI_VENDOR_ID_INTEL, .device_id =3D PCI_DEVICE_ID_INTEL_82371AB_2, .revision =3D 0x01, .irq_pin =3D 3, .unplug =3D true, },{ - .name =3D "ich9-usb-uhci1", /* 00:1d.0 */ + .name =3D TYPE_ICH9_USB_UHCI(1), /* 00:1d.0 */ .vendor_id =3D PCI_VENDOR_ID_INTEL, .device_id =3D PCI_DEVICE_ID_INTEL_82801I_UHCI1, .revision =3D 0x03, .irq_pin =3D 0, .unplug =3D false, },{ - .name =3D "ich9-usb-uhci2", /* 00:1d.1 */ + .name =3D TYPE_ICH9_USB_UHCI(2), /* 00:1d.1 */ .vendor_id =3D PCI_VENDOR_ID_INTEL, .device_id =3D PCI_DEVICE_ID_INTEL_82801I_UHCI2, .revision =3D 0x03, .irq_pin =3D 1, .unplug =3D false, },{ - .name =3D "ich9-usb-uhci3", /* 00:1d.2 */ + .name =3D TYPE_ICH9_USB_UHCI(3), /* 00:1d.2 */ .vendor_id =3D PCI_VENDOR_ID_INTEL, .device_id =3D PCI_DEVICE_ID_INTEL_82801I_UHCI3, .revision =3D 0x03, .irq_pin =3D 2, .unplug =3D false, },{ - .name =3D "ich9-usb-uhci4", /* 00:1a.0 */ + .name =3D TYPE_ICH9_USB_UHCI(4), /* 00:1a.0 */ .vendor_id =3D PCI_VENDOR_ID_INTEL, .device_id =3D PCI_DEVICE_ID_INTEL_82801I_UHCI4, .revision =3D 0x03, .irq_pin =3D 0, .unplug =3D false, },{ - .name =3D "ich9-usb-uhci5", /* 00:1a.1 */ + .name =3D TYPE_ICH9_USB_UHCI(5), /* 00:1a.1 */ .vendor_id =3D PCI_VENDOR_ID_INTEL, .device_id =3D PCI_DEVICE_ID_INTEL_82801I_UHCI5, .revision =3D 0x03, .irq_pin =3D 1, .unplug =3D false, },{ - .name =3D "ich9-usb-uhci6", /* 00:1a.2 */ + .name =3D TYPE_ICH9_USB_UHCI(6), /* 00:1a.2 */ .vendor_id =3D PCI_VENDOR_ID_INTEL, .device_id =3D PCI_DEVICE_ID_INTEL_82801I_UHCI6, .revision =3D 0x03, --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 06/31] hw/i386/pc_piix: Associate pci_map_irq_fn as soon as PCI bus is created Date: Thu, 5 Jan 2023 15:32:03 +0100 Message-Id: <20230105143228.244965-7-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=shentey@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929703858100002 Content-Type: text/plain; charset="utf-8" Observe that the pci_map_irq_fn's don't depend on the south bridge instance. So associate them immediately when the PCI bus is created to keep things logically together. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin --- hw/i386/pc_piix.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index edc0ac8cf1..d1f7d95936 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -229,6 +229,9 @@ static void pc_init1(MachineState *machine, x86ms->below_4g_mem_size, x86ms->above_4g_mem_size, pci_memory, ram_memory); + pci_bus_map_irqs(pci_bus, + xen_enabled() ? xen_pci_slot_get_pirq + : pci_slot_get_pirq); pcms->bus =3D pci_bus; =20 pci_dev =3D pci_create_simple_multifunction(pci_bus, -1, true, typ= e); @@ -236,10 +239,6 @@ static void pc_init1(MachineState *machine, piix3->pic =3D x86ms->gsi; piix3_devfn =3D piix3->dev.devfn; isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); - - pci_bus_map_irqs(pci_bus, - xen_enabled() ? xen_pci_slot_get_pirq - : pci_slot_get_pirq); } else { pci_bus =3D NULL; isa_bus =3D isa_bus_new(NULL, get_system_memory(), system_io, --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929949; cv=none; d=zohomail.com; s=zohoarc; b=hGAk/O4oq1rsYdNxt7MCbuoXpCJQDT6WuRD5UxU+Fye+oFu8PkyqqPCg7kPiHHATVfEqMP2xKZ+QPWQWjvxBWGxh7m+FOdAL+7mZfHnVC/7gwFEfhX0oht4W1aOs21MPymVfG5s7gvlr4wuVxUMk13pUsLRrnVb431GYlyevU+A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672929949; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YpTLCQQN9sJV5BZKqwLD7eLW09/Kk5l3kKtc6B53Yig=; b=iUrDRArAFz0hBuQgb5yzqFY4kxSGfnOaoNGtQfWvPosbNNvijXyRVnxDTpToPMD1sVIdnLAmk/ru+oI/Ger7IgdrIzGutNz4ol9R+Py0Donsa2OaUZbsbbGOXh9sRZd+4wCbiR/7Nbas/Q0Biu63cFfeCR1rH9/DLFkfLPDsqG0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672929949262672.6977729765531; Thu, 5 Jan 2023 06:45:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDRJO-000300-QX; Thu, 05 Jan 2023 09:33:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDRJ8-0002ko-HK; Thu, 05 Jan 2023 09:33:26 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDRIy-0006um-9H; Thu, 05 Jan 2023 09:33:17 -0500 Received: by mail-wr1-x430.google.com with SMTP id h16so36265542wrz.12; Thu, 05 Jan 2023 06:33:15 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow , Peter Maydell Subject: [PATCH v5 07/31] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge Date: Thu, 5 Jan 2023 15:32:04 +0100 Message-Id: <20230105143228.244965-8-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=shentey@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929950174100001 Content-Type: text/plain; charset="utf-8" The next patches will need to take advantage of it. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-3-shentey@gmail.com> --- hw/i386/pc_piix.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index d1f7d95936..f67893cd7c 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -234,7 +234,8 @@ static void pc_init1(MachineState *machine, : pci_slot_get_pirq); pcms->bus =3D pci_bus; =20 - pci_dev =3D pci_create_simple_multifunction(pci_bus, -1, true, typ= e); + pci_dev =3D pci_new_multifunction(-1, true, type); + pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); piix3 =3D PIIX3_PCI_DEVICE(pci_dev); piix3->pic =3D x86ms->gsi; piix3_devfn =3D piix3->dev.devfn; --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929685; cv=none; d=zohomail.com; s=zohoarc; b=VVruZbDU5/Qdab7TBOIeW45eZCCPtm2+VxPqBrp/5ah7ozIBZAS1lKKHOSzqAImLxrfqQuUoKdcA/2SfFq1yAiIB3IbLQ+NEBE7cHJ1N+Qd4ELYtvwOrQ0qDzC6gVlrw71gFpfnEZ2bdsEZ2OZY0SRbBMOcYrk6F08Lduu2Su7Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672929685; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hlJ2V1dMc5xPbrEFwOcXQd68GOIsjh9O4fMLI+RJdrM=; b=eweBCdRMCYD9ngCZ26CZjGv1JZoZYQpTk8fCRtqb65MJWOrRoWmETVVYbdV04eKiRN8aYzkkFS8EX/DIXF/jW661gUQlv3Sxy6fZa1XZyiSZTVcKRKQ504VuWZXa9o1U4wRopPPGfgEiP3NddarWKEFmBjJr4ngAqQurj111jJY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672929685818747.4497859314461; Thu, 5 Jan 2023 06:41:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDRJH-0002r6-8S; Thu, 05 Jan 2023 09:33:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDRJ8-0002ks-Hp; Thu, 05 Jan 2023 09:33:26 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDRIz-0006vC-0J; Thu, 05 Jan 2023 09:33:19 -0500 Received: by mail-wr1-x42b.google.com with SMTP id w1so24197736wrt.8; Thu, 05 Jan 2023 06:33:16 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow , Thomas Huth Subject: [PATCH v5 08/31] hw/i386/pc: Create RTC controllers in south bridges Date: Thu, 5 Jan 2023 15:32:05 +0100 Message-Id: <20230105143228.244965-9-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=shentey@gmail.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929687785100003 Content-Type: text/plain; charset="utf-8" Just like in the real hardware (and in PIIX4), create the RTC controllers in the south bridges. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Reviewed-by: Thomas Huth Message-Id: <20221022150508.26830-11-shentey@gmail.com> --- include/hw/i386/ich9.h | 2 ++ include/hw/southbridge/piix.h | 3 +++ hw/i386/pc.c | 12 +++++++++++- hw/i386/pc_piix.c | 8 ++++++++ hw/i386/pc_q35.c | 1 + hw/isa/lpc_ich9.c | 8 ++++++++ hw/isa/piix3.c | 15 +++++++++++++++ hw/isa/Kconfig | 2 ++ 8 files changed, 50 insertions(+), 1 deletion(-) diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index 23ee8e371b..672efc6bce 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -11,6 +11,7 @@ #include "hw/acpi/acpi.h" #include "hw/acpi/ich9.h" #include "hw/pci/pci_bus.h" +#include "hw/rtc/mc146818rtc.h" #include "qom/object.h" =20 void ich9_lpc_set_irq(void *opaque, int irq_num, int level); @@ -39,6 +40,7 @@ struct ICH9LPCState { */ uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; =20 + RTCState rtc; APMState apm; ICH9LPCPMRegs pm; uint32_t sci_level; /* track sci level */ diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 2693778b23..b1fa08dd2b 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -14,6 +14,7 @@ =20 #include "hw/pci/pci.h" #include "qom/object.h" +#include "hw/rtc/mc146818rtc.h" =20 /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 @@ -52,6 +53,8 @@ struct PIIXState { /* This member isn't used. Just for save/load compatibility */ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; =20 + RTCState rtc; + /* Reset Control Register contents */ uint8_t rcr; =20 diff --git a/hw/i386/pc.c b/hw/i386/pc.c index d489ecc0d1..448557333b 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1304,7 +1304,17 @@ void pc_basic_device_init(struct PCMachineState *pcm= s, pit_alt_irq =3D qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); rtc_irq =3D qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); } - *rtc_state =3D mc146818_rtc_init(isa_bus, 2000, rtc_irq); + + if (rtc_irq) { + qdev_connect_gpio_out(DEVICE(*rtc_state), 0, rtc_irq); + } else { + uint32_t irq =3D object_property_get_uint(OBJECT(*rtc_state), + "irq", + &error_fatal); + isa_connect_gpio_out(*rtc_state, 0, irq); + } + object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(*rtc_state), + "date"); =20 qemu_register_boot_set(pc_boot_set, *rtc_state); =20 diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index f67893cd7c..6bd8e70730 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -32,6 +32,7 @@ #include "hw/i386/pc.h" #include "hw/i386/apic.h" #include "hw/pci-host/i440fx.h" +#include "hw/rtc/mc146818rtc.h" #include "hw/southbridge/piix.h" #include "hw/display/ramfb.h" #include "hw/firmware/smbios.h" @@ -240,10 +241,17 @@ static void pc_init1(MachineState *machine, piix3->pic =3D x86ms->gsi; piix3_devfn =3D piix3->dev.devfn; isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); + rtc_state =3D ISA_DEVICE(object_resolve_path_component(OBJECT(pci_= dev), + "rtc")); } else { pci_bus =3D NULL; isa_bus =3D isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); + + rtc_state =3D isa_new(TYPE_MC146818_RTC); + qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000); + isa_realize_and_unref(rtc_state, isa_bus, &error_fatal); + i8257_dma_init(isa_bus, 0); pcms->hpet_enabled =3D false; } diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 83c57c6eb1..da97df69f7 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -239,6 +239,7 @@ static void pc_q35_init(MachineState *machine) lpc =3D pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_D= EV, ICH9_LPC_FUNC), true, TYPE_ICH9_LPC_DEVICE); + rtc_state =3D ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "r= tc")); =20 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, TYPE_HOTPLUG_HANDLER, diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 8d541e2b54..498175c1cc 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -663,6 +663,8 @@ static void ich9_lpc_initfn(Object *obj) static const uint8_t acpi_enable_cmd =3D ICH9_APM_ACPI_ENABLE; static const uint8_t acpi_disable_cmd =3D ICH9_APM_ACPI_DISABLE; =20 + object_initialize_child(obj, "rtc", &lpc->rtc, TYPE_MC146818_RTC); + object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT, &lpc->sci_gsi, OBJ_PROP_FLAG_READ); object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CM= D, @@ -728,6 +730,12 @@ static void ich9_lpc_realize(PCIDevice *d, Error **err= p) isa_bus_irqs(isa_bus, lpc->gsi); =20 i8257_dma_init(isa_bus, 0); + + /* RTC */ + qdev_prop_set_int32(DEVICE(&lpc->rtc), "base_year", 2000); + if (!qdev_realize(DEVICE(&lpc->rtc), BUS(isa_bus), errp)) { + return; + } } =20 static bool ich9_rst_cnt_needed(void *opaque) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 283b971ec4..e8ddb6a602 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -28,6 +28,7 @@ #include "hw/dma/i8257.h" #include "hw/southbridge/piix.h" #include "hw/irq.h" +#include "hw/qdev-properties.h" #include "hw/isa/isa.h" #include "hw/xen/xen.h" #include "sysemu/runstate.h" @@ -301,6 +302,12 @@ static void pci_piix3_realize(PCIDevice *dev, Error **= errp) PIIX_RCR_IOPORT, &d->rcr_mem, 1); =20 i8257_dma_init(isa_bus, 0); + + /* RTC */ + qdev_prop_set_int32(DEVICE(&d->rtc), "base_year", 2000); + if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) { + return; + } } =20 static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -327,6 +334,13 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml = *scope) } } =20 +static void pci_piix3_init(Object *obj) +{ + PIIX3State *d =3D PIIX3_PCI_DEVICE(obj); + + object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); +} + static void pci_piix3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -353,6 +367,7 @@ static const TypeInfo piix3_pci_type_info =3D { .name =3D TYPE_PIIX3_PCI_DEVICE, .parent =3D TYPE_PCI_DEVICE, .instance_size =3D sizeof(PIIX3State), + .instance_init =3D pci_piix3_init, .abstract =3D true, .class_init =3D pci_piix3_class_init, .interfaces =3D (InterfaceInfo[]) { diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 18b5c6bf3f..af5ec9cd61 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -35,6 +35,7 @@ config PIIX3 bool select I8257 select ISA_BUS + select MC146818RTC =20 config PIIX4 bool @@ -79,3 +80,4 @@ config LPC_ICH9 select ISA_BUS select ACPI_SMBUS select ACPI_X86_ICH + select MC146818RTC --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow , Peter Maydell , Thomas Huth Subject: [PATCH v5 09/31] hw/i386/pc: No need for rtc_state to be an out-parameter Date: Thu, 5 Jan 2023 15:32:06 +0100 Message-Id: <20230105143228.244965-10-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=shentey@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929936214100001 Now that the RTC is created as part of the southbridges it doesn't need to be an out-parameter any longer. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell Reviewed-by: Michael S. Tsirkin Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20221022150508.26830-12-shentey@gmail.com> --- include/hw/i386/pc.h | 2 +- hw/i386/pc.c | 12 ++++++------ hw/i386/pc_piix.c | 2 +- hw/i386/pc_q35.c | 2 +- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 991f905f5d..dd059e8667 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -169,7 +169,7 @@ uint64_t pc_pci_hole64_start(void); DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); void pc_basic_device_init(struct PCMachineState *pcms, ISABus *isa_bus, qemu_irq *gsi, - ISADevice **rtc_state, + ISADevice *rtc_state, bool create_fdctrl, uint32_t hpet_irqs); void pc_cmos_init(PCMachineState *pcms, diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 448557333b..53a5443e09 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1251,7 +1251,7 @@ static void pc_superio_init(ISABus *isa_bus, bool cre= ate_fdctrl, =20 void pc_basic_device_init(struct PCMachineState *pcms, ISABus *isa_bus, qemu_irq *gsi, - ISADevice **rtc_state, + ISADevice *rtc_state, bool create_fdctrl, uint32_t hpet_irqs) { @@ -1306,17 +1306,17 @@ void pc_basic_device_init(struct PCMachineState *pc= ms, } =20 if (rtc_irq) { - qdev_connect_gpio_out(DEVICE(*rtc_state), 0, rtc_irq); + qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); } else { - uint32_t irq =3D object_property_get_uint(OBJECT(*rtc_state), + uint32_t irq =3D object_property_get_uint(OBJECT(rtc_state), "irq", &error_fatal); - isa_connect_gpio_out(*rtc_state, 0, irq); + isa_connect_gpio_out(rtc_state, 0, irq); } - object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(*rtc_state), + object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), "date"); =20 - qemu_register_boot_set(pc_boot_set, *rtc_state); + qemu_register_boot_set(pc_boot_set, rtc_state); =20 if (!xen_enabled() && (x86ms->pit =3D=3D ON_OFF_AUTO_AUTO || x86ms->pit =3D=3D ON_OFF_AU= TO_ON)) { diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 6bd8e70730..c9d6c3dac3 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -277,7 +277,7 @@ static void pc_init1(MachineState *machine, } =20 /* init basic PC hardware */ - pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, true, + pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, true, 0x4); =20 pc_nic_init(pcmc, isa_bus, pci_bus); diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index da97df69f7..58c51fbd9e 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -293,7 +293,7 @@ static void pc_q35_init(MachineState *machine) } =20 /* init basic PC hardware */ - pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_fl= oppy, + pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, !mc->no_flo= ppy, 0xff0104); =20 /* connect pm stuff to lpc */ --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929263; cv=none; d=zohomail.com; s=zohoarc; b=dYMSpy8OV70SUXLX+5SYclK1H1aGvS4KrnsIMnqL/dSFq21U0R7olIKMsvMSkVHNLnTUz15ayd3K3gHYhcmS4lJ0xb04Z66Y49iB2CzHMXYBEh76bJMFJo7zci+8V5fcYAEMFboS3eTD52uEpAQ4WWULOo4Nn7tVCfaj4tXUAIE= ARC-Message-Signature: i=1; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 10/31] hw/isa/piix3: Create USB controller in host device Date: Thu, 5 Jan 2023 15:32:07 +0100 Message-Id: <20230105143228.244965-11-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=shentey@gmail.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929337471100001 Content-Type: text/plain; charset="utf-8" The USB controller is an integral part of PIIX3 (function 2). So create it as part of the south bridge. Note that the USB function is optional in QEMU. This is why it gets object_initialize_child()'ed in realize rather than in instance_init. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-13-shentey@gmail.com> --- include/hw/southbridge/piix.h | 4 ++++ hw/i386/pc_piix.c | 7 ++----- hw/isa/piix3.c | 17 +++++++++++++++++ hw/isa/Kconfig | 1 + 4 files changed, 24 insertions(+), 5 deletions(-) diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index b1fa08dd2b..5367917182 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" #include "hw/rtc/mc146818rtc.h" +#include "hw/usb/hcd-uhci.h" =20 /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 @@ -54,12 +55,15 @@ struct PIIXState { int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; =20 RTCState rtc; + UHCIState uhci; =20 /* Reset Control Register contents */ uint8_t rcr; =20 /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ MemoryRegion rcr_mem; + + bool has_usb; }; typedef struct PIIXState PIIX3State; =20 diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index c9d6c3dac3..bd21aa7f9d 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -52,7 +52,6 @@ #include "exec/memory.h" #include "hw/acpi/acpi.h" #include "hw/acpi/piix4.h" -#include "hw/usb/hcd-uhci.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/xen.h" @@ -236,6 +235,8 @@ static void pc_init1(MachineState *machine, pcms->bus =3D pci_bus; =20 pci_dev =3D pci_new_multifunction(-1, true, type); + object_property_set_bool(OBJECT(pci_dev), "has-usb", + machine_usb(machine), &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); piix3 =3D PIIX3_PCI_DEVICE(pci_dev); piix3->pic =3D x86ms->gsi; @@ -314,10 +315,6 @@ static void pc_init1(MachineState *machine, } #endif =20 - if (pcmc->pci_enabled && machine_usb(machine)) { - pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI); - } - if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms)= )) { PCIDevice *piix4_pm; =20 diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index e8ddb6a602..45c20dea17 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -288,6 +288,7 @@ static const MemoryRegionOps rcr_ops =3D { static void pci_piix3_realize(PCIDevice *dev, Error **errp) { PIIX3State *d =3D PIIX3_PCI_DEVICE(dev); + PCIBus *pci_bus =3D pci_get_bus(dev); ISABus *isa_bus; =20 isa_bus =3D isa_bus_new(DEVICE(d), pci_address_space(dev), @@ -308,6 +309,16 @@ static void pci_piix3_realize(PCIDevice *dev, Error **= errp) if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) { return; } + + /* USB */ + if (d->has_usb) { + object_initialize_child(OBJECT(dev), "uhci", &d->uhci, + TYPE_PIIX3_USB_UHCI); + qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2); + if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) { + return; + } + } } =20 static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -341,6 +352,11 @@ static void pci_piix3_init(Object *obj) object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); } =20 +static Property pci_piix3_props[] =3D { + DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), + DEFINE_PROP_END_OF_LIST(), +}; + static void pci_piix3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -360,6 +376,7 @@ static void pci_piix3_class_init(ObjectClass *klass, vo= id *data) * pc_piix.c's pc_init1() */ dc->user_creatable =3D false; + device_class_set_props(dc, pci_piix3_props); adevc->build_dev_aml =3D build_pci_isa_aml; } =20 diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index af5ec9cd61..97b8ea7c06 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -36,6 +36,7 @@ config PIIX3 select I8257 select ISA_BUS select MC146818RTC + select USB_UHCI =20 config PIIX4 bool --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 11/31] hw/isa/piix3: Create power management controller in host device Date: Thu, 5 Jan 2023 15:32:08 +0100 Message-Id: <20230105143228.244965-12-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=shentey@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929374694100011 Content-Type: text/plain; charset="utf-8" The power management controller is an integral part of PIIX3 (function 3). So create it as part of the south bridge. Note that the ACPI function is optional in QEMU. This is why it gets object_initialize_child()'ed in realize rather than in instance_init. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-14-shentey@gmail.com> --- include/hw/southbridge/piix.h | 6 ++++++ hw/i386/pc_piix.c | 24 ++++++++++++++---------- hw/isa/piix3.c | 14 ++++++++++++++ hw/isa/Kconfig | 1 + 4 files changed, 35 insertions(+), 10 deletions(-) diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 5367917182..1c291cc954 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -14,6 +14,7 @@ =20 #include "hw/pci/pci.h" #include "qom/object.h" +#include "hw/acpi/piix4.h" #include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" =20 @@ -56,6 +57,9 @@ struct PIIXState { =20 RTCState rtc; UHCIState uhci; + PIIX4PMState pm; + + uint32_t smb_io_base; =20 /* Reset Control Register contents */ uint8_t rcr; @@ -63,7 +67,9 @@ struct PIIXState { /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ MemoryRegion rcr_mem; =20 + bool has_acpi; bool has_usb; + bool smm_enabled; }; typedef struct PIIXState PIIX3State; =20 diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index bd21aa7f9d..eaf252187e 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -46,12 +46,12 @@ #include "sysemu/kvm.h" #include "hw/kvm/clock.h" #include "hw/sysbus.h" +#include "hw/i2c/i2c.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/xen/xen-x86.h" #include "hw/xen/xen.h" #include "exec/memory.h" #include "hw/acpi/acpi.h" -#include "hw/acpi/piix4.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/xen.h" @@ -97,6 +97,7 @@ static void pc_init1(MachineState *machine, MemoryRegion *system_io =3D get_system_io(); PCIBus *pci_bus; ISABus *isa_bus; + Object *piix4_pm; int piix3_devfn =3D -1; qemu_irq smi_irq; GSIState *gsi_state; @@ -237,15 +238,25 @@ static void pc_init1(MachineState *machine, pci_dev =3D pci_new_multifunction(-1, true, type); object_property_set_bool(OBJECT(pci_dev), "has-usb", machine_usb(machine), &error_abort); + object_property_set_bool(OBJECT(pci_dev), "has-acpi", + x86_machine_is_acpi_enabled(x86ms), + &error_abort); + qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100); + object_property_set_bool(OBJECT(pci_dev), "smm-enabled", + x86_machine_is_smm_enabled(x86ms), + &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); + piix3 =3D PIIX3_PCI_DEVICE(pci_dev); piix3->pic =3D x86ms->gsi; piix3_devfn =3D piix3->dev.devfn; isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); rtc_state =3D ISA_DEVICE(object_resolve_path_component(OBJECT(pci_= dev), "rtc")); + piix4_pm =3D object_resolve_path_component(OBJECT(pci_dev), "pm"); } else { pci_bus =3D NULL; + piix4_pm =3D NULL; isa_bus =3D isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); =20 @@ -315,15 +326,8 @@ static void pc_init1(MachineState *machine, } #endif =20 - if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms)= )) { - PCIDevice *piix4_pm; - + if (piix4_pm) { smi_irq =3D qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); - piix4_pm =3D pci_new(piix3_devfn + 3, TYPE_PIIX4_PM); - qdev_prop_set_uint32(DEVICE(piix4_pm), "smb_io_base", 0xb100); - qdev_prop_set_bit(DEVICE(piix4_pm), "smm-enabled", - x86_machine_is_smm_enabled(x86ms)); - pci_realize_and_unref(piix4_pm, pci_bus, &error_fatal); =20 qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]); qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_ir= q); @@ -337,7 +341,7 @@ static void pc_init1(MachineState *machine, object_property_allow_set_link, OBJ_PROP_LINK_STRONG); object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_P= ROP, - OBJECT(piix4_pm), &error_abort); + piix4_pm, &error_abort); } =20 if (machine->nvdimms_state->is_enabled) { diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 45c20dea17..ed7d58bc98 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -319,6 +319,17 @@ static void pci_piix3_realize(PCIDevice *dev, Error **= errp) return; } } + + /* Power Management */ + if (d->has_acpi) { + object_initialize_child(OBJECT(d), "pm", &d->pm, TYPE_PIIX4_PM); + qdev_prop_set_int32(DEVICE(&d->pm), "addr", dev->devfn + 3); + qdev_prop_set_uint32(DEVICE(&d->pm), "smb_io_base", d->smb_io_base= ); + qdev_prop_set_bit(DEVICE(&d->pm), "smm-enabled", d->smm_enabled); + if (!qdev_realize(DEVICE(&d->pm), BUS(pci_bus), errp)) { + return; + } + } } =20 static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -353,7 +364,10 @@ static void pci_piix3_init(Object *obj) } =20 static Property pci_piix3_props[] =3D { + DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), + DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 97b8ea7c06..6c154d88c7 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -33,6 +33,7 @@ config PC87312 =20 config PIIX3 bool + select ACPI_PIIX4 select I8257 select ISA_BUS select MC146818RTC --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 12/31] hw/intc/i8259: Make using the isa_pic singleton more type-safe Date: Thu, 5 Jan 2023 15:32:09 +0100 Message-Id: <20230105143228.244965-13-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=shentey@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929373041100007 Content-Type: text/plain; charset="utf-8" This even spares some casts in hot code paths along the way. Signed-off-by: Bernhard Beschow Reviewed-by: Mark Cave-Ayland Reviewed-by: Michael S. Tsirkin --- Note: The next patch will introduce a class "isa-pic", which is shall not be confused with the isa_pic singleton. --- include/hw/intc/i8259.h | 6 +++--- include/qemu/typedefs.h | 1 + hw/intc/i8259.c | 11 ++++------- 3 files changed, 8 insertions(+), 10 deletions(-) diff --git a/include/hw/intc/i8259.h b/include/hw/intc/i8259.h index e2b1e8c59a..a0e34dd990 100644 --- a/include/hw/intc/i8259.h +++ b/include/hw/intc/i8259.h @@ -3,10 +3,10 @@ =20 /* i8259.c */ =20 -extern DeviceState *isa_pic; +extern PICCommonState *isa_pic; qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq); qemu_irq *kvm_i8259_init(ISABus *bus); -int pic_get_output(DeviceState *d); -int pic_read_irq(DeviceState *d); +int pic_get_output(PICCommonState *s); +int pic_read_irq(PICCommonState *s); =20 #endif diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 688408e048..3d5944d2a4 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -98,6 +98,7 @@ typedef struct PCIExpressDevice PCIExpressDevice; typedef struct PCIExpressHost PCIExpressHost; typedef struct PCIHostDeviceAddress PCIHostDeviceAddress; typedef struct PCIHostState PCIHostState; +typedef struct PICCommonState PICCommonState; typedef struct PostcopyDiscardState PostcopyDiscardState; typedef struct Property Property; typedef struct PropertyInfo PropertyInfo; diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index cc4e21ffec..0261f087b2 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -55,7 +55,7 @@ struct PICClass { #ifdef DEBUG_IRQ_LATENCY static int64_t irq_time[16]; #endif -DeviceState *isa_pic; +PICCommonState *isa_pic; static PICCommonState *slave_pic; =20 /* return the highest priority found in mask (highest =3D smallest @@ -173,9 +173,8 @@ static void pic_intack(PICCommonState *s, int irq) pic_update_irq(s); } =20 -int pic_read_irq(DeviceState *d) +int pic_read_irq(PICCommonState *s) { - PICCommonState *s =3D PIC_COMMON(d); int irq, intno; =20 irq =3D pic_get_irq(s); @@ -354,10 +353,8 @@ static uint64_t pic_ioport_read(void *opaque, hwaddr a= ddr, return ret; } =20 -int pic_get_output(DeviceState *d) +int pic_get_output(PICCommonState *s) { - PICCommonState *s =3D PIC_COMMON(d); - return (pic_get_irq(s) >=3D 0); } =20 @@ -426,7 +423,7 @@ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq) irq_set[i] =3D qdev_get_gpio_in(dev, i); } =20 - isa_pic =3D dev; + isa_pic =3D PIC_COMMON(dev); =20 isadev =3D i8259_init_chip(TYPE_I8259, bus, false); dev =3D DEVICE(isadev); --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929832; cv=none; d=zohomail.com; s=zohoarc; b=UFXe4npJ/01+hPmTlq7G7Q0okNSGfpg3j/x/Aux3/VKJc+syLd8x5dOME05D6u7eTTI15dK99L7JC4wb1HSlvBIhK8IF3Rn6aKNvzqRLyaRZOUQx05ZuF1k93MGnUhjOLjlBqHKtXnFQJVha1xOHzL4puaGdWN9dRqVCUFc1VAc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672929832; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=f/stOBuXzPq61GBvXikiJZFmsdbNLA8hzR8SMDeaVvE=; b=YkVx5g0a+4ry9aQohGWOtu/lTPhAsrdXoeyAYAqk9RYA1PfIChw+QPGPekhf46I7rgjEeAG22BRtDrFAZvQEzKBFsuBXjuzYcXRXeIYI+sBAMSWWIL1ySrxA/l9tOCDRtPabYdDCy+mkgLVllbiUZv38PzJTUhtZx0Gm+r2FGsU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672929832210114.36829429046088; Thu, 5 Jan 2023 06:43:52 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDRJG-0002qX-Sd; Thu, 05 Jan 2023 09:33:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDRJ8-0002kz-Hi; Thu, 05 Jan 2023 09:33:26 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDRJ4-0006xI-FP; Thu, 05 Jan 2023 09:33:23 -0500 Received: by mail-wr1-x432.google.com with SMTP id az7so11916074wrb.5; Thu, 05 Jan 2023 06:33:21 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow , Mark Cave-Ayland Subject: [PATCH v5 13/31] hw/intc/i8259: Introduce i8259 proxy "isa-pic" Date: Thu, 5 Jan 2023 15:32:10 +0100 Message-Id: <20230105143228.244965-14-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=shentey@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929833503100007 Content-Type: text/plain; charset="utf-8" Having an i8259 proxy allows for ISA PICs to be created and wired up in southbridges. This is especially interesting for PIIX3 for two reasons: First, the southbridge doesn't need to care about the virtualization technology used (KVM, TCG, Xen) due to in-IRQs (where devices get attached) and out-IRQs (which will trigger the IRQs of the respective virtualization technology) are separated. Second, since the in-IRQs are populated with fully initialized qemu_irq's, they can already be wired up inside PIIX3. Cc: Mark Cave-Ayland Signed-off-by: Bernhard Beschow Reviewed-by: Mark Cave-Ayland Reviewed-by: Michael S. Tsirkin --- include/hw/intc/i8259.h | 19 +++++++++++++++++++ hw/intc/i8259.c | 27 +++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/include/hw/intc/i8259.h b/include/hw/intc/i8259.h index a0e34dd990..f666f5ee09 100644 --- a/include/hw/intc/i8259.h +++ b/include/hw/intc/i8259.h @@ -1,6 +1,25 @@ #ifndef HW_I8259_H #define HW_I8259_H =20 +#include "qom/object.h" +#include "hw/isa/isa.h" +#include "qemu/typedefs.h" + +#define TYPE_ISA_PIC "isa-pic" +OBJECT_DECLARE_SIMPLE_TYPE(ISAPICState, ISA_PIC) + +/* + * TYPE_ISA_PIC is currently a PIC proxy which allows for interrupt wiring= in + * a virtualization technology agnostic way. It could be turned into a pro= per + * GPIO-based ISA PIC in the future. + */ +struct ISAPICState { + DeviceState parent_obj; + + qemu_irq in_irqs[ISA_NUM_IRQS]; + qemu_irq out_irqs[ISA_NUM_IRQS]; +}; + /* i8259.c */ =20 extern PICCommonState *isa_pic; diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index 0261f087b2..e99d02136d 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -455,9 +455,36 @@ static const TypeInfo i8259_info =3D { .class_size =3D sizeof(PICClass), }; =20 +static void isapic_set_irq(void *opaque, int irq, int level) +{ + ISAPICState *s =3D opaque; + + qemu_set_irq(s->out_irqs[irq], level); +} + +static void isapic_init(Object *obj) +{ + ISAPICState *s =3D ISA_PIC(obj); + + qdev_init_gpio_in(DEVICE(s), isapic_set_irq, ISA_NUM_IRQS); + qdev_init_gpio_out(DEVICE(s), s->out_irqs, ISA_NUM_IRQS); + + for (int i =3D 0; i < ISA_NUM_IRQS; ++i) { + s->in_irqs[i] =3D qdev_get_gpio_in(DEVICE(s), i); + } +} + +static const TypeInfo isapic_info =3D { + .name =3D TYPE_ISA_PIC, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(ISAPICState), + .instance_init =3D isapic_init, +}; + static void pic_register_types(void) { type_register_static(&i8259_info); + type_register_static(&isapic_info); } =20 type_init(pic_register_types) --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929625; cv=none; d=zohomail.com; s=zohoarc; b=oHYfPOcH8cFnG9WdaLqslLoP6drnZVF1xTcPP1qfOK3rfiNAe0+ADMWVzhsutAr8+fGA9CL+LkZ9yyIqCkxOG2NxVzXaq4FYmknTmnd1blRx5LaqF5raxKe6yjMGAwkVU3IfNjDJKClXARnBfm7SZP4+Vzjd6PqaAfInIuK3534= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672929625; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Spss3rYzRpHnKYYLQNIO8kNwJfo2A0bp3WsUMKGw0FY=; b=kEC4KRWm/OgqoOyGzIPrwwSMhgQinMwgs/w1l9Jw3RiHApaeMbPVT/aZvEQqjp45kpvJKyVgAbsdY4H4Y707rP7uvIpPxUTBlrfKD/DIFTPmX1s6bc6S34J+QB6Vvg+1h9M+PQGki/gW1uKWC2IBLX491s2+FtMIYGfKJd97MLg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672929625755993.3916601623012; Thu, 5 Jan 2023 06:40:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDRJM-0002ws-M5; Thu, 05 Jan 2023 09:33:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDRJ8-0002l0-GJ; Thu, 05 Jan 2023 09:33:26 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDRJ4-0006u3-ST; Thu, 05 Jan 2023 09:33:24 -0500 Received: by mail-wr1-x42d.google.com with SMTP id m7so1872619wrn.10; Thu, 05 Jan 2023 06:33:22 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 14/31] hw/isa/piix3: Create ISA PIC in host device Date: Thu, 5 Jan 2023 15:32:11 +0100 Message-Id: <20230105143228.244965-15-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=shentey@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929627675100005 Content-Type: text/plain; charset="utf-8" Use the newly introduced TYPE_ISA_PIC which allows for wiring up devices in the southbridge where the virtualization technology used (KVM, TCG, Xen) is not yet known. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-16-shentey@gmail.com> --- include/hw/southbridge/piix.h | 4 ++-- hw/i386/pc_piix.c | 15 +++++++++------ hw/isa/piix3.c | 10 +++++++++- hw/i386/Kconfig | 1 + hw/isa/Kconfig | 1 + 5 files changed, 22 insertions(+), 9 deletions(-) diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 1c291cc954..7178147b75 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" #include "hw/acpi/piix4.h" +#include "hw/intc/i8259.h" #include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" =20 @@ -50,11 +51,10 @@ struct PIIXState { #endif uint64_t pic_levels; =20 - qemu_irq *pic; - /* This member isn't used. Just for save/load compatibility */ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; =20 + ISAPICState pic; RTCState rtc; UHCIState uhci; PIIX4PMState pm; diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index eaf252187e..f779251e79 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -219,10 +219,11 @@ static void pc_init1(MachineState *machine, gsi_state =3D pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); =20 if (pcmc->pci_enabled) { - PIIX3State *piix3; + DeviceState *dev; PCIDevice *pci_dev; const char *type =3D xen_enabled() ? TYPE_PIIX3_XEN_DEVICE : TYPE_PIIX3_DEVICE; + int i; =20 pci_bus =3D i440fx_init(pci_type, i440fx_host, @@ -247,10 +248,12 @@ static void pc_init1(MachineState *machine, &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); =20 - piix3 =3D PIIX3_PCI_DEVICE(pci_dev); - piix3->pic =3D x86ms->gsi; - piix3_devfn =3D piix3->dev.devfn; - isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); + dev =3D DEVICE(object_resolve_path_component(OBJECT(pci_dev), "pic= ")); + for (i =3D 0; i < ISA_NUM_IRQS; i++) { + qdev_connect_gpio_out(dev, i, x86ms->gsi[i]); + } + piix3_devfn =3D pci_dev->devfn; + isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); rtc_state =3D ISA_DEVICE(object_resolve_path_component(OBJECT(pci_= dev), "rtc")); piix4_pm =3D object_resolve_path_component(OBJECT(pci_dev), "pm"); @@ -259,6 +262,7 @@ static void pc_init1(MachineState *machine, piix4_pm =3D NULL; isa_bus =3D isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); + isa_bus_irqs(isa_bus, x86ms->gsi); =20 rtc_state =3D isa_new(TYPE_MC146818_RTC); qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000); @@ -267,7 +271,6 @@ static void pc_init1(MachineState *machine, i8257_dma_init(isa_bus, 0); pcms->hpet_enabled =3D false; } - isa_bus_irqs(isa_bus, x86ms->gsi); =20 if (x86ms->pic =3D=3D ON_OFF_AUTO_ON || x86ms->pic =3D=3D ON_OFF_AUTO_= AUTO) { pc_i8259_create(isa_bus, gsi_state->i8259_irq); diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index ed7d58bc98..88a6bf28ea 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -39,7 +39,7 @@ =20 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) { - qemu_set_irq(piix3->pic[pic_irq], + qemu_set_irq(piix3->pic.in_irqs[pic_irq], !!(piix3->pic_levels & (((1ULL << PIIX_NUM_PIRQS) - 1) << (pic_irq * PIIX_NUM_PIRQS)))); @@ -297,6 +297,13 @@ static void pci_piix3_realize(PCIDevice *dev, Error **= errp) return; } =20 + /* PIC */ + if (!qdev_realize(DEVICE(&d->pic), NULL, errp)) { + return; + } + + isa_bus_irqs(isa_bus, d->pic.in_irqs); + memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, "piix3-reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), @@ -360,6 +367,7 @@ static void pci_piix3_init(Object *obj) { PIIX3State *d =3D PIIX3_PCI_DEVICE(obj); =20 + object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); } =20 diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index d22ac4a4b9..79f5925dbe 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -72,6 +72,7 @@ config I440FX select PC_PCI select PC_ACPI select ACPI_SMBUS + select I8259 select PCI_I440FX select PIIX3 select IDE_PIIX diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 6c154d88c7..694c8840de 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -35,6 +35,7 @@ config PIIX3 bool select ACPI_PIIX4 select I8257 + select I8259 select ISA_BUS select MC146818RTC select USB_UHCI --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 15/31] hw/isa/piix3: Create IDE controller in host device Date: Thu, 5 Jan 2023 15:32:12 +0100 Message-Id: <20230105143228.244965-16-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=shentey@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929316255100003 Content-Type: text/plain; charset="utf-8" Now that PIIX3 contains the new isa-pic, it is possible to instantiate PIIX3 IDE in the PIIX3 southbridge. PIIX3 IDE wires up its interrupts to the ISA bus in its realize method which requires the interrupt controller to provide fully populated qemu_irqs. This is the case for isa-pic even though the virtualization technology not known yet. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-17-shentey@gmail.com> --- include/hw/southbridge/piix.h | 2 ++ hw/i386/pc_piix.c | 15 ++++++--------- hw/isa/piix3.c | 8 ++++++++ hw/i386/Kconfig | 1 - hw/isa/Kconfig | 1 + 5 files changed, 17 insertions(+), 10 deletions(-) diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 7178147b75..1f22eb1444 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" #include "hw/acpi/piix4.h" +#include "hw/ide/pci.h" #include "hw/intc/i8259.h" #include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" @@ -56,6 +57,7 @@ struct PIIXState { =20 ISAPICState pic; RTCState rtc; + PCIIDEState ide; UHCIState uhci; PIIX4PMState pm; =20 diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index f779251e79..f92fa34d76 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -41,7 +41,6 @@ #include "hw/usb.h" #include "net/net.h" #include "hw/ide/pci.h" -#include "hw/ide/piix.h" #include "hw/irq.h" #include "sysemu/kvm.h" #include "hw/kvm/clock.h" @@ -98,7 +97,6 @@ static void pc_init1(MachineState *machine, PCIBus *pci_bus; ISABus *isa_bus; Object *piix4_pm; - int piix3_devfn =3D -1; qemu_irq smi_irq; GSIState *gsi_state; BusState *idebus[MAX_IDE_BUS]; @@ -252,11 +250,14 @@ static void pc_init1(MachineState *machine, for (i =3D 0; i < ISA_NUM_IRQS; i++) { qdev_connect_gpio_out(dev, i, x86ms->gsi[i]); } - piix3_devfn =3D pci_dev->devfn; isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); rtc_state =3D ISA_DEVICE(object_resolve_path_component(OBJECT(pci_= dev), "rtc")); piix4_pm =3D object_resolve_path_component(OBJECT(pci_dev), "pm"); + dev =3D DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide= ")); + pci_ide_create_devs(PCI_DEVICE(dev)); + idebus[0] =3D qdev_get_child_bus(dev, "ide.0"); + idebus[1] =3D qdev_get_child_bus(dev, "ide.1"); } else { pci_bus =3D NULL; piix4_pm =3D NULL; @@ -270,6 +271,8 @@ static void pc_init1(MachineState *machine, =20 i8257_dma_init(isa_bus, 0); pcms->hpet_enabled =3D false; + idebus[0] =3D NULL; + idebus[1] =3D NULL; } =20 if (x86ms->pic =3D=3D ON_OFF_AUTO_ON || x86ms->pic =3D=3D ON_OFF_AUTO_= AUTO) { @@ -298,12 +301,6 @@ static void pc_init1(MachineState *machine, pc_nic_init(pcmc, isa_bus, pci_bus); =20 if (pcmc->pci_enabled) { - PCIDevice *dev; - - dev =3D pci_create_simple(pci_bus, piix3_devfn + 1, TYPE_PIIX3_IDE= ); - pci_ide_create_devs(dev); - idebus[0] =3D qdev_get_child_bus(&dev->qdev, "ide.0"); - idebus[1] =3D qdev_get_child_bus(&dev->qdev, "ide.1"); pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); } #ifdef CONFIG_IDE_ISA diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 88a6bf28ea..a549b1a8a5 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -29,6 +29,7 @@ #include "hw/southbridge/piix.h" #include "hw/irq.h" #include "hw/qdev-properties.h" +#include "hw/ide/piix.h" #include "hw/isa/isa.h" #include "hw/xen/xen.h" #include "sysemu/runstate.h" @@ -317,6 +318,12 @@ static void pci_piix3_realize(PCIDevice *dev, Error **= errp) return; } =20 + /* IDE */ + qdev_prop_set_int32(DEVICE(&d->ide), "addr", dev->devfn + 1); + if (!qdev_realize(DEVICE(&d->ide), BUS(pci_bus), errp)) { + return; + } + /* USB */ if (d->has_usb) { object_initialize_child(OBJECT(dev), "uhci", &d->uhci, @@ -369,6 +376,7 @@ static void pci_piix3_init(Object *obj) =20 object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); + object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); } =20 static Property pci_piix3_props[] =3D { diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index 79f5925dbe..39a35467ca 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -75,7 +75,6 @@ config I440FX select I8259 select PCI_I440FX select PIIX3 - select IDE_PIIX select DIMM select SMBIOS select FW_CFG_DMA diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 694c8840de..497cc29beb 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -36,6 +36,7 @@ config PIIX3 select ACPI_PIIX4 select I8257 select I8259 + select IDE_PIIX select ISA_BUS select MC146818RTC select USB_UHCI --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 16/31] hw/isa/piix3: Wire up ACPI interrupt internally Date: Thu, 5 Jan 2023 15:32:13 +0100 Message-Id: <20230105143228.244965-17-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=shentey@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929659643100001 Content-Type: text/plain; charset="utf-8" Now that PIIX3 has the PIC integrated, the ACPI controller can be wired up internally. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-18-shentey@gmail.com> --- hw/i386/pc_piix.c | 1 - hw/isa/piix3.c | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index f92fa34d76..aacdb72b7c 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -329,7 +329,6 @@ static void pc_init1(MachineState *machine, if (piix4_pm) { smi_irq =3D qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); =20 - qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]); qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_ir= q); pcms->smbus =3D I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c"= )); /* TODO: Populate SPD eeprom data. */ diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index a549b1a8a5..6d2ffd449c 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -343,6 +343,8 @@ static void pci_piix3_realize(PCIDevice *dev, Error **e= rrp) if (!qdev_realize(DEVICE(&d->pm), BUS(pci_bus), errp)) { return; } + qdev_connect_gpio_out(DEVICE(&d->pm), 0, + qdev_get_gpio_in(DEVICE(&d->pic), 9)); } } =20 --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929451; cv=none; d=zohomail.com; s=zohoarc; b=ZJlqmE8N54iNVzz+p2XKd7Tb2A+LMCtFYquomeC7Oi7Na82EmHfPE3ZYqMWipwUv7KBx20/REr8VzwMos83gShRNyzpzhr/o9+NLkfyidB6iL6Ia2Y2qsuSbiYQpZ1o8qO94GawtDWLLJObmsqA7OUkEWx74eojKMLnn71+zSUU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672929451; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lx7EgCXB+3A8OfGp+3/2Ac3vzft3Y18ByRxSeeBTdLg=; b=iYzZPnZbjhKBU0SOr9SXeAi81tiOhxMLGz7I1KikwYIDPtVb61vpH4WqsVGzGQwzXOeUowDH3eNh8X+sGhic2AK/Q4YRDP4eFsvS5Yt0pgbu236KMF9c82YuTqC4xAkCEd0euYmDwysZN46haXhqgy2dPZPj8GSqrEm3pWck5/Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672929451030507.96058134620864; Thu, 5 Jan 2023 06:37:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDRJL-0002wZ-T7; Thu, 05 Jan 2023 09:33:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDRJA-0002nA-7j; Thu, 05 Jan 2023 09:33:29 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDRJ8-0006tS-1b; Thu, 05 Jan 2023 09:33:28 -0500 Received: by mail-wr1-x434.google.com with SMTP id co23so36342690wrb.4; Thu, 05 Jan 2023 06:33:25 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 17/31] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS Date: Thu, 5 Jan 2023 15:32:14 +0100 Message-Id: <20230105143228.244965-18-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=shentey@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929451742100001 Content-Type: text/plain; charset="utf-8" PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise inconsistencies can occur. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-21-shentey@gmail.com> --- include/hw/southbridge/piix.h | 5 ++--- hw/isa/piix3.c | 8 ++++---- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 1f22eb1444..060f2ba60c 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -32,7 +32,6 @@ */ #define PIIX_RCR_IOPORT 0xcf9 =20 -#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ =20 struct PIIXState { @@ -44,10 +43,10 @@ struct PIIXState { * So one PIC level is tracked by PIIX_NUM_PIRQS bits. * * PIRQ is mapped to PIC pins, we track it by - * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS =3D 64 bits with + * PIIX_NUM_PIRQS * ISA_NUM_IRQS =3D 64 bits with * pic_irq * PIIX_NUM_PIRQS + pirq */ -#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 +#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64 #error "unable to encode pic state in 64bit in pic_levels." #endif uint64_t pic_levels; diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 6d2ffd449c..e813e20639 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -52,7 +52,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix= 3, int pirq, int level) uint64_t mask; =20 pic_irq =3D piix3->dev.config[PIIX_PIRQCA + pirq]; - if (pic_irq >=3D PIIX_NUM_PIC_IRQS) { + if (pic_irq >=3D ISA_NUM_IRQS) { return; } =20 @@ -66,7 +66,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pi= rq, int level) int pic_irq; =20 pic_irq =3D piix3->dev.config[PIIX_PIRQCA + pirq]; - if (pic_irq >=3D PIIX_NUM_PIC_IRQS) { + if (pic_irq >=3D ISA_NUM_IRQS) { return; } =20 @@ -87,7 +87,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opa= que, int pin) int irq =3D piix3->dev.config[PIIX_PIRQCA + pin]; PCIINTxRoute route; =20 - if (irq < PIIX_NUM_PIC_IRQS) { + if (irq < ISA_NUM_IRQS) { route.mode =3D PCI_INTX_ENABLED; route.irq =3D irq; } else { @@ -119,7 +119,7 @@ static void piix3_write_config(PCIDevice *dev, =20 pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); piix3_update_irq_levels(piix3); - for (pic_irq =3D 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { + for (pic_irq =3D 0; pic_irq < ISA_NUM_IRQS; pic_irq++) { piix3_set_irq_pic(piix3, pic_irq); } } --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929265; cv=none; d=zohomail.com; s=zohoarc; b=jauO4k2DvHQ/3AtZjVz+TV4QiM9PRUFPG011GFtrWGitslrY2rIWmzTi5jJ6w1IT1Ope8NUALyIHq95LhXN6RN/oLRS4Pv4KsDyDOybNB04XxT/Ve/EHY1XfBdPA8J70/rtWyJUwTnUrs8uFwk/GG5ekdveUCFWKwjMW2ua/XQ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672929265; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ROZS9DAh1LyOJO5f9sd5J7Flg4V9+Kkad/7x0aYqgvc=; b=SqPlbWfI/XQBYaFTsTV5n0pUB9VKAYo8TGUCjoopgdzcoxLXWY84e2Krq+an3oEVjDVhW9Yx2Ws377d4lgTWm7edIK7iUM9f1XC3uF2JSzRongkd44ufnPlOPo5YXlw2wVmjoSVK8/6anix8NrLIgbzhiuiYzRPS30cDJyLRUYM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672929265578836.894545461126; Thu, 5 Jan 2023 06:34:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDRJH-0002rI-C7; Thu, 05 Jan 2023 09:33:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDRJB-0002nE-AL; Thu, 05 Jan 2023 09:33:29 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDRJ9-0006zY-P8; Thu, 05 Jan 2023 09:33:29 -0500 Received: by mail-wr1-x42a.google.com with SMTP id bn26so16848214wrb.0; Thu, 05 Jan 2023 06:33:27 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin Message-Id: <20221022150508.26830-22-shentey@gmail.com> --- hw/isa/piix3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index e813e20639..c6659bbfda 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -381,7 +381,7 @@ static void pci_piix3_init(Object *obj) object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); } =20 -static Property pci_piix3_props[] =3D { +static Property pci_piix_props[] =3D { DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), @@ -408,7 +408,7 @@ static void pci_piix3_class_init(ObjectClass *klass, vo= id *data) * pc_piix.c's pc_init1() */ dc->user_creatable =3D false; - device_class_set_props(dc, pci_piix3_props); + device_class_set_props(dc, pci_piix_props); adevc->build_dev_aml =3D build_pci_isa_aml; } =20 --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929817; cv=none; d=zohomail.com; s=zohoarc; b=CiYan1KKQz9UFo+5fCIk206PuwHHDg/XUWQsptvUESt6Emja/jGkedSaRNQOkCNWSKnBPS03/B/AUfb2XFvqZYu43jdXMt56eD5hBHVvamoO2TUEEr9kJm1lPhqDmll4K9La2ojGfMvlvlKl4sTK/tqTDisq11cr7CChDGmw9YY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672929817; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oNVX7gPoz1BSpxO3xGWjfBNYIjlgV62/Ccs00KSMxZU=; b=gun4XZuG2c6YYR0lIqpcQM/lywtYj+8YJ6+KSAx7wgmp7XSmg3njexVvShPtppL1vt4M/Z2uJ2Pf/fC4yVgYi+V31xLDiqthqAiTgb1HMbTzX5ncYGS9hgOoubS82ACHCePlNDnL0Df7ReofaUxZFPeG0k8soyrvnsqNy0GP7jc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167292981792970.2777606719161; Thu, 5 Jan 2023 06:43:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDRJM-0002wi-Cd; Thu, 05 Jan 2023 09:33:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDRJB-0002nX-JP; Thu, 05 Jan 2023 09:33:30 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDRJA-0006vC-0l; Thu, 05 Jan 2023 09:33:29 -0500 Received: by mail-wr1-x42b.google.com with SMTP id w1so24198367wrt.8; Thu, 05 Jan 2023 06:33:27 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin Message-Id: <20221022150508.26830-23-shentey@gmail.com> --- hw/isa/piix3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index c6659bbfda..d674130fc9 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -145,7 +145,7 @@ static void piix3_write_config_xen(PCIDevice *dev, piix3_write_config(dev, address, val, len); } =20 -static void piix3_reset(DeviceState *dev) +static void piix_reset(DeviceState *dev) { PIIX3State *d =3D PIIX3_PCI_DEVICE(dev); uint8_t *pci_conf =3D d->dev.config; @@ -395,7 +395,7 @@ static void pci_piix3_class_init(ObjectClass *klass, vo= id *data) PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); AcpiDevAmlIfClass *adevc =3D ACPI_DEV_AML_IF_CLASS(klass); =20 - dc->reset =3D piix3_reset; + dc->reset =3D piix_reset; dc->desc =3D "ISA bridge"; dc->vmsd =3D &vmstate_piix3; dc->hotpluggable =3D false; --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929561; cv=none; d=zohomail.com; s=zohoarc; b=bWD74v1B61sGhl6NlFV+ALmXRvqBfKb9HA9jS3uopkkq8hv8BuUZfaAl/eAbUGaVmKKIujlNG48ZMFBI5Xv1tPVswA/wwMB2stcZdS/NyBlZFkiLwgoz4yIwgoG09lBLbb1drjbXpgmxOoZqa1UbLekCbPdeYLVSGoTjwUSzDZM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672929561; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yxTwn3T8SKicpRZkBUMmS8trNtCu2Q41suXsMyXog+8=; b=cf6X1LuZEu+g1FjAy4dvrX+UP6UGj1yd7oTmxnCOqUfo0wD6pLgeDTZj8LEZs1UewBU5ZGqq+t16VHzCq7jvZG93y0upJvagGUciBv3VcqKV8ZlUrPc5/OOqe/0vldnSVyCZJCT2RffVwe+cNN18cZL23IYSlXg6rpYVW5xHUL0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672929561249486.9833931024839; Thu, 5 Jan 2023 06:39:21 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDRJN-0002xE-5F; Thu, 05 Jan 2023 09:33:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDRJC-0002nk-UI; Thu, 05 Jan 2023 09:33:31 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDRJA-0006tk-Vo; Thu, 05 Jan 2023 09:33:30 -0500 Received: by mail-wr1-x42d.google.com with SMTP id r2so1494135wrv.7; Thu, 05 Jan 2023 06:33:28 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 20/31] hw/isa/piix3: Drop the "3" from PIIX base class Date: Thu, 5 Jan 2023 15:32:17 +0100 Message-Id: <20230105143228.244965-21-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=shentey@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929562405100003 Content-Type: text/plain; charset="utf-8" This commit marks the finalization of the PIIX3 preparations to be merged with PIIX4. In particular, PIIXState is prepared to be reused in piix4.c. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-25-shentey@gmail.com> --- include/hw/southbridge/piix.h | 6 ++-- hw/isa/piix3.c | 60 +++++++++++++++++------------------ 2 files changed, 32 insertions(+), 34 deletions(-) diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 060f2ba60c..5753c68710 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -72,11 +72,9 @@ struct PIIXState { bool has_usb; bool smm_enabled; }; -typedef struct PIIXState PIIX3State; =20 -#define TYPE_PIIX3_PCI_DEVICE "pci-piix3" -DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, - TYPE_PIIX3_PCI_DEVICE) +#define TYPE_PIIX_PCI_DEVICE "pci-piix" +OBJECT_DECLARE_SIMPLE_TYPE(PIIXState, PIIX_PCI_DEVICE) =20 #define TYPE_PIIX3_DEVICE "PIIX3" #define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen" diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index d674130fc9..4ce1653406 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -38,7 +38,7 @@ =20 #define XEN_PIIX_NUM_PIRQS 128ULL =20 -static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) +static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq) { qemu_set_irq(piix3->pic.in_irqs[pic_irq], !!(piix3->pic_levels & @@ -46,7 +46,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_= irq) (pic_irq * PIIX_NUM_PIRQS)))); } =20 -static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int = level) +static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int l= evel) { int pic_irq; uint64_t mask; @@ -61,7 +61,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix= 3, int pirq, int level) piix3->pic_levels |=3D mask * !!level; } =20 -static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) +static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level) { int pic_irq; =20 @@ -77,13 +77,13 @@ static void piix3_set_irq_level(PIIX3State *piix3, int = pirq, int level) =20 static void piix3_set_irq(void *opaque, int pirq, int level) { - PIIX3State *piix3 =3D opaque; + PIIXState *piix3 =3D opaque; piix3_set_irq_level(piix3, pirq, level); } =20 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { - PIIX3State *piix3 =3D opaque; + PIIXState *piix3 =3D opaque; int irq =3D piix3->dev.config[PIIX_PIRQCA + pin]; PCIINTxRoute route; =20 @@ -98,7 +98,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opa= que, int pin) } =20 /* irq routing is changed. so rebuild bitmap */ -static void piix3_update_irq_levels(PIIX3State *piix3) +static void piix3_update_irq_levels(PIIXState *piix3) { PCIBus *bus =3D pci_get_bus(&piix3->dev); int pirq; @@ -114,7 +114,7 @@ static void piix3_write_config(PCIDevice *dev, { pci_default_write_config(dev, address, val, len); if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { - PIIX3State *piix3 =3D PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 =3D PIIX_PCI_DEVICE(dev); int pic_irq; =20 pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); @@ -147,7 +147,7 @@ static void piix3_write_config_xen(PCIDevice *dev, =20 static void piix_reset(DeviceState *dev) { - PIIX3State *d =3D PIIX3_PCI_DEVICE(dev); + PIIXState *d =3D PIIX_PCI_DEVICE(dev); uint8_t *pci_conf =3D d->dev.config; =20 pci_conf[0x04] =3D 0x07; /* master, memory and I/O */ @@ -188,7 +188,7 @@ static void piix_reset(DeviceState *dev) =20 static int piix3_post_load(void *opaque, int version_id) { - PIIX3State *piix3 =3D opaque; + PIIXState *piix3 =3D opaque; int pirq; =20 /* @@ -211,7 +211,7 @@ static int piix3_post_load(void *opaque, int version_id) static int piix3_pre_save(void *opaque) { int i; - PIIX3State *piix3 =3D opaque; + PIIXState *piix3 =3D opaque; =20 for (i =3D 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { piix3->pci_irq_levels_vmstate[i] =3D @@ -223,7 +223,7 @@ static int piix3_pre_save(void *opaque) =20 static bool piix3_rcr_needed(void *opaque) { - PIIX3State *piix3 =3D opaque; + PIIXState *piix3 =3D opaque; =20 return (piix3->rcr !=3D 0); } @@ -234,7 +234,7 @@ static const VMStateDescription vmstate_piix3_rcr =3D { .minimum_version_id =3D 1, .needed =3D piix3_rcr_needed, .fields =3D (VMStateField[]) { - VMSTATE_UINT8(rcr, PIIX3State), + VMSTATE_UINT8(rcr, PIIXState), VMSTATE_END_OF_LIST() } }; @@ -246,8 +246,8 @@ static const VMStateDescription vmstate_piix3 =3D { .post_load =3D piix3_post_load, .pre_save =3D piix3_pre_save, .fields =3D (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIX3State), - VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, + VMSTATE_PCI_DEVICE(dev, PIIXState), + VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIXState, PIIX_NUM_PIRQS, 3), VMSTATE_END_OF_LIST() }, @@ -260,7 +260,7 @@ static const VMStateDescription vmstate_piix3 =3D { =20 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned le= n) { - PIIX3State *d =3D opaque; + PIIXState *d =3D opaque; =20 if (val & 4) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); @@ -271,7 +271,7 @@ static void rcr_write(void *opaque, hwaddr addr, uint64= _t val, unsigned len) =20 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) { - PIIX3State *d =3D opaque; + PIIXState *d =3D opaque; =20 return d->rcr; } @@ -288,7 +288,7 @@ static const MemoryRegionOps rcr_ops =3D { =20 static void pci_piix3_realize(PCIDevice *dev, Error **errp) { - PIIX3State *d =3D PIIX3_PCI_DEVICE(dev); + PIIXState *d =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); ISABus *isa_bus; =20 @@ -374,7 +374,7 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *= scope) =20 static void pci_piix3_init(Object *obj) { - PIIX3State *d =3D PIIX3_PCI_DEVICE(obj); + PIIXState *d =3D PIIX_PCI_DEVICE(obj); =20 object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); @@ -382,10 +382,10 @@ static void pci_piix3_init(Object *obj) } =20 static Property pci_piix_props[] =3D { - DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), - DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), - DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), - DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false), + DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0), + DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true), + DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -412,10 +412,10 @@ static void pci_piix3_class_init(ObjectClass *klass, = void *data) adevc->build_dev_aml =3D build_pci_isa_aml; } =20 -static const TypeInfo piix3_pci_type_info =3D { - .name =3D TYPE_PIIX3_PCI_DEVICE, +static const TypeInfo piix_pci_type_info =3D { + .name =3D TYPE_PIIX_PCI_DEVICE, .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PIIX3State), + .instance_size =3D sizeof(PIIXState), .instance_init =3D pci_piix3_init, .abstract =3D true, .class_init =3D pci_piix3_class_init, @@ -429,7 +429,7 @@ static const TypeInfo piix3_pci_type_info =3D { static void piix3_realize(PCIDevice *dev, Error **errp) { ERRP_GUARD(); - PIIX3State *piix3 =3D PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); =20 pci_piix3_realize(dev, errp); @@ -451,14 +451,14 @@ static void piix3_class_init(ObjectClass *klass, void= *data) =20 static const TypeInfo piix3_info =3D { .name =3D TYPE_PIIX3_DEVICE, - .parent =3D TYPE_PIIX3_PCI_DEVICE, + .parent =3D TYPE_PIIX_PCI_DEVICE, .class_init =3D piix3_class_init, }; =20 static void piix3_xen_realize(PCIDevice *dev, Error **errp) { ERRP_GUARD(); - PIIX3State *piix3 =3D PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); =20 pci_piix3_realize(dev, errp); @@ -485,13 +485,13 @@ static void piix3_xen_class_init(ObjectClass *klass, = void *data) =20 static const TypeInfo piix3_xen_info =3D { .name =3D TYPE_PIIX3_XEN_DEVICE, - .parent =3D TYPE_PIIX3_PCI_DEVICE, + .parent =3D TYPE_PIIX_PCI_DEVICE, .class_init =3D piix3_xen_class_init, }; =20 static void piix3_register_types(void) { - type_register_static(&piix3_pci_type_info); + type_register_static(&piix_pci_type_info); type_register_static(&piix3_info); type_register_static(&piix3_xen_info); } --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 21/31] hw/isa/piix4: Make PIIX4's ACPI and USB functions optional Date: Thu, 5 Jan 2023 15:32:18 +0100 Message-Id: <20230105143228.244965-22-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=shentey@gmail.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929356546100001 Content-Type: text/plain; charset="utf-8" This aligns PIIX4 with PIIX3. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-30-shentey@gmail.com> --- hw/isa/piix4.c | 44 ++++++++++++++++++++++++++++++++------------ hw/mips/malta.c | 6 ++++-- 2 files changed, 36 insertions(+), 14 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index de60ceef73..de4133f573 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -51,9 +51,16 @@ struct PIIX4State { PCIIDEState ide; UHCIState uhci; PIIX4PMState pm; + + uint32_t smb_io_base; + /* Reset Control Register */ MemoryRegion rcr_mem; uint8_t rcr; + + bool has_acpi; + bool has_usb; + bool smm_enabled; }; =20 OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE) @@ -234,17 +241,26 @@ static void piix4_realize(PCIDevice *dev, Error **err= p) } =20 /* USB */ - qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); - if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { - return; + if (s->has_usb) { + object_initialize_child(OBJECT(dev), "uhci", &s->uhci, + TYPE_PIIX4_USB_UHCI); + qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); + if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { + return; + } } =20 /* ACPI controller */ - qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); - if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { - return; + if (s->has_acpi) { + object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); + qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); + qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base= ); + qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); + if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { + return; + } + qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]); } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]); =20 pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); } @@ -255,13 +271,16 @@ static void piix4_init(Object *obj) =20 object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); - object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI); - - object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM); - qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", 0x1100); - qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", 0); } =20 +static Property piix4_props[] =3D { + DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0), + DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true), + DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false), + DEFINE_PROP_END_OF_LIST(), +}; + static void piix4_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -280,6 +299,7 @@ static void piix4_class_init(ObjectClass *klass, void *= data) */ dc->user_creatable =3D false; dc->hotpluggable =3D false; + device_class_set_props(dc, piix4_props); } =20 static const TypeInfo piix4_info =3D { diff --git a/hw/mips/malta.c b/hw/mips/malta.c index ef3e10dc4d..a930a91f00 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1448,8 +1448,10 @@ void mips_malta_init(MachineState *machine) empty_slot_init("GT64120", 0, 0x20000000); =20 /* Southbridge */ - piix4 =3D pci_create_simple_multifunction(pci_bus, PIIX4_PCI_DEVFN, tr= ue, - TYPE_PIIX4_PCI_DEVICE); + piix4 =3D pci_new_multifunction(PIIX4_PCI_DEVFN, true, + TYPE_PIIX4_PCI_DEVICE); + qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100); + pci_realize_and_unref(piix4, pci_bus, &error_fatal); isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); =20 dev =3D DEVICE(object_resolve_path_component(OBJECT(piix4), "ide")); --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929421; cv=none; d=zohomail.com; s=zohoarc; b=XRCz1S8OtL5TQWhZC2OBuARduhE+wgaocq/eS/Z4KwCuH3iRpBG44SvncIyLUM6xOZwKJkzfPAZXoD1yTkF5E99uJeh3Ps51Mz0tLlndM9llAL4YFmClMHBG86SMVsGBVpwfv2Fz7inuhTpWxkrVAWhHYNkvKkriSpsGKbMPRdA= ARC-Message-Signature: i=1; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 22/31] hw/isa/piix4: Remove unused inbound ISA interrupt lines Date: Thu, 5 Jan 2023 15:32:19 +0100 Message-Id: <20230105143228.244965-23-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=shentey@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929421843100001 Content-Type: text/plain; charset="utf-8" The Malta board, which is the only user of PIIX4, doesn't connect to the exported interrupt lines. PIIX3 doesn't expose such intterupt lines either, so remove them for PIIX4 for simplicity and consistency. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-32-shentey@gmail.com> --- hw/isa/piix4.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index de4133f573..9edaa5de3e 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -155,12 +155,6 @@ static void piix4_request_i8259_irq(void *opaque, int = irq, int level) qemu_set_irq(s->cpu_intr, level); } =20 -static void piix4_set_i8259_irq(void *opaque, int irq, int level) -{ - PIIX4State *s =3D opaque; - qemu_set_irq(s->isa[irq], level); -} - static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { @@ -204,8 +198,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } =20 - qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq, - "isa", ISA_NUM_IRQS); qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr, "intr", 1); =20 --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929625; cv=none; d=zohomail.com; s=zohoarc; b=naaoRBtPRoJyS5CZo3FSfUNFgXt2xxapxPWQ4z8XSDdCKvmnKv5G5Y6FFo3BZNz/gxtrRHarTgCYfrijHJoITJrHC7LQi2SVurAjnyBapZal37gMyoW72mnIxRfrs+0hRDx3roCz9I0VXjardCoOVs0f+OcSsiRbtLTgGPk2/w8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672929625; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yuUPAL39BWQGniG6VAc4FaCcHuPduEkKF2hR1Xdinn4=; b=KBMaH+xDYVP3t8awMj35F2fcnfCH8uVXFvSd3hBRahxIrHa4WGL+R/6q+XRpqlNCCYkh/gYJnrgCKZ9TA6xFdR0Z685ZNfJDCgmGGSkprWgoAFrMg593RMEayRyheGJNE0aQ95SqVW/HhtYlQysuz43TNPDPdxP6WELTGHMJO4Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672929625931663.2106149614202; Thu, 5 Jan 2023 06:40:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDRJN-0002xF-54; Thu, 05 Jan 2023 09:33:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDRJH-0002rP-EP; Thu, 05 Jan 2023 09:33:35 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDRJF-0006wx-KE; Thu, 05 Jan 2023 09:33:35 -0500 Received: by mail-wr1-x433.google.com with SMTP id t15so27446654wro.9; Thu, 05 Jan 2023 06:33:32 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 23/31] hw/isa/piix4: Use ISA PIC device Date: Thu, 5 Jan 2023 15:32:20 +0100 Message-Id: <20230105143228.244965-24-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=shentey@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929627731100006 Content-Type: text/plain; charset="utf-8" Aligns the code with PIIX3 such that PIIXState can be used in PIIX4, too. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-33-shentey@gmail.com> --- hw/isa/piix4.c | 28 ++++++++++------------------ hw/mips/malta.c | 11 +++++++++-- hw/mips/Kconfig | 1 + 3 files changed, 20 insertions(+), 20 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 9edaa5de3e..eae4db0182 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -44,9 +44,8 @@ =20 struct PIIX4State { PCIDevice dev; - qemu_irq cpu_intr; - qemu_irq *isa; =20 + ISAPICState pic; RTCState rtc; PCIIDEState ide; UHCIState uhci; @@ -82,7 +81,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int = level) pic_level |=3D pci_bus_get_irq_level(bus, i); } } - qemu_set_irq(s->isa[pic_irq], pic_level); + qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); } } =20 @@ -149,12 +148,6 @@ static const VMStateDescription vmstate_piix4 =3D { } }; =20 -static void piix4_request_i8259_irq(void *opaque, int irq, int level) -{ - PIIX4State *s =3D opaque; - qemu_set_irq(s->cpu_intr, level); -} - static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { @@ -190,7 +183,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) PIIX4State *s =3D PIIX4_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); ISABus *isa_bus; - qemu_irq *i8259_out_irq; =20 isa_bus =3D isa_bus_new(DEVICE(dev), pci_address_space(dev), pci_address_space_io(dev), errp); @@ -198,20 +190,18 @@ static void piix4_realize(PCIDevice *dev, Error **err= p) return; } =20 - qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr, - "intr", 1); - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, "reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &s->rcr_mem, 1); =20 /* initialize i8259 pic */ - i8259_out_irq =3D qemu_allocate_irqs(piix4_request_i8259_irq, s, 1); - s->isa =3D i8259_init(isa_bus, *i8259_out_irq); + if (!qdev_realize(DEVICE(&s->pic), NULL, errp)) { + return; + } =20 /* initialize ISA irqs */ - isa_bus_irqs(isa_bus, s->isa); + isa_bus_irqs(isa_bus, s->pic.in_irqs); =20 /* initialize pit */ i8254_pit_init(isa_bus, 0x40, 0, NULL); @@ -224,7 +214,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { return; } - s->rtc.irq =3D isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq); + s->rtc.irq =3D qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); =20 /* IDE */ qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); @@ -251,7 +241,8 @@ static void piix4_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { return; } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]); + qdev_connect_gpio_out(DEVICE(&s->pm), 0, + qdev_get_gpio_in(DEVICE(&s->pic), 9)); } =20 pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); @@ -261,6 +252,7 @@ static void piix4_init(Object *obj) { PIIX4State *s =3D PIIX4_PCI_DEVICE(obj); =20 + object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); } diff --git a/hw/mips/malta.c b/hw/mips/malta.c index a930a91f00..1bb493353b 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -29,6 +29,7 @@ #include "qemu/guest-random.h" #include "hw/clock.h" #include "hw/southbridge/piix.h" +#include "hw/intc/i8259.h" #include "hw/isa/superio.h" #include "hw/char/serial.h" #include "net/net.h" @@ -1280,10 +1281,11 @@ void mips_malta_init(MachineState *machine) PCIBus *pci_bus; ISABus *isa_bus; qemu_irq cbus_irq, i8259_irq; + qemu_irq *i8259; I2CBus *smbus; DriveInfo *dinfo; int fl_idx =3D 0; - int be; + int be, i; MaltaState *s; PCIDevice *piix4; DeviceState *dev; @@ -1458,7 +1460,12 @@ void mips_malta_init(MachineState *machine) pci_ide_create_devs(PCI_DEVICE(dev)); =20 /* Interrupt controller */ - qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq); + dev =3D DEVICE(object_resolve_path_component(OBJECT(piix4), "pic")); + i8259 =3D i8259_init(isa_bus, i8259_irq); + for (i =3D 0; i < ISA_NUM_IRQS; i++) { + qdev_connect_gpio_out(dev, i, i8259[i]); + } + g_free(i8259); =20 pci_bus_map_irqs(pci_bus, pci_slot_get_pirq); =20 diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index 4e7042f03d..d156de812c 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -1,5 +1,6 @@ config MALTA bool + select I8259 select ISA_SUPERIO select PIIX4 =20 --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 24/31] hw/isa/piix4: Reuse struct PIIXState from PIIX3 Date: Thu, 5 Jan 2023 15:32:21 +0100 Message-Id: <20230105143228.244965-25-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=shentey@gmail.com; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929374490100009 Content-Type: text/plain; charset="utf-8" Now that PIIX4 also uses the "proxy-pic", both implementations can share the same struct. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-34-shentey@gmail.com> --- hw/isa/piix4.c | 51 +++++++++++++++----------------------------------- 1 file changed, 15 insertions(+), 36 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index eae4db0182..ce88377630 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -42,32 +42,10 @@ #include "sysemu/runstate.h" #include "qom/object.h" =20 -struct PIIX4State { - PCIDevice dev; - - ISAPICState pic; - RTCState rtc; - PCIIDEState ide; - UHCIState uhci; - PIIX4PMState pm; - - uint32_t smb_io_base; - - /* Reset Control Register */ - MemoryRegion rcr_mem; - uint8_t rcr; - - bool has_acpi; - bool has_usb; - bool smm_enabled; -}; - -OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE) - static void piix4_set_irq(void *opaque, int irq_num, int level) { int i, pic_irq, pic_level; - PIIX4State *s =3D opaque; + PIIXState *s =3D opaque; PCIBus *bus =3D pci_get_bus(&s->dev); =20 /* now we change the pic irq level according to the piix irq mappings = */ @@ -87,7 +65,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int = level) =20 static void piix4_isa_reset(DeviceState *dev) { - PIIX4State *d =3D PIIX4_PCI_DEVICE(dev); + PIIXState *d =3D PIIX_PCI_DEVICE(dev); uint8_t *pci_conf =3D d->dev.config; =20 pci_conf[0x04] =3D 0x07; // master, memory and I/O @@ -122,12 +100,13 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0xac] =3D 0x00; pci_conf[0xae] =3D 0x00; =20 + d->pic_levels =3D 0; /* not used in PIIX4 */ d->rcr =3D 0; } =20 static int piix4_post_load(void *opaque, int version_id) { - PIIX4State *s =3D opaque; + PIIXState *s =3D opaque; =20 if (version_id =3D=3D 2) { s->rcr =3D 0; @@ -142,8 +121,8 @@ static const VMStateDescription vmstate_piix4 =3D { .minimum_version_id =3D 2, .post_load =3D piix4_post_load, .fields =3D (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIX4State), - VMSTATE_UINT8_V(rcr, PIIX4State, 3), + VMSTATE_PCI_DEVICE(dev, PIIXState), + VMSTATE_UINT8_V(rcr, PIIXState, 3), VMSTATE_END_OF_LIST() } }; @@ -151,7 +130,7 @@ static const VMStateDescription vmstate_piix4 =3D { static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { - PIIX4State *s =3D opaque; + PIIXState *s =3D opaque; =20 if (val & 4) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); @@ -163,7 +142,7 @@ static void piix4_rcr_write(void *opaque, hwaddr addr, = uint64_t val, =20 static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) { - PIIX4State *s =3D opaque; + PIIXState *s =3D opaque; =20 return s->rcr; } @@ -180,7 +159,7 @@ static const MemoryRegionOps piix4_rcr_ops =3D { =20 static void piix4_realize(PCIDevice *dev, Error **errp) { - PIIX4State *s =3D PIIX4_PCI_DEVICE(dev); + PIIXState *s =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); ISABus *isa_bus; =20 @@ -250,7 +229,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) =20 static void piix4_init(Object *obj) { - PIIX4State *s =3D PIIX4_PCI_DEVICE(obj); + PIIXState *s =3D PIIX_PCI_DEVICE(obj); =20 object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); @@ -258,10 +237,10 @@ static void piix4_init(Object *obj) } =20 static Property piix4_props[] =3D { - DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0), - DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true), - DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true), - DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false), + DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0), + DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true), + DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -289,7 +268,7 @@ static void piix4_class_init(ObjectClass *klass, void *= data) static const TypeInfo piix4_info =3D { .name =3D TYPE_PIIX4_PCI_DEVICE, .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PIIX4State), + .instance_size =3D sizeof(PIIXState), .instance_init =3D piix4_init, .class_init =3D piix4_class_init, .interfaces =3D (InterfaceInfo[]) { --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929797; cv=none; d=zohomail.com; s=zohoarc; b=RsXk7IGiAp6CqhFbfmBqgZPZ+i03wAJizey4QWzTgxKpyWZ4tznAZ6jQKK3y7OgR8gbXd6zU6tHMNOSlxTZBeBX4t9BUfo/5cHcprMNtVcEMYbRw1mGtG7QgRuvsM8UR8WeIuQQBKEaM0i0FARmNvCxgg34mxE2YaszIEK73AxU= ARC-Message-Signature: i=1; a=rsa-sha256; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 25/31] hw/isa/piix4: Rename reset control operations to match PIIX3 Date: Thu, 5 Jan 2023 15:32:22 +0100 Message-Id: <20230105143228.244965-26-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=shentey@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929799715100003 Both implementations are the same and will be shared upon merging. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-35-shentey@gmail.com> --- hw/isa/piix4.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index ce88377630..de7cde192f 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -127,7 +127,7 @@ static const VMStateDescription vmstate_piix4 =3D { } }; =20 -static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, +static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { PIIXState *s =3D opaque; @@ -140,16 +140,16 @@ static void piix4_rcr_write(void *opaque, hwaddr addr= , uint64_t val, s->rcr =3D val & 2; /* keep System Reset type only */ } =20 -static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) +static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned int len) { PIIXState *s =3D opaque; =20 return s->rcr; } =20 -static const MemoryRegionOps piix4_rcr_ops =3D { - .read =3D piix4_rcr_read, - .write =3D piix4_rcr_write, +static const MemoryRegionOps rcr_ops =3D { + .read =3D rcr_read, + .write =3D rcr_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .impl =3D { .min_access_size =3D 1, @@ -169,7 +169,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } =20 - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, "reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &s->rcr_mem, 1); --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929971; cv=none; d=zohomail.com; s=zohoarc; b=QKJxurJ251ss4qyk68p8WFAIY+dQsqTx/XzSsP5AKh5XiHHRTgalLhuFYXNqOdQ8EK2pn0W5A6xibIPLcWYNk0bbDTM3oFAil2FoaYhUY+osaW8a4g6DEAg9FhDU18NTDTjk6RL4SkiXR8clV+XFnharPdxZkY88LSqJ43CMFL4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672929971; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Zr1ioA6SjyrnMmwipMJLcdraYQPIIWJge112HiDfGD4=; b=XLthBwNm3tubNXNsOjDpXZREoFAFw+qpzqaChxvqzOsmFYK+fH3Hw+qkzyLtPcuX3rPHOXsAWjo64lt44kjZhSTOitLusXIs4ztlpw03mPLd37EfmwWAVRDjBfTsLOGRH7AUXVj+UsP/L3Z0w/Hkgz5mMEqXTbhReJYENJnjh0I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672929971457831.1677092317357; Thu, 5 Jan 2023 06:46:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDRJT-00037X-D0; Thu, 05 Jan 2023 09:33:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDRJM-0002wd-3a; Thu, 05 Jan 2023 09:33:40 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDRJJ-0006vC-B2; Thu, 05 Jan 2023 09:33:39 -0500 Received: by mail-wr1-x42b.google.com with SMTP id w1so24198838wrt.8; Thu, 05 Jan 2023 06:33:36 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id bt15-20020a056000080f00b00297dcfdc90fsm12260447wrb.24.2023.01.05.06.33.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 06:33:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zr1ioA6SjyrnMmwipMJLcdraYQPIIWJge112HiDfGD4=; b=GlttNvZrsvNcLBMIXoX436tchncswlD7zULhhnv6QohmQsoM6XkEZ/nf39DzCSlMIW c75RX4o43WywssmIWXgpCUX2u43+y+31OYPkefs5y8lPR/i3le2+N35wZW8UGb0NRFO8 uTGgMi7RprEse4MK39mDEjWSkc7coLrvkqz29fIvAdu4AaqjqLB0JcvtHlUdNmeGotNk SlUunf3qb0yKgt5l08JsdJ1LdL6x0V89lfyIr0uldPk3spnsN2zfbD24w4EXf0vfhPpc +ICYpX0Y9xq1XPNHp+I3t9jw2/5BdKX7cLii1WHDc5mbQi/yxJ7lbwqDLxmV1UeANzGS bEmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zr1ioA6SjyrnMmwipMJLcdraYQPIIWJge112HiDfGD4=; b=S/JpYyKPaPqnNVApys922Xmo68ETFE9G1oIbbpDaOc1olbJYzHoE1rBGi7v6e8X01g RuKz+Zs07KZtVQtQ9OTV1c1Z65eg5XMYH4NuJgy5l2EQmzBpwaOLl5cF/YgeLOryE2jp +sLhR23ZIzF982ONA4MAV3NZ4fh0MArizXQeT42S/RVRsvtjLzyniTXrPVm2BDcGSnCd 6gMm3BC4Dy478uRWMqPcrq9LkLO3gCUa18eubh4RL0o94A4yS03qjEiq55vUHn1l9emk d2GX40EtdTmT/tdCTW2kIBCwp6yJal+BXCGuZ4/5SIBExaxIUkrYP0ZepTg9peX2cN24 ljsQ== X-Gm-Message-State: AFqh2krPfu1w7SFqVL/APUDtPoZhKXChEHfEUlrvuNXLWpak8xGzYTK6 jiv+x9Jsz/VdmR73fyGOfKoXjLw55pwusQ== X-Google-Smtp-Source: AMrXdXutBps783Ne8znCDoeITQxI15KH7LSQtGv7y4aB+T8Eo/oucYgZHAT/u6v/qXebEtM9lJs3Bw== X-Received: by 2002:a5d:6dc4:0:b0:2b4:e5e:1e16 with SMTP id d4-20020a5d6dc4000000b002b40e5e1e16mr1336246wrz.35.1672929215889; Thu, 05 Jan 2023 06:33:35 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , qemu-block@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Ani Sinha , Richard Henderson , Jiaxun Yang , Aurelien Jarno , "Michael S. Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 26/31] hw/isa/piix3: Merge hw/isa/piix4.c Date: Thu, 5 Jan 2023 15:32:23 +0100 Message-Id: <20230105143228.244965-27-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=shentey@gmail.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929972334100001 Now that the PIIX3 and PIIX4 device models are sufficiently consolidated, their implementations can be merged into one file for further consolidation. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-37-shentey@gmail.com> --- hw/isa/{piix3.c =3D> piix.c} | 158 ++++++++++++++++++++ hw/isa/piix4.c | 285 ------------------------------------- MAINTAINERS | 6 +- hw/i386/Kconfig | 2 +- hw/isa/Kconfig | 12 +- hw/isa/meson.build | 3 +- hw/mips/Kconfig | 2 +- 7 files changed, 165 insertions(+), 303 deletions(-) rename hw/isa/{piix3.c =3D> piix.c} (75%) delete mode 100644 hw/isa/piix4.c diff --git a/hw/isa/piix3.c b/hw/isa/piix.c similarity index 75% rename from hw/isa/piix3.c rename to hw/isa/piix.c index 4ce1653406..81cb4e64ab 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix.c @@ -2,6 +2,7 @@ * QEMU PIIX PCI ISA Bridge Emulation * * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2018 Herv=C3=A9 Poussineau * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal @@ -27,6 +28,7 @@ #include "qapi/error.h" #include "hw/dma/i8257.h" #include "hw/southbridge/piix.h" +#include "hw/timer/i8254.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/ide/piix.h" @@ -81,6 +83,27 @@ static void piix3_set_irq(void *opaque, int pirq, int le= vel) piix3_set_irq_level(piix3, pirq, level); } =20 +static void piix4_set_irq(void *opaque, int irq_num, int level) +{ + int i, pic_irq, pic_level; + PIIXState *s =3D opaque; + PCIBus *bus =3D pci_get_bus(&s->dev); + + /* now we change the pic irq level according to the piix irq mappings = */ + /* XXX: optimize */ + pic_irq =3D s->dev.config[PIIX_PIRQCA + irq_num]; + if (pic_irq < ISA_NUM_IRQS) { + /* The pic level is the logical OR of all the PCI irqs mapped to i= t. */ + pic_level =3D 0; + for (i =3D 0; i < PIIX_NUM_PIRQS; i++) { + if (pic_irq =3D=3D s->dev.config[PIIX_PIRQCA + i]) { + pic_level |=3D pci_bus_get_irq_level(bus, i); + } + } + qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); + } +} + static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { PIIXState *piix3 =3D opaque; @@ -208,6 +231,17 @@ static int piix3_post_load(void *opaque, int version_i= d) return 0; } =20 +static int piix4_post_load(void *opaque, int version_id) +{ + PIIXState *s =3D opaque; + + if (version_id =3D=3D 2) { + s->rcr =3D 0; + } + + return 0; +} + static int piix3_pre_save(void *opaque) { int i; @@ -257,6 +291,17 @@ static const VMStateDescription vmstate_piix3 =3D { } }; =20 +static const VMStateDescription vmstate_piix4 =3D { + .name =3D "PIIX4", + .version_id =3D 3, + .minimum_version_id =3D 2, + .post_load =3D piix4_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_PCI_DEVICE(dev, PIIXState), + VMSTATE_UINT8_V(rcr, PIIXState, 3), + VMSTATE_END_OF_LIST() + } +}; =20 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned le= n) { @@ -489,11 +534,124 @@ static const TypeInfo piix3_xen_info =3D { .class_init =3D piix3_xen_class_init, }; =20 +static void piix4_realize(PCIDevice *dev, Error **errp) +{ + PIIXState *s =3D PIIX_PCI_DEVICE(dev); + PCIBus *pci_bus =3D pci_get_bus(dev); + ISABus *isa_bus; + + isa_bus =3D isa_bus_new(DEVICE(dev), pci_address_space(dev), + pci_address_space_io(dev), errp); + if (!isa_bus) { + return; + } + + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, + "reset-control", 1); + memory_region_add_subregion_overlap(pci_address_space_io(dev), + PIIX_RCR_IOPORT, &s->rcr_mem, 1); + + /* initialize i8259 pic */ + if (!qdev_realize(DEVICE(&s->pic), NULL, errp)) { + return; + } + + /* initialize ISA irqs */ + isa_bus_irqs(isa_bus, s->pic.in_irqs); + + /* initialize pit */ + i8254_pit_init(isa_bus, 0x40, 0, NULL); + + /* DMA */ + i8257_dma_init(isa_bus, 0); + + /* RTC */ + qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); + if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { + return; + } + s->rtc.irq =3D qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); + + /* IDE */ + qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); + if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { + return; + } + + /* USB */ + if (s->has_usb) { + object_initialize_child(OBJECT(dev), "uhci", &s->uhci, + TYPE_PIIX4_USB_UHCI); + qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); + if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { + return; + } + } + + /* ACPI controller */ + if (s->has_acpi) { + object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); + qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); + qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base= ); + qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); + if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { + return; + } + qdev_connect_gpio_out(DEVICE(&s->pm), 0, + qdev_get_gpio_in(DEVICE(&s->pic), 9)); + } + + pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); +} + +static void piix4_init(Object *obj) +{ + PIIXState *s =3D PIIX_PCI_DEVICE(obj); + + object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); + object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); + object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); +} + +static void piix4_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->realize =3D piix4_realize; + k->vendor_id =3D PCI_VENDOR_ID_INTEL; + k->device_id =3D PCI_DEVICE_ID_INTEL_82371AB_0; + k->class_id =3D PCI_CLASS_BRIDGE_ISA; + dc->reset =3D piix_reset; + dc->desc =3D "ISA bridge"; + dc->vmsd =3D &vmstate_piix4; + /* + * Reason: part of PIIX4 southbridge, needs to be wired up, + * e.g. by mips_malta_init() + */ + dc->user_creatable =3D false; + dc->hotpluggable =3D false; + device_class_set_props(dc, pci_piix_props); +} + +static const TypeInfo piix4_info =3D { + .name =3D TYPE_PIIX4_PCI_DEVICE, + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(PIIXState), + .instance_init =3D piix4_init, + .class_init =3D piix4_class_init, + .interfaces =3D (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, +}; + static void piix3_register_types(void) { type_register_static(&piix_pci_type_info); type_register_static(&piix3_info); type_register_static(&piix3_xen_info); + type_register_static(&piix4_info); } =20 type_init(piix3_register_types) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c deleted file mode 100644 index de7cde192f..0000000000 --- a/hw/isa/piix4.c +++ /dev/null @@ -1,285 +0,0 @@ -/* - * QEMU PIIX4 PCI Bridge Emulation - * - * Copyright (c) 2006 Fabrice Bellard - * Copyright (c) 2018 Herv=C3=A9 Poussineau - * - * Permission is hereby granted, free of charge, to any person obtaining a= copy - * of this software and associated documentation files (the "Software"), t= o deal - * in the Software without restriction, including without limitation the r= ights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included= in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN - * THE SOFTWARE. - */ - -#include "qemu/osdep.h" -#include "qapi/error.h" -#include "hw/irq.h" -#include "hw/southbridge/piix.h" -#include "hw/pci/pci.h" -#include "hw/ide/piix.h" -#include "hw/isa/isa.h" -#include "hw/intc/i8259.h" -#include "hw/dma/i8257.h" -#include "hw/timer/i8254.h" -#include "hw/rtc/mc146818rtc.h" -#include "hw/ide/pci.h" -#include "hw/acpi/piix4.h" -#include "hw/usb/hcd-uhci.h" -#include "migration/vmstate.h" -#include "sysemu/reset.h" -#include "sysemu/runstate.h" -#include "qom/object.h" - -static void piix4_set_irq(void *opaque, int irq_num, int level) -{ - int i, pic_irq, pic_level; - PIIXState *s =3D opaque; - PCIBus *bus =3D pci_get_bus(&s->dev); - - /* now we change the pic irq level according to the piix irq mappings = */ - /* XXX: optimize */ - pic_irq =3D s->dev.config[PIIX_PIRQCA + irq_num]; - if (pic_irq < ISA_NUM_IRQS) { - /* The pic level is the logical OR of all the PCI irqs mapped to i= t. */ - pic_level =3D 0; - for (i =3D 0; i < PIIX_NUM_PIRQS; i++) { - if (pic_irq =3D=3D s->dev.config[PIIX_PIRQCA + i]) { - pic_level |=3D pci_bus_get_irq_level(bus, i); - } - } - qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); - } -} - -static void piix4_isa_reset(DeviceState *dev) -{ - PIIXState *d =3D PIIX_PCI_DEVICE(dev); - uint8_t *pci_conf =3D d->dev.config; - - pci_conf[0x04] =3D 0x07; // master, memory and I/O - pci_conf[0x05] =3D 0x00; - pci_conf[0x06] =3D 0x00; - pci_conf[0x07] =3D 0x02; // PCI_status_devsel_medium - pci_conf[0x4c] =3D 0x4d; - pci_conf[0x4e] =3D 0x03; - pci_conf[0x4f] =3D 0x00; - pci_conf[0x60] =3D 0x80; - pci_conf[0x61] =3D 0x80; - pci_conf[0x62] =3D 0x80; - pci_conf[0x63] =3D 0x80; - pci_conf[0x69] =3D 0x02; - pci_conf[0x70] =3D 0x80; - pci_conf[0x76] =3D 0x0c; - pci_conf[0x77] =3D 0x0c; - pci_conf[0x78] =3D 0x02; - pci_conf[0x79] =3D 0x00; - pci_conf[0x80] =3D 0x00; - pci_conf[0x82] =3D 0x00; - pci_conf[0xa0] =3D 0x08; - pci_conf[0xa2] =3D 0x00; - pci_conf[0xa3] =3D 0x00; - pci_conf[0xa4] =3D 0x00; - pci_conf[0xa5] =3D 0x00; - pci_conf[0xa6] =3D 0x00; - pci_conf[0xa7] =3D 0x00; - pci_conf[0xa8] =3D 0x0f; - pci_conf[0xaa] =3D 0x00; - pci_conf[0xab] =3D 0x00; - pci_conf[0xac] =3D 0x00; - pci_conf[0xae] =3D 0x00; - - d->pic_levels =3D 0; /* not used in PIIX4 */ - d->rcr =3D 0; -} - -static int piix4_post_load(void *opaque, int version_id) -{ - PIIXState *s =3D opaque; - - if (version_id =3D=3D 2) { - s->rcr =3D 0; - } - - return 0; -} - -static const VMStateDescription vmstate_piix4 =3D { - .name =3D "PIIX4", - .version_id =3D 3, - .minimum_version_id =3D 2, - .post_load =3D piix4_post_load, - .fields =3D (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIXState), - VMSTATE_UINT8_V(rcr, PIIXState, 3), - VMSTATE_END_OF_LIST() - } -}; - -static void rcr_write(void *opaque, hwaddr addr, uint64_t val, - unsigned int len) -{ - PIIXState *s =3D opaque; - - if (val & 4) { - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); - return; - } - - s->rcr =3D val & 2; /* keep System Reset type only */ -} - -static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned int len) -{ - PIIXState *s =3D opaque; - - return s->rcr; -} - -static const MemoryRegionOps rcr_ops =3D { - .read =3D rcr_read, - .write =3D rcr_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, - .impl =3D { - .min_access_size =3D 1, - .max_access_size =3D 1, - }, -}; - -static void piix4_realize(PCIDevice *dev, Error **errp) -{ - PIIXState *s =3D PIIX_PCI_DEVICE(dev); - PCIBus *pci_bus =3D pci_get_bus(dev); - ISABus *isa_bus; - - isa_bus =3D isa_bus_new(DEVICE(dev), pci_address_space(dev), - pci_address_space_io(dev), errp); - if (!isa_bus) { - return; - } - - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, - "reset-control", 1); - memory_region_add_subregion_overlap(pci_address_space_io(dev), - PIIX_RCR_IOPORT, &s->rcr_mem, 1); - - /* initialize i8259 pic */ - if (!qdev_realize(DEVICE(&s->pic), NULL, errp)) { - return; - } - - /* initialize ISA irqs */ - isa_bus_irqs(isa_bus, s->pic.in_irqs); - - /* initialize pit */ - i8254_pit_init(isa_bus, 0x40, 0, NULL); - - /* DMA */ - i8257_dma_init(isa_bus, 0); - - /* RTC */ - qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); - if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { - return; - } - s->rtc.irq =3D qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); - - /* IDE */ - qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); - if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { - return; - } - - /* USB */ - if (s->has_usb) { - object_initialize_child(OBJECT(dev), "uhci", &s->uhci, - TYPE_PIIX4_USB_UHCI); - qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); - if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { - return; - } - } - - /* ACPI controller */ - if (s->has_acpi) { - object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); - qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); - qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base= ); - qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); - if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { - return; - } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, - qdev_get_gpio_in(DEVICE(&s->pic), 9)); - } - - pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); -} - -static void piix4_init(Object *obj) -{ - PIIXState *s =3D PIIX_PCI_DEVICE(obj); - - object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); - object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); - object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); -} - -static Property piix4_props[] =3D { - DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0), - DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true), - DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), - DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), - DEFINE_PROP_END_OF_LIST(), -}; - -static void piix4_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); - - k->realize =3D piix4_realize; - k->vendor_id =3D PCI_VENDOR_ID_INTEL; - k->device_id =3D PCI_DEVICE_ID_INTEL_82371AB_0; - k->class_id =3D PCI_CLASS_BRIDGE_ISA; - dc->reset =3D piix4_isa_reset; - dc->desc =3D "ISA bridge"; - dc->vmsd =3D &vmstate_piix4; - /* - * Reason: part of PIIX4 southbridge, needs to be wired up, - * e.g. by mips_malta_init() - */ - dc->user_creatable =3D false; - dc->hotpluggable =3D false; - device_class_set_props(dc, piix4_props); -} - -static const TypeInfo piix4_info =3D { - .name =3D TYPE_PIIX4_PCI_DEVICE, - .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PIIXState), - .instance_init =3D piix4_init, - .class_init =3D piix4_class_init, - .interfaces =3D (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, -}; - -static void piix4_register_types(void) -{ - type_register_static(&piix4_info); -} - -type_init(piix4_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index 7a40d4d865..569042c3a1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1236,7 +1236,7 @@ Malta M: Philippe Mathieu-Daud=C3=A9 R: Aurelien Jarno S: Odd Fixes -F: hw/isa/piix4.c +F: hw/isa/piix.c F: hw/acpi/piix4.c F: hw/mips/malta.c F: hw/mips/gt64xxx_pci.c @@ -1654,7 +1654,7 @@ F: hw/pci-host/pam.c F: include/hw/pci-host/i440fx.h F: include/hw/pci-host/q35.h F: include/hw/pci-host/pam.h -F: hw/isa/piix3.c +F: hw/isa/piix.c F: hw/isa/lpc_ich9.c F: hw/i2c/smbus_ich9.c F: hw/acpi/piix4.c @@ -2344,7 +2344,7 @@ PIIX4 South Bridge (i82371AB) M: Herv=C3=A9 Poussineau M: Philippe Mathieu-Daud=C3=A9 S: Maintained -F: hw/isa/piix4.c +F: hw/isa/piix.c F: include/hw/southbridge/piix.h =20 Firmware configuration (fw_cfg) diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index 39a35467ca..15442ddbdf 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -74,7 +74,7 @@ config I440FX select ACPI_SMBUS select I8259 select PCI_I440FX - select PIIX3 + select PIIX select DIMM select SMBIOS select FW_CFG_DMA diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 497cc29beb..847d20423a 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -31,17 +31,7 @@ config PC87312 select FDC_ISA select IDE_ISA =20 -config PIIX3 - bool - select ACPI_PIIX4 - select I8257 - select I8259 - select IDE_PIIX - select ISA_BUS - select MC146818RTC - select USB_UHCI - -config PIIX4 +config PIIX bool # For historical reasons, SuperIO devices are created in the board # for PIIX4. diff --git a/hw/isa/meson.build b/hw/isa/meson.build index 8bf678ca0a..314bbd0860 100644 --- a/hw/isa/meson.build +++ b/hw/isa/meson.build @@ -3,8 +3,7 @@ softmmu_ss.add(when: 'CONFIG_I82378', if_true: files('i8237= 8.c')) softmmu_ss.add(when: 'CONFIG_ISA_BUS', if_true: files('isa-bus.c')) softmmu_ss.add(when: 'CONFIG_ISA_SUPERIO', if_true: files('isa-superio.c')) softmmu_ss.add(when: 'CONFIG_PC87312', if_true: files('pc87312.c')) -softmmu_ss.add(when: 'CONFIG_PIIX3', if_true: files('piix3.c')) -softmmu_ss.add(when: 'CONFIG_PIIX4', if_true: files('piix4.c')) +softmmu_ss.add(when: 'CONFIG_PIIX', if_true: files('piix.c')) softmmu_ss.add(when: 'CONFIG_SMC37C669', if_true: files('smc37c669-superio= .c')) softmmu_ss.add(when: 'CONFIG_VT82C686', if_true: files('vt82c686.c')) =20 diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index d156de812c..5b16ff4ed2 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -2,7 +2,7 @@ config MALTA bool select I8259 select ISA_SUPERIO - select PIIX4 + select PIIX =20 config MIPSSIM bool --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 27/31] hw/isa/piix: Harmonize names of reset control memory regions Date: Thu, 5 Jan 2023 15:32:24 +0100 Message-Id: <20230105143228.244965-28-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=shentey@gmail.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929821464100005 There is no need for having different names here. Having the same name further allows code to be shared between PIIX3 and PIIX4. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-38-shentey@gmail.com> --- hw/isa/piix.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 81cb4e64ab..d8cd80e859 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -351,7 +351,7 @@ static void pci_piix3_realize(PCIDevice *dev, Error **e= rrp) isa_bus_irqs(isa_bus, d->pic.in_irqs); =20 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, - "piix3-reset-control", 1); + "piix-reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &d->rcr_mem, 1); =20 @@ -547,7 +547,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) } =20 memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, - "reset-control", 1); + "piix-reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &s->rcr_mem, 1); =20 --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929289; cv=none; d=zohomail.com; s=zohoarc; b=GLQsjIPGyMzDgiM2m5E2h2h3F5RspB6mwOFPTUWqw4xh12Nzb+p9TcQDaQGYHi2JkZtzKqf6aoz+wPRxg40m74rfNEbNP1+7+sfk/pCWUiUVFuSb0igcMBP6iSNYGiE2s+Aw5pFRqC33GJZaI9BbMCw543u7iN9ESXx5riN8xBs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672929289; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OKI3pQf10L0CafJmgzqflOFdUTw3VE2jrgkDejTMPzM=; b=iwrmNXmAy9u+f9k+9PzfOkhtO6lQ0viRcPt2Z9oirt/MULH1KK5RUpDK+qhif/M6FZzjTlsw4DqKV18r3rFhY+LIYFgEZnNhwX0mv7vN0IxjXZygAGyZr6gWr22iTZ11kifN4WekmxCxKGytpAZubmHflzPHfoyJTFy8jUN5ucU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167292928947859.43122863501162; Thu, 5 Jan 2023 06:34:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDRJS-00036L-Vk; Thu, 05 Jan 2023 09:33:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDRJN-0002y4-KK; Thu, 05 Jan 2023 09:33:41 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDRJL-0006xI-HU; Thu, 05 Jan 2023 09:33:41 -0500 Received: by mail-wr1-x432.google.com with SMTP id az7so11916972wrb.5; Thu, 05 Jan 2023 06:33:38 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 28/31] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 Date: Thu, 5 Jan 2023 15:32:25 +0100 Message-Id: <20230105143228.244965-29-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=shentey@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929370153100003 Content-Type: text/plain; charset="utf-8" Resolves duplicate code. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-39-shentey@gmail.com> --- hw/isa/piix.c | 65 +++++++-------------------------------------------- 1 file changed, 9 insertions(+), 56 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index d8cd80e859..0132f6e70a 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -331,7 +331,8 @@ static const MemoryRegionOps rcr_ops =3D { }, }; =20 -static void pci_piix3_realize(PCIDevice *dev, Error **errp) +static void pci_piix_realize(PCIDevice *dev, const char *uhci_type, + Error **errp) { PIIXState *d =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); @@ -371,8 +372,7 @@ static void pci_piix3_realize(PCIDevice *dev, Error **e= rrp) =20 /* USB */ if (d->has_usb) { - object_initialize_child(OBJECT(dev), "uhci", &d->uhci, - TYPE_PIIX3_USB_UHCI); + object_initialize_child(OBJECT(dev), "uhci", &d->uhci, uhci_type); qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2); if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) { return; @@ -477,7 +477,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp) PIIXState *piix3 =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); =20 - pci_piix3_realize(dev, errp); + pci_piix_realize(dev, TYPE_PIIX3_USB_UHCI, errp); if (*errp) { return; } @@ -506,7 +506,7 @@ static void piix3_xen_realize(PCIDevice *dev, Error **e= rrp) PIIXState *piix3 =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); =20 - pci_piix3_realize(dev, errp); + pci_piix_realize(dev, TYPE_PIIX3_USB_UHCI, errp); if (*errp) { return; } @@ -536,71 +536,24 @@ static const TypeInfo piix3_xen_info =3D { =20 static void piix4_realize(PCIDevice *dev, Error **errp) { + ERRP_GUARD(); PIIXState *s =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); ISABus *isa_bus; =20 - isa_bus =3D isa_bus_new(DEVICE(dev), pci_address_space(dev), - pci_address_space_io(dev), errp); - if (!isa_bus) { - return; - } - - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, - "piix-reset-control", 1); - memory_region_add_subregion_overlap(pci_address_space_io(dev), - PIIX_RCR_IOPORT, &s->rcr_mem, 1); - - /* initialize i8259 pic */ - if (!qdev_realize(DEVICE(&s->pic), NULL, errp)) { + pci_piix_realize(dev, TYPE_PIIX4_USB_UHCI, errp); + if (*errp) { return; } =20 - /* initialize ISA irqs */ - isa_bus_irqs(isa_bus, s->pic.in_irqs); + isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(dev), "isa.0")); =20 /* initialize pit */ i8254_pit_init(isa_bus, 0x40, 0, NULL); =20 - /* DMA */ - i8257_dma_init(isa_bus, 0); - /* RTC */ - qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); - if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { - return; - } s->rtc.irq =3D qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); =20 - /* IDE */ - qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); - if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { - return; - } - - /* USB */ - if (s->has_usb) { - object_initialize_child(OBJECT(dev), "uhci", &s->uhci, - TYPE_PIIX4_USB_UHCI); - qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); - if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { - return; - } - } - - /* ACPI controller */ - if (s->has_acpi) { - object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); - qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); - qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base= ); - qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); - if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { - return; - } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, - qdev_get_gpio_in(DEVICE(&s->pic), 9)); - } - pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); } =20 --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929797; cv=none; d=zohomail.com; s=zohoarc; b=lrfj1JviTsMp7734WOy2VCk8AS/ZmJCvN1xOHoTZFsL+dLZ2InuE0spG2Ne6FbKufzpLvmpMlzcfwn014A+26/Lt+2ggTXy5UWhaDA2f4UAsOXw+4YhjYixSqLAkdWl543m1amYSi9qJ9mdooGqGJYJ75jPLQ9vIS9AHaLAhHXc= ARC-Message-Signature: i=1; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 29/31] hw/isa/piix: Rename functions to be shared for interrupt triggering Date: Thu, 5 Jan 2023 15:32:26 +0100 Message-Id: <20230105143228.244965-30-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=shentey@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929799520100001 Content-Type: text/plain; charset="utf-8" PIIX4 will get the same optimizations which are already implemented for PIIX3. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-40-shentey@gmail.com> --- hw/isa/piix.c | 56 +++++++++++++++++++++++++-------------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 0132f6e70a..33ea5275ec 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -40,47 +40,47 @@ =20 #define XEN_PIIX_NUM_PIRQS 128ULL =20 -static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq) +static void piix_set_irq_pic(PIIXState *piix, int pic_irq) { - qemu_set_irq(piix3->pic.in_irqs[pic_irq], - !!(piix3->pic_levels & + qemu_set_irq(piix->pic.in_irqs[pic_irq], + !!(piix->pic_levels & (((1ULL << PIIX_NUM_PIRQS) - 1) << (pic_irq * PIIX_NUM_PIRQS)))); } =20 -static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int l= evel) +static void piix_set_irq_level_internal(PIIXState *piix, int pirq, int lev= el) { int pic_irq; uint64_t mask; =20 - pic_irq =3D piix3->dev.config[PIIX_PIRQCA + pirq]; + pic_irq =3D piix->dev.config[PIIX_PIRQCA + pirq]; if (pic_irq >=3D ISA_NUM_IRQS) { return; } =20 mask =3D 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); - piix3->pic_levels &=3D ~mask; - piix3->pic_levels |=3D mask * !!level; + piix->pic_levels &=3D ~mask; + piix->pic_levels |=3D mask * !!level; } =20 -static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level) +static void piix_set_irq_level(PIIXState *piix, int pirq, int level) { int pic_irq; =20 - pic_irq =3D piix3->dev.config[PIIX_PIRQCA + pirq]; + pic_irq =3D piix->dev.config[PIIX_PIRQCA + pirq]; if (pic_irq >=3D ISA_NUM_IRQS) { return; } =20 - piix3_set_irq_level_internal(piix3, pirq, level); + piix_set_irq_level_internal(piix, pirq, level); =20 - piix3_set_irq_pic(piix3, pic_irq); + piix_set_irq_pic(piix, pic_irq); } =20 -static void piix3_set_irq(void *opaque, int pirq, int level) +static void piix_set_irq(void *opaque, int pirq, int level) { - PIIXState *piix3 =3D opaque; - piix3_set_irq_level(piix3, pirq, level); + PIIXState *piix =3D opaque; + piix_set_irq_level(piix, pirq, level); } =20 static void piix4_set_irq(void *opaque, int irq_num, int level) @@ -121,29 +121,29 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void = *opaque, int pin) } =20 /* irq routing is changed. so rebuild bitmap */ -static void piix3_update_irq_levels(PIIXState *piix3) +static void piix_update_irq_levels(PIIXState *piix) { - PCIBus *bus =3D pci_get_bus(&piix3->dev); + PCIBus *bus =3D pci_get_bus(&piix->dev); int pirq; =20 - piix3->pic_levels =3D 0; + piix->pic_levels =3D 0; for (pirq =3D 0; pirq < PIIX_NUM_PIRQS; pirq++) { - piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq)); + piix_set_irq_level(piix, pirq, pci_bus_get_irq_level(bus, pirq)); } } =20 -static void piix3_write_config(PCIDevice *dev, - uint32_t address, uint32_t val, int len) +static void piix_write_config(PCIDevice *dev, uint32_t address, uint32_t v= al, + int len) { pci_default_write_config(dev, address, val, len); if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { - PIIXState *piix3 =3D PIIX_PCI_DEVICE(dev); + PIIXState *piix =3D PIIX_PCI_DEVICE(dev); int pic_irq; =20 - pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); - piix3_update_irq_levels(piix3); + pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix->dev)); + piix_update_irq_levels(piix); for (pic_irq =3D 0; pic_irq < ISA_NUM_IRQS; pic_irq++) { - piix3_set_irq_pic(piix3, pic_irq); + piix_set_irq_pic(piix, pic_irq); } } } @@ -165,7 +165,7 @@ static void piix3_write_config_xen(PCIDevice *dev, } } =20 - piix3_write_config(dev, address, val, len); + piix_write_config(dev, address, val, len); } =20 static void piix_reset(DeviceState *dev) @@ -225,7 +225,7 @@ static int piix3_post_load(void *opaque, int version_id) */ piix3->pic_levels =3D 0; for (pirq =3D 0; pirq < PIIX_NUM_PIRQS; pirq++) { - piix3_set_irq_level_internal(piix3, pirq, + piix_set_irq_level_internal(piix3, pirq, pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq)); } return 0; @@ -482,7 +482,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp) return; } =20 - pci_bus_irqs(pci_bus, piix3_set_irq, piix3, PIIX_NUM_PIRQS); + pci_bus_irqs(pci_bus, piix_set_irq, piix3, PIIX_NUM_PIRQS); pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); } =20 @@ -490,7 +490,7 @@ static void piix3_class_init(ObjectClass *klass, void *= data) { PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 - k->config_write =3D piix3_write_config; + k->config_write =3D piix_write_config; k->realize =3D piix3_realize; } =20 --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929446; cv=none; d=zohomail.com; s=zohoarc; b=ksTdBlEVyv1IiKAXLh1AR8Uyk0FRYIVVKeXvxiev5qwflnsBNleqw0y1OX2ARhHqIqs4w2Fgr1X2qZK63FVvhOAWkYWxHmY9naTfxy3DWlWlkFPTRRsgvx0fVfiUWqIMeu7++YicD+RBt+QlUioOYtgYHxUjoDV9RCHWW6W39YE= ARC-Message-Signature: i=1; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PATCH v5 30/31] hw/isa/piix: Consolidate IRQ triggering Date: Thu, 5 Jan 2023 15:32:27 +0100 Message-Id: <20230105143228.244965-31-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=shentey@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929447770100001 Content-Type: text/plain; charset="utf-8" Speeds up PIIX4 which resolves an old TODO. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20221022150508.26830-41-shentey@gmail.com> --- hw/isa/piix.c | 26 +++----------------------- 1 file changed, 3 insertions(+), 23 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 33ea5275ec..f125a6175f 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -83,27 +83,6 @@ static void piix_set_irq(void *opaque, int pirq, int lev= el) piix_set_irq_level(piix, pirq, level); } =20 -static void piix4_set_irq(void *opaque, int irq_num, int level) -{ - int i, pic_irq, pic_level; - PIIXState *s =3D opaque; - PCIBus *bus =3D pci_get_bus(&s->dev); - - /* now we change the pic irq level according to the piix irq mappings = */ - /* XXX: optimize */ - pic_irq =3D s->dev.config[PIIX_PIRQCA + irq_num]; - if (pic_irq < ISA_NUM_IRQS) { - /* The pic level is the logical OR of all the PCI irqs mapped to i= t. */ - pic_level =3D 0; - for (i =3D 0; i < PIIX_NUM_PIRQS; i++) { - if (pic_irq =3D=3D s->dev.config[PIIX_PIRQCA + i]) { - pic_level |=3D pci_bus_get_irq_level(bus, i); - } - } - qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); - } -} - static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { PIIXState *piix3 =3D opaque; @@ -239,7 +218,7 @@ static int piix4_post_load(void *opaque, int version_id) s->rcr =3D 0; } =20 - return 0; + return piix3_post_load(opaque, version_id); } =20 static int piix3_pre_save(void *opaque) @@ -554,7 +533,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) /* RTC */ s->rtc.irq =3D qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); =20 - pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); + pci_bus_irqs(pci_bus, piix_set_irq, s, PIIX_NUM_PIRQS); } =20 static void piix4_init(Object *obj) @@ -571,6 +550,7 @@ static void piix4_class_init(ObjectClass *klass, void *= data) DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 + k->config_write =3D piix_write_config; k->realize =3D piix4_realize; k->vendor_id =3D PCI_VENDOR_ID_INTEL; k->device_id =3D PCI_DEVICE_ID_INTEL_82371AB_0; --=20 2.39.0 From nobody Thu May 16 21:43:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1672929367; cv=none; d=zohomail.com; s=zohoarc; b=asqP4WTbJ17GYZb3rAxbkwz1jmHOyV+ETidctXTznZVr4o/6SESsxsYQdIsO+yNCknAo6/C7XKqJuMEx4XrVHg2quSi4sD8LJAPKwvKJxEjrssNIwj29GiWoYPqjMW3nuD6HB0R2HYZ0CetHO/TG63Iy0XQHwqg1bFnmBqreYP0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672929367; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dn+yeGFQIMdJW7Gi0bvDMswZATWnQh3mXrYoXnwfAnI=; b=G5/Q7V5RWDeDEEpx1zumV3KA0wtkdfoVeVpGGBZhSdU1YwHLUT44RIrKVxJfXmDH2JNPjwG1EhPHbc0gLFTv1Phucldd96a6J7ItY1/LVNy4FCSUfqpc5eCWOfwK4hV1slM1rUNpWV6CuednnBxPLhT3eEBH6P+m2sM5oLuCFbw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672929367233377.67833208253785; Thu, 5 Jan 2023 06:36:07 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDRJU-00038U-IG; Thu, 05 Jan 2023 09:33:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDRJR-00033i-UZ; Thu, 05 Jan 2023 09:33:45 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDRJQ-000765-5d; Thu, 05 Jan 2023 09:33:45 -0500 Received: by mail-wr1-x435.google.com with SMTP id bk16so23104222wrb.11; Thu, 05 Jan 2023 06:33:43 -0800 (PST) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow , Thomas Huth Subject: [PATCH v5 31/31] hw/isa/piix: Share PIIX3's base class with PIIX4 Date: Thu, 5 Jan 2023 15:32:28 +0100 Message-Id: <20230105143228.244965-32-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105143228.244965-1-shentey@gmail.com> References: <20230105143228.244965-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=shentey@gmail.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1672929375970100013 Content-Type: text/plain; charset="utf-8" Having a common base class will allow for substituting PIIX3 with PIIX4 and vice versa. Moreover, it makes PIIX4 implement the acpi-dev-aml-interface. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Reviewed-by: Thomas Huth Message-Id: <20221022150508.26830-42-shentey@gmail.com> --- hw/isa/piix.c | 49 ++++++++++++++++++++++--------------------------- 1 file changed, 22 insertions(+), 27 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index f125a6175f..54a1246a9d 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -396,13 +396,12 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml= *scope) } } =20 -static void pci_piix3_init(Object *obj) +static void pci_piix_init(Object *obj) { PIIXState *d =3D PIIX_PCI_DEVICE(obj); =20 object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); - object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); } =20 static Property pci_piix_props[] =3D { @@ -413,7 +412,7 @@ static Property pci_piix_props[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -static void pci_piix3_class_init(ObjectClass *klass, void *data) +static void pci_piix_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); @@ -421,11 +420,8 @@ static void pci_piix3_class_init(ObjectClass *klass, v= oid *data) =20 dc->reset =3D piix_reset; dc->desc =3D "ISA bridge"; - dc->vmsd =3D &vmstate_piix3; dc->hotpluggable =3D false; k->vendor_id =3D PCI_VENDOR_ID_INTEL; - /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ - k->device_id =3D PCI_DEVICE_ID_INTEL_82371SB_0; k->class_id =3D PCI_CLASS_BRIDGE_ISA; /* * Reason: part of PIIX3 southbridge, needs to be wired up by @@ -440,9 +436,9 @@ static const TypeInfo piix_pci_type_info =3D { .name =3D TYPE_PIIX_PCI_DEVICE, .parent =3D TYPE_PCI_DEVICE, .instance_size =3D sizeof(PIIXState), - .instance_init =3D pci_piix3_init, + .instance_init =3D pci_piix_init, .abstract =3D true, - .class_init =3D pci_piix3_class_init, + .class_init =3D pci_piix_class_init, .interfaces =3D (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, { TYPE_ACPI_DEV_AML_IF }, @@ -465,17 +461,29 @@ static void piix3_realize(PCIDevice *dev, Error **err= p) pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); } =20 +static void piix3_init(Object *obj) +{ + PIIXState *d =3D PIIX_PCI_DEVICE(obj); + + object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); +} + static void piix3_class_init(ObjectClass *klass, void *data) { + DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 k->config_write =3D piix_write_config; k->realize =3D piix3_realize; + /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ + k->device_id =3D PCI_DEVICE_ID_INTEL_82371SB_0; + dc->vmsd =3D &vmstate_piix3; } =20 static const TypeInfo piix3_info =3D { .name =3D TYPE_PIIX3_DEVICE, .parent =3D TYPE_PIIX_PCI_DEVICE, + .instance_init =3D piix3_init, .class_init =3D piix3_class_init, }; =20 @@ -501,15 +509,20 @@ static void piix3_xen_realize(PCIDevice *dev, Error *= *errp) =20 static void piix3_xen_class_init(ObjectClass *klass, void *data) { + DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 k->config_write =3D piix3_write_config_xen; k->realize =3D piix3_xen_realize; + /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ + k->device_id =3D PCI_DEVICE_ID_INTEL_82371SB_0; + dc->vmsd =3D &vmstate_piix3; } =20 static const TypeInfo piix3_xen_info =3D { .name =3D TYPE_PIIX3_XEN_DEVICE, .parent =3D TYPE_PIIX_PCI_DEVICE, + .instance_init =3D piix3_init, .class_init =3D piix3_xen_class_init, }; =20 @@ -540,8 +553,6 @@ static void piix4_init(Object *obj) { PIIXState *s =3D PIIX_PCI_DEVICE(obj); =20 - object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); - object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); } =20 @@ -552,31 +563,15 @@ static void piix4_class_init(ObjectClass *klass, void= *data) =20 k->config_write =3D piix_write_config; k->realize =3D piix4_realize; - k->vendor_id =3D PCI_VENDOR_ID_INTEL; k->device_id =3D PCI_DEVICE_ID_INTEL_82371AB_0; - k->class_id =3D PCI_CLASS_BRIDGE_ISA; - dc->reset =3D piix_reset; - dc->desc =3D "ISA bridge"; dc->vmsd =3D &vmstate_piix4; - /* - * Reason: part of PIIX4 southbridge, needs to be wired up, - * e.g. by mips_malta_init() - */ - dc->user_creatable =3D false; - dc->hotpluggable =3D false; - device_class_set_props(dc, pci_piix_props); } =20 static const TypeInfo piix4_info =3D { .name =3D TYPE_PIIX4_PCI_DEVICE, - .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PIIXState), + .parent =3D TYPE_PIIX_PCI_DEVICE, .instance_init =3D piix4_init, .class_init =3D piix4_class_init, - .interfaces =3D (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, }; =20 static void piix3_register_types(void) --=20 2.39.0