From nobody Sat May 18 23:55:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1672412338; cv=none; d=zohomail.com; s=zohoarc; b=irVfDqwYzyYKifT0CTiVyO/yOj8fbDWIEzuP/hK9RwWQDsUtUCNVJiG2BLsbyWM/TtHDTUBMJy6mHxEMmop1JMgMWl4ZdCPY/X6ezlbRxiMLcAjvmaQpwFwN8DB7B8REcVfq213rnYziux8dn7/s9BwJb6ynXbV035zBfDIfdAk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672412338; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=U/Nk8gJKOu+Wd1xGoiLRIOJEf3ci/5fQf7tVlXDcnaw=; b=J0QAXJU2oOKScRpMXWz/eb7NDN1wCJp5I6Ib+Sp081hU+1rqugWPjJme8e5frmJm8Ssckny4Tnn08wPf+3BwVa8Ttp1lTiE04yb9PTaI/u1/Rtr1mcBGO7Md3N1KkSgAAWEQNHlEB4yQAIdSdrCWHYvLUALCxYJ//yifSxIaaxM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672412338960339.50124856539264; Fri, 30 Dec 2022 06:58:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pBGpY-00006B-Il; Fri, 30 Dec 2022 09:57:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pBGpU-0008WH-Q6; Fri, 30 Dec 2022 09:57:52 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pBGpT-0000V5-7X; Fri, 30 Dec 2022 09:57:52 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D8DF761548; Fri, 30 Dec 2022 14:57:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 77699C433F1; Fri, 30 Dec 2022 14:57:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672412262; bh=8uO/hG+gqxwzfZetPnXbVsoGAJrSaIma2YNzOEHR3wQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CialPsGjCbXsWKbj+Qgd4KYIvd+8eFcpLzAJDbNjQw8s+m2ZnojNepDZhXYFvOi0M 94SML0PzXfaIFH1ZGIMQhO3nCG57IDAjl6H8V7yYu8JH0stscUNZFFxyKHqC+4eUO9 EeeAz2K76YBbG1Bb5G0xIV+CEIQINdX/Bg7EzXp/tdLguKnjjX+sjSqwJSA8rEPwWG n5ViZCdU9xvyaIs4YjgRXYAT5XSH/+3KZDQnHesTgT0b7Y4lHnUGYXai3J+J4ZXRTC V0MCSUglbPamSDcKuQvmly6fk1/VnX3G4pDK5Ceb4Hev2cGJbpNKleAcLGNlxysqBx 4hSs1uAPSEBYg== From: Felipe Balbi To: Alistair Francis , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Felipe Balbi , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/2] hw/arm/stm32f405: correctly describe the memory layout Date: Fri, 30 Dec 2022 16:57:32 +0200 Message-Id: <20221230145733.200496-2-balbi@kernel.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221230145733.200496-1-balbi@kernel.org> References: <20221230145733.200496-1-balbi@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=139.178.84.217; envelope-from=balbi@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1672412339895000001 STM32F405 has 128K of SRAM and another 64K of CCM (Core-coupled Memory) at a different base address. Correctly describe the memory layout to give existing FW images a chance to run unmodified. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Felipe Balbi --- Changes since v1: - None hw/arm/stm32f405_soc.c | 8 ++++++++ include/hw/arm/stm32f405_soc.h | 5 ++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c index c07947d9f8b1..cef23d7ee41a 100644 --- a/hw/arm/stm32f405_soc.c +++ b/hw/arm/stm32f405_soc.c @@ -139,6 +139,14 @@ static void stm32f405_soc_realize(DeviceState *dev_soc= , Error **errp) } memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram= ); =20 + memory_region_init_ram(&s->ccm, NULL, "STM32F405.ccm", CCM_SIZE, + &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(system_memory, CCM_BASE_ADDRESS, &s->ccm); + armv7m =3D DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h index 5bb0c8d56979..249ab5434ec7 100644 --- a/include/hw/arm/stm32f405_soc.h +++ b/include/hw/arm/stm32f405_soc.h @@ -46,7 +46,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC) #define FLASH_BASE_ADDRESS 0x08000000 #define FLASH_SIZE (1024 * 1024) #define SRAM_BASE_ADDRESS 0x20000000 -#define SRAM_SIZE (192 * 1024) +#define SRAM_SIZE (128 * 1024) +#define CCM_BASE_ADDRESS 0x10000000 +#define CCM_SIZE (64 * 1024) =20 struct STM32F405State { /*< private >*/ @@ -65,6 +67,7 @@ struct STM32F405State { STM32F2XXADCState adc[STM_NUM_ADCS]; STM32F2XXSPIState spi[STM_NUM_SPIS]; =20 + MemoryRegion ccm; MemoryRegion sram; MemoryRegion flash; MemoryRegion flash_alias; --=20 2.39.0 From nobody Sat May 18 23:55:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1672412347; cv=none; d=zohomail.com; s=zohoarc; b=oJCBk+lmu4H/U10muH5GMhtjq8HdWNRjtX6uzzxB9W6zDC8QtYOH6TwH//QT6lKP733qSPkqQJeHHT82JrIsSAS/a6kYAR6uzEk6LFdQRvIky+PzfC2X1XrJKSssS0EHni6K7fKEX4y/yPmgWyGUeyF73Kt+2NnYfhv65mMElQg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672412347; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iEd3eL+4m8ejz8U5TPHg82yUGGKwxGRJZ7d//uQuNiY=; b=eyIuwpB+iRiM6qbUMVM2aD3jCx/+uHdl8Jd3PeFHOWpkam1XvUPSlc44IK2WSVmamMg95RwPfh89qaRt8J8XbWjvvs53/sc+HhWoLEWZndmNrHvdaqF57uCd4+MarwU/eZdENQZZE/AlfECZlV/Qi1EB7OyyMbZecOABFyRgoJ0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167241234714461.240881278679694; Fri, 30 Dec 2022 06:59:07 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pBGpY-00006E-Jk; Fri, 30 Dec 2022 09:57:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pBGpX-00005Y-9B; Fri, 30 Dec 2022 09:57:55 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pBGpV-0000VQ-91; Fri, 30 Dec 2022 09:57:54 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0322761229; Fri, 30 Dec 2022 14:57:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C574EC433D2; Fri, 30 Dec 2022 14:57:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672412264; bh=tS1h+RoInBuflihKgL7AEisEZQke6048q0BOPbzTk28=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=H/YDJs/0tRksxxgYWrx6CSptYarZGcHcbg+yglZpSMpRGuBnK5zVBS7pNIEUWb7Of 1JQflovmgm8BEalWcic5+cC5YqN4RP89mE6/umc9J9UfDIyTG+753mptA7/6pyxaKv N4ytSqr6TQ3QSLzDDZVF2KHv5nEIAdU1LJpiar2no9aUbDNznQlpYoCCwOGAOOyw/3 jkRN48PklCHk9FDT/dg0SGAe3m2kx4PbtrjhKo59OEIAnXzehqTeJVJ3VpDFBC8r3a qCf3RCBSbWTXJTPmaRvRxbPioJ2hu11wf0zBKonHGDlsHFsLzgWgUcyYKYmXXpRIoY 7CVP6dCLjnjnw== From: Felipe Balbi To: Alistair Francis , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Felipe Balbi Subject: [PATCH v2 2/2] hw/arm: Add Olimex H405 Date: Fri, 30 Dec 2022 16:57:33 +0200 Message-Id: <20221230145733.200496-3-balbi@kernel.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221230145733.200496-1-balbi@kernel.org> References: <20221230145733.200496-1-balbi@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=139.178.84.217; envelope-from=balbi@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1672412347911000003 Content-Type: text/plain; charset="utf-8" Olimex makes a series of low-cost STM32 boards. This commit introduces the minimum setup to support SMT32-H405. See [1] for details [1] https://www.olimex.com/Products/ARM/ST/STM32-H405/ Signed-off-by: Felipe Balbi Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Changes since v1: - Add a note in stm32.rst - Initialize default_cpu_type to cortex-m4 - 0-initialize default_ram_size MAINTAINERS | 6 +++ configs/devices/arm-softmmu/default.mak | 1 + docs/system/arm/stm32.rst | 1 + hw/arm/Kconfig | 4 ++ hw/arm/meson.build | 1 + hw/arm/olimex-stm32-h405.c | 69 +++++++++++++++++++++++++ 6 files changed, 82 insertions(+) create mode 100644 hw/arm/olimex-stm32-h405.c diff --git a/MAINTAINERS b/MAINTAINERS index 3bd433b65a55..e37846df0071 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1026,6 +1026,12 @@ L: qemu-arm@nongnu.org S: Maintained F: hw/arm/netduinoplus2.c =20 +Olimex STM32 H405 +M: Felipe Balbi +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/olimex-stm32-h405.c + SmartFusion2 M: Subbaraya Sundeep M: Peter Maydell diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-= softmmu/default.mak index 6985a25377a0..1b49a7830c7e 100644 --- a/configs/devices/arm-softmmu/default.mak +++ b/configs/devices/arm-softmmu/default.mak @@ -30,6 +30,7 @@ CONFIG_COLLIE=3Dy CONFIG_ASPEED_SOC=3Dy CONFIG_NETDUINO2=3Dy CONFIG_NETDUINOPLUS2=3Dy +CONFIG_OLIMEX_STM32_H405=3Dy CONFIG_MPS2=3Dy CONFIG_RASPI=3Dy CONFIG_DIGIC=3Dy diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst index 508b92cf862b..d7265b763d47 100644 --- a/docs/system/arm/stm32.rst +++ b/docs/system/arm/stm32.rst @@ -20,6 +20,7 @@ The STM32F4 series is based on ARM Cortex-M4F core. This = series is pin-to-pin compatible with STM32F2 series. The following machines are based on this c= hip : =20 - ``netduinoplus2`` Netduino Plus 2 board with STM32F405RGT6 microcont= roller +- ``olimex-stm32-h405`` Olimex STM32 H405 board with STM32F405RGT6 microco= ntroller =20 There are many other STM32 series that are currently not supported by QEMU. =20 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 17fcde8e1ccc..9143533ef792 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -119,6 +119,10 @@ config NETDUINOPLUS2 bool select STM32F405_SOC =20 +config OLIMEX_STM32_H405 + bool + select STM32F405_SOC + config NSERIES bool select OMAP diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 92f9f6e000ea..76d4d650e42e 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -12,6 +12,7 @@ arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('micro= bit.c')) arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c')) arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) +arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-= h405.c')) arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_bo= ards.c')) arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c')) arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c')) diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c new file mode 100644 index 000000000000..3aa61c91b759 --- /dev/null +++ b/hw/arm/olimex-stm32-h405.c @@ -0,0 +1,69 @@ +/* + * ST STM32VLDISCOVERY machine + * Olimex STM32-H405 machine + * + * Copyright (c) 2022 Felipe Balbi + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" +#include "qemu/error-report.h" +#include "hw/arm/stm32f405_soc.h" +#include "hw/arm/boot.h" + +/* olimex-stm32-h405 implementation is derived from netduinoplus2 */ + +/* Main SYSCLK frequency in Hz (168MHz) */ +#define SYSCLK_FRQ 168000000ULL + +static void olimex_stm32_h405_init(MachineState *machine) +{ + DeviceState *dev; + Clock *sysclk; + + /* This clock doesn't need migration because it is fixed-frequency */ + sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(sysclk, SYSCLK_FRQ); + + dev =3D qdev_new(TYPE_STM32F405_SOC); + qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); + qdev_connect_clock_in(dev, "sysclk", sysclk); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + armv7m_load_kernel(ARM_CPU(first_cpu), + machine->kernel_filename, + 0, FLASH_SIZE); +} + +static void olimex_stm32_h405_machine_init(MachineClass *mc) +{ + mc->desc =3D "Olimex STM32-H405 (Cortex-M4)"; + mc->init =3D olimex_stm32_h405_init; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m4"); + + /* SRAM pre-allocated as part of the SoC instantiation */ + mc->default_ram_size =3D 0; +} + +DEFINE_MACHINE("olimex-stm32-h405", olimex_stm32_h405_machine_init) --=20 2.39.0