From nobody Thu Oct 31 23:59:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167239448895350.80650073597553; Fri, 30 Dec 2022 02:01:28 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pBCBI-0003kw-3v; Fri, 30 Dec 2022 05:00:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pBCBF-0003j6-ID for qemu-devel@nongnu.org; Fri, 30 Dec 2022 05:00:01 -0500 Received: from mail.loongson.cn ([114.242.206.163] helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pBCBD-0005Rr-Az for qemu-devel@nongnu.org; Fri, 30 Dec 2022 05:00:01 -0500 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8AxuuiXtq5jbnYJAA--.1207S3; Fri, 30 Dec 2022 17:59:51 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxtOWWtq5jCSAQAA--.53838S3; Fri, 30 Dec 2022 17:59:51 +0800 (CST) From: Tianrui Zhao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, maobibo@loongson.cn, philmd@linaro.org Subject: [PATCH v4 1/3] hw/intc/loongarch_pch_msi: add irq number property Date: Fri, 30 Dec 2022 17:59:48 +0800 Message-Id: <20221230095950.2217103-2-zhaotianrui@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221230095950.2217103-1-zhaotianrui@loongson.cn> References: <20221230095950.2217103-1-zhaotianrui@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8BxtOWWtq5jCSAQAA--.53838S3 X-CM-SenderInfo: p2kd03xldq233l6o00pqjv00gofq/ X-Coremail-Antispam: 1Uk129KBjvJXoW3XF43WF48Wr1xGF4fur1Dtrb_yoW7GFy5pr WDuFy5tr48Gw4UuFZ3G347ur98JFn7GFyIvF43KryxCr4UAr90q3WkJ39rWF1UK3yrGryq v34kCa9rW3WUCaDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bn8Fc2x0x2IEx4CE42xK8VAvwI8IcIk0rVWrJVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4 AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF 7I0E14v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7 CjxVAFwI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2 zVCFFI0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VCjz48v1sIEY20_WwAm72CE4IkC6x 0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2Ij64vIr41l42xK82IY6x8ErcxF aVAv8VWrMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxV Cjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY 6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6x AIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY 1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvj4RC_MaUUUUU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=zhaotianrui@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1672394493234000001 Content-Type: text/plain; charset="utf-8" This patch adds irq number property for loongarch msi interrupt controller, and remove hard coding irq number macro. Signed-off-by: Tianrui Zhao Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/loongarch_pch_msi.c | 33 ++++++++++++++++++++++++++--- hw/loongarch/virt.c | 13 +++++++----- include/hw/intc/loongarch_pch_msi.h | 3 ++- include/hw/pci-host/ls7a.h | 1 - 4 files changed, 40 insertions(+), 10 deletions(-) diff --git a/hw/intc/loongarch_pch_msi.c b/hw/intc/loongarch_pch_msi.c index b36d6d76e4..09d3890ade 100644 --- a/hw/intc/loongarch_pch_msi.c +++ b/hw/intc/loongarch_pch_msi.c @@ -32,7 +32,7 @@ static void loongarch_msi_mem_write(void *opaque, hwaddr = addr, */ irq_num =3D (val & 0xff) - s->irq_base; trace_loongarch_msi_set_irq(irq_num); - assert(irq_num < PCH_MSI_IRQ_NUM); + assert(irq_num < s->irq_num); qemu_set_irq(s->pch_msi_irq[irq_num], 1); } =20 @@ -49,6 +49,32 @@ static void pch_msi_irq_handler(void *opaque, int irq, i= nt level) qemu_set_irq(s->pch_msi_irq[irq], level); } =20 +static void loongarch_pch_msi_realize(DeviceState *dev, Error **errp) +{ + LoongArchPCHMSI *s =3D LOONGARCH_PCH_MSI(dev); + + if (!s->irq_num || s->irq_num > PCH_MSI_IRQ_NUM) { + error_setg(errp, "Invalid 'msi_irq_num'"); + return; + } + + s->pch_msi_irq =3D g_new(qemu_irq, s->irq_num); + if (!s->pch_msi_irq) { + error_report("loongarch_pch_msi: fail to alloc memory"); + exit(1); + } + + qdev_init_gpio_out(dev, s->pch_msi_irq, s->irq_num); + qdev_init_gpio_in(dev, pch_msi_irq_handler, s->irq_num); +} + +static void loongarch_pch_msi_unrealize(DeviceState *dev) +{ + LoongArchPCHMSI *s =3D LOONGARCH_PCH_MSI(dev); + + g_free(s->pch_msi_irq); +} + static void loongarch_pch_msi_init(Object *obj) { LoongArchPCHMSI *s =3D LOONGARCH_PCH_MSI(obj); @@ -59,12 +85,11 @@ static void loongarch_pch_msi_init(Object *obj) sysbus_init_mmio(sbd, &s->msi_mmio); msi_nonbroken =3D true; =20 - qdev_init_gpio_out(DEVICE(obj), s->pch_msi_irq, PCH_MSI_IRQ_NUM); - qdev_init_gpio_in(DEVICE(obj), pch_msi_irq_handler, PCH_MSI_IRQ_NUM); } =20 static Property loongarch_msi_properties[] =3D { DEFINE_PROP_UINT32("msi_irq_base", LoongArchPCHMSI, irq_base, 0), + DEFINE_PROP_UINT32("msi_irq_num", LoongArchPCHMSI, irq_num, 0), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -72,6 +97,8 @@ static void loongarch_pch_msi_class_init(ObjectClass *kla= ss, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + dc->realize =3D loongarch_pch_msi_realize; + dc->unrealize =3D loongarch_pch_msi_unrealize; device_class_set_props(dc, loongarch_msi_properties); } =20 diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 958be74fa1..1e58346aeb 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -496,7 +496,7 @@ static void loongarch_irq_init(LoongArchMachineState *l= ams) LoongArchCPU *lacpu; CPULoongArchState *env; CPUState *cpu_state; - int cpu, pin, i; + int cpu, pin, i, start, num; =20 ipi =3D qdev_new(TYPE_LOONGARCH_IPI); sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); @@ -576,14 +576,17 @@ static void loongarch_irq_init(LoongArchMachineState = *lams) } =20 pch_msi =3D qdev_new(TYPE_LOONGARCH_PCH_MSI); - qdev_prop_set_uint32(pch_msi, "msi_irq_base", PCH_MSI_IRQ_START); + start =3D PCH_PIC_IRQ_NUM; + num =3D EXTIOI_IRQS - start; + qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); + qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); d =3D SYS_BUS_DEVICE(pch_msi); sysbus_realize_and_unref(d, &error_fatal); sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); - for (i =3D 0; i < PCH_MSI_IRQ_NUM; i++) { - /* Connect 192 pch_msi irqs to extioi */ + for (i =3D 0; i < num; i++) { + /* Connect pch_msi irqs to extioi */ qdev_connect_gpio_out(DEVICE(d), i, - qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_STA= RT)); + qdev_get_gpio_in(extioi, i + start)); } =20 loongarch_devices_init(pch_pic, lams); diff --git a/include/hw/intc/loongarch_pch_msi.h b/include/hw/intc/loongarc= h_pch_msi.h index 6d67560dea..c5a52bc327 100644 --- a/include/hw/intc/loongarch_pch_msi.h +++ b/include/hw/intc/loongarch_pch_msi.h @@ -15,8 +15,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH= _MSI) =20 struct LoongArchPCHMSI { SysBusDevice parent_obj; - qemu_irq pch_msi_irq[PCH_MSI_IRQ_NUM]; + qemu_irq *pch_msi_irq; MemoryRegion msi_mmio; /* irq base passed to upper extioi intc */ unsigned int irq_base; + unsigned int irq_num; }; diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h index df7fa55a30..6443327bd7 100644 --- a/include/hw/pci-host/ls7a.h +++ b/include/hw/pci-host/ls7a.h @@ -34,7 +34,6 @@ */ #define PCH_PIC_IRQ_OFFSET 64 #define VIRT_DEVICE_IRQS 16 -#define VIRT_PCI_IRQS 48 #define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2) #define VIRT_UART_BASE 0x1fe001e0 #define VIRT_UART_SIZE 0X100 --=20 2.31.1 From nobody Thu Oct 31 23:59:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672394459721320.6923923926703; Fri, 30 Dec 2022 02:00:59 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pBCBI-0003kx-5K; Fri, 30 Dec 2022 05:00:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pBCBF-0003ik-04 for qemu-devel@nongnu.org; Fri, 30 Dec 2022 05:00:01 -0500 Received: from mail.loongson.cn ([114.242.206.163] helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pBCBC-0005Ru-Gg for qemu-devel@nongnu.org; Fri, 30 Dec 2022 05:00:00 -0500 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8AxuuiXtq5jcHYJAA--.1209S3; Fri, 30 Dec 2022 17:59:51 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxtOWWtq5jCSAQAA--.53838S4; Fri, 30 Dec 2022 17:59:51 +0800 (CST) From: Tianrui Zhao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, maobibo@loongson.cn, philmd@linaro.org Subject: [PATCH v4 2/3] hw/intc/loongarch_pch_pic: add irq number property Date: Fri, 30 Dec 2022 17:59:49 +0800 Message-Id: <20221230095950.2217103-3-zhaotianrui@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221230095950.2217103-1-zhaotianrui@loongson.cn> References: <20221230095950.2217103-1-zhaotianrui@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8BxtOWWtq5jCSAQAA--.53838S4 X-CM-SenderInfo: p2kd03xldq233l6o00pqjv00gofq/ X-Coremail-Antispam: 1Uk129KBjvJXoW3Ww13tFW8Ar45GF45tw4rAFb_yoW7AF4kpF W7uFW3tF4kJr47Xrn7Z345uwn7JFs29ry29anIkryxCr1DJr98XF1kJw4DXF1UK395Jryq qrZ5CayY93WUJaUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bn8Fc2x0x2IEx4CE42xK8VAvwI8IcIk0rVWrJVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4 AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF 7I0E14v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7 CjxVAFwI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2 zVCFFI0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VCjz48v1sIEY20_WwAm72CE4IkC6x 0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2Ij64vIr41l42xK82IY6x8ErcxF aVAv8VWrMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxV Cjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY 6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6x AIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY 1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvj4RC_MaUUUUU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=zhaotianrui@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1672394461376000001 Content-Type: text/plain; charset="utf-8" With loongarch 7A1000 manual, irq number supported can be set in PCH_PIC_INT_ID_HI register. This patch adds irq number property for loongarch_pch_pic, so that virt machine can set different irq number when pch_pic intc is added. Signed-off-by: Tianrui Zhao --- hw/intc/loongarch_pch_pic.c | 33 +++++++++++++++++++++++++---- hw/loongarch/virt.c | 8 ++++--- include/hw/intc/loongarch_pch_pic.h | 5 ++--- 3 files changed, 36 insertions(+), 10 deletions(-) diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c index 3380b09807..1440195837 100644 --- a/hw/intc/loongarch_pch_pic.c +++ b/hw/intc/loongarch_pch_pic.c @@ -10,8 +10,10 @@ #include "hw/loongarch/virt.h" #include "hw/irq.h" #include "hw/intc/loongarch_pch_pic.h" +#include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "trace.h" +#include "qapi/error.h" =20 static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int leve= l) { @@ -40,7 +42,7 @@ static void pch_pic_irq_handler(void *opaque, int irq, in= t level) LoongArchPCHPIC *s =3D LOONGARCH_PCH_PIC(opaque); uint64_t mask =3D 1ULL << irq; =20 - assert(irq < PCH_PIC_IRQ_NUM); + assert(irq < s->irq_num); trace_loongarch_pch_pic_irq_handler(irq, level); =20 if (s->intedge & mask) { @@ -78,7 +80,12 @@ static uint64_t loongarch_pch_pic_low_readw(void *opaque= , hwaddr addr, val =3D PCH_PIC_INT_ID_VAL; break; case PCH_PIC_INT_ID_HI: - val =3D PCH_PIC_INT_ID_NUM; + /* + * With 7A1000 manual + * bit 0-15 pch irqchip version + * bit 16-31 irq number supported with pch irqchip + */ + val =3D PCH_PIC_INT_ID_VER + ((s->irq_num - 1) << 16); break; case PCH_PIC_INT_MASK_LO: val =3D (uint32_t)s->int_mask; @@ -365,6 +372,19 @@ static void loongarch_pch_pic_reset(DeviceState *d) s->int_polarity =3D 0x0; } =20 +static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp) +{ + LoongArchPCHPIC *s =3D LOONGARCH_PCH_PIC(dev); + + if (!s->irq_num || s->irq_num > PCH_PIC_IRQ_NUM) { + error_setg(errp, "Invalid 'pic_irq_num'"); + return; + } + + qdev_init_gpio_out(dev, s->parent_irq, s->irq_num); + qdev_init_gpio_in(dev, pch_pic_irq_handler, s->irq_num); +} + static void loongarch_pch_pic_init(Object *obj) { LoongArchPCHPIC *s =3D LOONGARCH_PCH_PIC(obj); @@ -382,10 +402,13 @@ static void loongarch_pch_pic_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem8); sysbus_init_mmio(sbd, &s->iomem32_high); =20 - qdev_init_gpio_out(DEVICE(obj), s->parent_irq, PCH_PIC_IRQ_NUM); - qdev_init_gpio_in(DEVICE(obj), pch_pic_irq_handler, PCH_PIC_IRQ_NUM); } =20 +static Property loongarch_pch_pic_properties[] =3D { + DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPCHPIC, irq_num, 0), + DEFINE_PROP_END_OF_LIST(), +}; + static const VMStateDescription vmstate_loongarch_pch_pic =3D { .name =3D TYPE_LOONGARCH_PCH_PIC, .version_id =3D 1, @@ -411,8 +434,10 @@ static void loongarch_pch_pic_class_init(ObjectClass *= klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + dc->realize =3D loongarch_pch_pic_realize; dc->reset =3D loongarch_pch_pic_reset; dc->vmsd =3D &vmstate_loongarch_pch_pic; + device_class_set_props(dc, loongarch_pch_pic_properties); } =20 static const TypeInfo loongarch_pch_pic_info =3D { diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 1e58346aeb..a39704e1e7 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -559,6 +559,8 @@ static void loongarch_irq_init(LoongArchMachineState *l= ams) } =20 pch_pic =3D qdev_new(TYPE_LOONGARCH_PCH_PIC); + num =3D PCH_PIC_IRQ_NUM; + qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); d =3D SYS_BUS_DEVICE(pch_pic); sysbus_realize_and_unref(d, &error_fatal); memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, @@ -570,13 +572,13 @@ static void loongarch_irq_init(LoongArchMachineState = *lams) VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, sysbus_mmio_get_region(d, 2)); =20 - /* Connect 64 pch_pic irqs to extioi */ - for (int i =3D 0; i < PCH_PIC_IRQ_NUM; i++) { + /* Connect pch_pic irqs to extioi */ + for (int i =3D 0; i < num; i++) { qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); } =20 pch_msi =3D qdev_new(TYPE_LOONGARCH_PCH_MSI); - start =3D PCH_PIC_IRQ_NUM; + start =3D num; num =3D EXTIOI_IRQS - start; qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarc= h_pch_pic.h index 2d4aa9ed6f..ba3a47fa88 100644 --- a/include/hw/intc/loongarch_pch_pic.h +++ b/include/hw/intc/loongarch_pch_pic.h @@ -9,11 +9,9 @@ #define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC) =20 -#define PCH_PIC_IRQ_START 0 -#define PCH_PIC_IRQ_END 63 #define PCH_PIC_IRQ_NUM 64 #define PCH_PIC_INT_ID_VAL 0x7000000UL -#define PCH_PIC_INT_ID_NUM 0x3f0001UL +#define PCH_PIC_INT_ID_VER 0x1UL =20 #define PCH_PIC_INT_ID_LO 0x00 #define PCH_PIC_INT_ID_HI 0x04 @@ -66,4 +64,5 @@ struct LoongArchPCHPIC { MemoryRegion iomem32_low; MemoryRegion iomem32_high; MemoryRegion iomem8; + unsigned int irq_num; }; --=20 2.31.1 From nobody Thu Oct 31 23:59:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672394441593839.01495521357; Fri, 30 Dec 2022 02:00:41 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pBCBH-0003k7-1q; Fri, 30 Dec 2022 05:00:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pBCBE-0003ii-Q5 for qemu-devel@nongnu.org; Fri, 30 Dec 2022 05:00:00 -0500 Received: from mail.loongson.cn ([114.242.206.163] helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pBCBC-0005Rs-Gd for qemu-devel@nongnu.org; Fri, 30 Dec 2022 05:00:00 -0500 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8AxB_GXtq5jcnYJAA--.20561S3; Fri, 30 Dec 2022 17:59:51 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxtOWWtq5jCSAQAA--.53838S5; Fri, 30 Dec 2022 17:59:51 +0800 (CST) From: Tianrui Zhao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, maobibo@loongson.cn, philmd@linaro.org Subject: [PATCH v4 3/3] hw/intc/loongarch_pch: Change default irq number of pch irq controller Date: Fri, 30 Dec 2022 17:59:50 +0800 Message-Id: <20221230095950.2217103-4-zhaotianrui@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221230095950.2217103-1-zhaotianrui@loongson.cn> References: <20221230095950.2217103-1-zhaotianrui@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8BxtOWWtq5jCSAQAA--.53838S5 X-CM-SenderInfo: p2kd03xldq233l6o00pqjv00gofq/ X-Coremail-Antispam: 1Uk129KBjvJXoWxXr1UGF1UJr4rWFW3CrWfZrb_yoW5tr1kpF ZrCF9akF4kWrWUXr92v343Xwn7JFs3ury29F4a9Fy8Cr43JrykXw1kJw4DWFyUKws5Jryq qrZ5C3yYv3WUXaUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bn8Fc2x0x2IEx4CE42xK8VAvwI8IcIk0rVWrJVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4 AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF 7I0E14v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7 CjxVAFwI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2 zVCFFI0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VCjz48v1sIEY20_WwAm72CE4IkC6x 0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2Ij64vIr41l42xK82IY6x8ErcxF aVAv8VWrMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxV Cjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY 6xIIjxv20xvE14v26r1I6r4UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6x AIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY 1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvj4RC_MaUUUUU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=zhaotianrui@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1672394442629000001 Content-Type: text/plain; charset="utf-8" Change the default irq number of pch pic to 32, so that the irq number of pch msi is 224(256 - 32), and move the 'PCH_PIC_IRQ_NUM' macro to pci-host/ls7a.h and add prefix 'VIRT' on it to keep standard format. Signed-off-by: Tianrui Zhao Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/loongarch_pch_pic.c | 3 ++- hw/loongarch/virt.c | 2 +- include/hw/intc/loongarch_pch_msi.h | 6 +++--- include/hw/intc/loongarch_pch_pic.h | 1 - include/hw/pci-host/ls7a.h | 1 + 5 files changed, 7 insertions(+), 6 deletions(-) diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c index 1440195837..47fd5f20e0 100644 --- a/hw/intc/loongarch_pch_pic.c +++ b/hw/intc/loongarch_pch_pic.c @@ -8,6 +8,7 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "hw/loongarch/virt.h" +#include "hw/pci-host/ls7a.h" #include "hw/irq.h" #include "hw/intc/loongarch_pch_pic.h" #include "hw/qdev-properties.h" @@ -376,7 +377,7 @@ static void loongarch_pch_pic_realize(DeviceState *dev,= Error **errp) { LoongArchPCHPIC *s =3D LOONGARCH_PCH_PIC(dev); =20 - if (!s->irq_num || s->irq_num > PCH_PIC_IRQ_NUM) { + if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) { error_setg(errp, "Invalid 'pic_irq_num'"); return; } diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index a39704e1e7..8f3bb85d58 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -559,7 +559,7 @@ static void loongarch_irq_init(LoongArchMachineState *l= ams) } =20 pch_pic =3D qdev_new(TYPE_LOONGARCH_PCH_PIC); - num =3D PCH_PIC_IRQ_NUM; + num =3D VIRT_PCH_PIC_IRQ_NUM; qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); d =3D SYS_BUS_DEVICE(pch_pic); sysbus_realize_and_unref(d, &error_fatal); diff --git a/include/hw/intc/loongarch_pch_msi.h b/include/hw/intc/loongarc= h_pch_msi.h index c5a52bc327..a1172f56ff 100644 --- a/include/hw/intc/loongarch_pch_msi.h +++ b/include/hw/intc/loongarch_pch_msi.h @@ -8,10 +8,10 @@ #define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi" OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI) =20 -/* Msi irq start start from 64 to 255 */ -#define PCH_MSI_IRQ_START 64 +/* Msi irq start start from 32 to 255 */ +#define PCH_MSI_IRQ_START 32 #define PCH_MSI_IRQ_END 255 -#define PCH_MSI_IRQ_NUM 192 +#define PCH_MSI_IRQ_NUM 224 =20 struct LoongArchPCHMSI { SysBusDevice parent_obj; diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarc= h_pch_pic.h index ba3a47fa88..4ea8808592 100644 --- a/include/hw/intc/loongarch_pch_pic.h +++ b/include/hw/intc/loongarch_pch_pic.h @@ -9,7 +9,6 @@ #define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC) =20 -#define PCH_PIC_IRQ_NUM 64 #define PCH_PIC_INT_ID_VAL 0x7000000UL #define PCH_PIC_INT_ID_VER 0x1UL =20 diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h index 6443327bd7..8061c4bbbf 100644 --- a/include/hw/pci-host/ls7a.h +++ b/include/hw/pci-host/ls7a.h @@ -32,6 +32,7 @@ * 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs * used for pci device. */ +#define VIRT_PCH_PIC_IRQ_NUM 32 #define PCH_PIC_IRQ_OFFSET 64 #define VIRT_DEVICE_IRQS 16 #define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2) --=20 2.31.1