From nobody Fri Nov 1 00:15:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1672234607; cv=none; d=zohomail.com; s=zohoarc; b=hA3yVVvHKF2u0VcnoUlGXx9GJAOTZNepHSpdI4NVBhEWxIBGG85Ei8PERs+ZzwZNgsr7Mx4J70YJZaWJma87rz1KYhTYHkPjvlSbGX6WuVdXXN5Xbpk8A3xZlOhiLpkBdNtvejQmISyFDkCqyckVm1gXNfBrR7xSbbV6zDFQNhA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672234607; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Hbm0SUMgOyGVm9UYUYsWKLbt1FN4F94mBirfTGyOnNA=; b=QD7jsSAvR3JuBkcoE9/rMAzrM7yaEuSiayfEizpMNCjSt9dsMSG66Px1mfnhfqTk2+Lwc6YU2NMVdp9Xx6xtIk0jieWDNEIm91pvuGXiAM7UFkXkRD4dLjSExdHeAaAm210n8+4/fhUAy0/mcRbkWGqFvdWnaFskGxi93aGb2GE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672234607065450.56980455395217; Wed, 28 Dec 2022 05:36:47 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pAWZ7-0004eQ-1y; Wed, 28 Dec 2022 08:33:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pAWZ4-0004bk-PX for qemu-devel@nongnu.org; Wed, 28 Dec 2022 08:33:50 -0500 Received: from mail-oi1-x231.google.com ([2607:f8b0:4864:20::231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pAWZ3-0008Aq-1l for qemu-devel@nongnu.org; Wed, 28 Dec 2022 08:33:50 -0500 Received: by mail-oi1-x231.google.com with SMTP id d127so13464759oif.12 for ; Wed, 28 Dec 2022 05:33:48 -0800 (PST) Received: from fedora.. ([191.17.222.139]) by smtp.gmail.com with ESMTPSA id bl22-20020a056808309600b0035e7d07bf9dsm6991626oib.16.2022.12.28.05.33.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 05:33:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hbm0SUMgOyGVm9UYUYsWKLbt1FN4F94mBirfTGyOnNA=; b=MYXdVhuYh3XS7uMOlqTaMiRl6Lqywy+7hzWtnSwgYmb3x7SEA45fo3bh+NPC49R6b6 9931hqsOZEKwBx0TAm1eHQS7z8xRYMeut1YsiFNVUm66+RPd5U5SxrnethglIJAzN12U tDYScwP6caq5uyS4VyCAWCyKwW3Jeadwezcsh9QmiDWmWHOm02jXxy2JkbesfL/nagDA T+tSrT0AhHqXfxi8Jk18oULZOAbMakEHa+I0ghJoUYj/qtcH9SgtBWvRnS+kB9avecbx au0tdbPKQILPzPfy29zWpYvFqrB2AUkVSu1je2bg1D/rl447hSJzQcdEHWVPEyK9hZsp ZPwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hbm0SUMgOyGVm9UYUYsWKLbt1FN4F94mBirfTGyOnNA=; b=LnCYGEvZ+75nbMIO9zYaG3Mont2uO+Y1JhU/fx/NfkIQy9rKi181ug/ZLmKE+5mpDZ 6f/LKkAnvj99iZo1iwMmXXT5C4zscG/6oBf9ldRw9Ie/8bvYbKrR0oysjc9rsMYnPuQe s3A3jT+Nr1WFa1+gIcMK/EwJvfkZoQWvzxvdX4T9vtCAGXJ5ycVkk1eRlDVWVb76UVdA 0Ye3YLtTLUy/1QgQ3V2yx/tEEoqQYL3o7i1GgBNTOpAL4iGV6w8aHogK4MImyt6Fiw4R 7GXSO3hu94i670mrnWtxQGUFv+4nFvNQVAMcoazAisPhKZerVuPQxQHS/W79IoofgyXk HmRQ== X-Gm-Message-State: AFqh2ko5+HVg6hR9KzJX/nhubyFr09nnnao/L6iqODaInpZUnFcuVeNY 6pmL608FogVGVVWPqERoOpFUM7sS9fSc6XqS X-Google-Smtp-Source: AMrXdXuZoWC5/AZUnEONG+Ef2jKWLWewi+gKetbmM0zh2Pk36Pep0OA+j33dG8hJJk044bUOdJB2aw== X-Received: by 2002:a05:6808:bc3:b0:360:d800:d10c with SMTP id o3-20020a0568080bc300b00360d800d10cmr15595466oik.34.1672234427736; Wed, 28 Dec 2022 05:33:47 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Cleber Rosa , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 01/10] tests/avocado: add RISC-V opensbi boot test Date: Wed, 28 Dec 2022 10:33:27 -0300 Message-Id: <20221228133336.197467-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221228133336.197467-1-dbarboza@ventanamicro.com> References: <20221228133336.197467-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1672234608307000001 This test is used to do a quick sanity check to ensure that we're able to run the existing QEMU FW image. 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | RISCV32_BIOS_BIN firmware with minimal options. The riscv32 'spike' machine isn't bootable at this moment, requiring an Opensbi fix [1] and QEMU side changes [2]. We could just leave at that or add a 'skip' test to remind us about it. To work as a reminder that we have a riscv32 'spike' test that should be enabled as soon as Opensbi QEMU rom receives the fix, we're adding a 'skip' test: (11/18) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv32_spike: SKIP: requires OpenSBI fix to work [1] https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.18605= 69-1-bmeng@tinylab.org/ [2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=3D334159 Cc: Cleber Rosa Cc: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng Tested-by: Bin Meng --- tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 tests/avocado/riscv_opensbi.py diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py new file mode 100644 index 0000000000..3549d36a11 --- /dev/null +++ b/tests/avocado/riscv_opensbi.py @@ -0,0 +1,65 @@ +# OpenSBI boot test for RISC-V machines +# +# Copyright (c) 2022, Ventana Micro +# +# This work is licensed under the terms of the GNU GPL, version 2 or +# later. See the COPYING file in the top-level directory. + +from avocado_qemu import QemuSystemTest +from avocado import skip +from avocado_qemu import wait_for_console_pattern + +class RiscvOpensbi(QemuSystemTest): + """ + :avocado: tags=3Daccel:tcg + """ + timeout =3D 5 + + def boot_opensbi(self): + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + def test_riscv64_virt(self): + """ + :avocado: tags=3Darch:riscv64 + :avocado: tags=3Dmachine:virt + """ + self.boot_opensbi() + + def test_riscv64_spike(self): + """ + :avocado: tags=3Darch:riscv64 + :avocado: tags=3Dmachine:spike + """ + self.boot_opensbi() + + def test_riscv64_sifive_u(self): + """ + :avocado: tags=3Darch:riscv64 + :avocado: tags=3Dmachine:sifive_u + """ + self.boot_opensbi() + + def test_riscv32_virt(self): + """ + :avocado: tags=3Darch:riscv32 + :avocado: tags=3Dmachine:virt + """ + self.boot_opensbi() + + def test_riscv32_sifive_u(self): + """ + :avocado: tags=3Darch:riscv32 + :avocado: tags=3Dmachine:sifive_u + """ + self.boot_opensbi() + + @skip("requires OpenSBI fix to work") + def test_riscv32_spike(self): + """ + :avocado: tags=3Darch:riscv32 + :avocado: tags=3Dmachine:spike + """ + self.boot_opensbi() --=20 2.38.1 From nobody Fri Nov 1 00:15:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1672234497; cv=none; d=zohomail.com; s=zohoarc; b=QoaA79w2m6GMfLz8LtWKKkqe7De/tF8rwdpdzSpox9N47QttDxj9JjqdmtdIDnP2W8XimNdYe10nap+USQltkQWFFr5HmthoYI2zRGGceAxYQ8kOqjT4m4m5yRlmbP4MFaVKF0SfK+U5hOk43Z4fRz3MliStP+BBP0Q3PspgM5c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672234497; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=14j0rjtt0NAYgU5LJ1kqKbCWT8XXgNf4j+2giaEVxKo=; b=NTF/Buv0bM05jIXnkm6agb8Qs908JZaSGr733WDkQXtqEfWAAn/EfTGIo9eCgYwAQU5iVg/im7h4OhIuO3GZxuSFP1gqWlVEHQUbh9p/Q8eLnO0rB0UBb8SjAS7wy1imfhZgeMltZ1xXsK2F+ye7zhjjxQo6lTnT3P3+jU/30iY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672234497432155.52856053090284; Wed, 28 Dec 2022 05:34:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pAWZE-0004gR-HT; Wed, 28 Dec 2022 08:34:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pAWZ7-0004ed-I7 for qemu-devel@nongnu.org; Wed, 28 Dec 2022 08:33:53 -0500 Received: from mail-oi1-x235.google.com ([2607:f8b0:4864:20::235]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pAWZ6-0008BQ-1y for qemu-devel@nongnu.org; Wed, 28 Dec 2022 08:33:53 -0500 Received: by mail-oi1-x235.google.com with SMTP id v70so14844089oie.3 for ; Wed, 28 Dec 2022 05:33:51 -0800 (PST) Received: from fedora.. ([191.17.222.139]) by smtp.gmail.com with ESMTPSA id bl22-20020a056808309600b0035e7d07bf9dsm6991626oib.16.2022.12.28.05.33.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 05:33:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=14j0rjtt0NAYgU5LJ1kqKbCWT8XXgNf4j+2giaEVxKo=; b=ZpIGj2qwxzpz6/fqM84QzXSrfzz6R10DAzyXqwXqtSaznzaC3/dTftfdjwCkhNvPIo yWTmKOE7UPoVz5ExOTOBNciX/FQQ/6/2lSs8Wb6uqAGbABeZUzmpuVCcdBC1Dh960yUA wu2wdK5t4y4SbyWyW9qgFDZgNHbKYI3U6KtYbfamVPAZa7h7Yi+tnvBuh6SD0VjWAjtp 5YqdyALr1V1ELxFFsXRC0VITL4fzXdlcCVD9cqqDY9ijUQcm/JGzbdiIVd5y38nsmjB2 fHtRxgK1JpQh19DCk9TOTPWNwQdC5rHTQdX+1HbhhFEjjvPCOgcQX9AJ7gQZFtX0iNfd 8dTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=14j0rjtt0NAYgU5LJ1kqKbCWT8XXgNf4j+2giaEVxKo=; b=sPdi5n1UM10Zso5paHB6BapUjWLbrPCeZUGdvo/aDrryMffq/Dx+3TpisVdePfGqTF /jtavzUnKPkCxA7I/hJoX7+VM0fmqYUXJIugSVR7DCQo5gdfmTbwjzX9uNGrLLka77oo MMj0EdDq920OB1w80mOnU+EobosupORGRp2+PD9REfwqYyD3hxfiH64n2N+Qh7LOuteL 97S33QE/jtoDFzUzB8J2+HP1S4UA9yXC0gKrUq+WucgLIfXBQRMQ89NXy+UDGuqdqijv Z4fchsp6N4asSXlNmWHE8yByCDIvHdDIcUGItoXRMqfgavK25kiOFUzntrmglLyB3AIW L73w== X-Gm-Message-State: AFqh2kpTPlsM4UqevpHsqzEPTkJcWQcU9NAHVpeE7Ajor7Cl1WSilqvj /LZh6V6C3dnrRIptm+1YsxapL5z8M4ByzcS4 X-Google-Smtp-Source: AMrXdXuRFubBTPUaoFhcOqWzNYBUDtE9+pbv8B3kVh72X2pAucM43g7YAfFrDa015biFL+NWjreLUg== X-Received: by 2002:a05:6808:488:b0:360:c988:f07c with SMTP id z8-20020a056808048800b00360c988f07cmr11447726oid.34.1672234430464; Wed, 28 Dec 2022 05:33:50 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v3 02/10] hw/riscv/spike: use 'fdt' from MachineState Date: Wed, 28 Dec 2022 10:33:28 -0300 Message-Id: <20221228133336.197467-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221228133336.197467-1-dbarboza@ventanamicro.com> References: <20221228133336.197467-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1672234499015000002 The MachineState object provides a 'fdt' pointer that is already being used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP command. Remove the 'fdt' pointer from SpikeState and use MachineState::fdt instead. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/spike.c | 12 +++++------- include/hw/riscv/spike.h | 2 -- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 1b747d8f7c..426c383cef 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -53,6 +53,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *= memmap, bool is_32_bit, bool htif_custom_base) { void *fdt; + int fdt_size; uint64_t addr, size; unsigned long clint_addr; int cpu, socket; @@ -65,7 +66,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *= memmap, "sifive,clint0", "riscv,clint0" }; =20 - fdt =3D s->fdt =3D create_device_tree(&s->fdt_size); + fdt =3D mc->fdt =3D create_device_tree(&fdt_size); if (!fdt) { error_report("create_device_tree() failed"); exit(1); @@ -322,18 +323,15 @@ static void spike_board_init(MachineState *machine) hwaddr end =3D riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, &start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", end); } =20 /* Compute the fdt load address in dram */ fdt_load_addr =3D riscv_load_fdt(memmap[SPIKE_DRAM].base, - machine->ram_size, s->fdt); - - /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ - machine->fdt =3D s->fdt; + machine->ram_size, machine->fdt); =20 /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index 73d69234de..d13a147942 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -37,8 +37,6 @@ struct SpikeState { =20 /*< public >*/ RISCVHartArrayState soc[SPIKE_SOCKETS_MAX]; - void *fdt; - int fdt_size; }; =20 enum { --=20 2.38.1 From nobody Fri Nov 1 00:15:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1672234497; cv=none; d=zohomail.com; s=zohoarc; b=MnXV0VgvhWPIaKFtOI+AQSm6RTPodp2MhSRro6ITWhkiPBL6KWnUrdl9j0s7XYfenP9egSsA8v4jO608LHcgeBrAf+jOc/u2O1VM0nuMSld7n9ZBotz7VF0WFR9W4ubnbr+KaQpbdtrM7tyX3gBk3lONqP+3ONt/SPfwWaAx5X8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672234497; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sHU/59DX/o1/r0pnySH91c8qF73tF/MEtRKTLilJBpE=; b=l92XduxzPqJ7W291U4wgrwtFmb7g3GfidxWtwwATvw2BvvlUG8szeh+vsvZCvYSvpsz3tlqWPcglvhs/6+C2uka1J5xJf2LQOylIN2dWQAi5K5h5YrgzRVkYysmFGrdkRl7sLwcv21c1mB5N55pATEvVl3kHiATsXfi4iGKa4SI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672234497453376.1572347442162; Wed, 28 Dec 2022 05:34:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pAWZH-0004jb-KD; Wed, 28 Dec 2022 08:34:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pAWZC-0004g5-Gk for qemu-devel@nongnu.org; Wed, 28 Dec 2022 08:33:59 -0500 Received: from mail-oi1-x231.google.com ([2607:f8b0:4864:20::231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pAWZ8-0008Al-RH for qemu-devel@nongnu.org; Wed, 28 Dec 2022 08:33:58 -0500 Received: by mail-oi1-x231.google.com with SMTP id r11so14799643oie.13 for ; Wed, 28 Dec 2022 05:33:54 -0800 (PST) Received: from fedora.. ([191.17.222.139]) by smtp.gmail.com with ESMTPSA id bl22-20020a056808309600b0035e7d07bf9dsm6991626oib.16.2022.12.28.05.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 05:33:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sHU/59DX/o1/r0pnySH91c8qF73tF/MEtRKTLilJBpE=; b=W6IRxRovR8tGZZmwl7xtijJKEy6nw8idWUopl6p7bNVyd0nOpDeN+wwmR9EdgySb/P jpKpWihgUabpf5uxlWSQgHFh9ggNsOBEtTOc0d13XH5adH6psHU7J68WKYX++jJ98TAh +sOZB3SPHjJWPDKKb8JxXN1cKebFuOyue1TIgs1yEm2EeaLdC12Ywk913KPvA2ACdVFh ItEM/34v5THkExP2hCQ+ytlb3EIM3RPqie5CUXF4CurJYmtAFiLcGjSK2jau2g6bJFO+ 5yCEbUO0Oq1QP8hSOxoJqBvzfDQTEmM3G8dh+QdNh4lHvzF8pOwuSiWuLuuaExKXNoIz qYuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sHU/59DX/o1/r0pnySH91c8qF73tF/MEtRKTLilJBpE=; b=v4E6eV6Xzw0h4mcgnv3Pb81Dg/sIp4L9eZhMhf9CohmVe7UEJp5PdvUCX29srL32VX Ur8amebrrMowiLiQXXPcIUgnIwgYGTGpDYgVutX4rrJiHT8bav9kFLnCkE4QcHC4KZH2 wYACxRFtKB3i9Q4r1e3KEdyEtveginovXuz6+raVi5Ojw4p2AaGKD30HrPAFMVIT3qSK 287S9Bcv9hl4uSq0ZjJh79r5uqcqbozrVgIC0zgrwoYNU94D1dQsb+Uc/k/LdXl7b8yu GsnI731UsD1qLriEc0+v8KpLAL7RE+iTRvh3bw9qXhRJ436x3hN5bG2IwhnI6wKuyDvr 2Njg== X-Gm-Message-State: AFqh2kpcxJUggd1MUrsDAPzh3cf/FEJznXBnuiHdwaJiMNkfF9s6wglU VAzjlzgzczWG8m+SLBc7ymQUw/Fmee84JqIT X-Google-Smtp-Source: AMrXdXtla2PvfehMaVs+OlPskZO99IgjuINyJ0/o9geeiL/BjQhwffcrCWkML3/MdFQs+jdW8kIjyQ== X-Received: by 2002:a05:6808:53:b0:360:e9b4:3765 with SMTP id v19-20020a056808005300b00360e9b43765mr10574382oic.42.1672234433663; Wed, 28 Dec 2022 05:33:53 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v3 03/10] hw/riscv/sifive_u: use 'fdt' from MachineState Date: Wed, 28 Dec 2022 10:33:29 -0300 Message-Id: <20221228133336.197467-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221228133336.197467-1-dbarboza@ventanamicro.com> References: <20221228133336.197467-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1672234499992000005 The MachineState object provides a 'fdt' pointer that is already being used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP command. Remove the 'fdt' pointer from SiFiveUState and use MachineState::fdt instead. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/sifive_u.c | 15 ++++++--------- include/hw/riscv/sifive_u.h | 3 --- 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index a58ddb36ac..ddceb750ea 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -98,7 +98,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry= *memmap, { MachineState *ms =3D MACHINE(qdev_get_machine()); void *fdt; - int cpu; + int cpu, fdt_size; uint32_t *cells; char *nodename; uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle =3D 1; @@ -112,14 +112,14 @@ static void create_fdt(SiFiveUState *s, const MemMapE= ntry *memmap, }; =20 if (ms->dtb) { - fdt =3D s->fdt =3D load_device_tree(ms->dtb, &s->fdt_size); + fdt =3D ms->fdt =3D load_device_tree(ms->dtb, &fdt_size); if (!fdt) { error_report("load_device_tree() failed"); exit(1); } goto update_bootargs; } else { - fdt =3D s->fdt =3D create_device_tree(&s->fdt_size); + fdt =3D ms->fdt =3D create_device_tree(&fdt_size); if (!fdt) { error_report("create_device_tree() failed"); exit(1); @@ -612,9 +612,9 @@ static void sifive_u_machine_init(MachineState *machine) hwaddr end =3D riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, &start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-e= nd", end); } } else { @@ -627,14 +627,11 @@ static void sifive_u_machine_init(MachineState *machi= ne) =20 /* Compute the fdt load address in dram */ fdt_load_addr =3D riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, - machine->ram_size, s->fdt); + machine->ram_size, machine->fdt); if (!riscv_is_32bit(&s->soc.u_cpus)) { start_addr_hi32 =3D (uint64_t)start_addr >> 32; } =20 - /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ - machine->fdt =3D s->fdt; - /* reset vector */ uint32_t reset_vec[12] =3D { s->msel, /* MSEL pin state */ diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index e680d61ece..4a8828a30e 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -67,9 +67,6 @@ typedef struct SiFiveUState { /*< public >*/ SiFiveUSoCState soc; =20 - void *fdt; - int fdt_size; - bool start_in_flash; uint32_t msel; uint32_t serial; --=20 2.38.1 From nobody Fri Nov 1 00:15:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1672234585; cv=none; d=zohomail.com; s=zohoarc; b=ajiErAroX4zHDJN4xpQ1zizyZz/dZfRU8OidZA8OwqN7tgvuddm3hCiZQcQFSigsBLkwkivK26VnFJMayybFNnDypvVmSDLW58wswGw3OWMJriRfLzK3sMAcoAtawuit5FeCLpTeMZqrSXAVuzH6BvGp90cwEbC2Q1ZeeDQtdRQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672234585; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QE2XJgRkAH08Shs2lwlBT8vzcOTk7Tw+J/29kSs4rCU=; b=ARMLFDFtBYhdu+yDWUTQJ7L6LVmMqyfv6z/BLMZcDZNQfN9dwKvQGrkNA31b2bRLh8w8xg6FCmrfHlA8TewD/KPTVKDHmTS1GE7EjYMekVlI52pW0ZepVr9lVf6jX31KBB1nqSatTkRgKmR9Sk6/sMsPwmzA5GfEjdEbrjQuiis= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672234585991351.929320013012; Wed, 28 Dec 2022 05:36:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pAWZM-0004nF-Ng; Wed, 28 Dec 2022 08:34:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pAWZE-0004hc-2h for qemu-devel@nongnu.org; Wed, 28 Dec 2022 08:34:00 -0500 Received: from mail-oi1-x230.google.com ([2607:f8b0:4864:20::230]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pAWZC-0008IH-23 for qemu-devel@nongnu.org; Wed, 28 Dec 2022 08:33:59 -0500 Received: by mail-oi1-x230.google.com with SMTP id e205so14814751oif.11 for ; Wed, 28 Dec 2022 05:33:57 -0800 (PST) Received: from fedora.. ([191.17.222.139]) by smtp.gmail.com with ESMTPSA id bl22-20020a056808309600b0035e7d07bf9dsm6991626oib.16.2022.12.28.05.33.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 05:33:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QE2XJgRkAH08Shs2lwlBT8vzcOTk7Tw+J/29kSs4rCU=; b=PY+zEq5WxuHdmgJoaTmFojQQjRgi8MYe66EiwgIZ4a5kvh15S1K1SFlYTLKL2wlVwW D0H9nSWQkOGv5Wmc4fjbyl7IJf/d78umhV7Pu17CQyQxLt4lcdg/lwpE09Q3buUBbVNk pTTUUhoaLsqGrBRv++H7x/109MUVf5/9njFJNRMvTORDv5SeKWtDG/tzzWNxBNxraOeW xBNsrK2Fu/yNwaASHtDnTl1eB85mX8ucO3yR0rzJgMAbGfvAoj3eYQAkcXy30EDw5XcM FJ+8IIdh4R3obXFz2bGpz8uyjj2uvfI1zDISWtVTxjYD+9gpcWo5wlswypFtCKuwuOLD 1VuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QE2XJgRkAH08Shs2lwlBT8vzcOTk7Tw+J/29kSs4rCU=; b=qvXtyaLzWKND3ttsdCcXlmwJxcA7QOO9hhOTfLPWUYlZbdxAzHZHK39m87wA4TXUkz 2FEHwhCUPvpo6hr/JN8D8aBazdFSM8LGP5vufal6WB2HS/Agb6hZwTTwLL7g1FijfRGH EUAAxtFvS4xxsQtoNSKGFiyuEdiggwU2SXbuUPMt527xcV+m/uN10m+7f7Y05yP9iGHH 6g4NMo7G0R3pRMS77xc4zncm2cvFKKQ+0uj2EI3bJGtd6CS4MsyhWI/x4/wdJxmRDpFZ GsZNqGm1pnqDauVwrZb1EQN5e8plA7j3l13znoUa2Vrry4XXFzEJaEanwBxc6ssxlYuP t9dQ== X-Gm-Message-State: AFqh2kpp9F14vHOMAf+JPIPBkrQlmQ6LL59sKQO6FJY8RjcYpBZmq3U4 pqmdW1NyupICPod5a7cZsJ0WhbBnhoZQ3AGS X-Google-Smtp-Source: AMrXdXvUd+KbqMfe3nfJzdUlxuDUfgwb9looEDYPz4/Jxvac2QN+Rr1bcF2nFjYRxwX8j7Ne+Slqwg== X-Received: by 2002:a05:6808:55:b0:360:e1dc:8b18 with SMTP id v21-20020a056808005500b00360e1dc8b18mr11114671oic.20.1672234436543; Wed, 28 Dec 2022 05:33:56 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v3 04/10] hw/riscv/spike.c: load initrd right after riscv_load_kernel() Date: Wed, 28 Dec 2022 10:33:30 -0300 Message-Id: <20221228133336.197467-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221228133336.197467-1-dbarboza@ventanamicro.com> References: <20221228133336.197467-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1672234586336000001 This will make the code more in line with what the other boards are doing. We'll also avoid an extra check to machine->kernel_filename since we already checked that before executing riscv_load_kernel(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/spike.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 426c383cef..0d2feea930 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -297,6 +297,10 @@ static void spike_board_init(MachineState *machine) g_free(firmware_name); } =20 + /* Create device tree */ + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, + riscv_is_32bit(&s->soc[0]), htif_custom_base); + /* Load kernel */ if (machine->kernel_filename) { kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], @@ -305,6 +309,17 @@ static void spike_board_init(MachineState *machine) kernel_entry =3D riscv_load_kernel(machine->kernel_filename, kernel_start_addr, htif_symbol_callback); + + if (machine->initrd_filename) { + hwaddr start; + hwaddr end =3D riscv_load_initrd(machine->initrd_filename, + machine->ram_size, kernel_entry, + &start); + qemu_fdt_setprop_cell(machine->fdt, "/chosen", + "linux,initrd-start", start); + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-e= nd", + end); + } } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode @@ -313,22 +328,6 @@ static void spike_board_init(MachineState *machine) kernel_entry =3D 0; } =20 - /* Create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc[0]), htif_custom_base); - - /* Load initrd */ - if (machine->kernel_filename && machine->initrd_filename) { - hwaddr start; - hwaddr end =3D riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", - end); - } - /* Compute the fdt load address in dram */ fdt_load_addr =3D riscv_load_fdt(memmap[SPIKE_DRAM].base, machine->ram_size, machine->fdt); --=20 2.38.1 From nobody Fri Nov 1 00:15:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1672234579; cv=none; d=zohomail.com; s=zohoarc; b=aWRNNIcNBwWUbW085UwQt9oKbHeCdAJrHiKXxZn5S56yvwriG7vm5MiAvI4ce/s4LUiBszUYcj900zoOaJ8PlkHWo+s9/kSOmJgDm708FXJMeRG3/Shuc2ACN8N5ckMMH9UJpijVSVN0LnY6NL/7VvRmUkf0I2U8tjHTaur6z2k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672234579; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oikBKkKahhZEdm4ld5dwcA6luVTj35JLzUpMpaRato4=; b=c4NSUmfeKaM0CUNMxGD1g7ns36v9jOcXURAFCtjMvr3GLI8kvF6eX3sg7lPtKzgQhh4FS9Ndl5Nu6c7CN2z8QtaYbGBqdRNbaIBZj5JHb/PgurQ6beun5cr/M+kPcLt01t+MeeAwbOgbLub76DN5ZnvVkvRlIEd7LxOs5a0gVNo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672234579519164.88163615135818; Wed, 28 Dec 2022 05:36:19 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pAWZQ-0004rg-4i; Wed, 28 Dec 2022 08:34:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pAWZG-0004j1-El for qemu-devel@nongnu.org; Wed, 28 Dec 2022 08:34:02 -0500 Received: from mail-oi1-x231.google.com ([2607:f8b0:4864:20::231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pAWZE-0008Aq-LB for qemu-devel@nongnu.org; Wed, 28 Dec 2022 08:34:02 -0500 Received: by mail-oi1-x231.google.com with SMTP id d127so13465115oif.12 for ; Wed, 28 Dec 2022 05:34:00 -0800 (PST) Received: from fedora.. ([191.17.222.139]) by smtp.gmail.com with ESMTPSA id bl22-20020a056808309600b0035e7d07bf9dsm6991626oib.16.2022.12.28.05.33.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 05:33:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oikBKkKahhZEdm4ld5dwcA6luVTj35JLzUpMpaRato4=; b=Oq71clq/m1poNzX4JdGFqGSfIuzQr5RAJFpSc5c9YpFGEuNta0pObEXv4WTe/XYeoq gLOq1zQNCZb9B175GbIPNEjgwVJ3a1SjmgQLgFNBTV0V9UQ2kmv2M4YJKx/igH9w/fBl jbeM2HX61Y3NCIYFkbEpR2DKYG/0sbz9711KtR5oJ5Ps9LkJ9UgkVQHpf2Pylb4JZmLN U2F3wavfUO9IgUNLn2T5w4/j8veEktsowoOzqszDeBYXg3FyMtbZfLXdaTsLNYqVYa5a mhmeFn9+abJTfuPgJi4DCkbFVEqrp8rYhAzUSH8wixuWYepkY8FnEzdDqpoV7/3OT3qu 2cBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oikBKkKahhZEdm4ld5dwcA6luVTj35JLzUpMpaRato4=; b=rGLbfTzwekpD+fIVdJH0kTIWdXZxTkJ65A7FA1cU4UVy1oukWNNUkFohKLd+EzgrJe kXzhQUhZzEt2VFF3GulcRF3RU8FhhWfvjRHy7HbFH/GjO7/DbXt2mH77yyrgpSawBtPR mU8BP/aqpltTTnJEvaduwIG/dJm4Hjdd1qX2BRnFley04l1rXKo3OhqTbtchyZahqDEf yv5KsD5n6gmqWqaTKoyW2KPka5R1Dr2ZGWK8rzpaOqE3Q332ADha2jdjDhd4S0b4/Hc8 UQ4/VOV4k2as0XM8WiswFGvaV3tpOiEaCxqVP8i7qP7vSPHRh2yW9nyICKlyRlIQW6h3 KSUw== X-Gm-Message-State: AFqh2kpc441QPZEyMTlpakLrpXoWcSwxvzASdxP5eC6Rr0vW8Vz/jHKI oPRNvTT527LoaBVDbV16AQtYk03JjPL8rTex X-Google-Smtp-Source: AMrXdXsRStfU2A/qAxNENdIMUtVzdVepat1auzx0IA481TmGUnh3W1DDg51Fh+NS/RpUXw8TGtHVGw== X-Received: by 2002:a05:6808:638e:b0:360:d0db:d3c2 with SMTP id ec14-20020a056808638e00b00360d0dbd3c2mr12976253oib.15.1672234439509; Wed, 28 Dec 2022 05:33:59 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt , Bin Meng Subject: [PATCH v3 05/10] hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() Date: Wed, 28 Dec 2022 10:33:31 -0300 Message-Id: <20221228133336.197467-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221228133336.197467-1-dbarboza@ventanamicro.com> References: <20221228133336.197467-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1672234580164000005 riscv_load_initrd() returns the initrd end addr while also writing a 'start' var to mark the addr start. These informations are being used just to write the initrd FDT node. Every existing caller of riscv_load_initrd() is writing the FDT in the same manner. We can simplify things by writing the FDT inside riscv_load_initrd(), sparing callers from having to manage start/end addrs to write the FDT themselves. An 'if (fdt)' check is already inserted at the end of the function because we'll end up using it later on with other boards that doesn=C2=B4t have a FDT. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng --- hw/riscv/boot.c | 18 ++++++++++++------ hw/riscv/microchip_pfsoc.c | 10 ++-------- hw/riscv/sifive_u.c | 10 ++-------- hw/riscv/spike.c | 10 ++-------- hw/riscv/virt.c | 10 ++-------- include/hw/riscv/boot.h | 4 ++-- 6 files changed, 22 insertions(+), 40 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 98b80af51b..d3c71b3f0b 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -204,9 +204,10 @@ target_ulong riscv_load_kernel(const char *kernel_file= name, exit(1); } =20 -hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, - uint64_t kernel_entry, hwaddr *start) +void riscv_load_initrd(const char *filename, uint64_t mem_size, + uint64_t kernel_entry, void *fdt) { + hwaddr start, end; ssize_t size; =20 /* @@ -220,18 +221,23 @@ hwaddr riscv_load_initrd(const char *filename, uint64= _t mem_size, * halfway into RAM, and for boards with 256MB of RAM or more we put * the initrd at 128MB. */ - *start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); + start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); =20 - size =3D load_ramdisk(filename, *start, mem_size - *start); + size =3D load_ramdisk(filename, start, mem_size - start); if (size =3D=3D -1) { - size =3D load_image_targphys(filename, *start, mem_size - *start); + size =3D load_image_targphys(filename, start, mem_size - start); if (size =3D=3D -1) { error_report("could not load ramdisk '%s'", filename); exit(1); } } =20 - return *start + size; + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ + if (fdt) { + end =3D start + size; + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + } } =20 uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index b10321b564..593a799549 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -633,14 +633,8 @@ static void microchip_icicle_kit_machine_init(MachineS= tate *machine) kernel_start_addr, NULL); =20 if (machine->initrd_filename) { - hwaddr start; - hwaddr end =3D riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-end", end); + riscv_load_initrd(machine->initrd_filename, machine->ram_size, + kernel_entry, machine->fdt); } =20 if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index ddceb750ea..37f5087172 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -608,14 +608,8 @@ static void sifive_u_machine_init(MachineState *machin= e) kernel_start_addr, NULL); =20 if (machine->initrd_filename) { - hwaddr start; - hwaddr end =3D riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-e= nd", - end); + riscv_load_initrd(machine->initrd_filename, machine->ram_size, + kernel_entry, machine->fdt); } } else { /* diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 0d2feea930..360bf83564 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -311,14 +311,8 @@ static void spike_board_init(MachineState *machine) htif_symbol_callback); =20 if (machine->initrd_filename) { - hwaddr start; - hwaddr end =3D riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-e= nd", - end); + riscv_load_initrd(machine->initrd_filename, machine->ram_size, + kernel_entry, machine->fdt); } } else { /* diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 408f7a2256..5967b136b4 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1291,14 +1291,8 @@ static void virt_machine_done(Notifier *notifier, vo= id *data) kernel_start_addr, NULL); =20 if (machine->initrd_filename) { - hwaddr start; - hwaddr end =3D riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-e= nd", - end); + riscv_load_initrd(machine->initrd_filename, machine->ram_size, + kernel_entry, machine->fdt); } } else { /* diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index b273ab22f7..e37e1d1238 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -46,8 +46,8 @@ target_ulong riscv_load_firmware(const char *firmware_fil= ename, target_ulong riscv_load_kernel(const char *kernel_filename, target_ulong firmware_end_addr, symbol_fn_t sym_cb); -hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, - uint64_t kernel_entry, hwaddr *start); +void riscv_load_initrd(const char *filename, uint64_t mem_size, + uint64_t kernel_entry, void *fdt); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState = *harts, hwaddr saddr, --=20 2.38.1 From nobody Fri Nov 1 00:15:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1672234497; cv=none; d=zohomail.com; s=zohoarc; b=k0ULlOvzUyvTuutlgDXBSZ1ckiA7LzUsjB9jRGyavEV+gr/MeccUCQgX6sPXz9lAxQvyPGClz2Gm7rEjauTtJCQZYxLngmQGqXMZKR52E5mSct4PYtHwrC+ns7R32Mw76zAILTJNthjDJpZ7VCTe5GMXl5yqBR3+kjfKe/I+Q2Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672234497; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GeCiC3GKUs9WcRKhA9RfO9im1F+/KYIPp7kBcBoEaXc=; b=gkP+XtHSndaCASHs6nA+QaAq0QdBVo4ck6ytkros+PeQVkNrtJKCJrGqxgKeb1ziN5yBRkyQHY9/2HbhI5rTkg2F7tVLU3hsYJoOgxc++Rwi1QadxrFinINtfP1ppgtCbOuGzJX/biw8DaBqjCK7dFg11WPN+tdwL8zx/vQDVxc= ARC-Authentication-Results: i=1; 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([191.17.222.139]) by smtp.gmail.com with ESMTPSA id bl22-20020a056808309600b0035e7d07bf9dsm6991626oib.16.2022.12.28.05.33.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 05:34:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GeCiC3GKUs9WcRKhA9RfO9im1F+/KYIPp7kBcBoEaXc=; b=SIXZXOLsTJgzvIJHJeMgL89skTwcg7Jw76EInMaVYlXeaeu60Tjq+SZTd5zHmmYPaK SHnGLXhENZE+jDOXr80BHU80Svuxk0eSWozel7R2BfUFztlC93W5/ZarVAZR5zhhYc5V 4ginaipoFyVjuqIIscrnk0+Fihnl6xTf4EW9ePNq6XZ7jqYqzyJYKR7qI+Q/a3NTcCJ0 WUn5zsDbl7PuHbZwZM+YxvdzrRCQzfBa6NlDI+dKakbrYK+yBMRW+dvteAscnqmAPEt2 x4EOpHyiTzEJJcXk5cpkM+K/mSUG53u3NPbZgUFOdVDXspZr9h8qSkdSWjtuPjm2kDil ekoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GeCiC3GKUs9WcRKhA9RfO9im1F+/KYIPp7kBcBoEaXc=; b=TLVeToOREIuS7yRCDY5zVOz/KHlVsCRdv57xqcq9hS4ak05LGUa+73m+86XuCzZoIb T9zmAQheEYYnQKUTzBrnmulQrMLIODz8KpbyQsOCK+YRCVZlyiqOAateL4qSCpcxpCrD +UsS5kAzRWnnou8FLvHEkSx0bBZuWte8AsR8Ne23/FtWldDwwFpRd6sUAAst1P0gs24U OqkolpDtYa2xgNR5gmyqHWwP/TgZUl2wa5saUoQPH9/FsDSf7KfWpJThbKqvhHFqFdeG LGHyQFqJQa7OfRnsJiXdnwvRbq2pFlJSH1JF6Rz9xcvEiLgydyELJLEjNNpCTsVEw7cs BZWA== X-Gm-Message-State: AFqh2kq84j942dS27mCT9HJIftvmsSODslcvehelaTOIxqBPHcAQ7bKZ zr/E5FK2yoY6ZaEQqzR6J4A1a9yTMUGixixZ X-Google-Smtp-Source: AMrXdXuEnRVmNE3ZBPjyLP6dckRRisqCSzYFHXCss4lkVGhOmby+CVSpQKj/Q8lRWSrByWx5ppAf1Q== X-Received: by 2002:a05:6808:1a03:b0:35e:d61b:fdb7 with SMTP id bk3-20020a0568081a0300b0035ed61bfdb7mr13581231oib.2.1672234442318; Wed, 28 Dec 2022 05:34:02 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt , Bin Meng Subject: [PATCH v3 06/10] hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() Date: Wed, 28 Dec 2022 10:33:32 -0300 Message-Id: <20221228133336.197467-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221228133336.197467-1-dbarboza@ventanamicro.com> References: <20221228133336.197467-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1672234499003000001 Content-Type: text/plain; charset="utf-8" The sifive_u, spike and virt machines are writing the 'bootargs' FDT node during their respective create_fdt(). Given that bootargs is written only when '-append' is used, and this option is only allowed with the '-kernel' option, which in turn is already being check before executing riscv_load_kernel(), write 'bootargs' in the same code path as riscv_load_kernel(). Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng --- hw/riscv/sifive_u.c | 11 +++++------ hw/riscv/spike.c | 9 +++++---- hw/riscv/virt.c | 11 +++++------ 3 files changed, 15 insertions(+), 16 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 37f5087172..3e6df87b5b 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -117,7 +117,6 @@ static void create_fdt(SiFiveUState *s, const MemMapEnt= ry *memmap, error_report("load_device_tree() failed"); exit(1); } - goto update_bootargs; } else { fdt =3D ms->fdt =3D create_device_tree(&fdt_size); if (!fdt) { @@ -510,11 +509,6 @@ static void create_fdt(SiFiveUState *s, const MemMapEn= try *memmap, qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); =20 g_free(nodename); - -update_bootargs: - if (cmdline && *cmdline) { - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); - } } =20 static void sifive_u_machine_reset(void *opaque, int n, int level) @@ -611,6 +605,11 @@ static void sifive_u_machine_init(MachineState *machin= e) riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, machine->fdt); } + + if (machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 360bf83564..775f910a50 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -179,10 +179,6 @@ static void create_fdt(SpikeState *s, const MemMapEntr= y *memmap, =20 qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); - - if (cmdline && *cmdline) { - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); - } } =20 static bool spike_test_elf_image(char *filename) @@ -314,6 +310,11 @@ static void spike_board_init(MachineState *machine) riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, machine->fdt); } + + if (machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 5967b136b4..6c946b6def 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1012,7 +1012,6 @@ static void create_fdt(RISCVVirtState *s, const MemMa= pEntry *memmap, error_report("load_device_tree() failed"); exit(1); } - goto update_bootargs; } else { mc->fdt =3D create_device_tree(&s->fdt_size); if (!mc->fdt) { @@ -1050,11 +1049,6 @@ static void create_fdt(RISCVVirtState *s, const MemM= apEntry *memmap, create_fdt_fw_cfg(s, memmap); create_fdt_pmu(s); =20 -update_bootargs: - if (cmdline && *cmdline) { - qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline); - } - /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_= seed)); @@ -1294,6 +1288,11 @@ static void virt_machine_done(Notifier *notifier, vo= id *data) riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, machine->fdt); } + + if (machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode --=20 2.38.1 From nobody Fri Nov 1 00:15:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1672234663; cv=none; d=zohomail.com; s=zohoarc; b=HXD+JdgzqnkavNcRnIKhgF71k9RTTeGztSTjYzM71CHAyckLm/G8VyIBWBASYFZiBYz4bJk4JGz+fxaBxU9L+fMMXtMNUAkym8b9zLnui6vVRfA3CrY0G3cgjA3y93NZiLIN1krI0nNk440XJJ4vI4KkQVF/QnFOPi7astFR7CY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672234663; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([191.17.222.139]) by smtp.gmail.com with ESMTPSA id bl22-20020a056808309600b0035e7d07bf9dsm6991626oib.16.2022.12.28.05.34.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 05:34:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M0I6I7BTYvBBitBG8CZ1/GT6K54bRfBzh9f9r61PxUs=; b=KPX8O34kFW+7ro8uMu+ANsgh9GXEoa85S1u3XDLEMXQEzvwLaSma3L+csIGWU/+0pG n29vv63NLFsKApvo5G6J09uBRsLujXtt1U6QQ9xmN7YRo1lLqAwUr87HtW6L5H6WHOle wwIH3sh+lXT1t60p7QyOzcQO0KoiVom3/p7aljs9eKcop1GKsYj0U6rhw1ALh8PokH2K GTcb0xgv95LxPlLzUw8SlvVsDJyib9dlcdmLh2mJPq9AxbwAFCQRQnBD0LI5YOq8vXGh azaS5r5NA1rjLD8JytEKxvTqX9FaaKiau6dF+tWb502xCqMjON8HptsFZKBWjD3WGaFx ZzDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M0I6I7BTYvBBitBG8CZ1/GT6K54bRfBzh9f9r61PxUs=; b=lCbMaYu59viKT4UBySVdZi+ZNrx0RQtm5jDI6TC33Taq7Clh/Y9KHnBt1PLs+MvVhG /3+GOZP8PqISkelXm4GP9N1tB4PeoXvo8CsBhVGg2+T1i0KaOrz6nnUGWE5WumPyh4G+ 9hp9Zdj1SaYg2JD78swIABttORJ/mWKgC+1vV78ZuORT/kpkkbarNIBIYA18nJR2OdWr mxxdWu60SwJFlSZK6pelrDozw72LlPSdr9tEU+OSHC44/B6ED2bLBRYnv+DMWCnEgudM KaMBNAj9FjUyoLCKKq7JgFEjfRGfO6wxRi5BvRZLNgQFd7HjvubU5kphYbLU9mkNt41D DptQ== X-Gm-Message-State: AFqh2kpxTD0i7GiKsfU39kL5KB1T2Ak8jfTRK+7MY/jOjp58ciscwCpa pSo/PIINsuEgxTVHpVe8lNRA8eAaeyxRnfoi X-Google-Smtp-Source: AMrXdXsDz8wI+fcXEP6JWLEx1AuPWogUuhU9VFMI1imDIzRNA13k+t12hHpryGaigJCLF3CZWdzY7Q== X-Received: by 2002:a05:6808:2387:b0:360:e45e:18d6 with SMTP id bp7-20020a056808238700b00360e45e18d6mr14739844oib.59.1672234445232; Wed, 28 Dec 2022 05:34:05 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v3 07/10] hw/riscv/boot.c: use MachineState in riscv_load_initrd() Date: Wed, 28 Dec 2022 10:33:33 -0300 Message-Id: <20221228133336.197467-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221228133336.197467-1-dbarboza@ventanamicro.com> References: <20221228133336.197467-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1672234664656000001 'filename', 'mem_size' and 'fdt' from riscv_load_initrd() can all be retrieved by the MachineState object for all callers. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bin Meng --- hw/riscv/boot.c | 6 ++++-- hw/riscv/microchip_pfsoc.c | 3 +-- hw/riscv/sifive_u.c | 3 +-- hw/riscv/spike.c | 3 +-- hw/riscv/virt.c | 3 +-- include/hw/riscv/boot.h | 3 +-- 6 files changed, 9 insertions(+), 12 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index d3c71b3f0b..f7e806143a 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -204,9 +204,11 @@ target_ulong riscv_load_kernel(const char *kernel_file= name, exit(1); } =20 -void riscv_load_initrd(const char *filename, uint64_t mem_size, - uint64_t kernel_entry, void *fdt) +void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) { + const char *filename =3D machine->initrd_filename; + uint64_t mem_size =3D machine->ram_size; + void *fdt =3D machine->fdt; hwaddr start, end; ssize_t size; =20 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 593a799549..1e9b0a420e 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -633,8 +633,7 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) kernel_start_addr, NULL); =20 if (machine->initrd_filename) { - riscv_load_initrd(machine->initrd_filename, machine->ram_size, - kernel_entry, machine->fdt); + riscv_load_initrd(machine, kernel_entry); } =20 if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 3e6df87b5b..c40885ed5c 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -602,8 +602,7 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr, NULL); =20 if (machine->initrd_filename) { - riscv_load_initrd(machine->initrd_filename, machine->ram_size, - kernel_entry, machine->fdt); + riscv_load_initrd(machine, kernel_entry); } =20 if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 775f910a50..0c22978b12 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -307,8 +307,7 @@ static void spike_board_init(MachineState *machine) htif_symbol_callback); =20 if (machine->initrd_filename) { - riscv_load_initrd(machine->initrd_filename, machine->ram_size, - kernel_entry, machine->fdt); + riscv_load_initrd(machine, kernel_entry); } =20 if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 6c946b6def..02f1369843 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1285,8 +1285,7 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) kernel_start_addr, NULL); =20 if (machine->initrd_filename) { - riscv_load_initrd(machine->initrd_filename, machine->ram_size, - kernel_entry, machine->fdt); + riscv_load_initrd(machine, kernel_entry); } =20 if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index e37e1d1238..cfd72ecabf 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -46,8 +46,7 @@ target_ulong riscv_load_firmware(const char *firmware_fil= ename, target_ulong riscv_load_kernel(const char *kernel_filename, target_ulong firmware_end_addr, symbol_fn_t sym_cb); -void riscv_load_initrd(const char *filename, uint64_t mem_size, - uint64_t kernel_entry, void *fdt); +void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState = *harts, hwaddr saddr, --=20 2.38.1 From nobody Fri Nov 1 00:15:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1672234576; cv=none; d=zohomail.com; s=zohoarc; b=RANeXyAtyvOjYNvHGTZy3npSxdb/SVAbyk53QjSzGKD95gGMevMe+2n+IsggTXhc1qYE189sIZBo9vsyjxfSGgouz0jEzSy3lO7rqCagZCwr9WK2hRDQH6BEjEG+iCGJHjeK7qDWV5eW6GOYKVifAnIz+cSdrZv9DqI3+RQX7z4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672234576; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([191.17.222.139]) by smtp.gmail.com with ESMTPSA id bl22-20020a056808309600b0035e7d07bf9dsm6991626oib.16.2022.12.28.05.34.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 05:34:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h4URkCnDXZ52ZiFju+e2eRoOimDur6z8+OMmjMNkZuk=; b=gByYQlK2ZAa5QNI5o4XJJUmRXJH9N3wKYBZGeZnzfZOAd4FLDEd/A28Q8nJD+3Xv6l /iptq/wcUiux9E3RTHIyybNCPtI64QewsHm/V8jZ3EcwsBHofPfH6XRFPxfWyTkiWUBT QgRnogUyjeGwvBTUFVRnz/4hz+2/71P/UuD6kaCPC9BfAO4LhY3Y1VKCMDwYNfAZK69x il+aPP18PbsngrNf+lvauEtAyczfX4DsGroFWuuh2CsgTtVGxsohuVOyWD1W1sDLMZVA T5u6D2dzbKzcKPn736HD8eWa1uUH2xf+unJyVswml2Gn+H2l+Y+YAtX9IBvnzAb0soQY jYhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h4URkCnDXZ52ZiFju+e2eRoOimDur6z8+OMmjMNkZuk=; b=eeOqIlYIkhTQhZEofLQ5GyekxB4ls9bvtZwZpwMRWWOpx+zX2lARxsgr7HlhD3RMX+ 8dkcFuk0zn/ITM1ZuemMdciIlQ5WBfRyZs4vpY+wNqMqhBFtibBh7iyvwvvmVXsGr+uz n0tMYJDM+wJoPPSM4ZTVqqlQ6nbIWHNXp9B/WI+3Wyg9JONkuWSBrYWvOC4XoasLmvQG aukDWodcH44+qPtqmpzEUq7e2h3TWd852/hRksmEz2lLcRwtCMA6Zr7G7tNyoGnMHlXl yDLjUhEPkEO1GM+OIRd2WxekUzxC/pvB+9VDRTo9HCXhRpFd6U6iEXEiI9hl3vNnCQLy U92g== X-Gm-Message-State: AFqh2ko58XXnFURt6eTigEMU4jWs+arvFlmHQS3+5UJq9pg/NbyX9Lhc WPb+ldfV+/yhR8byaeke+OY6xs+a76Y/DwGd X-Google-Smtp-Source: AMrXdXu2zf4aEb8AB+SqvyyCGZXC3ba/Z5VSnGT+YBsO2eEwEiiKTCemaQ4ySK4XspmiNqmpI2nmog== X-Received: by 2002:a05:6808:2119:b0:35e:d67e:3dcd with SMTP id r25-20020a056808211900b0035ed67e3dcdmr23167829oiw.58.1672234448363; Wed, 28 Dec 2022 05:34:08 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v3 08/10] hw/riscv/boot.c: use MachineState in riscv_load_kernel() Date: Wed, 28 Dec 2022 10:33:34 -0300 Message-Id: <20221228133336.197467-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221228133336.197467-1-dbarboza@ventanamicro.com> References: <20221228133336.197467-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1672234579097000002 All callers are using kernel_filename as machine->kernel_filename. This will also simplify the changes in riscv_load_kernel() that we're going to do next. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bin Meng --- hw/riscv/boot.c | 3 ++- hw/riscv/microchip_pfsoc.c | 3 +-- hw/riscv/opentitan.c | 3 +-- hw/riscv/sifive_e.c | 3 +-- hw/riscv/sifive_u.c | 3 +-- hw/riscv/spike.c | 3 +-- hw/riscv/virt.c | 3 +-- include/hw/riscv/boot.h | 2 +- 8 files changed, 9 insertions(+), 14 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index f7e806143a..cd9c989edb 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -171,10 +171,11 @@ target_ulong riscv_load_firmware(const char *firmware= _filename, exit(1); } =20 -target_ulong riscv_load_kernel(const char *kernel_filename, +target_ulong riscv_load_kernel(MachineState *machine, target_ulong kernel_start_addr, symbol_fn_t sym_cb) { + const char *kernel_filename =3D machine->kernel_filename; uint64_t kernel_load_base, kernel_entry; =20 /* diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 1e9b0a420e..82ae5e7023 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -629,8 +629,7 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, NULL); + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); =20 if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 85ffdac5be..64d5d435b9 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -101,8 +101,7 @@ static void opentitan_board_init(MachineState *machine) } =20 if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename, - memmap[IBEX_DEV_RAM].base, NULL); + riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); } } =20 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index d65d2fd869..3e3f4b0088 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,8 +114,7 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_m= emory); =20 if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename, - memmap[SIFIVE_E_DEV_DTIM].base, NULL); + riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); } } =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index c40885ed5c..bac394c959 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -598,8 +598,7 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, NULL); + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); =20 if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 0c22978b12..0bba5c1640 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -302,8 +302,7 @@ static void spike_board_init(MachineState *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, htif_symbol_callback); =20 if (machine->initrd_filename) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 02f1369843..c8e35f861e 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1281,8 +1281,7 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, NULL); + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); =20 if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index cfd72ecabf..f94653a09b 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -43,7 +43,7 @@ char *riscv_find_firmware(const char *firmware_filename, target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); -target_ulong riscv_load_kernel(const char *kernel_filename, +target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, symbol_fn_t sym_cb); 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([191.17.222.139]) by smtp.gmail.com with ESMTPSA id bl22-20020a056808309600b0035e7d07bf9dsm6991626oib.16.2022.12.28.05.34.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 05:34:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0c8v4Kzp6n3Errv259XkpaJdjC4fJUPdPSAlyN0HvCw=; b=cCq6zkOGRpS+JsKCBNo7X1DEtTy4ZZhnkt+3PkHqqsLcNljC1K8kP3Px51QIHINJ+f rAfvU/blQ0QwGvotpehO9IBmQBOEV0n6xfKG0Ail03SGmou8AT5jHow8Uf20Xx/Pqkv5 d+t2VIl7aRG3rvAWjTfohxJ6smSexW643HgMe4LhwZlsMiRdt8cngM0zfKGWlz6Jk4Bv clV5R4FBts1207KO/cOwupeufV+BnDOAbqkTL+ynFoJWIWdbQVqmoIjgaHFVy6vUYj9n crMa0w0FEhKxbJlHRF6RK/y50gKd8cCSJ2YqEgJJBknWFsp00eET5vKkMC/iC2/GFGbi KZLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0c8v4Kzp6n3Errv259XkpaJdjC4fJUPdPSAlyN0HvCw=; b=7rwmQLP+lJ9zxnjMSVWrQZ1xLX+rGGoB2bpT6ZavcDhjYBs8vm0XmGyeHyJSOl9PUk 72P1+ZyAM/Q3Ds1UVYuxnvhXLy7kvn228UuRdzmQLvOc50dnkGda/U/3KEfq+v4VG2+r x4io30V2FHmDNdHMx5dlEfi+enXMTIjJF+qoF+ZaejtWv/e5xQwyRZ7jB7gFEankH20n Ig3LFHJCcjZ7RwWAfg9ffYg5SC4yvGpJ5nJZlRj/AwP8gB6s/YON1h74enrfKrYQ2e2E Nc/BWOyzfdqiIchRK7XAOJa4Tqeo28KkCikdyLqt5vRfFXzmLmQ7oa41FCdn3QlrwVKZ G0/g== X-Gm-Message-State: AFqh2koUG1LUfhBhb7IRxhMy+KREk4S3gTudA2Vo+FY8lA/IrO66cz/0 2jyF9YazzV3beniTitcJ2H7bDzvb/W6ff3Dm X-Google-Smtp-Source: AMrXdXuAimBhANkHmed6YrUBZGAGNyLjzm5M3uSZBmH9blCDPwqeqfrkUJs6ECRgKZffiSwnGUciPQ== X-Received: by 2002:a54:458a:0:b0:35e:85a8:2dc7 with SMTP id z10-20020a54458a000000b0035e85a82dc7mr11067751oib.26.1672234450925; Wed, 28 Dec 2022 05:34:10 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt Subject: [PATCH v3 09/10] hw/riscv/boot.c: introduce riscv_load_kernel_and_initrd() Date: Wed, 28 Dec 2022 10:33:35 -0300 Message-Id: <20221228133336.197467-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221228133336.197467-1-dbarboza@ventanamicro.com> References: <20221228133336.197467-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1672234526348000003 Content-Type: text/plain; charset="utf-8" The microchip_icicle_kit, sifive_u, spike and virt boards are now doing the same steps when '-kernel' is used: - execute load_kernel() - load init_rd() - write kernel_cmdline in the fdt Let's fold everything inside riscv_load_kernel() to avoid code repetition. Every other board that uses riscv_load_kernel() will have this same behavior, including boards that doesn't have a valid FDT, so we need to take care to not do FDT operations without checking it first. Since we're now doing way more than just loading the kernel, rename riscv_load_kernel() to riscv_load_kernel_and_initrd(). Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/boot.c | 27 +++++++++++++++++++++------ hw/riscv/microchip_pfsoc.c | 12 ++---------- hw/riscv/opentitan.c | 2 +- hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 12 ++---------- hw/riscv/spike.c | 14 +++----------- hw/riscv/virt.c | 12 ++---------- include/hw/riscv/boot.h | 6 +++--- 8 files changed, 36 insertions(+), 52 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index cd9c989edb..6d1243ad8b 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -171,12 +171,13 @@ target_ulong riscv_load_firmware(const char *firmware= _filename, exit(1); } =20 -target_ulong riscv_load_kernel(MachineState *machine, - target_ulong kernel_start_addr, - symbol_fn_t sym_cb) +target_ulong riscv_load_kernel_and_initrd(MachineState *machine, + target_ulong kernel_start_addr, + symbol_fn_t sym_cb) { const char *kernel_filename =3D machine->kernel_filename; uint64_t kernel_load_base, kernel_entry; + void *fdt =3D machine->fdt; =20 /* * NB: Use low address not ELF entry point to ensure that the fw_dynam= ic @@ -188,21 +189,35 @@ target_ulong riscv_load_kernel(MachineState *machine, if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL, &kernel_load_base, NULL, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { - return kernel_load_base; + kernel_entry =3D kernel_load_base; + goto out; } =20 if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, NULL, NULL, NULL) > 0) { - return kernel_entry; + goto out; } =20 if (load_image_targphys_as(kernel_filename, kernel_start_addr, current_machine->ram_size, NULL) > 0) { - return kernel_start_addr; + kernel_entry =3D kernel_start_addr; + goto out; } =20 error_report("could not load kernel '%s'", kernel_filename); exit(1); + +out: + if (machine->initrd_filename) { + riscv_load_initrd(machine, kernel_entry); + } + + if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } + + return kernel_entry; } =20 void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 82ae5e7023..b64631f166 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -629,16 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineS= tate *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", - "bootargs", machine->kernel_cmdline); - } + kernel_entry =3D riscv_load_kernel_and_initrd(machine, kernel_star= t_addr, + NULL); =20 /* Compute the fdt load address in dram */ fdt_load_addr =3D riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].b= ase, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 64d5d435b9..0818d9610c 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -101,7 +101,7 @@ static void opentitan_board_init(MachineState *machine) } =20 if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); + riscv_load_kernel_and_initrd(machine, memmap[IBEX_DEV_RAM].base, N= ULL); } } =20 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 3e3f4b0088..e22628b623 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_m= emory); =20 if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); + riscv_load_kernel_and_initrd(machine, memmap[SIFIVE_E_DEV_DTIM].ba= se, + NULL); } } =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index bac394c959..b6fb715a9f 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -598,16 +598,8 @@ static void sifive_u_machine_init(MachineState *machin= e) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_entry =3D riscv_load_kernel_and_initrd(machine, kernel_star= t_addr, + NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 0bba5c1640..a23ada8a03 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -302,17 +302,9 @@ static void spike_board_init(MachineState *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, - htif_symbol_callback); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_entry =3D riscv_load_kernel_and_initrd(machine, + kernel_start_addr, + htif_symbol_callback); } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c8e35f861e..eadf057940 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1281,16 +1281,8 @@ static void virt_machine_done(Notifier *notifier, vo= id *data) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_entry =3D riscv_load_kernel_and_initrd(machine, kernel_star= t_addr, + NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index f94653a09b..16b86450d3 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -43,9 +43,9 @@ char *riscv_find_firmware(const char *firmware_filename, target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); -target_ulong riscv_load_kernel(MachineState *machine, - target_ulong firmware_end_addr, - symbol_fn_t sym_cb); +target_ulong riscv_load_kernel_and_initrd(MachineState *machine, + target_ulong firmware_end_addr, + symbol_fn_t sym_cb); void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState = *harts, --=20 2.38.1 From nobody Fri Nov 1 00:15:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1672234567; cv=none; d=zohomail.com; s=zohoarc; b=I6Gt9r+cB5MYB3T5RGLX9/HheKmX4E6tjZByjFm2qhcK8inm257/TGa2vBTRwNYtW7cbWx+1lCq3tH+Oj19TbPPgy6v6dnxI54WfzMiy239K9QBm1vDMJ7KeDF+sgfUT/m5kyZXnnSzMd+8CW8G/32M2C3JB+hcZKErT+Es4wgU= ARC-Message-Signature: i=1; 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([191.17.222.139]) by smtp.gmail.com with ESMTPSA id bl22-20020a056808309600b0035e7d07bf9dsm6991626oib.16.2022.12.28.05.34.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 05:34:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=URSBFO5Y07ig/B0eN3m2FMoCUzD0Tx0ChZa1jRpi5NI=; b=ZWMAqUpqnLpAmp3yObsIqlqO2bzL7V5xc7jFUpjJsMRMuVbbiRd5zT/cq1NM/3sFXF Z5NkCI1mIdU+FAiERft25KMkotBuFnsvQplnXVnaKZMrVPz5HSOP2BHs4eLQeTBIdYGH MjfEFFQp7UM9LXKUeUmOPLhfJqdfZWAjhvl1a8FYFHocio6uo7YHQRe9Ve3XnxLX0cgH 7yOriqWyp9wGAEFAEp/BdU++6XD3Sef+1pFI3umy/Am7tJ6KbeV+TAHEvGcJMCpSBmKP HbrqE4xnPbrrBgeEfdt7Dq5O/y04HguLXOk9NK+aOw1UJOomW6IYoT+jJ2ClG+2jcC/e Xy9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=URSBFO5Y07ig/B0eN3m2FMoCUzD0Tx0ChZa1jRpi5NI=; b=IAk5yINQcQzFOwg3RU6g99nr0peK3vsXgD/foF8X61s1ZnaavUQA0s/P/a9Wnivvvc h0TuvyOjBvceQg49Vs9z8apTlw4Kc4fRthRKpnzTMvs7acHknTe3CQMtRc7LCOYmM16E ktxN56CzKjp44kTIzYYa+wCJ5OP3+EmeUNZTt5P5wNTQHIj1augr6Z9lk4nWFQTXlunG xM69EU85L1xBxxggnFp4v8VD0EX7NY81WoqP2wEwfiP36kPaiZd+nV30AFAS15pQ/0Hi +M14qO1kDkV4y8Nao79afLvgTJf9RdoHnIOoLpDbgoo9U/CFj7+VYFiVRssD6oKpgwTv z2kQ== X-Gm-Message-State: AFqh2kqAVT7fmTmIdDg1RNh0JB6xLtyJyI+9WWPHNSafeLcqpuz5Kmpe xStJKJ5fHuhX2OF3dVvjNxFA/x8lhxWIBUD6 X-Google-Smtp-Source: AMrXdXu/bKo1QOuDRFo1nuPOBMnNszEQGeTA9FPR8Zfe+OCqkcnAF7ffG8X9uM0qyDfiK8x0Af3SkA== X-Received: by 2002:a05:6808:28e:b0:35e:cdd7:d8fe with SMTP id z14-20020a056808028e00b0035ecdd7d8femr11851783oic.53.1672234453739; Wed, 28 Dec 2022 05:34:13 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v3 10/10] hw/riscv/boot.c: make riscv_load_initrd() static Date: Wed, 28 Dec 2022 10:33:36 -0300 Message-Id: <20221228133336.197467-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221228133336.197467-1-dbarboza@ventanamicro.com> References: <20221228133336.197467-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1672234568285000002 The only remaining caller is riscv_load_kernel_and_initrd() which belongs to the same file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bin Meng --- hw/riscv/boot.c | 76 ++++++++++++++++++++--------------------- include/hw/riscv/boot.h | 1 - 2 files changed, 38 insertions(+), 39 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 6d1243ad8b..8a46c8e8f8 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -171,6 +171,44 @@ target_ulong riscv_load_firmware(const char *firmware_= filename, exit(1); } =20 +static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) +{ + const char *filename =3D machine->initrd_filename; + uint64_t mem_size =3D machine->ram_size; + void *fdt =3D machine->fdt; + hwaddr start, end; + ssize_t size; + + /* + * We want to put the initrd far enough into RAM that when the + * kernel is uncompressed it will not clobber the initrd. However + * on boards without much RAM we must ensure that we still leave + * enough room for a decent sized initrd, and on boards with large + * amounts of RAM we must avoid the initrd being so far up in RAM + * that it is outside lowmem and inaccessible to the kernel. + * So for boards with less than 256MB of RAM we put the initrd + * halfway into RAM, and for boards with 256MB of RAM or more we put + * the initrd at 128MB. + */ + start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); + + size =3D load_ramdisk(filename, start, mem_size - start); + if (size =3D=3D -1) { + size =3D load_image_targphys(filename, start, mem_size - start); + if (size =3D=3D -1) { + error_report("could not load ramdisk '%s'", filename); + exit(1); + } + } + + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ + if (fdt) { + end =3D start + size; + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + } +} + target_ulong riscv_load_kernel_and_initrd(MachineState *machine, target_ulong kernel_start_addr, symbol_fn_t sym_cb) @@ -220,44 +258,6 @@ out: return kernel_entry; } =20 -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) -{ - const char *filename =3D machine->initrd_filename; - uint64_t mem_size =3D machine->ram_size; - void *fdt =3D machine->fdt; - hwaddr start, end; - ssize_t size; - - /* - * We want to put the initrd far enough into RAM that when the - * kernel is uncompressed it will not clobber the initrd. However - * on boards without much RAM we must ensure that we still leave - * enough room for a decent sized initrd, and on boards with large - * amounts of RAM we must avoid the initrd being so far up in RAM - * that it is outside lowmem and inaccessible to the kernel. - * So for boards with less than 256MB of RAM we put the initrd - * halfway into RAM, and for boards with 256MB of RAM or more we put - * the initrd at 128MB. - */ - start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); - - size =3D load_ramdisk(filename, start, mem_size - start); - if (size =3D=3D -1) { - size =3D load_image_targphys(filename, start, mem_size - start); - if (size =3D=3D -1) { - error_report("could not load ramdisk '%s'", filename); - exit(1); - } - } - - /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ - if (fdt) { - end =3D start + size; - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); - } -} - uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) { uint64_t temp, fdt_addr; diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 16b86450d3..9c2bd92eff 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -46,7 +46,6 @@ target_ulong riscv_load_firmware(const char *firmware_fil= ename, target_ulong riscv_load_kernel_and_initrd(MachineState *machine, target_ulong firmware_end_addr, symbol_fn_t sym_cb); -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState = *harts, hwaddr saddr, --=20 2.38.1