From nobody Sat May 18 21:26:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1671377090; cv=none; d=zohomail.com; s=zohoarc; b=nQd032AI/JgCb/KjWi3stOKg7Wpgnh1GxVj5J/hGWuXMx4E4JnQqTw9cy1NeTYnZARq2eerd3w2VZ3vaW67LnTkxDSYI5W8i2LbGRMG54Wbr49C2TSVZampKt72bNOui6ZzEWXjW0A5ATmuITYYZTE7k+NVG1/23D1FQ/kd00GU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671377090; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hcvEgX17Zsvo6JOaqqf3agGgGY7EyKmilb8OeV6ogUU=; b=c/bumwBcaWMFtanNk59YuSSkha0FI20zzNjS7RDJx5KL5NRsyEFYjzl9jc/uep3vzmY6+sJOmpFMRizqAgXmbUWDxVOoDd60wTtc7bLtIWawBjRZGUyUOHb+fHTGq95CmHgwBUuj2pq1fZwwp5hw/KCZ/bIPvcvz9WkrGU76f/4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1671377090258402.22553112723267; Sun, 18 Dec 2022 07:24:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p6vVw-0005Mr-NP; Sun, 18 Dec 2022 10:23:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p6nqp-0008BW-C6; Sun, 18 Dec 2022 02:12:47 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p6nqn-0000lQ-MH; Sun, 18 Dec 2022 02:12:47 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CC40160CF6; Sun, 18 Dec 2022 07:12:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D1255C433EF; Sun, 18 Dec 2022 07:12:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1671347557; bh=b3d9vk3zLGZG4IIuROtpmXxmwdL8U1GX7bE+FZvVm0Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MAmzqduXM8ukzRDLKxBcnf7K0nW9a5pfKiRsnuhDGyYIYfqoLzkPpSogMCFn7HVTv kir8+VtkedJYnTZrDGaytV+LG81vSFabTN47fSAloR7s/YlA7yyuQF+sIwtM7Oer1q SRirKqcQJ4T/fvUWWV1P7+8JSb1nfH0TvNELPWNTD6GQZW46+I1HgpIl0l3eANNHVV HQSJnto1qD3ylEShsITl27iifq8SrUy8PML/F/Tv/B9wYB1nWmWByK9ritnbXeuATd /TLjAIFN0UHRunY4Dm5/Hx1ef7zJkVuTh6k2Lewp43vpA4rm5GGnK3tsFk3mEtgP4G ZaXY6FA+fMmcw== From: Felipe Balbi To: Alistair Francis , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Felipe Balbi Subject: [PATCH 1/2] hw/arm/stm32f405: correctly describe the memory layout Date: Sun, 18 Dec 2022 09:12:28 +0200 Message-Id: <20221218071229.484944-2-balbi@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221218071229.484944-1-balbi@kernel.org> References: <20221218071229.484944-1-balbi@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=139.178.84.217; envelope-from=balbi@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 18 Dec 2022 10:23:41 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1671377091382100001 Content-Type: text/plain; charset="utf-8" STM32F405 has 128K of SRAM and another 64K of CCM (Core-coupled Memory) at a different base address. Correctly describe the memory layout to give existing FW images have a chance to run unmodified. Signed-off-by: Felipe Balbi Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/stm32f405_soc.c | 8 ++++++++ include/hw/arm/stm32f405_soc.h | 5 ++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c index c07947d9f8b1..cef23d7ee41a 100644 --- a/hw/arm/stm32f405_soc.c +++ b/hw/arm/stm32f405_soc.c @@ -139,6 +139,14 @@ static void stm32f405_soc_realize(DeviceState *dev_soc= , Error **errp) } memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram= ); =20 + memory_region_init_ram(&s->ccm, NULL, "STM32F405.ccm", CCM_SIZE, + &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(system_memory, CCM_BASE_ADDRESS, &s->ccm); + armv7m =3D DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h index 5bb0c8d56979..249ab5434ec7 100644 --- a/include/hw/arm/stm32f405_soc.h +++ b/include/hw/arm/stm32f405_soc.h @@ -46,7 +46,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC) #define FLASH_BASE_ADDRESS 0x08000000 #define FLASH_SIZE (1024 * 1024) #define SRAM_BASE_ADDRESS 0x20000000 -#define SRAM_SIZE (192 * 1024) +#define SRAM_SIZE (128 * 1024) +#define CCM_BASE_ADDRESS 0x10000000 +#define CCM_SIZE (64 * 1024) =20 struct STM32F405State { /*< private >*/ @@ -65,6 +67,7 @@ struct STM32F405State { STM32F2XXADCState adc[STM_NUM_ADCS]; STM32F2XXSPIState spi[STM_NUM_SPIS]; =20 + MemoryRegion ccm; MemoryRegion sram; MemoryRegion flash; MemoryRegion flash_alias; --=20 2.38.1 From nobody Sat May 18 21:26:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1671377110; cv=none; d=zohomail.com; s=zohoarc; b=dChuYxMj7G2as5prPRYfMuWfZBLC1M+DQpiXJzqRkJ0whb5UAoG3Az1PzQG2x2MT+OFE/rgRTCHjGBMOPdCqnVAN13SW4yJ1KpcSVTJh/JZiUP9jazVU9N9XQJUofQ5SID1VZOXRL0i+d1kMW1ZMuh8MkFaziosyU/p2BsQR6BU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671377110; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Sun, 18 Dec 2022 02:12:47 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 70BFEB80B45; Sun, 18 Dec 2022 07:12:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B38BAC433F2; Sun, 18 Dec 2022 07:12:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1671347559; bh=yGe1sQrHHWksNESJwDTSM2bZGmCWGZPCXGrx3AJlxDg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jaWt2JyEgbgFIbxtfHzRUgQ7OKhj0L4xhbEGI0u/yPGkAMYFpG5UB2Rjr9WCuGZ8L Xlg4GXexmfD3UYM3zT49mi2j+7J5OlyLz2xW6oWlwLx3Wh+gbBXmFdxfigXYVlHk/c IagCJGiinJy/w2vWez6GRiF7eOwjQlKbaOC9Me0Nctf/AxV5fd4rDEdGmt7UJu/Li8 ZnBVV6sH+Qj/U6Y1fhUW8FYy15CzVj7xGrRFLKz6AfMoyWEXDgGEV0O//BEFICxRwd dbuwqbzs/eFraKyYyflz6m4tgrhSYCJVvNQ/4p8p4JBubmUFu2sYOeqs7dXDQIwh5U svxHYKtSXeebQ== From: Felipe Balbi To: Alistair Francis , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Felipe Balbi Subject: [PATCH 2/2] hw/arm: Add Olimex H405 Date: Sun, 18 Dec 2022 09:12:29 +0200 Message-Id: <20221218071229.484944-3-balbi@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221218071229.484944-1-balbi@kernel.org> References: <20221218071229.484944-1-balbi@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2604:1380:4601:e00::1; envelope-from=balbi@kernel.org; helo=ams.source.kernel.org X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 18 Dec 2022 10:23:41 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1671377111207100001 Content-Type: text/plain; charset="utf-8" Olimex makes a series of low-cost STM32 boards. This commit introduces the minimum setup to support SMT32-H405. See [1] for details [1] https://www.olimex.com/Products/ARM/ST/STM32-H405/ Signed-off-by: Felipe Balbi --- MAINTAINERS | 6 +++ configs/devices/arm-softmmu/default.mak | 1 + hw/arm/Kconfig | 4 ++ hw/arm/meson.build | 1 + hw/arm/olimex-stm32-h405.c | 65 +++++++++++++++++++++++++ 5 files changed, 77 insertions(+) create mode 100644 hw/arm/olimex-stm32-h405.c diff --git a/MAINTAINERS b/MAINTAINERS index 3bd433b65a55..e37846df0071 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1026,6 +1026,12 @@ L: qemu-arm@nongnu.org S: Maintained F: hw/arm/netduinoplus2.c =20 +Olimex STM32 H405 +M: Felipe Balbi +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/olimex-stm32-h405.c + SmartFusion2 M: Subbaraya Sundeep M: Peter Maydell diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-= softmmu/default.mak index 6985a25377a0..1b49a7830c7e 100644 --- a/configs/devices/arm-softmmu/default.mak +++ b/configs/devices/arm-softmmu/default.mak @@ -30,6 +30,7 @@ CONFIG_COLLIE=3Dy CONFIG_ASPEED_SOC=3Dy CONFIG_NETDUINO2=3Dy CONFIG_NETDUINOPLUS2=3Dy +CONFIG_OLIMEX_STM32_H405=3Dy CONFIG_MPS2=3Dy CONFIG_RASPI=3Dy CONFIG_DIGIC=3Dy diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 17fcde8e1ccc..9143533ef792 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -119,6 +119,10 @@ config NETDUINOPLUS2 bool select STM32F405_SOC =20 +config OLIMEX_STM32_H405 + bool + select STM32F405_SOC + config NSERIES bool select OMAP diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 92f9f6e000ea..76d4d650e42e 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -12,6 +12,7 @@ arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('micro= bit.c')) arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c')) arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) +arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-= h405.c')) arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_bo= ards.c')) arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c')) arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c')) diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c new file mode 100644 index 000000000000..5171a66074bb --- /dev/null +++ b/hw/arm/olimex-stm32-h405.c @@ -0,0 +1,65 @@ +/* + * ST STM32VLDISCOVERY machine + * Olimex STM32-H405 machine + * + * Copyright (c) 2022 Felipe Balbi + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" +#include "qemu/error-report.h" +#include "hw/arm/stm32f405_soc.h" +#include "hw/arm/boot.h" + +/* olimex-stm32-h405 implementation is derived from netduinoplus2 */ + +/* Main SYSCLK frequency in Hz (168MHz) */ +#define SYSCLK_FRQ 168000000ULL + +static void olimex_stm32_h405_init(MachineState *machine) +{ + DeviceState *dev; + Clock *sysclk; + + /* This clock doesn't need migration because it is fixed-frequency */ + sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(sysclk, SYSCLK_FRQ); + + dev =3D qdev_new(TYPE_STM32F405_SOC); + qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); + qdev_connect_clock_in(dev, "sysclk", sysclk); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + armv7m_load_kernel(ARM_CPU(first_cpu), + machine->kernel_filename, + 0, FLASH_SIZE); +} + +static void olimex_stm32_h405_machine_init(MachineClass *mc) +{ + mc->desc =3D "Olimex STM32-H405 (Cortex-M4)"; + mc->init =3D olimex_stm32_h405_init; +} + +DEFINE_MACHINE("olimex-stm32-h405", olimex_stm32_h405_machine_init) --=20 2.38.1