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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1670584709714100003 "target/arm/internals.h" is supposed to be *internal* to target/arm/. hw/arm/virt.c includes it to get arm_pamax() declaration. Move this declaration to "cpu.h" which can be included out of target/arm/, and move the implementation in machine.c which is always built with system emulation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- RFC: Do we need a new pair of c/h for architectural helpers? ptw.c should be restricted to TCG. --- hw/arm/virt.c | 2 +- target/arm/cpu.h | 9 +++++++++ target/arm/internals.h | 9 --------- target/arm/machine.c | 39 +++++++++++++++++++++++++++++++++++++++ target/arm/ptw.c | 39 --------------------------------------- 5 files changed, 49 insertions(+), 49 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b871350856..4528ca8da2 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -70,7 +70,6 @@ #include "standard-headers/linux/input.h" #include "hw/arm/smmuv3.h" #include "hw/acpi/acpi.h" -#include "target/arm/internals.h" #include "hw/mem/memory-device.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" @@ -79,6 +78,7 @@ #include "hw/virtio/virtio-iommu.h" #include "hw/char/pl011.h" #include "qemu/guest-random.h" +#include "target/arm/cpu.h" =20 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9aeed3c848..8cdad4855f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3444,6 +3444,15 @@ static inline target_ulong cpu_untagged_addr(CPUStat= e *cs, target_ulong x) } #endif =20 +/* + * arm_pamax + * @cpu: ARMCPU + * + * Returns the implementation defined bit-width of physical addresses. + * The ARMv8 reference manuals refer to this as PAMax(). + */ +unsigned int arm_pamax(ARMCPU *cpu); + /* * Naming convention for isar_feature functions: * Functions which test 32-bit ID registers should have _aa32_ in diff --git a/target/arm/internals.h b/target/arm/internals.h index 161e42d50f..5e9546b6a3 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -241,15 +241,6 @@ static inline void update_spsel(CPUARMState *env, uint= 32_t imm) aarch64_restore_sp(env, cur_el); } =20 -/* - * arm_pamax - * @cpu: ARMCPU - * - * Returns the implementation defined bit-width of physical addresses. - * The ARMv8 reference manuals refer to this as PAMax(). - */ -unsigned int arm_pamax(ARMCPU *cpu); - /* Return true if extended addresses are enabled. * This is always the case if our translation regime is 64 bit, * but depends on TTBCR.EAE for 32 bit. diff --git a/target/arm/machine.c b/target/arm/machine.c index 54c5c62433..51f84f90f0 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -6,6 +6,45 @@ #include "internals.h" #include "migration/cpu.h" =20 +/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. = */ +static const uint8_t pamax_map[] =3D { + [0] =3D 32, + [1] =3D 36, + [2] =3D 40, + [3] =3D 42, + [4] =3D 44, + [5] =3D 48, + [6] =3D 52, +}; + +/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ +unsigned int arm_pamax(ARMCPU *cpu) +{ + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + unsigned int parange =3D + FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); + + /* + * id_aa64mmfr0 is a read-only register so values outside of the + * supported mappings can be considered an implementation error. + */ + assert(parange < ARRAY_SIZE(pamax_map)); + return pamax_map[parange]; + } + + /* + * In machvirt_init, we call arm_pamax on a cpu that is not fully + * initialized, so we can't rely on the propagation done in realize. + */ + if (arm_feature(&cpu->env, ARM_FEATURE_LPAE) || + arm_feature(&cpu->env, ARM_FEATURE_V7VE)) { + /* v7 with LPAE */ + return 40; + } + /* Anything else */ + return 32; +} + static bool vfp_needed(void *opaque) { ARMCPU *cpu =3D opaque; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index f812734bfb..03703cb107 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -42,45 +42,6 @@ static bool get_phys_addr_with_struct(CPUARMState *env, = S1Translate *ptw, ARMMMUFaultInfo *fi) __attribute__((nonnull)); =20 -/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. = */ -static const uint8_t pamax_map[] =3D { - [0] =3D 32, - [1] =3D 36, - [2] =3D 40, - [3] =3D 42, - [4] =3D 44, - [5] =3D 48, - [6] =3D 52, -}; - -/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ -unsigned int arm_pamax(ARMCPU *cpu) -{ - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - unsigned int parange =3D - FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); - - /* - * id_aa64mmfr0 is a read-only register so values outside of the - * supported mappings can be considered an implementation error. - */ - assert(parange < ARRAY_SIZE(pamax_map)); - return pamax_map[parange]; - } - - /* - * In machvirt_init, we call arm_pamax on a cpu that is not fully - * initialized, so we can't rely on the propagation done in realize. - */ - if (arm_feature(&cpu->env, ARM_FEATURE_LPAE) || - arm_feature(&cpu->env, ARM_FEATURE_V7VE)) { - /* v7 with LPAE */ - return 40; - } - /* Anything else */ - return 32; -} - /* * Convert a possible stage1+2 MMU index into the appropriate stage 1 MMU = index */ --=20 2.38.1