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gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2d; envelope-from=mchitale@ventanamicro.com; helo=mail-oo1-xc2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1670511393617100003 Sync headers with kernel commit 76dcd734eca2 Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones Acked-by: Bin Meng --- include/standard-headers/drm/drm_fourcc.h | 34 ++++- include/standard-headers/linux/ethtool.h | 63 +++++++- include/standard-headers/linux/fuse.h | 6 +- .../linux/input-event-codes.h | 1 + include/standard-headers/linux/virtio_blk.h | 19 +++ linux-headers/asm-generic/hugetlb_encode.h | 26 ++-- linux-headers/asm-generic/mman-common.h | 2 + linux-headers/asm-mips/mman.h | 2 + linux-headers/asm-riscv/kvm.h | 4 + linux-headers/linux/kvm.h | 1 + linux-headers/linux/psci.h | 14 ++ linux-headers/linux/userfaultfd.h | 4 + linux-headers/linux/vfio.h | 142 ++++++++++++++++++ 13 files changed, 298 insertions(+), 20 deletions(-) diff --git a/include/standard-headers/drm/drm_fourcc.h b/include/standard-h= eaders/drm/drm_fourcc.h index 48b620cbef..b868488f93 100644 --- a/include/standard-headers/drm/drm_fourcc.h +++ b/include/standard-headers/drm/drm_fourcc.h @@ -98,18 +98,42 @@ extern "C" { #define DRM_FORMAT_INVALID 0 =20 /* color index */ +#define DRM_FORMAT_C1 fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C= 3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */ +#define DRM_FORMAT_C2 fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C= 3 2:2:2:2 four pixels/byte */ +#define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 = two pixels/byte */ #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ =20 -/* 8 bpp Red */ +/* 1 bpp Darkness (inverse relationship between channel value and brightne= ss) */ +#define DRM_FORMAT_D1 fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D= 3:D4:D5:D6:D7 1:1:1:1:1:1:1:1 eight pixels/byte */ + +/* 2 bpp Darkness (inverse relationship between channel value and brightne= ss) */ +#define DRM_FORMAT_D2 fourcc_code('D', '2', ' ', ' ') /* [7:0] D0:D1:D2:D= 3 2:2:2:2 four pixels/byte */ + +/* 4 bpp Darkness (inverse relationship between channel value and brightne= ss) */ +#define DRM_FORMAT_D4 fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 = two pixels/byte */ + +/* 8 bpp Darkness (inverse relationship between channel value and brightne= ss) */ +#define DRM_FORMAT_D8 fourcc_code('D', '8', ' ', ' ') /* [7:0] D */ + +/* 1 bpp Red (direct relationship between channel value and brightness) */ +#define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R= 3:R4:R5:R6:R7 1:1:1:1:1:1:1:1 eight pixels/byte */ + +/* 2 bpp Red (direct relationship between channel value and brightness) */ +#define DRM_FORMAT_R2 fourcc_code('R', '2', ' ', ' ') /* [7:0] R0:R1:R2:R= 3 2:2:2:2 four pixels/byte */ + +/* 4 bpp Red (direct relationship between channel value and brightness) */ +#define DRM_FORMAT_R4 fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 = two pixels/byte */ + +/* 8 bpp Red (direct relationship between channel value and brightness) */ #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ =20 -/* 10 bpp Red */ +/* 10 bpp Red (direct relationship between channel value and brightness) */ #define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10= little endian */ =20 -/* 12 bpp Red */ +/* 12 bpp Red (direct relationship between channel value and brightness) */ #define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12= little endian */ =20 -/* 16 bpp Red */ +/* 16 bpp Red (direct relationship between channel value and brightness) */ #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little= endian */ =20 /* 16 bpp RG */ @@ -204,7 +228,9 @@ extern "C" { #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:= Y0:Cr0 8:8:8:8 little endian */ =20 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:= Cr 8:8:8:8 little endian */ +#define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr= :Cb:Y 8:8:8:8 little endian */ #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:= Cb:Cr 8:8:8:8 little endian */ +#define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr= :Cb:Y 8:8:8:8 little endian */ #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:= Y 8:8:8 little endian */ #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed= by U then V, 10:10:10. Non-linear modifier only */ =20 diff --git a/include/standard-headers/linux/ethtool.h b/include/standard-he= aders/linux/ethtool.h index 4537da20cc..1dc56cdc0a 100644 --- a/include/standard-headers/linux/ethtool.h +++ b/include/standard-headers/linux/ethtool.h @@ -736,6 +736,51 @@ enum ethtool_module_power_mode { ETHTOOL_MODULE_POWER_MODE_HIGH, }; =20 +/** + * enum ethtool_podl_pse_admin_state - operational state of the PoDL PSE + * functions. IEEE 802.3-2018 30.15.1.1.2 aPoDLPSEAdminState + * @ETHTOOL_PODL_PSE_ADMIN_STATE_UNKNOWN: state of PoDL PSE functions are + * unknown + * @ETHTOOL_PODL_PSE_ADMIN_STATE_DISABLED: PoDL PSE functions are disabled + * @ETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED: PoDL PSE functions are enabled + */ +enum ethtool_podl_pse_admin_state { + ETHTOOL_PODL_PSE_ADMIN_STATE_UNKNOWN =3D 1, + ETHTOOL_PODL_PSE_ADMIN_STATE_DISABLED, + ETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED, +}; + +/** + * enum ethtool_podl_pse_pw_d_status - power detection status of the PoDL = PSE. + * IEEE 802.3-2018 30.15.1.1.3 aPoDLPSEPowerDetectionStatus: + * @ETHTOOL_PODL_PSE_PW_D_STATUS_UNKNOWN: PoDL PSE + * @ETHTOOL_PODL_PSE_PW_D_STATUS_DISABLED: "The enumeration =E2=80=9Cdisab= led=E2=80=9D is + * asserted true when the PoDL PSE state diagram variable mr_pse_enable is + * false" + * @ETHTOOL_PODL_PSE_PW_D_STATUS_SEARCHING: "The enumeration =E2=80=9Csear= ching=E2=80=9D is + * asserted true when either of the PSE state diagram variables + * pi_detecting or pi_classifying is true." + * @ETHTOOL_PODL_PSE_PW_D_STATUS_DELIVERING: "The enumeration =E2=80=9Cdel= iveringPower=E2=80=9D + * is asserted true when the PoDL PSE state diagram variable pi_powered is + * true." + * @ETHTOOL_PODL_PSE_PW_D_STATUS_SLEEP: "The enumeration =E2=80=9Csleep=E2= =80=9D is asserted + * true when the PoDL PSE state diagram variable pi_sleeping is true." + * @ETHTOOL_PODL_PSE_PW_D_STATUS_IDLE: "The enumeration =E2=80=9Cidle=E2= =80=9D is asserted true + * when the logical combination of the PoDL PSE state diagram variables + * pi_prebiased*!pi_sleeping is true." + * @ETHTOOL_PODL_PSE_PW_D_STATUS_ERROR: "The enumeration =E2=80=9Cerror=E2= =80=9D is asserted + * true when the PoDL PSE state diagram variable overload_held is true." + */ +enum ethtool_podl_pse_pw_d_status { + ETHTOOL_PODL_PSE_PW_D_STATUS_UNKNOWN =3D 1, + ETHTOOL_PODL_PSE_PW_D_STATUS_DISABLED, + ETHTOOL_PODL_PSE_PW_D_STATUS_SEARCHING, + ETHTOOL_PODL_PSE_PW_D_STATUS_DELIVERING, + ETHTOOL_PODL_PSE_PW_D_STATUS_SLEEP, + ETHTOOL_PODL_PSE_PW_D_STATUS_IDLE, + ETHTOOL_PODL_PSE_PW_D_STATUS_ERROR, +}; + /** * struct ethtool_gstrings - string set for data tagging * @cmd: Command number =3D %ETHTOOL_GSTRINGS @@ -1840,6 +1885,20 @@ static inline int ethtool_validate_duplex(uint8_t du= plex) #define MASTER_SLAVE_STATE_SLAVE 3 #define MASTER_SLAVE_STATE_ERR 4 =20 +/* These are used to throttle the rate of data on the phy interface when t= he + * native speed of the interface is higher than the link speed. These shou= ld + * not be used for phy interfaces which natively support multiple speeds (= e.g. + * MII or SGMII). + */ +/* No rate matching performed. */ +#define RATE_MATCH_NONE 0 +/* The phy sends pause frames to throttle the MAC. */ +#define RATE_MATCH_PAUSE 1 +/* The phy asserts CRS to prevent the MAC from transmitting. */ +#define RATE_MATCH_CRS 2 +/* The MAC is programmed with a sufficiently-large IPG. */ +#define RATE_MATCH_OPEN_LOOP 3 + /* Which connector port. */ #define PORT_TP 0x00 #define PORT_AUI 0x01 @@ -2033,8 +2092,8 @@ enum ethtool_reset_flags { * reported consistently by PHYLIB. Read-only. * @master_slave_cfg: Master/slave port mode. * @master_slave_state: Master/slave port state. + * @rate_matching: Rate adaptation performed by the PHY * @reserved: Reserved for future use; see the note on reserved space. - * @reserved1: Reserved for future use; see the note on reserved space. * @link_mode_masks: Variable length bitmaps. * * If autonegotiation is disabled, the speed and @duplex represent the @@ -2085,7 +2144,7 @@ struct ethtool_link_settings { uint8_t transceiver; uint8_t master_slave_cfg; uint8_t master_slave_state; - uint8_t reserved1[1]; + uint8_t rate_matching; uint32_t reserved[7]; uint32_t link_mode_masks[]; /* layout of link_mode_masks fields: diff --git a/include/standard-headers/linux/fuse.h b/include/standard-heade= rs/linux/fuse.h index bda06258be..713d259768 100644 --- a/include/standard-headers/linux/fuse.h +++ b/include/standard-headers/linux/fuse.h @@ -194,6 +194,9 @@ * - add FUSE_SECURITY_CTX init flag * - add security context to create, mkdir, symlink, and mknod requests * - add FUSE_HAS_INODE_DAX, FUSE_ATTR_DAX + * + * 7.37 + * - add FUSE_TMPFILE */ =20 #ifndef _LINUX_FUSE_H @@ -225,7 +228,7 @@ #define FUSE_KERNEL_VERSION 7 =20 /** Minor version number of this interface */ -#define FUSE_KERNEL_MINOR_VERSION 36 +#define FUSE_KERNEL_MINOR_VERSION 37 =20 /** The node ID of the root inode */ #define FUSE_ROOT_ID 1 @@ -533,6 +536,7 @@ enum fuse_opcode { FUSE_SETUPMAPPING =3D 48, FUSE_REMOVEMAPPING =3D 49, FUSE_SYNCFS =3D 50, + FUSE_TMPFILE =3D 51, =20 /* CUSE specific operations */ CUSE_INIT =3D 4096, diff --git a/include/standard-headers/linux/input-event-codes.h b/include/s= tandard-headers/linux/input-event-codes.h index 50790aee5a..815f7a1dff 100644 --- a/include/standard-headers/linux/input-event-codes.h +++ b/include/standard-headers/linux/input-event-codes.h @@ -862,6 +862,7 @@ #define ABS_TOOL_WIDTH 0x1c =20 #define ABS_VOLUME 0x20 +#define ABS_PROFILE 0x21 =20 #define ABS_MISC 0x28 =20 diff --git a/include/standard-headers/linux/virtio_blk.h b/include/standard= -headers/linux/virtio_blk.h index 2dcc90826a..e81715cd70 100644 --- a/include/standard-headers/linux/virtio_blk.h +++ b/include/standard-headers/linux/virtio_blk.h @@ -40,6 +40,7 @@ #define VIRTIO_BLK_F_MQ 12 /* support more than one vq */ #define VIRTIO_BLK_F_DISCARD 13 /* DISCARD is supported */ #define VIRTIO_BLK_F_WRITE_ZEROES 14 /* WRITE ZEROES is supported */ +#define VIRTIO_BLK_F_SECURE_ERASE 16 /* Secure Erase is supported */ =20 /* Legacy feature bits */ #ifndef VIRTIO_BLK_NO_LEGACY @@ -119,6 +120,21 @@ struct virtio_blk_config { uint8_t write_zeroes_may_unmap; =20 uint8_t unused1[3]; + + /* the next 3 entries are guarded by VIRTIO_BLK_F_SECURE_ERASE */ + /* + * The maximum secure erase sectors (in 512-byte sectors) for + * one segment. + */ + __virtio32 max_secure_erase_sectors; + /* + * The maximum number of secure erase segments in a + * secure erase command. + */ + __virtio32 max_secure_erase_seg; + /* Secure erase commands must be aligned to this number of sectors. */ + __virtio32 secure_erase_sector_alignment; + } QEMU_PACKED; =20 /* @@ -153,6 +169,9 @@ struct virtio_blk_config { /* Write zeroes command */ #define VIRTIO_BLK_T_WRITE_ZEROES 13 =20 +/* Secure erase command */ +#define VIRTIO_BLK_T_SECURE_ERASE 14 + #ifndef VIRTIO_BLK_NO_LEGACY /* Barrier before this op. */ #define VIRTIO_BLK_T_BARRIER 0x80000000 diff --git a/linux-headers/asm-generic/hugetlb_encode.h b/linux-headers/asm= -generic/hugetlb_encode.h index 4f3d5aaa11..de687009bf 100644 --- a/linux-headers/asm-generic/hugetlb_encode.h +++ b/linux-headers/asm-generic/hugetlb_encode.h @@ -20,18 +20,18 @@ #define HUGETLB_FLAG_ENCODE_SHIFT 26 #define HUGETLB_FLAG_ENCODE_MASK 0x3f =20 -#define HUGETLB_FLAG_ENCODE_16KB (14 << HUGETLB_FLAG_ENCODE_SHIFT) -#define HUGETLB_FLAG_ENCODE_64KB (16 << HUGETLB_FLAG_ENCODE_SHIFT) -#define HUGETLB_FLAG_ENCODE_512KB (19 << HUGETLB_FLAG_ENCODE_SHIFT) -#define HUGETLB_FLAG_ENCODE_1MB (20 << HUGETLB_FLAG_ENCODE_SHIFT) -#define HUGETLB_FLAG_ENCODE_2MB (21 << HUGETLB_FLAG_ENCODE_SHIFT) -#define HUGETLB_FLAG_ENCODE_8MB (23 << HUGETLB_FLAG_ENCODE_SHIFT) -#define HUGETLB_FLAG_ENCODE_16MB (24 << HUGETLB_FLAG_ENCODE_SHIFT) -#define HUGETLB_FLAG_ENCODE_32MB (25 << HUGETLB_FLAG_ENCODE_SHIFT) -#define HUGETLB_FLAG_ENCODE_256MB (28 << HUGETLB_FLAG_ENCODE_SHIFT) -#define HUGETLB_FLAG_ENCODE_512MB (29 << HUGETLB_FLAG_ENCODE_SHIFT) -#define HUGETLB_FLAG_ENCODE_1GB (30 << HUGETLB_FLAG_ENCODE_SHIFT) -#define HUGETLB_FLAG_ENCODE_2GB (31 << HUGETLB_FLAG_ENCODE_SHIFT) -#define HUGETLB_FLAG_ENCODE_16GB (34 << HUGETLB_FLAG_ENCODE_SHIFT) +#define HUGETLB_FLAG_ENCODE_16KB (14U << HUGETLB_FLAG_ENCODE_SHIFT) +#define HUGETLB_FLAG_ENCODE_64KB (16U << HUGETLB_FLAG_ENCODE_SHIFT) +#define HUGETLB_FLAG_ENCODE_512KB (19U << HUGETLB_FLAG_ENCODE_SHIFT) +#define HUGETLB_FLAG_ENCODE_1MB (20U << HUGETLB_FLAG_ENCODE_SHIFT) +#define HUGETLB_FLAG_ENCODE_2MB (21U << HUGETLB_FLAG_ENCODE_SHIFT) +#define HUGETLB_FLAG_ENCODE_8MB (23U << HUGETLB_FLAG_ENCODE_SHIFT) +#define HUGETLB_FLAG_ENCODE_16MB (24U << HUGETLB_FLAG_ENCODE_SHIFT) +#define HUGETLB_FLAG_ENCODE_32MB (25U << HUGETLB_FLAG_ENCODE_SHIFT) +#define HUGETLB_FLAG_ENCODE_256MB (28U << HUGETLB_FLAG_ENCODE_SHIFT) +#define HUGETLB_FLAG_ENCODE_512MB (29U << HUGETLB_FLAG_ENCODE_SHIFT) +#define HUGETLB_FLAG_ENCODE_1GB (30U << HUGETLB_FLAG_ENCODE_SHIFT) +#define HUGETLB_FLAG_ENCODE_2GB (31U << HUGETLB_FLAG_ENCODE_SHIFT) +#define HUGETLB_FLAG_ENCODE_16GB (34U << HUGETLB_FLAG_ENCODE_SHIFT) =20 #endif /* _ASM_GENERIC_HUGETLB_ENCODE_H_ */ diff --git a/linux-headers/asm-generic/mman-common.h b/linux-headers/asm-ge= neric/mman-common.h index 6c1aa92a92..6ce1f1ceb4 100644 --- a/linux-headers/asm-generic/mman-common.h +++ b/linux-headers/asm-generic/mman-common.h @@ -77,6 +77,8 @@ =20 #define MADV_DONTNEED_LOCKED 24 /* like DONTNEED, but drop locked pages to= o */ =20 +#define MADV_COLLAPSE 25 /* Synchronous hugepage collapse */ + /* compatibility flags */ #define MAP_FILE 0 =20 diff --git a/linux-headers/asm-mips/mman.h b/linux-headers/asm-mips/mman.h index 1be428663c..c6e1fc77c9 100644 --- a/linux-headers/asm-mips/mman.h +++ b/linux-headers/asm-mips/mman.h @@ -103,6 +103,8 @@ =20 #define MADV_DONTNEED_LOCKED 24 /* like DONTNEED, but drop locked pages to= o */ =20 +#define MADV_COLLAPSE 25 /* Synchronous hugepage collapse */ + /* compatibility flags */ #define MAP_FILE 0 =20 diff --git a/linux-headers/asm-riscv/kvm.h b/linux-headers/asm-riscv/kvm.h index 7351417afd..8985ff234c 100644 --- a/linux-headers/asm-riscv/kvm.h +++ b/linux-headers/asm-riscv/kvm.h @@ -48,6 +48,7 @@ struct kvm_sregs { /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ struct kvm_riscv_config { unsigned long isa; + unsigned long zicbom_block_size; }; =20 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ @@ -98,6 +99,9 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_M, KVM_RISCV_ISA_EXT_SVPBMT, KVM_RISCV_ISA_EXT_SSTC, + KVM_RISCV_ISA_EXT_SVINVAL, + KVM_RISCV_ISA_EXT_ZIHINTPAUSE, + KVM_RISCV_ISA_EXT_ZICBOM, KVM_RISCV_ISA_EXT_MAX, }; =20 diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index ebdafa576d..b2783c5202 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1175,6 +1175,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_VM_DISABLE_NX_HUGE_PAGES 220 #define KVM_CAP_S390_ZPCI_OP 221 #define KVM_CAP_S390_CPU_TOPOLOGY 222 +#define KVM_CAP_DIRTY_LOG_RING_ACQ_REL 223 =20 #ifdef KVM_CAP_IRQ_ROUTING =20 diff --git a/linux-headers/linux/psci.h b/linux-headers/linux/psci.h index 213b2a0f70..e60dfd8907 100644 --- a/linux-headers/linux/psci.h +++ b/linux-headers/linux/psci.h @@ -48,12 +48,26 @@ #define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7) =20 #define PSCI_1_0_FN_PSCI_FEATURES PSCI_0_2_FN(10) +#define PSCI_1_0_FN_CPU_FREEZE PSCI_0_2_FN(11) +#define PSCI_1_0_FN_CPU_DEFAULT_SUSPEND PSCI_0_2_FN(12) +#define PSCI_1_0_FN_NODE_HW_STATE PSCI_0_2_FN(13) #define PSCI_1_0_FN_SYSTEM_SUSPEND PSCI_0_2_FN(14) #define PSCI_1_0_FN_SET_SUSPEND_MODE PSCI_0_2_FN(15) +#define PSCI_1_0_FN_STAT_RESIDENCY PSCI_0_2_FN(16) +#define PSCI_1_0_FN_STAT_COUNT PSCI_0_2_FN(17) + #define PSCI_1_1_FN_SYSTEM_RESET2 PSCI_0_2_FN(18) +#define PSCI_1_1_FN_MEM_PROTECT PSCI_0_2_FN(19) +#define PSCI_1_1_FN_MEM_PROTECT_CHECK_RANGE PSCI_0_2_FN(19) =20 +#define PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND PSCI_0_2_FN64(12) +#define PSCI_1_0_FN64_NODE_HW_STATE PSCI_0_2_FN64(13) #define PSCI_1_0_FN64_SYSTEM_SUSPEND PSCI_0_2_FN64(14) +#define PSCI_1_0_FN64_STAT_RESIDENCY PSCI_0_2_FN64(16) +#define PSCI_1_0_FN64_STAT_COUNT PSCI_0_2_FN64(17) + #define PSCI_1_1_FN64_SYSTEM_RESET2 PSCI_0_2_FN64(18) +#define PSCI_1_1_FN64_MEM_PROTECT_CHECK_RANGE PSCI_0_2_FN64(19) =20 /* PSCI v0.2 power state encoding for CPU_SUSPEND function */ #define PSCI_0_2_POWER_STATE_ID_MASK 0xffff diff --git a/linux-headers/linux/userfaultfd.h b/linux-headers/linux/userfa= ultfd.h index a3a377cd44..ba5d0df52f 100644 --- a/linux-headers/linux/userfaultfd.h +++ b/linux-headers/linux/userfaultfd.h @@ -12,6 +12,10 @@ =20 #include =20 +/* ioctls for /dev/userfaultfd */ +#define USERFAULTFD_IOC 0xAA +#define USERFAULTFD_IOC_NEW _IO(USERFAULTFD_IOC, 0x00) + /* * If the UFFDIO_API is upgraded someday, the UFFDIO_UNREGISTER and * UFFDIO_WAKE ioctls should be defined as _IOW and not as _IOR. In diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h index ede44b5572..bee7e42198 100644 --- a/linux-headers/linux/vfio.h +++ b/linux-headers/linux/vfio.h @@ -986,6 +986,148 @@ enum vfio_device_mig_state { VFIO_DEVICE_STATE_RUNNING_P2P =3D 5, }; =20 +/* + * Upon VFIO_DEVICE_FEATURE_SET, allow the device to be moved into a low p= ower + * state with the platform-based power management. Device use of lower po= wer + * states depends on factors managed by the runtime power management core, + * including system level support and coordinating support among dependent + * devices. Enabling device low power entry does not guarantee lower power + * usage by the device, nor is a mechanism provided through this feature to + * know the current power state of the device. If any device access happe= ns + * (either from the host or through the vfio uAPI) when the device is in t= he + * low power state, then the host will move the device out of the low power + * state as necessary prior to the access. Once the access is completed, = the + * device may re-enter the low power state. For single shot low power sup= port + * with wake-up notification, see + * VFIO_DEVICE_FEATURE_LOW_POWER_ENTRY_WITH_WAKEUP below. Access to mmap'd + * device regions is disabled on LOW_POWER_ENTRY and may only be resumed a= fter + * calling LOW_POWER_EXIT. + */ +#define VFIO_DEVICE_FEATURE_LOW_POWER_ENTRY 3 + +/* + * This device feature has the same behavior as + * VFIO_DEVICE_FEATURE_LOW_POWER_ENTRY with the exception that the user + * provides an eventfd for wake-up notification. When the device moves ou= t of + * the low power state for the wake-up, the host will not allow the device= to + * re-enter a low power state without a subsequent user call to one of the= low + * power entry device feature IOCTLs. Access to mmap'd device regions is + * disabled on LOW_POWER_ENTRY_WITH_WAKEUP and may only be resumed after t= he + * low power exit. The low power exit can happen either through LOW_POWER= _EXIT + * or through any other access (where the wake-up notification has been + * generated). The access to mmap'd device regions will not trigger low p= ower + * exit. + * + * The notification through the provided eventfd will be generated only wh= en + * the device has entered and is resumed from a low power state after + * calling this device feature IOCTL. A device that has not entered low p= ower + * state, as managed through the runtime power management core, will not + * generate a notification through the provided eventfd on access. Callin= g the + * LOW_POWER_EXIT feature is optional in the case where notification has b= een + * signaled on the provided eventfd that a resume from low power has occur= red. + */ +struct vfio_device_low_power_entry_with_wakeup { + __s32 wakeup_eventfd; + __u32 reserved; +}; + +#define VFIO_DEVICE_FEATURE_LOW_POWER_ENTRY_WITH_WAKEUP 4 + +/* + * Upon VFIO_DEVICE_FEATURE_SET, disallow use of device low power states as + * previously enabled via VFIO_DEVICE_FEATURE_LOW_POWER_ENTRY or + * VFIO_DEVICE_FEATURE_LOW_POWER_ENTRY_WITH_WAKEUP device features. + * This device feature IOCTL may itself generate a wakeup eventfd notifica= tion + * in the latter case if the device had previously entered a low power sta= te. + */ +#define VFIO_DEVICE_FEATURE_LOW_POWER_EXIT 5 + +/* + * Upon VFIO_DEVICE_FEATURE_SET start/stop device DMA logging. + * VFIO_DEVICE_FEATURE_PROBE can be used to detect if the device supports + * DMA logging. + * + * DMA logging allows a device to internally record what DMAs the device is + * initiating and report them back to userspace. It is part of the VFIO + * migration infrastructure that allows implementing dirty page tracking + * during the pre copy phase of live migration. Only DMA WRITEs are logged, + * and this API is not connected to VFIO_DEVICE_FEATURE_MIG_DEVICE_STATE. + * + * When DMA logging is started a range of IOVAs to monitor is provided and= the + * device can optimize its logging to cover only the IOVA range given. Each + * DMA that the device initiates inside the range will be logged by the de= vice + * for later retrieval. + * + * page_size is an input that hints what tracking granularity the device + * should try to achieve. If the device cannot do the hinted page size then + * it's the driver choice which page size to pick based on its support. + * On output the device will return the page size it selected. + * + * ranges is a pointer to an array of + * struct vfio_device_feature_dma_logging_range. + * + * The core kernel code guarantees to support by minimum num_ranges that f= it + * into a single kernel page. User space can try higher values but should = give + * up if the above can't be achieved as of some driver limitations. + * + * A single call to start device DMA logging can be issued and a matching = stop + * should follow at the end. Another start is not allowed in the meantime. + */ +struct vfio_device_feature_dma_logging_control { + __aligned_u64 page_size; + __u32 num_ranges; + __u32 __reserved; + __aligned_u64 ranges; +}; + +struct vfio_device_feature_dma_logging_range { + __aligned_u64 iova; + __aligned_u64 length; +}; + +#define VFIO_DEVICE_FEATURE_DMA_LOGGING_START 6 + +/* + * Upon VFIO_DEVICE_FEATURE_SET stop device DMA logging that was started + * by VFIO_DEVICE_FEATURE_DMA_LOGGING_START + */ +#define VFIO_DEVICE_FEATURE_DMA_LOGGING_STOP 7 + +/* + * Upon VFIO_DEVICE_FEATURE_GET read back and clear the device DMA log + * + * Query the device's DMA log for written pages within the given IOVA rang= e. + * During querying the log is cleared for the IOVA range. + * + * bitmap is a pointer to an array of u64s that will hold the output bitmap + * with 1 bit reporting a page_size unit of IOVA. The mapping of IOVA to b= its + * is given by: + * bitmap[(addr - iova)/page_size] & (1ULL << (addr % 64)) + * + * The input page_size can be any power of two value and does not have to + * match the value given to VFIO_DEVICE_FEATURE_DMA_LOGGING_START. The dri= ver + * will format its internal logging to match the reporting page size, poss= ibly + * by replicating bits if the internal page size is lower than requested. + * + * The LOGGING_REPORT will only set bits in the bitmap and never clear or + * perform any initialization of the user provided bitmap. + * + * If any error is returned userspace should assume that the dirty log is + * corrupted. Error recovery is to consider all memory dirty and try to + * restart the dirty tracking, or to abort/restart the whole migration. + * + * If DMA logging is not enabled, an error will be returned. + * + */ +struct vfio_device_feature_dma_logging_report { + __aligned_u64 iova; + __aligned_u64 length; + __aligned_u64 page_size; + __aligned_u64 bitmap; +}; + +#define VFIO_DEVICE_FEATURE_DMA_LOGGING_REPORT 8 + /* -------- API for Type1 VFIO IOMMU -------- */ =20 /** --=20 2.34.1 From nobody Wed May 15 16:11:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1670511369; cv=none; d=zohomail.com; s=zohoarc; b=kC7DvsDzh+eIgwigDGIsqqFY3RuqT1S18CJGc4ZP/LsFpRcWqFNpHnDAyPCs+yaCZllGtLJOnIkIibF4/pb6+FjSUj6+bcU7eefoVGCg4DmdYKh5blQn06/7gcO0IN6KhaHF5IswJDlRu6daIVX77BTlLej8gyEGzPpVFmsXaLo= ARC-Message-Signature: i=1; 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Thu, 08 Dec 2022 06:54:37 -0800 (PST) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Mayuresh Chitale , Alistair Francis , Bin Meng , Andrew Jones , Bin Meng Subject: [PATCH v3 2/3] target/riscv: Extend isa_ext_data for single letter extensions Date: Thu, 8 Dec 2022 20:24:10 +0530 Message-Id: <20221208145411.122799-3-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221208145411.122799-1-mchitale@ventanamicro.com> References: <20221208145411.122799-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2d; envelope-from=mchitale@ventanamicro.com; helo=mail-oo1-xc2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1670511369465100003 Content-Type: text/plain; charset="utf-8" Currently the ISA string for a CPU is generated from two different arrays, one for single letter extensions and another for multi letter extensions. Add all the single letter extensions to the isa_ext_data array and use it for generating the ISA string. Also drop 'P' and 'Q' extensions from the list of single letter extensions as those are not supported yet. Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.c | 41 +++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 042fd541b4..8c8f085a80 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -41,8 +41,6 @@ (QEMU_VERSION_MICRO)) #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID =20 -static const char riscv_single_letter_exts[] =3D "IEMAFDQCPVH"; - struct isa_ext_data { const char *name; bool multi_letter; @@ -71,6 +69,13 @@ struct isa_ext_data { * extensions by an underscore. */ static const struct isa_ext_data isa_edata_arr[] =3D { + ISA_EXT_DATA_ENTRY(i, false, PRIV_VERSION_1_10_0, ext_i), + ISA_EXT_DATA_ENTRY(e, false, PRIV_VERSION_1_10_0, ext_e), + ISA_EXT_DATA_ENTRY(m, false, PRIV_VERSION_1_10_0, ext_m), + ISA_EXT_DATA_ENTRY(a, false, PRIV_VERSION_1_10_0, ext_a), + ISA_EXT_DATA_ENTRY(f, false, PRIV_VERSION_1_10_0, ext_f), + ISA_EXT_DATA_ENTRY(d, false, PRIV_VERSION_1_10_0, ext_d), + ISA_EXT_DATA_ENTRY(c, false, PRIV_VERSION_1_10_0, ext_c), ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), @@ -1196,16 +1201,23 @@ static void riscv_cpu_class_init(ObjectClass *c, vo= id *data) device_class_set_props(dc, riscv_cpu_properties); } =20 -static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_st= r_len) +static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str) { char *old =3D *isa_str; char *new =3D *isa_str; int i; =20 for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_edata_arr[i].multi_letter && - isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { - new =3D g_strconcat(old, "_", isa_edata_arr[i].name, NULL); + if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { + if (isa_edata_arr[i].multi_letter) { + if (cpu->cfg.short_isa_string) { + continue; + } + new =3D g_strconcat(old, "_", isa_edata_arr[i].name, NULL); + } else { + new =3D g_strconcat(old, isa_edata_arr[i].name, NULL); + } + g_free(old); old =3D new; } @@ -1216,19 +1228,12 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, cha= r **isa_str, int max_str_len) =20 char *riscv_isa_string(RISCVCPU *cpu) { - int i; - const size_t maxlen =3D sizeof("rv128") + sizeof(riscv_single_letter_e= xts); + const size_t maxlen =3D sizeof("rv128"); char *isa_str =3D g_new(char, maxlen); - char *p =3D isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BI= TS); - for (i =3D 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { - if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { - *p++ =3D qemu_tolower(riscv_single_letter_exts[i]); - } - } - *p =3D '\0'; - if (!cpu->cfg.short_isa_string) { - riscv_isa_string_ext(cpu, &isa_str, maxlen); - } + + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); + riscv_isa_string_ext(cpu, &isa_str); + return isa_str; } =20 --=20 2.34.1 From nobody Wed May 15 16:11:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1670511412; cv=none; d=zohomail.com; s=zohoarc; b=VhMCV0dMLzM1rb/f3FxfGTvIeqvlGvzvif/BB9a2LEOV3KWl0TputUtfeGC+afc4y1ZAwI3e6eiMUTTvMasP46fH5NotmO1CbTI76juldaMuLdFFBZ+Gd8YZKUOU1BW8DoCWvbZj1k+5nWCV5N5SzmGKqYD4/zT5kndwvGziPjE= ARC-Message-Signature: i=1; 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Thu, 08 Dec 2022 06:54:43 -0800 (PST) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Mayuresh Chitale , Alistair Francis , Bin Meng , Andrew Jones Subject: [PATCH v3 3/3] target/riscv: kvm: Support selecting VCPU extensions Date: Thu, 8 Dec 2022 20:24:11 +0530 Message-Id: <20221208145411.122799-4-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221208145411.122799-1-mchitale@ventanamicro.com> References: <20221208145411.122799-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2e; envelope-from=mchitale@ventanamicro.com; helo=mail-oo1-xc2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1670511413888100003 Content-Type: text/plain; charset="utf-8" Set the state of each ISA extension on the vcpu depending on what is set in the CPU property and what is allowed by KVM for that extension. Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 11 ++++- target/riscv/kvm.c | 88 ++++++++++++++++++++++++++++++++++------ target/riscv/kvm_riscv.h | 2 +- 3 files changed, 87 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8c8f085a80..4b2c1dadf4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1205,10 +1205,19 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, cha= r **isa_str) { char *old =3D *isa_str; char *new =3D *isa_str; - int i; + int i, offset; =20 for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { + offset =3D isa_edata_arr[i].ext_enable_offset; + if (kvm_enabled() && !kvm_riscv_ext_supported(offset)) { +#ifndef CONFIG_USER_ONLY + info_report("disabling %s extension for hart %d as kvm doe= s " + "not support it", isa_edata_arr[i].name, + (int)cpu->env.mhartid); +#endif + continue; + } if (isa_edata_arr[i].multi_letter) { if (cpu->cfg.short_isa_string) { continue; diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 30f21453d6..79029ad328 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -42,6 +42,29 @@ #include "migration/migration.h" #include "sysemu/runstate.h" =20 +struct isa_ext_info { + const char *name; + target_ulong misa_bit; + int ext_enable_offset; +}; + +#define ISA_EXT_DATA_ENTRY(_name, _bit, _prop) \ + {#_name, _bit, offsetof(struct RISCVCPUConfig, _prop)} + +static const struct isa_ext_info isa_info_arr[] =3D { + ISA_EXT_DATA_ENTRY(a, RVA, ext_a), + ISA_EXT_DATA_ENTRY(c, RVC, ext_c), + ISA_EXT_DATA_ENTRY(d, RVD, ext_d), + ISA_EXT_DATA_ENTRY(f, RVF, ext_f), + ISA_EXT_DATA_ENTRY(h, RVH, ext_h), + ISA_EXT_DATA_ENTRY(i, RVI, ext_i), + ISA_EXT_DATA_ENTRY(m, RVM, ext_m), + ISA_EXT_DATA_ENTRY(svpbmt, 0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(sstc, 0, ext_sstc), + ISA_EXT_DATA_ENTRY(svinval, 0, ext_svinval), + ISA_EXT_DATA_ENTRY(zihintpause, 0, ext_zihintpause), +}; + static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, uint64_t idx) { @@ -394,25 +417,66 @@ void kvm_arch_init_irq_routing(KVMState *s) { } =20 +bool kvm_riscv_ext_supported(int offset) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(isa_info_arr); ++i) { + if (isa_info_arr[i].ext_enable_offset =3D=3D offset) { + return true; + } + } + return false; +} + +static void kvm_riscv_set_isa_ext(CPUState *cs, CPURISCVState *env) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + unsigned long isa_ext_out; + bool *ext_state; + uint64_t id; + int i, ret; + + env->misa_ext =3D 0; + for (i =3D 0; i < ARRAY_SIZE(isa_info_arr); i++) { + ext_state =3D (void *)&cpu->cfg + isa_info_arr[i].ext_enable_offse= t; + id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, i); + ret =3D kvm_get_one_reg(cs, id, &isa_ext_out); + if (ret) { + warn_report("Disabling ext %s due to failure %d", + isa_info_arr[i].name, ret); + *ext_state =3D false; + continue; + } + if (isa_ext_out !=3D (*ext_state)) { + isa_ext_out =3D *ext_state; + ret =3D kvm_set_one_reg(cs, id, &isa_ext_out); + if (ret) { + warn_report("Could not %s ext %s due to failure %d", + (isa_ext_out ? "enable" : "disable"), + isa_info_arr[i].name, ret); + *ext_state =3D !isa_ext_out; + } + } + /* + * If the single letter extension is supported by KVM then set + * the corresponding misa bit for the guest vcpu. + */ + if (isa_info_arr[i].misa_bit && (*ext_state)) { + env->misa_ext |=3D isa_info_arr[i].misa_bit; + } + } +} + int kvm_arch_init_vcpu(CPUState *cs) { - int ret =3D 0; - target_ulong isa; RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - uint64_t id; =20 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); =20 - id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, - KVM_REG_RISCV_CONFIG_REG(isa)); - ret =3D kvm_get_one_reg(cs, id, &isa); - if (ret) { - return ret; - } - env->misa_ext =3D isa; - - return ret; + kvm_riscv_set_isa_ext(cs, env); + return 0; } =20 int kvm_arch_msi_data_to_gsi(uint32_t data) diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index ed281bdce0..bdcccc0da4 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -21,5 +21,5 @@ =20 void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); - +bool kvm_riscv_ext_supported(int offset); #endif --=20 2.34.1