From nobody Fri May 17 02:03:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1668621044; cv=none; d=zohomail.com; s=zohoarc; b=nAs3uNTpRIvLhOOMj/xMhsge10uskWYJdH74rvSvV+7iQG+uVGe5jTY80RIXGNnb5k8qG58biadfLTWKdIblUaZrh0im8UO9zdBj18Trr8YrluqZRwD09UbrOuozLK19nfVjJwNXg4DrhD9vufYW2BSOLQ5TV2wtC0fkm99wQRI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1668621044; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gVklva7qaGu+78w2hhVWCTET/uWU06awEtpwvAuMm5o=; b=LTkHXZG0g6JUawbp4yb2FUZZ14LyeW/yQE+/eKDgmV2Jy5fEo2uz8vVZC4gTbYSbeUVq1GAplMRB46ZIUyfkZdjwqtO/mS9d/T76gmX5By50Vx6wQysYU/4pcitr+8//wuJZ82n1/92gIynRv3Bw//tJ+4bhwmbA0+2kfe7P5hc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1668621044830482.96066728107553; Wed, 16 Nov 2022 09:50:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ovMWK-0006M0-JX; Wed, 16 Nov 2022 12:48:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ovMWI-0006Ki-HU; Wed, 16 Nov 2022 12:48:18 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ovMWF-00013k-JJ; Wed, 16 Nov 2022 12:48:18 -0500 Received: by mail-wr1-x434.google.com with SMTP id v1so31102269wrt.11; Wed, 16 Nov 2022 09:48:14 -0800 (PST) Received: from localhost.localdomain (229.19.205.77.rev.sfr.net. [77.205.19.229]) by smtp.gmail.com with ESMTPSA id n17-20020a05600c465100b003cf483ee8e0sm2477490wmo.24.2022.11.16.09.48.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 16 Nov 2022 09:48:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gVklva7qaGu+78w2hhVWCTET/uWU06awEtpwvAuMm5o=; b=XpyCQK6NWV4Ute0bcxG3tIq9MjC7kfRWIL2/1YQdAEFLRnLOCjGxxbOtWUrCmBU6o+ /eeKtG2gTIpDL03kXsdBPInjz7nuNCTuxqmAkx5CFC2dQgDoMRrFXx2WRTAc5i0UDXRH 9jj5UQk97HoixjYOJ2MfeaUCjfS7EjRmmbVLL02WL47WXwq8vnuxmypXwglPP+zItMNj +dnNhpOGRDNWgQFS+gp9IMclWmB/5Wifozz/iP+3n8xk8feM2IQ6UtTsTGVNPe2bngKi wdOc0KBXwRG/jJR46m2CWIftwhkE5jjTGzlhQ2ew6HV4IuHfb+VDhBQklu3hcl2AGzsx qdPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gVklva7qaGu+78w2hhVWCTET/uWU06awEtpwvAuMm5o=; b=JQNewXbuxKqJoRl668Bk69gEjvDzEqjL3KH18gbidytb9M28HxEWIXly7GekiF3bZ5 jZiPZj7IRxVwMWwKRskXjdk9W56jB2cjM5K5D+tKS8TEqD+zfg9oEU3r/CAwB5+pwXWS jKYsENN35KvD9oQhdwCXgMWhfuwhzYOrJaBZMFV6Ykyw82BVUolNe1/goJ0ltSOawu/V nghGZH0u8slOjX1y9+5epSCINULNQQwD6tqO0XFxcI+FcKuIxbJ3pynkCUUERcdCnY34 c04mFlSk6mIOITv/aYyKufPUGjPePYyWg5PqsQQ0CZVSfKIi+3mDrd/Hqgb8dNuXekLF m7/A== X-Gm-Message-State: ANoB5pmp6rhv7BKuN3fW8JwP48+F1jh6C4U/aQFmvv8lH492gWsO5/ZU mgYqlRwGhMa73tiRXd+R2+0Azg54tulIqw== X-Google-Smtp-Source: AA0mqf56Tj5vzausWsT9CwWO7j8WdTUUFE18KzjMiqnwGyN+/bOQA391xylCYq+oDcEYzgbTbkZVQw== X-Received: by 2002:a5d:4744:0:b0:236:8ead:4871 with SMTP id o4-20020a5d4744000000b002368ead4871mr14654528wrs.498.1668620893549; Wed, 16 Nov 2022 09:48:13 -0800 (PST) From: francesco.cagnin@gmail.com X-Google-Original-From: fcagnin@quarkslab.com To: qemu-devel@nongnu.org Cc: mads@ynddal.dk, dirty@apple.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, agraf@csgraf.de, pbonzini@redhat.com, alex.bennee@linaro.org, Francesco Cagnin Subject: [PATCH v2 1/3] arm: move KVM breakpoints helpers Date: Wed, 16 Nov 2022 18:47:47 +0100 Message-Id: <20221116174749.65175-2-fcagnin@quarkslab.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116174749.65175-1-fcagnin@quarkslab.com> References: <20221116174749.65175-1-fcagnin@quarkslab.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=francesco.cagnin@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1668621065558100001 Content-Type: text/plain; charset="utf-8" From: Francesco Cagnin These helpers will be also used for HVF. Aside from reformatting a couple of comments for 'checkpatch.pl' and updating meson to compile 'hyp_gdbstub.c', this is just code motion. Signed-off-by: Francesco Cagnin Acked-by: Alex Benn=C3=A9e --- target/arm/hyp_gdbstub.c | 242 ++++++++++++++++++++++++++++++++++ target/arm/internals.h | 50 +++++++ target/arm/kvm64.c | 276 --------------------------------------- target/arm/meson.build | 3 +- 4 files changed, 294 insertions(+), 277 deletions(-) create mode 100644 target/arm/hyp_gdbstub.c diff --git a/target/arm/hyp_gdbstub.c b/target/arm/hyp_gdbstub.c new file mode 100644 index 0000000000..22b2b7de7b --- /dev/null +++ b/target/arm/hyp_gdbstub.c @@ -0,0 +1,242 @@ +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/gdbstub.h" + +/* Maximum and current break/watch point counts */ +int max_hw_bps, max_hw_wps; +GArray *hw_breakpoints, *hw_watchpoints; + +/** + * insert_hw_breakpoint() + * @addr: address of breakpoint + * + * See ARM ARM D2.9.1 for details but here we are only going to create + * simple un-linked breakpoints (i.e. we don't chain breakpoints + * together to match address and context or vmid). The hardware is + * capable of fancier matching but that will require exposing that + * fanciness to GDB's interface + * + * DBGBCR_EL1, Debug Breakpoint Control Registers + * + * 31 24 23 20 19 16 15 14 13 12 9 8 5 4 3 2 1 0 + * +------+------+-------+-----+----+------+-----+------+-----+---+ + * | RES0 | BT | LBN | SSC | HMC| RES0 | BAS | RES0 | PMC | E | + * +------+------+-------+-----+----+------+-----+------+-----+---+ + * + * BT: Breakpoint type (0 =3D unlinked address match) + * LBN: Linked BP number (0 =3D unused) + * SSC/HMC/PMC: Security, Higher and Priv access control (Table D-12) + * BAS: Byte Address Select (RES1 for AArch64) + * E: Enable bit + * + * DBGBVR_EL1, Debug Breakpoint Value Registers + * + * 63 53 52 49 48 2 1 0 + * +------+-----------+----------+-----+ + * | RESS | VA[52:49] | VA[48:2] | 0 0 | + * +------+-----------+----------+-----+ + * + * Depending on the addressing mode bits the top bits of the register + * are a sign extension of the highest applicable VA bit. Some + * versions of GDB don't do it correctly so we ensure they are correct + * here so future PC comparisons will work properly. + */ + +int insert_hw_breakpoint(target_ulong addr) +{ + HWBreakpoint brk =3D { + .bcr =3D 0x1, /* BCR E=3D1, enable */ + .bvr =3D sextract64(addr, 0, 53) + }; + + if (cur_hw_bps >=3D max_hw_bps) { + return -ENOBUFS; + } + + brk.bcr =3D deposit32(brk.bcr, 1, 2, 0x3); /* PMC =3D 11 */ + brk.bcr =3D deposit32(brk.bcr, 5, 4, 0xf); /* BAS =3D RES1 */ + + g_array_append_val(hw_breakpoints, brk); + + return 0; +} + +/** + * delete_hw_breakpoint() + * @pc: address of breakpoint + * + * Delete a breakpoint and shuffle any above down + */ + +int delete_hw_breakpoint(target_ulong pc) +{ + int i; + for (i =3D 0; i < hw_breakpoints->len; i++) { + HWBreakpoint *brk =3D get_hw_bp(i); + if (brk->bvr =3D=3D pc) { + g_array_remove_index(hw_breakpoints, i); + return 0; + } + } + return -ENOENT; +} + +/** + * insert_hw_watchpoint() + * @addr: address of watch point + * @len: size of area + * @type: type of watch point + * + * See ARM ARM D2.10. As with the breakpoints we can do some advanced + * stuff if we want to. The watch points can be linked with the break + * points above to make them context aware. However for simplicity + * currently we only deal with simple read/write watch points. + * + * D7.3.11 DBGWCR_EL1, Debug Watchpoint Control Registers + * + * 31 29 28 24 23 21 20 19 16 15 14 13 12 5 4 3 2 1 0 + * +------+-------+------+----+-----+-----+-----+-----+-----+-----+---+ + * | RES0 | MASK | RES0 | WT | LBN | SSC | HMC | BAS | LSC | PAC | E | + * +------+-------+------+----+-----+-----+-----+-----+-----+-----+---+ + * + * MASK: num bits addr mask (0=3Dnone,01/10=3Dres,11=3D3 bits (8 bytes)) + * WT: 0 - unlinked, 1 - linked (not currently used) + * LBN: Linked BP number (not currently used) + * SSC/HMC/PAC: Security, Higher and Priv access control (Table D2-11) + * BAS: Byte Address Select + * LSC: Load/Store control (01: load, 10: store, 11: both) + * E: Enable + * + * The bottom 2 bits of the value register are masked. Therefore to + * break on any sizes smaller than an unaligned word you need to set + * MASK=3D0, BAS=3Dbit per byte in question. For larger regions (^2) you + * need to ensure you mask the address as required and set BAS=3D0xff + */ + +int insert_hw_watchpoint(target_ulong addr, target_ulong len, int type) +{ + HWWatchpoint wp =3D { + .wcr =3D R_DBGWCR_E_MASK, /* E=3D1, enable */ + .wvr =3D addr & (~0x7ULL), + .details =3D { .vaddr =3D addr, .len =3D len } + }; + + if (cur_hw_wps >=3D max_hw_wps) { + return -ENOBUFS; + } + + /* + * HMC=3D0 SSC=3D0 PAC=3D3 will hit EL0 or EL1, any security state, + * valid whether EL3 is implemented or not + */ + wp.wcr =3D FIELD_DP64(wp.wcr, DBGWCR, PAC, 3); + + switch (type) { + case GDB_WATCHPOINT_READ: + wp.wcr =3D FIELD_DP64(wp.wcr, DBGWCR, LSC, 1); + wp.details.flags =3D BP_MEM_READ; + break; + case GDB_WATCHPOINT_WRITE: + wp.wcr =3D FIELD_DP64(wp.wcr, DBGWCR, LSC, 2); + wp.details.flags =3D BP_MEM_WRITE; + break; + case GDB_WATCHPOINT_ACCESS: + wp.wcr =3D FIELD_DP64(wp.wcr, DBGWCR, LSC, 3); + wp.details.flags =3D BP_MEM_ACCESS; + break; + default: + g_assert_not_reached(); + break; + } + if (len <=3D 8) { + /* we align the address and set the bits in BAS */ + int off =3D addr & 0x7; + int bas =3D (1 << len) - 1; + + wp.wcr =3D deposit32(wp.wcr, 5 + off, 8 - off, bas); + } else { + /* For ranges above 8 bytes we need to be a power of 2 */ + if (is_power_of_2(len)) { + int bits =3D ctz64(len); + + wp.wvr &=3D ~((1 << bits) - 1); + wp.wcr =3D FIELD_DP64(wp.wcr, DBGWCR, MASK, bits); + wp.wcr =3D FIELD_DP64(wp.wcr, DBGWCR, BAS, 0xff); + } else { + return -ENOBUFS; + } + } + + g_array_append_val(hw_watchpoints, wp); + return 0; +} + +bool check_watchpoint_in_range(int i, target_ulong addr) +{ + HWWatchpoint *wp =3D get_hw_wp(i); + uint64_t addr_top, addr_bottom =3D wp->wvr; + int bas =3D extract32(wp->wcr, 5, 8); + int mask =3D extract32(wp->wcr, 24, 4); + + if (mask) { + addr_top =3D addr_bottom + (1 << mask); + } else { + /* + * BAS must be contiguous but can offset against the base + * address in DBGWVR + */ + addr_bottom =3D addr_bottom + ctz32(bas); + addr_top =3D addr_bottom + clo32(bas); + } + + if (addr >=3D addr_bottom && addr <=3D addr_top) { + return true; + } + + return false; +} + +/** + * delete_hw_watchpoint() + * @addr: address of breakpoint + * + * Delete a breakpoint and shuffle any above down + */ + +int delete_hw_watchpoint(target_ulong addr, target_ulong len, int type) +{ + int i; + for (i =3D 0; i < cur_hw_wps; i++) { + if (check_watchpoint_in_range(i, addr)) { + g_array_remove_index(hw_watchpoints, i); + return 0; + } + } + return -ENOENT; +} + +bool find_hw_breakpoint(CPUState *cpu, target_ulong pc) +{ + int i; + + for (i =3D 0; i < cur_hw_bps; i++) { + HWBreakpoint *bp =3D get_hw_bp(i); + if (bp->bvr =3D=3D pc) { + return true; + } + } + return false; +} + +CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr) +{ + int i; + + for (i =3D 0; i < cur_hw_wps; i++) { + if (check_watchpoint_in_range(i, addr)) { + return &get_hw_wp(i)->details; + } + } + return NULL; +} diff --git a/target/arm/internals.h b/target/arm/internals.h index d9121d9ff8..54382e7d76 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1369,4 +1369,54 @@ static inline uint64_t arm_mdcr_el2_eff(CPUARMState = *env) ((1 << (1 - 1)) | (1 << (2 - 1)) | \ (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1))) =20 +/* + * Although the ARM implementation of hardware assisted debugging + * allows for different breakpoints per-core, the current GDB + * interface treats them as a global pool of registers (which seems to + * be the case for x86, ppc and s390). As a result we store one copy + * of registers which is used for all active cores. + * + * Write access is serialised by virtue of the GDB protocol which + * updates things. Read access (i.e. when the values are copied to the + * vCPU) is also gated by GDB's run control. + * + * This is not unreasonable as most of the time debugging kernels you + * never know which core will eventually execute your function. + */ + +typedef struct { + uint64_t bcr; + uint64_t bvr; +} HWBreakpoint; + +/* + * The watchpoint registers can cover more area than the requested + * watchpoint so we need to store the additional information + * somewhere. We also need to supply a CPUWatchpoint to the GDB stub + * when the watchpoint is hit. + */ +typedef struct { + uint64_t wcr; + uint64_t wvr; + CPUWatchpoint details; +} HWWatchpoint; + +/* Maximum and current break/watch point counts */ +extern int max_hw_bps, max_hw_wps; +extern GArray *hw_breakpoints, *hw_watchpoints; + +#define cur_hw_wps (hw_watchpoints->len) +#define cur_hw_bps (hw_breakpoints->len) +#define get_hw_bp(i) (&g_array_index(hw_breakpoints, HWBreakpoint, i)) +#define get_hw_wp(i) (&g_array_index(hw_watchpoints, HWWatchpoint, i)) + +bool find_hw_breakpoint(CPUState *cpu, target_ulong pc); +int insert_hw_breakpoint(target_ulong pc); +int delete_hw_breakpoint(target_ulong pc); + +bool check_watchpoint_in_range(int i, target_ulong addr); +CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr); +int insert_hw_watchpoint(target_ulong addr, target_ulong len, int type); +int delete_hw_watchpoint(target_ulong addr, target_ulong len, int type); + #endif diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 1197253d12..fb7bb65947 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -34,46 +34,6 @@ =20 static bool have_guest_debug; =20 -/* - * Although the ARM implementation of hardware assisted debugging - * allows for different breakpoints per-core, the current GDB - * interface treats them as a global pool of registers (which seems to - * be the case for x86, ppc and s390). As a result we store one copy - * of registers which is used for all active cores. - * - * Write access is serialised by virtue of the GDB protocol which - * updates things. Read access (i.e. when the values are copied to the - * vCPU) is also gated by GDB's run control. - * - * This is not unreasonable as most of the time debugging kernels you - * never know which core will eventually execute your function. - */ - -typedef struct { - uint64_t bcr; - uint64_t bvr; -} HWBreakpoint; - -/* The watchpoint registers can cover more area than the requested - * watchpoint so we need to store the additional information - * somewhere. We also need to supply a CPUWatchpoint to the GDB stub - * when the watchpoint is hit. - */ -typedef struct { - uint64_t wcr; - uint64_t wvr; - CPUWatchpoint details; -} HWWatchpoint; - -/* Maximum and current break/watch point counts */ -int max_hw_bps, max_hw_wps; -GArray *hw_breakpoints, *hw_watchpoints; - -#define cur_hw_wps (hw_watchpoints->len) -#define cur_hw_bps (hw_breakpoints->len) -#define get_hw_bp(i) (&g_array_index(hw_breakpoints, HWBreakpoint, i)) -#define get_hw_wp(i) (&g_array_index(hw_watchpoints, HWWatchpoint, i)) - /** * kvm_arm_init_debug() - check for guest debug capabilities * @cs: CPUState @@ -97,217 +57,6 @@ static void kvm_arm_init_debug(CPUState *cs) return; } =20 -/** - * insert_hw_breakpoint() - * @addr: address of breakpoint - * - * See ARM ARM D2.9.1 for details but here we are only going to create - * simple un-linked breakpoints (i.e. we don't chain breakpoints - * together to match address and context or vmid). The hardware is - * capable of fancier matching but that will require exposing that - * fanciness to GDB's interface - * - * DBGBCR_EL1, Debug Breakpoint Control Registers - * - * 31 24 23 20 19 16 15 14 13 12 9 8 5 4 3 2 1 0 - * +------+------+-------+-----+----+------+-----+------+-----+---+ - * | RES0 | BT | LBN | SSC | HMC| RES0 | BAS | RES0 | PMC | E | - * +------+------+-------+-----+----+------+-----+------+-----+---+ - * - * BT: Breakpoint type (0 =3D unlinked address match) - * LBN: Linked BP number (0 =3D unused) - * SSC/HMC/PMC: Security, Higher and Priv access control (Table D-12) - * BAS: Byte Address Select (RES1 for AArch64) - * E: Enable bit - * - * DBGBVR_EL1, Debug Breakpoint Value Registers - * - * 63 53 52 49 48 2 1 0 - * +------+-----------+----------+-----+ - * | RESS | VA[52:49] | VA[48:2] | 0 0 | - * +------+-----------+----------+-----+ - * - * Depending on the addressing mode bits the top bits of the register - * are a sign extension of the highest applicable VA bit. Some - * versions of GDB don't do it correctly so we ensure they are correct - * here so future PC comparisons will work properly. - */ - -static int insert_hw_breakpoint(target_ulong addr) -{ - HWBreakpoint brk =3D { - .bcr =3D 0x1, /* BCR E=3D1, enable */ - .bvr =3D sextract64(addr, 0, 53) - }; - - if (cur_hw_bps >=3D max_hw_bps) { - return -ENOBUFS; - } - - brk.bcr =3D deposit32(brk.bcr, 1, 2, 0x3); /* PMC =3D 11 */ - brk.bcr =3D deposit32(brk.bcr, 5, 4, 0xf); /* BAS =3D RES1 */ - - g_array_append_val(hw_breakpoints, brk); - - return 0; -} - -/** - * delete_hw_breakpoint() - * @pc: address of breakpoint - * - * Delete a breakpoint and shuffle any above down - */ - -static int delete_hw_breakpoint(target_ulong pc) -{ - int i; - for (i =3D 0; i < hw_breakpoints->len; i++) { - HWBreakpoint *brk =3D get_hw_bp(i); - if (brk->bvr =3D=3D pc) { - g_array_remove_index(hw_breakpoints, i); - return 0; - } - } - return -ENOENT; -} - -/** - * insert_hw_watchpoint() - * @addr: address of watch point - * @len: size of area - * @type: type of watch point - * - * See ARM ARM D2.10. As with the breakpoints we can do some advanced - * stuff if we want to. The watch points can be linked with the break - * points above to make them context aware. However for simplicity - * currently we only deal with simple read/write watch points. - * - * D7.3.11 DBGWCR_EL1, Debug Watchpoint Control Registers - * - * 31 29 28 24 23 21 20 19 16 15 14 13 12 5 4 3 2 1 0 - * +------+-------+------+----+-----+-----+-----+-----+-----+-----+---+ - * | RES0 | MASK | RES0 | WT | LBN | SSC | HMC | BAS | LSC | PAC | E | - * +------+-------+------+----+-----+-----+-----+-----+-----+-----+---+ - * - * MASK: num bits addr mask (0=3Dnone,01/10=3Dres,11=3D3 bits (8 bytes)) - * WT: 0 - unlinked, 1 - linked (not currently used) - * LBN: Linked BP number (not currently used) - * SSC/HMC/PAC: Security, Higher and Priv access control (Table D2-11) - * BAS: Byte Address Select - * LSC: Load/Store control (01: load, 10: store, 11: both) - * E: Enable - * - * The bottom 2 bits of the value register are masked. Therefore to - * break on any sizes smaller than an unaligned word you need to set - * MASK=3D0, BAS=3Dbit per byte in question. For larger regions (^2) you - * need to ensure you mask the address as required and set BAS=3D0xff - */ - -static int insert_hw_watchpoint(target_ulong addr, - target_ulong len, int type) -{ - HWWatchpoint wp =3D { - .wcr =3D R_DBGWCR_E_MASK, /* E=3D1, enable */ - .wvr =3D addr & (~0x7ULL), - .details =3D { .vaddr =3D addr, .len =3D len } - }; - - if (cur_hw_wps >=3D max_hw_wps) { - return -ENOBUFS; - } - - /* - * HMC=3D0 SSC=3D0 PAC=3D3 will hit EL0 or EL1, any security state, - * valid whether EL3 is implemented or not - */ - wp.wcr =3D FIELD_DP64(wp.wcr, DBGWCR, PAC, 3); - - switch (type) { - case GDB_WATCHPOINT_READ: - wp.wcr =3D FIELD_DP64(wp.wcr, DBGWCR, LSC, 1); - wp.details.flags =3D BP_MEM_READ; - break; - case GDB_WATCHPOINT_WRITE: - wp.wcr =3D FIELD_DP64(wp.wcr, DBGWCR, LSC, 2); - wp.details.flags =3D BP_MEM_WRITE; - break; - case GDB_WATCHPOINT_ACCESS: - wp.wcr =3D FIELD_DP64(wp.wcr, DBGWCR, LSC, 3); - wp.details.flags =3D BP_MEM_ACCESS; - break; - default: - g_assert_not_reached(); - break; - } - if (len <=3D 8) { - /* we align the address and set the bits in BAS */ - int off =3D addr & 0x7; - int bas =3D (1 << len) - 1; - - wp.wcr =3D deposit32(wp.wcr, 5 + off, 8 - off, bas); - } else { - /* For ranges above 8 bytes we need to be a power of 2 */ - if (is_power_of_2(len)) { - int bits =3D ctz64(len); - - wp.wvr &=3D ~((1 << bits) - 1); - wp.wcr =3D FIELD_DP64(wp.wcr, DBGWCR, MASK, bits); - wp.wcr =3D FIELD_DP64(wp.wcr, DBGWCR, BAS, 0xff); - } else { - return -ENOBUFS; - } - } - - g_array_append_val(hw_watchpoints, wp); - return 0; -} - - -static bool check_watchpoint_in_range(int i, target_ulong addr) -{ - HWWatchpoint *wp =3D get_hw_wp(i); - uint64_t addr_top, addr_bottom =3D wp->wvr; - int bas =3D extract32(wp->wcr, 5, 8); - int mask =3D extract32(wp->wcr, 24, 4); - - if (mask) { - addr_top =3D addr_bottom + (1 << mask); - } else { - /* BAS must be contiguous but can offset against the base - * address in DBGWVR */ - addr_bottom =3D addr_bottom + ctz32(bas); - addr_top =3D addr_bottom + clo32(bas); - } - - if (addr >=3D addr_bottom && addr <=3D addr_top) { - return true; - } - - return false; -} - -/** - * delete_hw_watchpoint() - * @addr: address of breakpoint - * - * Delete a breakpoint and shuffle any above down - */ - -static int delete_hw_watchpoint(target_ulong addr, - target_ulong len, int type) -{ - int i; - for (i =3D 0; i < cur_hw_wps; i++) { - if (check_watchpoint_in_range(i, addr)) { - g_array_remove_index(hw_watchpoints, i); - return 0; - } - } - return -ENOENT; -} - - int kvm_arch_insert_hw_breakpoint(target_ulong addr, target_ulong len, int type) { @@ -372,31 +121,6 @@ bool kvm_arm_hw_debug_active(CPUState *cs) return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); } =20 -static bool find_hw_breakpoint(CPUState *cpu, target_ulong pc) -{ - int i; - - for (i =3D 0; i < cur_hw_bps; i++) { - HWBreakpoint *bp =3D get_hw_bp(i); - if (bp->bvr =3D=3D pc) { - return true; - } - } - return false; -} - -static CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr) -{ - int i; - - for (i =3D 0; i < cur_hw_wps; i++) { - if (check_watchpoint_in_range(i, addr)) { - return &get_hw_wp(i)->details; - } - } - return NULL; -} - static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *= attr, const char *name) { diff --git a/target/arm/meson.build b/target/arm/meson.build index 87e911b27f..63f5d30dd8 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -40,7 +40,8 @@ arm_ss.add(files( )) arm_ss.add(zlib) =20 -arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_fals= e: files('kvm-stub.c')) +arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c', 'k= vm64.c'), if_false: files('kvm-stub.c')) +arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'cpu64.c', --=20 2.38.1 From nobody Fri May 17 02:03:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1668620956; cv=none; d=zohomail.com; s=zohoarc; b=I9g59Ztt1HsX/xd2sEyGbP4rrak7UP4H4vJyRa4fBslNjauwWeVY4Qe/TsMPhQjQ3+GOpCMPHHm67WwJgoqfggmeip6fa5B0etShxVX6IJUNWVSJe+q3/cWZ/Q+eZB5KwSPetNr1BpP3GeU1PGf1bXhAGYZhpkPkC3HJRzr7jMk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1668620956; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=p7NsJDp/JrHpKGCJphejeFdwXcPwioqdjw87NrGNIJo=; b=AfGfdfUYjdKsoyVwQWbGxvrXZDpLuUG84l8o1MxPgvNeH9SlIbxN7SUj+zp8+8rfj5uLDyPL9TTY9c1w8XxsYuAohA5b+zzasDGNI7HScE7h+6n/+EUNmUqLHvLaRcVpXfVcqxDZPDyWSMDrMrzz2FkZ2dUKJ4DBTqgN9HnO09c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1668620956345799.9547167102164; Wed, 16 Nov 2022 09:49:16 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ovMWP-0006RW-KU; Wed, 16 Nov 2022 12:48:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ovMWM-0006Or-Ok; Wed, 16 Nov 2022 12:48:22 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ovMWK-00013r-38; Wed, 16 Nov 2022 12:48:22 -0500 Received: by mail-wm1-x330.google.com with SMTP id r127-20020a1c4485000000b003cfdd569507so1177775wma.4; Wed, 16 Nov 2022 09:48:17 -0800 (PST) Received: from localhost.localdomain (229.19.205.77.rev.sfr.net. [77.205.19.229]) by smtp.gmail.com with ESMTPSA id n17-20020a05600c465100b003cf483ee8e0sm2477490wmo.24.2022.11.16.09.48.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 16 Nov 2022 09:48:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p7NsJDp/JrHpKGCJphejeFdwXcPwioqdjw87NrGNIJo=; b=bVmwjrQ9Fz2BqooY06UHyWtg1lrJYH/0SylTtV7JFWI+ZwiBYjMAqs0lGfxm8EPcf0 v4MaY4Er2yjWywmAtCwGafv/Sk0Bv0Gryb5uwpEgQpmc9K9d7ehj+g2gP2pSgmo54RkZ ghGucd3+AC3yGSEQ0ko2gQpY/uUOTncyA05lzrtgnsZllRiOZD9SCftMKmjrjIDFeZoZ Bni1okk4fYqrwLYzGRITib/ZeRL38yBzrCFPKDE18lOF1dYZhHr6wuA6vkSt0PALgSnH e7U5p074jThhzjJWen3hOO6WTCTO1zKhImljUGtMAYhOskgQXMSJCnRA0b/TcAmr0rq/ T1UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p7NsJDp/JrHpKGCJphejeFdwXcPwioqdjw87NrGNIJo=; b=8QfmiIgiOBprfs8dchKfLHziru9siJ297vvyTyPlwfIWuNIJ8npBzfG0rFC0HJK1x+ 0wkWFMX6uKdkEe7R1sB6uBqOJqceS5PHGpvr2Jemml4wjJhjdWi4aCgfHa+J4eYvW0jM cYEqdZW/vOyBoUSOJLFxJRVaSS5e07PKVXuH+6U1s6fB4PSKKmkl9eUD3A9B07TDY+wI hoaUN8bdPpcv7ByE8CUTOdcpC/QmLkU0B1a0lSFUqUAUbudReVElsw6YDiCBgONOZIEs b5aiuZmyaDdTYgYEiWb7BQuNUK3qGAcuw62LDXLcdR66x3dNG/tX6JC3axVqsVb5zJe+ 9uWA== X-Gm-Message-State: ANoB5plgU1b1K7VyZV6oSQOUQs2NDCHU7gmVHs7z7XBmdjUe3TF9Zz9b mwglL2DI098dPXrk8ZRtwcrIXO8+iOSndQ== X-Google-Smtp-Source: AA0mqf6/h5kvMzP1dKaDDEbetoxIc5HUf16g0wNBx55zyAJpG50A8jEmawUkkL5io6gIOVbP8G5Sqw== X-Received: by 2002:a05:600c:5408:b0:3cf:85e7:7b40 with SMTP id he8-20020a05600c540800b003cf85e77b40mr195508wmb.63.1668620896608; Wed, 16 Nov 2022 09:48:16 -0800 (PST) From: francesco.cagnin@gmail.com X-Google-Original-From: fcagnin@quarkslab.com To: qemu-devel@nongnu.org Cc: mads@ynddal.dk, dirty@apple.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, agraf@csgraf.de, pbonzini@redhat.com, alex.bennee@linaro.org, Francesco Cagnin Subject: [PATCH v2 2/3] hvf: implement guest debugging on Apple Silicon hosts Date: Wed, 16 Nov 2022 18:47:48 +0100 Message-Id: <20221116174749.65175-3-fcagnin@quarkslab.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116174749.65175-1-fcagnin@quarkslab.com> References: <20221116174749.65175-1-fcagnin@quarkslab.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=francesco.cagnin@gmail.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1668621017101100001 Content-Type: text/plain; charset="utf-8" From: Francesco Cagnin Support is added for single-stepping, software breakpoints, hardware breakpoints and watchpoints. The code has been structured like the KVM counterpart (and many parts are basically identical). Guests can be debugged through the gdbstub. Signed-off-by: Francesco Cagnin Reviewed-by: Mads Ynddal --- accel/hvf/hvf-accel-ops.c | 123 ++++++++++++++++++++++++ accel/hvf/hvf-all.c | 24 +++++ cpu.c | 3 + include/sysemu/hvf.h | 29 ++++++ include/sysemu/hvf_int.h | 1 + target/arm/hvf/hvf.c | 194 +++++++++++++++++++++++++++++++++++++- 6 files changed, 372 insertions(+), 2 deletions(-) diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index 24913ca9c4..1ce0f94a64 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -52,6 +52,7 @@ #include "qemu/main-loop.h" #include "exec/address-spaces.h" #include "exec/exec-all.h" +#include "exec/gdbstub.h" #include "sysemu/cpus.h" #include "sysemu/hvf.h" #include "sysemu/hvf_int.h" @@ -340,12 +341,18 @@ static int hvf_accel_init(MachineState *ms) return hvf_arch_init(); } =20 +static int hvf_gdbstub_sstep_flags(void) +{ + return SSTEP_ENABLE | SSTEP_NOIRQ; +} + static void hvf_accel_class_init(ObjectClass *oc, void *data) { AccelClass *ac =3D ACCEL_CLASS(oc); ac->name =3D "HVF"; ac->init_machine =3D hvf_accel_init; ac->allowed =3D &hvf_allowed; + ac->gdbstub_supported_sstep_flags =3D hvf_gdbstub_sstep_flags; } =20 static const TypeInfo hvf_accel_type =3D { @@ -462,6 +469,117 @@ static void hvf_start_vcpu_thread(CPUState *cpu) cpu, QEMU_THREAD_JOINABLE); } =20 +static bool hvf_supports_guest_debug(void) +{ +#ifdef TARGET_AARCH64 + return true; +#else + return false; +#endif +} + +static int hvf_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwa= ddr len) +{ + struct hvf_sw_breakpoint *bp; + int err; + + if (type =3D=3D GDB_BREAKPOINT_SW) { + bp =3D hvf_find_sw_breakpoint(cpu, addr); + if (bp) { + bp->use_count++; + return 0; + } + + bp =3D g_new(struct hvf_sw_breakpoint, 1); + bp->pc =3D addr; + bp->use_count =3D 1; + err =3D hvf_arch_insert_sw_breakpoint(cpu, bp); + if (err) { + g_free(bp); + return err; + } + + QTAILQ_INSERT_HEAD(&cpu->hvf->hvf_sw_breakpoints, bp, entry); + } else { + err =3D hvf_arch_insert_hw_breakpoint(addr, len, type); + if (err) { + return err; + } + } + + CPU_FOREACH(cpu) { + err =3D hvf_update_guest_debug(cpu); + if (err) { + return err; + } + } + return 0; +} + +static int hvf_remove_breakpoint(CPUState *cpu, int type, hwaddr addr, hwa= ddr len) +{ + struct hvf_sw_breakpoint *bp; + int err; + + if (type =3D=3D GDB_BREAKPOINT_SW) { + bp =3D hvf_find_sw_breakpoint(cpu, addr); + if (!bp) { + return -ENOENT; + } + + if (bp->use_count > 1) { + bp->use_count--; + return 0; + } + + err =3D hvf_arch_remove_sw_breakpoint(cpu, bp); + if (err) { + return err; + } + + QTAILQ_REMOVE(&cpu->hvf->hvf_sw_breakpoints, bp, entry); + g_free(bp); + } else { + err =3D hvf_arch_remove_hw_breakpoint(addr, len, type); + if (err) { + return err; + } + } + + CPU_FOREACH(cpu) { + err =3D hvf_update_guest_debug(cpu); + if (err) { + return err; + } + } + return 0; +} + +static void hvf_remove_all_breakpoints(CPUState *cpu) +{ + struct hvf_sw_breakpoint *bp, *next; + CPUState *tmpcpu; + + QTAILQ_FOREACH_SAFE(bp, &cpu->hvf->hvf_sw_breakpoints, entry, next) { + if (hvf_arch_remove_sw_breakpoint(cpu, bp) !=3D 0) { + /* Try harder to find a CPU that currently sees the breakpoint= . */ + CPU_FOREACH(tmpcpu) + { + if (hvf_arch_remove_sw_breakpoint(tmpcpu, bp) =3D=3D 0) { + break; + } + } + } + QTAILQ_REMOVE(&cpu->hvf->hvf_sw_breakpoints, bp, entry); + g_free(bp); + } + hvf_arch_remove_all_hw_breakpoints(); + + CPU_FOREACH(cpu) { + hvf_update_guest_debug(cpu); + } +} + static void hvf_accel_ops_class_init(ObjectClass *oc, void *data) { AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); @@ -473,6 +591,11 @@ static void hvf_accel_ops_class_init(ObjectClass *oc, = void *data) ops->synchronize_post_init =3D hvf_cpu_synchronize_post_init; ops->synchronize_state =3D hvf_cpu_synchronize_state; ops->synchronize_pre_loadvm =3D hvf_cpu_synchronize_pre_loadvm; + + ops->supports_guest_debug =3D hvf_supports_guest_debug; + ops->insert_breakpoint =3D hvf_insert_breakpoint; + ops->remove_breakpoint =3D hvf_remove_breakpoint; + ops->remove_all_breakpoints =3D hvf_remove_all_breakpoints; }; static const TypeInfo hvf_accel_ops_type =3D { .name =3D ACCEL_OPS_NAME("hvf"), diff --git a/accel/hvf/hvf-all.c b/accel/hvf/hvf-all.c index 0043f4d308..3f02c090b1 100644 --- a/accel/hvf/hvf-all.c +++ b/accel/hvf/hvf-all.c @@ -10,6 +10,7 @@ =20 #include "qemu/osdep.h" #include "qemu/error-report.h" +#include "exec/gdbstub.h" #include "sysemu/hvf.h" #include "sysemu/hvf_int.h" =20 @@ -44,3 +45,26 @@ void assert_hvf_ok(hv_return_t ret) =20 abort(); } + +struct hvf_sw_breakpoint *hvf_find_sw_breakpoint(CPUState *cpu, target_ulo= ng pc) +{ + struct hvf_sw_breakpoint *bp; + + QTAILQ_FOREACH(bp, &cpu->hvf->hvf_sw_breakpoints, entry) { + if (bp->pc =3D=3D pc) { + return bp; + } + } + return NULL; +} + +int hvf_sw_breakpoints_active(CPUState *cpu) +{ + return !QTAILQ_EMPTY(&cpu->hvf->hvf_sw_breakpoints); +} + +int hvf_update_guest_debug(CPUState *cpu) +{ + hvf_arch_update_guest_debug(cpu); + return 0; +} diff --git a/cpu.c b/cpu.c index 4a7d865427..1fd531aabd 100644 --- a/cpu.c +++ b/cpu.c @@ -33,6 +33,7 @@ #endif #include "sysemu/tcg.h" #include "sysemu/kvm.h" +#include "sysemu/hvf.h" #include "sysemu/replay.h" #include "exec/cpu-common.h" #include "exec/exec-all.h" @@ -389,6 +390,8 @@ void cpu_single_step(CPUState *cpu, int enabled) cpu->singlestep_enabled =3D enabled; if (kvm_enabled()) { kvm_update_guest_debug(cpu, 0); + } else if (hvf_enabled()) { + hvf_update_guest_debug(cpu); } trace_breakpoint_singlestep(cpu->cpu_index, enabled); } diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h index bb70082e45..3e99c80416 100644 --- a/include/sysemu/hvf.h +++ b/include/sysemu/hvf.h @@ -36,4 +36,33 @@ typedef struct HVFState HVFState; DECLARE_INSTANCE_CHECKER(HVFState, HVF_STATE, TYPE_HVF_ACCEL) =20 +#ifdef NEED_CPU_H +#include "cpu.h" + +int hvf_update_guest_debug(CPUState *cpu); + +struct hvf_sw_breakpoint { + target_ulong pc; + target_ulong saved_insn; + int use_count; + QTAILQ_ENTRY(hvf_sw_breakpoint) entry; +}; + +struct hvf_sw_breakpoint *hvf_find_sw_breakpoint(CPUState *cpu, + target_ulong pc); + +int hvf_sw_breakpoints_active(CPUState *cpu); + +int hvf_arch_insert_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint = *bp); +int hvf_arch_remove_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint = *bp); +int hvf_arch_insert_hw_breakpoint(target_ulong addr, target_ulong len, + int type); +int hvf_arch_remove_hw_breakpoint(target_ulong addr, target_ulong len, + int type); +void hvf_arch_remove_all_hw_breakpoints(void); + +void hvf_arch_update_guest_debug(CPUState *cpu); + +#endif /* NEED_CPU_H */ + #endif diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h index 6545f7cd61..a7957d046b 100644 --- a/include/sysemu/hvf_int.h +++ b/include/sysemu/hvf_int.h @@ -53,6 +53,7 @@ struct hvf_vcpu_state { void *exit; bool vtimer_masked; sigset_t unblock_ipi_mask; + QTAILQ_HEAD(, hvf_sw_breakpoint) hvf_sw_breakpoints; }; =20 void assert_hvf_ok(hv_return_t ret); diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 060aa0ccf4..66fc82e9b9 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -31,6 +31,22 @@ #include "trace/trace-target_arm_hvf.h" #include "migration/vmstate.h" =20 +#include "exec/gdbstub.h" + +static void hvf_arm_init_debug(CPUState *cpu) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + + max_hw_bps =3D arm_num_brps(arm_cpu); + hw_breakpoints =3D + g_array_sized_new(true, true, sizeof(HWBreakpoint), max_hw_bps); + + max_hw_wps =3D arm_num_wrps(arm_cpu); + hw_watchpoints =3D + g_array_sized_new(true, true, sizeof(HWWatchpoint), max_hw_wps); + return; +} + #define HVF_SYSREG(crn, crm, op0, op1, op2) \ ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) #define PL1_WRITE_MASK 0x4 @@ -621,6 +637,8 @@ int hvf_arch_init_vcpu(CPUState *cpu) &arm_cpu->isar.id_aa64mmfr0); assert_hvf_ok(ret); =20 + hvf_arm_init_debug(cpu); + return 0; } =20 @@ -1166,11 +1184,12 @@ int hvf_vcpu_exec(CPUState *cpu) { ARMCPU *arm_cpu =3D ARM_CPU(cpu); CPUARMState *env =3D &arm_cpu->env; + int ret; hv_vcpu_exit_t *hvf_exit =3D cpu->hvf->exit; hv_return_t r; bool advance_pc =3D false; =20 - if (hvf_inject_interrupts(cpu)) { + if (!(cpu->singlestep_enabled & SSTEP_NOIRQ) && hvf_inject_interrupts(= cpu)) { return EXCP_INTERRUPT; } =20 @@ -1188,6 +1207,7 @@ int hvf_vcpu_exec(CPUState *cpu) uint64_t syndrome =3D hvf_exit->exception.syndrome; uint32_t ec =3D syn_get_ec(syndrome); =20 + ret =3D 0; qemu_mutex_lock_iothread(); switch (exit_reason) { case HV_EXIT_REASON_EXCEPTION: @@ -1207,6 +1227,47 @@ int hvf_vcpu_exec(CPUState *cpu) hvf_sync_vtimer(cpu); =20 switch (ec) { + case EC_SOFTWARESTEP: { + ret =3D EXCP_DEBUG; + + if (!cpu->singlestep_enabled) { + error_report("EC_SOFTWARESTEP but single-stepping not enabled"= ); + } + break; + } + case EC_AA64_BKPT: { + ret =3D EXCP_DEBUG; + + cpu_synchronize_state(cpu); + + if (!hvf_find_sw_breakpoint(cpu, env->pc)) { + error_report("EC_AA64_BKPT but unknown sw breakpoint"); + } + break; + } + case EC_BREAKPOINT: { + ret =3D EXCP_DEBUG; + + cpu_synchronize_state(cpu); + + if (!find_hw_breakpoint(cpu, env->pc)) { + error_report("EC_BREAKPOINT but unknown hw breakpoint"); + } + break; + } + case EC_WATCHPOINT: { + ret =3D EXCP_DEBUG; + + cpu_synchronize_state(cpu); + + CPUWatchpoint *wp =3D + find_hw_watchpoint(cpu, hvf_exit->exception.virtual_address); + if (!wp) { + error_report("EXCP_DEBUG but unknown hw watchpoint"); + } + cpu->watchpoint_hit =3D wp; + break; + } case EC_DATAABORT: { bool isv =3D syndrome & ARM_EL_ISV; bool iswrite =3D (syndrome >> 6) & 1; @@ -1313,7 +1374,7 @@ int hvf_vcpu_exec(CPUState *cpu) assert_hvf_ok(r); } =20 - return 0; + return ret; } =20 static const VMStateDescription vmstate_hvf_vtimer =3D { @@ -1347,3 +1408,132 @@ int hvf_arch_init(void) qemu_add_vm_change_state_handler(hvf_vm_state_change, &vtimer); return 0; } + +static inline bool hvf_arm_hw_debug_active(CPUState *cpu) +{ + return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); +} + +static const uint32_t brk_insn =3D 0xd4200000; + +int hvf_arch_insert_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint = *bp) +{ + if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0)= || + cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { + return -EINVAL; + } + return 0; +} + +int hvf_arch_remove_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint = *bp) +{ + static uint32_t brk; + + if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk, 4, 0) || + brk !=3D brk_insn || + cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)= ) { + return -EINVAL; + } + return 0; +} + +int hvf_arch_insert_hw_breakpoint(target_ulong addr, target_ulong len, int= type) +{ + switch (type) { + case GDB_BREAKPOINT_HW: + return insert_hw_breakpoint(addr); + case GDB_WATCHPOINT_READ: + case GDB_WATCHPOINT_WRITE: + case GDB_WATCHPOINT_ACCESS: + return insert_hw_watchpoint(addr, len, type); + default: + return -ENOSYS; + } +} + +int hvf_arch_remove_hw_breakpoint(target_ulong addr, target_ulong len, int= type) +{ + switch (type) { + case GDB_BREAKPOINT_HW: + return delete_hw_breakpoint(addr); + case GDB_WATCHPOINT_READ: + case GDB_WATCHPOINT_WRITE: + case GDB_WATCHPOINT_ACCESS: + return delete_hw_watchpoint(addr, len, type); + default: + return -ENOSYS; + } +} + +void hvf_arch_remove_all_hw_breakpoints(void) +{ + if (cur_hw_wps > 0) { + g_array_remove_range(hw_watchpoints, 0, cur_hw_wps); + } + if (cur_hw_bps > 0) { + g_array_remove_range(hw_breakpoints, 0, cur_hw_bps); + } +} + +#define MDSCR_EL1_SS_SHIFT 0 +#define MDSCR_EL1_MDE_SHIFT 15 + +void hvf_arch_update_guest_debug(CPUState *cpu) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + hv_return_t r =3D HV_SUCCESS; + bool trap_debug_exceptions =3D false; + + cpu_synchronize_state(cpu); + + if (cpu->singlestep_enabled) { + trap_debug_exceptions =3D true; + + env->cp15.mdscr_el1 =3D + deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 1); + pstate_write(env, pstate_read(env) | PSTATE_SS); + } else { + env->cp15.mdscr_el1 =3D + deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 0); + } + + if (hvf_sw_breakpoints_active(cpu)) { + trap_debug_exceptions =3D true; + } + + if (hvf_arm_hw_debug_active(cpu)) { + trap_debug_exceptions =3D true; + + env->cp15.mdscr_el1 =3D + deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 1); + + int i; + for (i =3D 0; i < cur_hw_bps; i++) { + HWBreakpoint *bp =3D get_hw_bp(i); + env->cp15.dbgbcr[i] =3D bp->bcr; + env->cp15.dbgbvr[i] =3D bp->bvr; + } + for (i =3D 0; i < cur_hw_wps; i++) { + HWWatchpoint *bp =3D get_hw_wp(i); + env->cp15.dbgwcr[i] =3D bp->wcr; + env->cp15.dbgwvr[i] =3D bp->wvr; + } + } else { + env->cp15.mdscr_el1 =3D + deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 0); + + int i; + for (i =3D 0; i < max_hw_bps; i++) { + env->cp15.dbgbcr[i] =3D 0; + env->cp15.dbgbvr[i] =3D 0; + } + for (i =3D 0; i < max_hw_wps; i++) { + env->cp15.dbgwcr[i] =3D 0; + env->cp15.dbgwvr[i] =3D 0; + } + } + + r =3D hv_vcpu_set_trap_debug_exceptions(cpu->hvf->fd, trap_debug_excep= tions); + assert_hvf_ok(r); +} --=20 2.38.1 From nobody Fri May 17 02:03:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1668621039; cv=none; d=zohomail.com; s=zohoarc; b=gKiOdAGWmnH1QPtDvWGOXlM1+bG6u0AWSMZJzlV0BOEFYBsoi/86+/sAh3MeTTY1BCJqCMcZhkQ8m5SWV1DoeaVeIkapXTwM2peBl+Wo5AwkmKXkJcNRkbyGvSh3uk96QWebPI3B03lMZOrlyyw1MdxveQbv6+kZZdHGhx0YkDs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1668621039; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KrvwPOtZNfEKsXjuC0ZbgXfL4yPk3ZZbpxNJSMb/UOA=; b=SNSJ2qDXbSePktkGIso+7UOujx0bkthAskU+xAhE/+PwifMpRHasQcSdR9fMcbNCB2GinA5dIWXQGuNcVsXq3tEEc2/zjT43bLxsvfUp/TiTCQ44A3z15+OsPftGuq2sD1aeJTPz/epJtbFkl0mTV00c83uQwcLrwsOfKji8Z/Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166862103994048.73870159373587; Wed, 16 Nov 2022 09:50:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ovMWN-0006Q1-US; Wed, 16 Nov 2022 12:48:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ovMWM-0006Ol-MN; Wed, 16 Nov 2022 12:48:22 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ovMWK-00014J-PT; Wed, 16 Nov 2022 12:48:22 -0500 Received: by mail-wm1-x331.google.com with SMTP id p16so12431923wmc.3; Wed, 16 Nov 2022 09:48:20 -0800 (PST) Received: from localhost.localdomain (229.19.205.77.rev.sfr.net. [77.205.19.229]) by smtp.gmail.com with ESMTPSA id n17-20020a05600c465100b003cf483ee8e0sm2477490wmo.24.2022.11.16.09.48.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 16 Nov 2022 09:48:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KrvwPOtZNfEKsXjuC0ZbgXfL4yPk3ZZbpxNJSMb/UOA=; b=kv5/q0izde86fUAHLrYnS/iqNpfCZR5yIllPFKLWllH/3jTLFYKnSVqvENoNgR+rgT PZowt2UvPJkFgTgr8hZMVAfVBCp0QhejBqscpDb5NiROzyhFdVkw4+I/N8ddB38VaZtl Yl3nFT8mxdorI5rCSQIJvZ0vsSpqKNqOL0R10WyDTHsNGEoKyuevGtDvfgs3DMFqSwoD ck59Qxyzcg3mmEdgQMyn3WDV0dekpu/ZpRhYBe01apNx19o07xC4S1RqkC64S1HZK1Ly D/ecKc8ZsrpH8q7plDDj+1/EyPk6cQD98oESeUWHUpFpXJwoJzoQQR0tj7SbKFtCSXgz dj7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KrvwPOtZNfEKsXjuC0ZbgXfL4yPk3ZZbpxNJSMb/UOA=; b=DIeQWv9RDrK6jF6Sg2Ul1cOCzPx1tgDs+0V2UsNGGku0ch6p6ZySfMSqOjawXUGtqf bB40jKDqRAyOq5aREpFTYhxCKbEsyOu9wKZ4jo6ad0+BIyNHSd7PtuZzN+PBO5lSnuCb LjZWPdBY/tLvCr8PxEmESVPnEBjkG2F6AAZa7UboUJcDCS0DN2d6H7ywzd/C3BlJ0h3c yPlbqU/+Dm2u7J2cnKTQpazhyVaEukcOeROT5l/3HmDXW5XXU86f9DXl+uDrshRuMPVr YtjgMEU5zGjY/kQCJXDhJrPtv18UxpWnyWg8suXuiFzXBEiRQUxR8vPn8okyNG9v/9i3 G5AQ== X-Gm-Message-State: ANoB5pm0hd7ZBaWRCw8IDr8ptwu+9iLMSNuRhdg4xTe6nUqlFAlluQ75 3lUU4/t00yJZjT+eUTX1NMcN70IX29Ii7Q== X-Google-Smtp-Source: AA0mqf6wdc3n0wBAT6sQF53c/7LvqiuSfO5xEgRE5OdT/HVAIB6I/w/aMLJ+tDVBV0+683DzVBMb6Q== X-Received: by 2002:a05:600c:3d1b:b0:3cf:670e:63cc with SMTP id bh27-20020a05600c3d1b00b003cf670e63ccmr2975784wmb.150.1668620899089; Wed, 16 Nov 2022 09:48:19 -0800 (PST) From: francesco.cagnin@gmail.com X-Google-Original-From: fcagnin@quarkslab.com To: qemu-devel@nongnu.org Cc: mads@ynddal.dk, dirty@apple.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, agraf@csgraf.de, pbonzini@redhat.com, alex.bennee@linaro.org, Francesco Cagnin Subject: [PATCH v2 3/3] hvf: handle writes of MDSCR_EL1 and DBG*_EL1 Date: Wed, 16 Nov 2022 18:47:49 +0100 Message-Id: <20221116174749.65175-4-fcagnin@quarkslab.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116174749.65175-1-fcagnin@quarkslab.com> References: <20221116174749.65175-1-fcagnin@quarkslab.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=francesco.cagnin@gmail.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1668621058923100001 Content-Type: text/plain; charset="utf-8" From: Francesco Cagnin This proved to be required when debugging the Linux kernel's initial code, as the Hypervisor framework was triggering 'EC_SYSTEMREGISTERTRAP' VM exits after enabling trap exceptions with 'hv_vcpu_set_trap_debug_exceptions()'. Signed-off-by: Francesco Cagnin Reviewed-by: Mads Ynddal --- target/arm/hvf/hvf.c | 140 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 66fc82e9b9..c28c3dbdaa 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -95,6 +95,71 @@ static void hvf_arm_init_debug(CPUState *cpu) #define SYSREG_PMCEID1_EL0 SYSREG(3, 3, 9, 12, 7) #define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0) #define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7) +#define SYSREG_MDSCR_EL1 SYSREG(2, 0, 0, 2, 2) +#define SYSREG_DBGBVR0_EL1 SYSREG(2, 0, 0, 0, 4) +#define SYSREG_DBGBCR0_EL1 SYSREG(2, 0, 0, 0, 5) +#define SYSREG_DBGWVR0_EL1 SYSREG(2, 0, 0, 0, 6) +#define SYSREG_DBGWCR0_EL1 SYSREG(2, 0, 0, 0, 7) +#define SYSREG_DBGBVR1_EL1 SYSREG(2, 0, 0, 1, 4) +#define SYSREG_DBGBCR1_EL1 SYSREG(2, 0, 0, 1, 5) +#define SYSREG_DBGWVR1_EL1 SYSREG(2, 0, 0, 1, 6) +#define SYSREG_DBGWCR1_EL1 SYSREG(2, 0, 0, 1, 7) +#define SYSREG_DBGBVR2_EL1 SYSREG(2, 0, 0, 2, 4) +#define SYSREG_DBGBCR2_EL1 SYSREG(2, 0, 0, 2, 5) +#define SYSREG_DBGWVR2_EL1 SYSREG(2, 0, 0, 2, 6) +#define SYSREG_DBGWCR2_EL1 SYSREG(2, 0, 0, 2, 7) +#define SYSREG_DBGBVR3_EL1 SYSREG(2, 0, 0, 3, 4) +#define SYSREG_DBGBCR3_EL1 SYSREG(2, 0, 0, 3, 5) +#define SYSREG_DBGWVR3_EL1 SYSREG(2, 0, 0, 3, 6) +#define SYSREG_DBGWCR3_EL1 SYSREG(2, 0, 0, 3, 7) +#define SYSREG_DBGBVR4_EL1 SYSREG(2, 0, 0, 4, 4) +#define SYSREG_DBGBCR4_EL1 SYSREG(2, 0, 0, 4, 5) +#define SYSREG_DBGWVR4_EL1 SYSREG(2, 0, 0, 4, 6) +#define SYSREG_DBGWCR4_EL1 SYSREG(2, 0, 0, 4, 7) +#define SYSREG_DBGBVR5_EL1 SYSREG(2, 0, 0, 5, 4) +#define SYSREG_DBGBCR5_EL1 SYSREG(2, 0, 0, 5, 5) +#define SYSREG_DBGWVR5_EL1 SYSREG(2, 0, 0, 5, 6) +#define SYSREG_DBGWCR5_EL1 SYSREG(2, 0, 0, 5, 7) +#define SYSREG_DBGBVR6_EL1 SYSREG(2, 0, 0, 6, 4) +#define SYSREG_DBGBCR6_EL1 SYSREG(2, 0, 0, 6, 5) +#define SYSREG_DBGWVR6_EL1 SYSREG(2, 0, 0, 6, 6) +#define SYSREG_DBGWCR6_EL1 SYSREG(2, 0, 0, 6, 7) +#define SYSREG_DBGBVR7_EL1 SYSREG(2, 0, 0, 7, 4) +#define SYSREG_DBGBCR7_EL1 SYSREG(2, 0, 0, 7, 5) +#define SYSREG_DBGWVR7_EL1 SYSREG(2, 0, 0, 7, 6) +#define SYSREG_DBGWCR7_EL1 SYSREG(2, 0, 0, 7, 7) +#define SYSREG_DBGBVR8_EL1 SYSREG(2, 0, 0, 8, 4) +#define SYSREG_DBGBCR8_EL1 SYSREG(2, 0, 0, 8, 5) +#define SYSREG_DBGWVR8_EL1 SYSREG(2, 0, 0, 8, 6) +#define SYSREG_DBGWCR8_EL1 SYSREG(2, 0, 0, 8, 7) +#define SYSREG_DBGBVR9_EL1 SYSREG(2, 0, 0, 9, 4) +#define SYSREG_DBGBCR9_EL1 SYSREG(2, 0, 0, 9, 5) +#define SYSREG_DBGWVR9_EL1 SYSREG(2, 0, 0, 9, 6) +#define SYSREG_DBGWCR9_EL1 SYSREG(2, 0, 0, 9, 7) +#define SYSREG_DBGBVR10_EL1 SYSREG(2, 0, 0, 10, 4) +#define SYSREG_DBGBCR10_EL1 SYSREG(2, 0, 0, 10, 5) +#define SYSREG_DBGWVR10_EL1 SYSREG(2, 0, 0, 10, 6) +#define SYSREG_DBGWCR10_EL1 SYSREG(2, 0, 0, 10, 7) +#define SYSREG_DBGBVR11_EL1 SYSREG(2, 0, 0, 11, 4) +#define SYSREG_DBGBCR11_EL1 SYSREG(2, 0, 0, 11, 5) +#define SYSREG_DBGWVR11_EL1 SYSREG(2, 0, 0, 11, 6) +#define SYSREG_DBGWCR11_EL1 SYSREG(2, 0, 0, 11, 7) +#define SYSREG_DBGBVR12_EL1 SYSREG(2, 0, 0, 12, 4) +#define SYSREG_DBGBCR12_EL1 SYSREG(2, 0, 0, 12, 5) +#define SYSREG_DBGWVR12_EL1 SYSREG(2, 0, 0, 12, 6) +#define SYSREG_DBGWCR12_EL1 SYSREG(2, 0, 0, 12, 7) +#define SYSREG_DBGBVR13_EL1 SYSREG(2, 0, 0, 13, 4) +#define SYSREG_DBGBCR13_EL1 SYSREG(2, 0, 0, 13, 5) +#define SYSREG_DBGWVR13_EL1 SYSREG(2, 0, 0, 13, 6) +#define SYSREG_DBGWCR13_EL1 SYSREG(2, 0, 0, 13, 7) +#define SYSREG_DBGBVR14_EL1 SYSREG(2, 0, 0, 14, 4) +#define SYSREG_DBGBCR14_EL1 SYSREG(2, 0, 0, 14, 5) +#define SYSREG_DBGWVR14_EL1 SYSREG(2, 0, 0, 14, 6) +#define SYSREG_DBGWCR14_EL1 SYSREG(2, 0, 0, 14, 7) +#define SYSREG_DBGBVR15_EL1 SYSREG(2, 0, 0, 15, 4) +#define SYSREG_DBGBCR15_EL1 SYSREG(2, 0, 0, 15, 5) +#define SYSREG_DBGWVR15_EL1 SYSREG(2, 0, 0, 15, 6) +#define SYSREG_DBGWCR15_EL1 SYSREG(2, 0, 0, 15, 7) =20 #define WFX_IS_WFE (1 << 0) =20 @@ -1039,6 +1104,81 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t = reg, uint64_t val) case SYSREG_OSDLR_EL1: /* Dummy register */ break; + case SYSREG_MDSCR_EL1: + env->cp15.mdscr_el1 =3D val; + break; + case SYSREG_DBGBVR0_EL1: + case SYSREG_DBGBVR1_EL1: + case SYSREG_DBGBVR2_EL1: + case SYSREG_DBGBVR3_EL1: + case SYSREG_DBGBVR4_EL1: + case SYSREG_DBGBVR5_EL1: + case SYSREG_DBGBVR6_EL1: + case SYSREG_DBGBVR7_EL1: + case SYSREG_DBGBVR8_EL1: + case SYSREG_DBGBVR9_EL1: + case SYSREG_DBGBVR10_EL1: + case SYSREG_DBGBVR11_EL1: + case SYSREG_DBGBVR12_EL1: + case SYSREG_DBGBVR13_EL1: + case SYSREG_DBGBVR14_EL1: + case SYSREG_DBGBVR15_EL1: + env->cp15.dbgbvr[SYSREG_CRM(reg)] =3D val; + break; + case SYSREG_DBGBCR0_EL1: + case SYSREG_DBGBCR1_EL1: + case SYSREG_DBGBCR2_EL1: + case SYSREG_DBGBCR3_EL1: + case SYSREG_DBGBCR4_EL1: + case SYSREG_DBGBCR5_EL1: + case SYSREG_DBGBCR6_EL1: + case SYSREG_DBGBCR7_EL1: + case SYSREG_DBGBCR8_EL1: + case SYSREG_DBGBCR9_EL1: + case SYSREG_DBGBCR10_EL1: + case SYSREG_DBGBCR11_EL1: + case SYSREG_DBGBCR12_EL1: + case SYSREG_DBGBCR13_EL1: + case SYSREG_DBGBCR14_EL1: + case SYSREG_DBGBCR15_EL1: + env->cp15.dbgbcr[SYSREG_CRM(reg)] =3D val; + break; + case SYSREG_DBGWVR0_EL1: + case SYSREG_DBGWVR1_EL1: + case SYSREG_DBGWVR2_EL1: + case SYSREG_DBGWVR3_EL1: + case SYSREG_DBGWVR4_EL1: + case SYSREG_DBGWVR5_EL1: + case SYSREG_DBGWVR6_EL1: + case SYSREG_DBGWVR7_EL1: + case SYSREG_DBGWVR8_EL1: + case SYSREG_DBGWVR9_EL1: + case SYSREG_DBGWVR10_EL1: + case SYSREG_DBGWVR11_EL1: + case SYSREG_DBGWVR12_EL1: + case SYSREG_DBGWVR13_EL1: + case SYSREG_DBGWVR14_EL1: + case SYSREG_DBGWVR15_EL1: + env->cp15.dbgwvr[SYSREG_CRM(reg)] =3D val; + break; + case SYSREG_DBGWCR0_EL1: + case SYSREG_DBGWCR1_EL1: + case SYSREG_DBGWCR2_EL1: + case SYSREG_DBGWCR3_EL1: + case SYSREG_DBGWCR4_EL1: + case SYSREG_DBGWCR5_EL1: + case SYSREG_DBGWCR6_EL1: + case SYSREG_DBGWCR7_EL1: + case SYSREG_DBGWCR8_EL1: + case SYSREG_DBGWCR9_EL1: + case SYSREG_DBGWCR10_EL1: + case SYSREG_DBGWCR11_EL1: + case SYSREG_DBGWCR12_EL1: + case SYSREG_DBGWCR13_EL1: + case SYSREG_DBGWCR14_EL1: + case SYSREG_DBGWCR15_EL1: + env->cp15.dbgwcr[SYSREG_CRM(reg)] =3D val; + break; default: cpu_synchronize_state(cpu); trace_hvf_unhandled_sysreg_write(env->pc, reg, --=20 2.38.1