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[2001:44b8:2176:c800:8228:b676:fb42:ee07]) by smtp.gmail.com with ESMTPSA id m8-20020a17090a71c800b00213d08fa459sm2743062pjs.17.2022.11.11.23.56.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Nov 2022 23:56:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qw1tQpgpqGjwOWEsHHDVfFOA6fud/wYsdJ0Bljtybvo=; b=yPdh0JqbVJqLF4ge0ZEF8z/Mvj46uHEhEmBxWuT7G3YCb4yrBVHy+qaiBsM9kxxWmR vvW1zbCvumKq6ZHeKe02yHDAUP9r+3nOs8+gPFMvV+wtZblCBaE/x6YVpap8w4zwIVYx Iyhu/qk/pfWd2WRk+2voqE2cP4e4FEqpNteMVVCbQsiMGIHnEEK9RB9JYzkNIa1pX+5v 065PlYokLlA7R6a5ZILy13hRX80zhtQETGryjwywrF10VsU3ComkbPY/1Dinnmx5STxb Qt+r8lhIxmit7FZ7qkW7GJmCsjr9pBcOhd1y/xvPdfsluIFT/uvPSugHyxNXcrqjqXb+ Yaig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qw1tQpgpqGjwOWEsHHDVfFOA6fud/wYsdJ0Bljtybvo=; b=tyc6FvSVdKJW7lPnbBQQ1zpnnys3pIvodZ8F4p/bgog+bWF80ZuH0/4CNIQqCpr92A cStd3mih29ZP7nzJ1I9Ey1hI7Q8fLqqTrlSRSub+6lnAAKnG9N1g5ATyV4upAoqz99A0 ct4vY3+xqMdGcHIU4IAUqfgGo8JYyVz3N+YefsQCIQbhw05TUouYrDy9VcRKspvpCc+V UPlUgDFoLaS4yyJghgRtgUn2VOyzvbKxhnCQkHdWTKP3ZXsW6FM9gU4aiAzqCGYAaIZu 2qd/HyfnxXjlBZV8iRNFyi4N0JNpKPZTztOoxEbOxPJB6ULhEpc1fFKw2ETI8aJlYZLA DqIw== X-Gm-Message-State: ANoB5pkL+PpMUqbtjBqpJqANoZd0kjQnLOdRzelZkg9OQ3vu0sUiUcYb DUseMVa9AWqNnAszQSuuYox1nNsVzDjeohAj X-Google-Smtp-Source: AA0mqf42P/jUU9BYUrsRoRlDrLsgppFLDEG5JKeGFNyZtVfjqtFE3PIEqOhgV1xYCNn0YMqh28r40Q== X-Received: by 2002:a17:902:d64f:b0:186:6381:f180 with SMTP id y15-20020a170902d64f00b001866381f180mr5726125plh.100.1668239814279; Fri, 11 Nov 2022 23:56:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH for-8.0 1/3] target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16b Date: Sat, 12 Nov 2022 17:56:43 +1000 Message-Id: <20221112075645.2850679-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221112075645.2850679-1-richard.henderson@linaro.org> References: <20221112075645.2850679-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668239838489100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 48 ++++++++++++++++++++++++------------- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 28a4e6dc1d..1175540a2c 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2974,6 +2974,34 @@ static void gen_sty_env_A0(DisasContext *s, int offs= et, bool align) #include "emit.c.inc" #include "decode-new.c.inc" =20 +static void gen_cmpxchg8b(DisasContext *s, CPUX86State *env, int modrm) +{ + gen_lea_modrm(env, s, modrm); + + if ((s->prefix & PREFIX_LOCK) && + (tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_helper_cmpxchg8b(cpu_env, s->A0); + } else { + gen_helper_cmpxchg8b_unlocked(cpu_env, s->A0); + } + set_cc_op(s, CC_OP_EFLAGS); +} + +#ifdef TARGET_X86_64 +static void gen_cmpxchg16b(DisasContext *s, CPUX86State *env, int modrm) +{ + gen_lea_modrm(env, s, modrm); + + if ((s->prefix & PREFIX_LOCK) && + (tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_helper_cmpxchg16b(cpu_env, s->A0); + } else { + gen_helper_cmpxchg16b_unlocked(cpu_env, s->A0); + } + set_cc_op(s, CC_OP_EFLAGS); +} +#endif + /* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ static bool disas_insn(DisasContext *s, CPUState *cpu) @@ -3814,28 +3842,14 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) { goto illegal_op; } - gen_lea_modrm(env, s, modrm); - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg16b(cpu_env, s->A0); - } else { - gen_helper_cmpxchg16b_unlocked(cpu_env, s->A0); - } - set_cc_op(s, CC_OP_EFLAGS); + gen_cmpxchg16b(s, env, modrm); break; } -#endif =20 +#endif if (!(s->cpuid_features & CPUID_CX8)) { goto illegal_op; } - gen_lea_modrm(env, s, modrm); - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg8b(cpu_env, s->A0); - } else { - gen_helper_cmpxchg8b_unlocked(cpu_env, s->A0); - } - set_cc_op(s, CC_OP_EFLAGS); + gen_cmpxchg8b(s, env, modrm); break; =20 case 7: /* RDSEED */ --=20 2.34.1 From nobody Sun May 12 08:50:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1668239912; cv=none; d=zohomail.com; s=zohoarc; b=mMMaSzfB1O7BycSEMxwAXsP+NSu48FRnd/ruLM6T7jYmcmY7W1HKQngO/CqBrUn75G1XJ2pLcZHD0jcRBMPayyppXUnKxpBj0lq6g57w3QV5ZDiOQdIXugORx598YdA+zVzPWhUZ2uFkmULAxpIPaqF0ec9BsTRoT+EB+UFoERw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1668239912; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tAuzr1+zL/74qkOPgnHR21GwFVmTlAsrzfx9yY4tIMY=; b=LmbU4MnQXnBT/6dHncWkDujuNHgf81tlULCv8rhAPvlfyQ3G5lQsnxG2w3aDm/HVhHzDgnEQ3ZJ+VBHkvvzaFoDAh/7vcM01xcdcXf1W7wvmpKnYBrJjRNmp+7E5Vxm0TmEPRLIJQhDpghorVfKyPqtIu8rumhH1MvUi3kZYyts= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1668239912522355.0141408771467; Fri, 11 Nov 2022 23:58:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1otlNv-0006At-6n; Sat, 12 Nov 2022 02:57:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1otlNs-0006AD-Kd for qemu-devel@nongnu.org; Sat, 12 Nov 2022 02:57:01 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1otlNq-0008CC-RZ for qemu-devel@nongnu.org; Sat, 12 Nov 2022 02:57:00 -0500 Received: by mail-pj1-x102b.google.com with SMTP id m14-20020a17090a3f8e00b00212dab39bcdso9615583pjc.0 for ; Fri, 11 Nov 2022 23:56:58 -0800 (PST) Received: from stoup.lan (2001-44b8-2176-c800-8228-b676-fb42-ee07.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8228:b676:fb42:ee07]) by smtp.gmail.com with ESMTPSA id m8-20020a17090a71c800b00213d08fa459sm2743062pjs.17.2022.11.11.23.56.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Nov 2022 23:56:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tAuzr1+zL/74qkOPgnHR21GwFVmTlAsrzfx9yY4tIMY=; b=bHhkkPYeoZJbnO5gb8nT7s0BfBl8uQ7xpv2TxK34SYOeaHIut5K8rEfOoi1Di93exb TsPk85N3ZssaQkLFv7qbjLOlxfglWXMRnbKOO5Qc2uAuDLgJHVtuGpAjlXsOWoxe3+Sy 0F9T9nRkn2cCQIgQl5ngdepG7xHuGuWp+Fm1VVdmRxF5iU4s+a0OP+r6RlSQIVcwUOal oy5paApT3F/6fVINAZGtYNEyhaHPk+CRfd6Cl68gtW0Gb+TBrxfMgvvkNvHQbTm5CARV amEIWW8z/kpTc0JBxl1uzwD32iRAWndmE5mVDr+s2q0D2YAd1uiY8c5js5rHVcue0UQp padQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tAuzr1+zL/74qkOPgnHR21GwFVmTlAsrzfx9yY4tIMY=; b=OZ0083YVSJQ65YK8QHy9KdlQ4u7+2k0oNgaAnlY/zBygZkbyPEOZVtDXxPePPNzMLp 6UHS0moW94FFMuGWqkl5+zB6ub4OALwqVLbiUy3ebNZQS2ym2/ASRk1gcFFMIPXHtX3X NK4cTCMkJ3BBdy4juu2m5L07bh0yTDsP3ZbKfj9sU4hTB5u8yWfmUdzzXp8cVXkiAGaJ zMArlYfd/m5d9uTPCLdZv+4Ezva+RXyGAXdEqvZIVppHwKxk4j9z/WAZD1BmNPFNNAq0 AAtWbGV6WT72g+WnN5cPEbC6v6L/qQemwY8Mz97c270DRh4gg17oeUudn9Jc6HJIeyhW J8Jw== X-Gm-Message-State: ANoB5pn3dbGz+fWIb4uxuiYM1lgvv9MpUxW0yFfXOVCp9NcXBQqk6KPl srXH1cen5EybFkNydpTvA6LIoYD0MBcRGccE X-Google-Smtp-Source: AA0mqf7KwE2FZxd7w2cN4k7tbfNVWSyojYFSzOV3ayt4kA5QL29SeN4q49bLHciBiMrcVnL24VDD8g== X-Received: by 2002:a17:90a:4544:b0:212:bfc3:3271 with SMTP id r4-20020a17090a454400b00212bfc33271mr5395061pjm.99.1668239817356; Fri, 11 Nov 2022 23:56:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH for-8.0 2/3] target/i386: Inline cmpxchg8b Date: Sat, 12 Nov 2022 17:56:44 +1000 Message-Id: <20221112075645.2850679-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221112075645.2850679-1-richard.henderson@linaro.org> References: <20221112075645.2850679-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668239914686100003 Content-Type: text/plain; charset="utf-8" Use tcg_gen_atomic_cmpxchg_i64 for the atomic case, and tcg_gen_nonatomic_cmpxchg_i64 otherwise. Signed-off-by: Richard Henderson --- target/i386/helper.h | 2 -- target/i386/tcg/mem_helper.c | 57 ------------------------------------ target/i386/tcg/translate.c | 54 ++++++++++++++++++++++++++++++---- 3 files changed, 49 insertions(+), 64 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index b7de5429ef..2df8049f91 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -66,8 +66,6 @@ DEF_HELPER_1(rsm, void, env) #endif /* !CONFIG_USER_ONLY */ =20 DEF_HELPER_2(into, void, env, int) -DEF_HELPER_2(cmpxchg8b_unlocked, void, env, tl) -DEF_HELPER_2(cmpxchg8b, void, env, tl) #ifdef TARGET_X86_64 DEF_HELPER_2(cmpxchg16b_unlocked, void, env, tl) DEF_HELPER_2(cmpxchg16b, void, env, tl) diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index e3cdafd2d4..814786bb87 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -27,63 +27,6 @@ #include "tcg/tcg.h" #include "helper-tcg.h" =20 -void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0) -{ - uintptr_t ra =3D GETPC(); - uint64_t oldv, cmpv, newv; - int eflags; - - eflags =3D cpu_cc_compute_all(env, CC_OP); - - cmpv =3D deposit64(env->regs[R_EAX], 32, 32, env->regs[R_EDX]); - newv =3D deposit64(env->regs[R_EBX], 32, 32, env->regs[R_ECX]); - - oldv =3D cpu_ldq_data_ra(env, a0, ra); - newv =3D (cmpv =3D=3D oldv ? newv : oldv); - /* always do the store */ - cpu_stq_data_ra(env, a0, newv, ra); - - if (oldv =3D=3D cmpv) { - eflags |=3D CC_Z; - } else { - env->regs[R_EAX] =3D (uint32_t)oldv; - env->regs[R_EDX] =3D (uint32_t)(oldv >> 32); - eflags &=3D ~CC_Z; - } - CC_SRC =3D eflags; -} - -void helper_cmpxchg8b(CPUX86State *env, target_ulong a0) -{ -#ifdef CONFIG_ATOMIC64 - uint64_t oldv, cmpv, newv; - int eflags; - - eflags =3D cpu_cc_compute_all(env, CC_OP); - - cmpv =3D deposit64(env->regs[R_EAX], 32, 32, env->regs[R_EDX]); - newv =3D deposit64(env->regs[R_EBX], 32, 32, env->regs[R_ECX]); - - { - uintptr_t ra =3D GETPC(); - int mem_idx =3D cpu_mmu_index(env, false); - MemOpIdx oi =3D make_memop_idx(MO_TEUQ, mem_idx); - oldv =3D cpu_atomic_cmpxchgq_le_mmu(env, a0, cmpv, newv, oi, ra); - } - - if (oldv =3D=3D cmpv) { - eflags |=3D CC_Z; - } else { - env->regs[R_EAX] =3D (uint32_t)oldv; - env->regs[R_EDX] =3D (uint32_t)(oldv >> 32); - eflags &=3D ~CC_Z; - } - CC_SRC =3D eflags; -#else - cpu_loop_exit_atomic(env_cpu(env), GETPC()); -#endif /* CONFIG_ATOMIC64 */ -} - #ifdef TARGET_X86_64 void helper_cmpxchg16b_unlocked(CPUX86State *env, target_ulong a0) { diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 1175540a2c..a134d63946 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2976,15 +2976,59 @@ static void gen_sty_env_A0(DisasContext *s, int off= set, bool align) =20 static void gen_cmpxchg8b(DisasContext *s, CPUX86State *env, int modrm) { + TCGv_i64 cmp, val, old; + TCGv Z; + gen_lea_modrm(env, s, modrm); =20 - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg8b(cpu_env, s->A0); + cmp =3D tcg_temp_new_i64(); + val =3D tcg_temp_new_i64(); + old =3D tcg_temp_new_i64(); + + /* Construct the comparison values from the register pair. */ + tcg_gen_concat_tl_i64(cmp, cpu_regs[R_EAX], cpu_regs[R_EDX]); + tcg_gen_concat_tl_i64(val, cpu_regs[R_EBX], cpu_regs[R_ECX]); + + /* Only require atomic with LOCK; non-parallel handled in generator. */ + if (s->prefix & PREFIX_LOCK) { + tcg_gen_atomic_cmpxchg_i64(old, s->A0, cmp, val, s->mem_index, MO_= TEUQ); } else { - gen_helper_cmpxchg8b_unlocked(cpu_env, s->A0); + tcg_gen_nonatomic_cmpxchg_i64(old, s->A0, cmp, val, + s->mem_index, MO_TEUQ); } - set_cc_op(s, CC_OP_EFLAGS); + tcg_temp_free_i64(val); + + /* Set tmp0 to match the required value of Z. */ + tcg_gen_setcond_i64(TCG_COND_EQ, cmp, old, cmp); + Z =3D tcg_temp_new(); + tcg_gen_trunc_i64_tl(Z, cmp); + tcg_temp_free_i64(cmp); + + /* + * Extract the result values for the register pair. + * For 32-bit, we may do this unconditionally, because on success (Z= =3D1), + * the old value matches the previous value in EDX:EAX. For x86_64, + * the store must be conditional, because we must leave the source + * registers unchanged on success, and zero-extend the writeback + * on failure (Z=3D0). + */ + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_gen_extr_i64_tl(cpu_regs[R_EAX], cpu_regs[R_EDX], old); + } else { + TCGv zero =3D tcg_constant_tl(0); + + tcg_gen_extr_i64_tl(s->T0, s->T1, old); + tcg_gen_movcond_tl(TCG_COND_EQ, cpu_regs[R_EAX], Z, zero, + s->T0, cpu_regs[R_EAX]); + tcg_gen_movcond_tl(TCG_COND_EQ, cpu_regs[R_EDX], Z, zero, + s->T1, cpu_regs[R_EDX]); + } + tcg_temp_free_i64(old); + + /* Update Z. */ + gen_compute_eflags(s); + tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, Z, ctz32(CC_Z), 1); + tcg_temp_free(Z); } =20 #ifdef TARGET_X86_64 --=20 2.34.1 From nobody Sun May 12 08:50:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1668239875; cv=none; d=zohomail.com; s=zohoarc; b=KChtkE3W11I/jVyQydtqGvdSRzzB+Fez9pjj7uEcnwDg84puzDSY/pjmfF0bFZ1pkttXZD5bRS1hyhKoI86axF37J8A0uKjNznOyVjABroXVJppkx8rXka3wjr+Fu2DKOylf39nAIhoDLOCGcvXeeK7bQ2coRK13njUtPmn7uQg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1668239875; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uZPaYOgpXH2xCLOdQ104Ejv9oIO+hb8rMy2pf7ORzjY=; b=mmo3M3GTD3Yk0r3kzgGd2N+UUW05sP9NYYgPWKSn1n6aPc4pu31YmpUc6n2juirnaDrNlhLzDAbC/uQqC5z86kk/C+hS+O+wyGyfZXh+/Lt4lBo6FnH49W+AvAbsV945e27t43IY4mLSUIxbhn/R0A2NQl7TN2S1ZdZvPC6/iKg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1668239875681422.1339867221376; Fri, 11 Nov 2022 23:57:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1otlNx-0006BW-8G; Sat, 12 Nov 2022 02:57:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1otlNv-0006Av-A0 for qemu-devel@nongnu.org; Sat, 12 Nov 2022 02:57:03 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1otlNt-0008CX-Ii for qemu-devel@nongnu.org; Sat, 12 Nov 2022 02:57:03 -0500 Received: by mail-pl1-x62e.google.com with SMTP id g24so6002077plq.3 for ; Fri, 11 Nov 2022 23:57:01 -0800 (PST) Received: from stoup.lan (2001-44b8-2176-c800-8228-b676-fb42-ee07.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8228:b676:fb42:ee07]) by smtp.gmail.com with ESMTPSA id m8-20020a17090a71c800b00213d08fa459sm2743062pjs.17.2022.11.11.23.56.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Nov 2022 23:56:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uZPaYOgpXH2xCLOdQ104Ejv9oIO+hb8rMy2pf7ORzjY=; b=px694ABq8q/a6Z+wJaBZ0m7j/QEqDLn2u5UbdiP0DM9+LLKeSoaWeqr9cskhsSyg21 QQk3ZVt3peM+uTkH2gosbrKFJc+uyulLGAGj/8szS0IyUOrc15oxspACei+2y1FdTKPt Nf4u8QNQ1hJ+BKYh/TqvN8FdqJCaJDEADbQECFoKXqHhOGxunu+Fw20DxUnk/wMLOCK9 XHp3uzn2fvIIdzB41qrD+jpggQjx59/SzEL0w7uazNqNQaZHC/VWVWGTEl+69/0+DWsH z3bug2t5LEQ6pOTlIBk243GO5MDQ2N4eWpzlIHil4j4TzvwtX3H4nCLToAqOoVpSVAdl 4zqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uZPaYOgpXH2xCLOdQ104Ejv9oIO+hb8rMy2pf7ORzjY=; b=WqlhU0NqnOSPLVSw/bq1Ho+EzV9MM5/i3u9lqUmHDOCMpHg4Sq/oFF08r/hOVpJsYh Cg1podJKwCdxbaKqHnBpVjsXZ7z5li+0WoKe7X8jgiNgksgIdeL91oxxzp1i++yyUZhw MzlaHGxe1SeI3imQyIUWoahFLqPCdAImxROzgbg6Eq4tPACnjB3luf3tz7iCUYa6tnND V75flUpmNAYQWBSAm5CWfcf/IDnn1WVXNWG8aCR/8XvUP8I201MVmSFu4+9iTlHt7tAg 1vZi8ax4DAZxMMi1itX6obOJdAFfOvO7gxzhVo8sQN3QiRgpC4oTX/0aLcjynLO1sqOO XDyQ== X-Gm-Message-State: ANoB5pl4/INyqUtPiMgv0QE9Ytbk/8vqF5TwkiOGiSM0gEWbufl7mFmN UKF64wgYnbvAxskHLdovUEPw+KsbrCXUr/nE X-Google-Smtp-Source: AA0mqf6CK/0ZyYfqvstietY8m6wyIV2YcXAKCCy2nBOjE/jcxN0cv2j/aB1ZyJDs1iPY/ZyQauTR2Q== X-Received: by 2002:a17:902:7296:b0:186:e222:9f05 with SMTP id d22-20020a170902729600b00186e2229f05mr5909063pll.61.1668239820087; Fri, 11 Nov 2022 23:57:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH for-8.0 3/3] target/i386: Inline cmpxchg16b Date: Sat, 12 Nov 2022 17:56:45 +1000 Message-Id: <20221112075645.2850679-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221112075645.2850679-1-richard.henderson@linaro.org> References: <20221112075645.2850679-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668239876505100001 Content-Type: text/plain; charset="utf-8" Use tcg_gen_atomic_cmpxchg_i128 for the atomic case, and tcg_gen_qemu_ld/st_i128 otherwise. Signed-off-by: Richard Henderson --- target/i386/helper.h | 4 --- target/i386/tcg/mem_helper.c | 69 ------------------------------------ target/i386/tcg/translate.c | 44 ++++++++++++++++++++--- 3 files changed, 39 insertions(+), 78 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index 2df8049f91..e627a93107 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -66,10 +66,6 @@ DEF_HELPER_1(rsm, void, env) #endif /* !CONFIG_USER_ONLY */ =20 DEF_HELPER_2(into, void, env, int) -#ifdef TARGET_X86_64 -DEF_HELPER_2(cmpxchg16b_unlocked, void, env, tl) -DEF_HELPER_2(cmpxchg16b, void, env, tl) -#endif DEF_HELPER_FLAGS_1(single_step, TCG_CALL_NO_WG, noreturn, env) DEF_HELPER_1(rechecking_single_step, void, env) DEF_HELPER_1(cpuid, void, env) diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 814786bb87..3ef84e90d9 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -27,75 +27,6 @@ #include "tcg/tcg.h" #include "helper-tcg.h" =20 -#ifdef TARGET_X86_64 -void helper_cmpxchg16b_unlocked(CPUX86State *env, target_ulong a0) -{ - uintptr_t ra =3D GETPC(); - Int128 oldv, cmpv, newv; - uint64_t o0, o1; - int eflags; - bool success; - - if ((a0 & 0xf) !=3D 0) { - raise_exception_ra(env, EXCP0D_GPF, GETPC()); - } - eflags =3D cpu_cc_compute_all(env, CC_OP); - - cmpv =3D int128_make128(env->regs[R_EAX], env->regs[R_EDX]); - newv =3D int128_make128(env->regs[R_EBX], env->regs[R_ECX]); - - o0 =3D cpu_ldq_data_ra(env, a0 + 0, ra); - o1 =3D cpu_ldq_data_ra(env, a0 + 8, ra); - - oldv =3D int128_make128(o0, o1); - success =3D int128_eq(oldv, cmpv); - if (!success) { - newv =3D oldv; - } - - cpu_stq_data_ra(env, a0 + 0, int128_getlo(newv), ra); - cpu_stq_data_ra(env, a0 + 8, int128_gethi(newv), ra); - - if (success) { - eflags |=3D CC_Z; - } else { - env->regs[R_EAX] =3D int128_getlo(oldv); - env->regs[R_EDX] =3D int128_gethi(oldv); - eflags &=3D ~CC_Z; - } - CC_SRC =3D eflags; -} - -void helper_cmpxchg16b(CPUX86State *env, target_ulong a0) -{ - uintptr_t ra =3D GETPC(); - - if ((a0 & 0xf) !=3D 0) { - raise_exception_ra(env, EXCP0D_GPF, ra); - } else if (HAVE_CMPXCHG128) { - int eflags =3D cpu_cc_compute_all(env, CC_OP); - - Int128 cmpv =3D int128_make128(env->regs[R_EAX], env->regs[R_EDX]); - Int128 newv =3D int128_make128(env->regs[R_EBX], env->regs[R_ECX]); - - int mem_idx =3D cpu_mmu_index(env, false); - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx); - Int128 oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, a0, cmpv, newv, oi= , ra); - - if (int128_eq(oldv, cmpv)) { - eflags |=3D CC_Z; - } else { - env->regs[R_EAX] =3D int128_getlo(oldv); - env->regs[R_EDX] =3D int128_gethi(oldv); - eflags &=3D ~CC_Z; - } - CC_SRC =3D eflags; - } else { - cpu_loop_exit_atomic(env_cpu(env), ra); - } -} -#endif - void helper_boundw(CPUX86State *env, target_ulong a0, int v) { int low, high; diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index a134d63946..6dfcfaf31a 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -3034,15 +3034,49 @@ static void gen_cmpxchg8b(DisasContext *s, CPUX86St= ate *env, int modrm) #ifdef TARGET_X86_64 static void gen_cmpxchg16b(DisasContext *s, CPUX86State *env, int modrm) { + MemOp mop =3D MO_TE | MO_128 | MO_ALIGN; + TCGv_i64 t0, t1; + TCGv_i128 cmp, val; + gen_lea_modrm(env, s, modrm); =20 - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg16b(cpu_env, s->A0); + cmp =3D tcg_temp_new_i128(); + val =3D tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(cmp, cpu_regs[R_EAX], cpu_regs[R_EDX]); + tcg_gen_concat_i64_i128(val, cpu_regs[R_EBX], cpu_regs[R_ECX]); + + /* Only require atomic with LOCK; non-parallel handled in generator. */ + if (s->prefix & PREFIX_LOCK) { + tcg_gen_atomic_cmpxchg_i128(val, s->A0, cmp, val, s->mem_index, mo= p); } else { - gen_helper_cmpxchg16b_unlocked(cpu_env, s->A0); + tcg_gen_nonatomic_cmpxchg_i128(val, s->A0, cmp, val, s->mem_index,= mop); } - set_cc_op(s, CC_OP_EFLAGS); + + tcg_gen_extr_i128_i64(s->T0, s->T1, val); + tcg_temp_free_i128(cmp); + tcg_temp_free_i128(val); + + /* Determine success after the fact. */ + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + tcg_gen_xor_i64(t0, s->T0, cpu_regs[R_EAX]); + tcg_gen_xor_i64(t1, s->T1, cpu_regs[R_EDX]); + tcg_gen_or_i64(t0, t0, t1); + tcg_temp_free_i64(t1); + + /* Update Z. */ + gen_compute_eflags(s); + tcg_gen_setcondi_i64(TCG_COND_EQ, t0, t0, 0); + tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, t0, ctz32(CC_Z), 1); + tcg_temp_free_i64(t0); + + /* + * Extract the result values for the register pair. We may do this + * unconditionally, because on success (Z=3D1), the old value matches + * the previous value in RDX:RAX. + */ + tcg_gen_mov_i64(cpu_regs[R_EAX], s->T0); + tcg_gen_mov_i64(cpu_regs[R_EDX], s->T1); } #endif =20 --=20 2.34.1