From nobody Thu May 16 00:53:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1668166893; cv=none; d=zohomail.com; s=zohoarc; b=jLi4EXCBsqMyB1i1rQDfUnjlVT8ABXULb3L0+uBVd9s+7Myz0MW50Zg2f4xhzp/qFd5woTLkP6e1Kpq6rejhTAIJ1uzMniln0gevstty7cNQ89V+YKIWAtT2diiPfvtEq6e/tcVMGZHM1A4p93yHdi+DpzmHJFwTfD9cnLTBF/k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1668166893; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6M3iRFNhKVd0TwGrz26oDC6xvInu5XUK/efCOgi0W1w=; b=Ui6Lxip8MkqWUQPd9NJvYtktg5CecpKsUx1POhp1E62fTFHjfHGucpVSig4lME2fB9pzdD6v5kSSmXsJE8qf71upBf81loXKCd+tlc4fMlgqJRE9JeXYAh1YSkuP3nf3Au1qHQPOIEYE1/BR32QPr6984Ch/jCnMtf+Lwo/c1KU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1668166893403881.8710012923311; Fri, 11 Nov 2022 03:41:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1otSP7-0003ml-7x; Fri, 11 Nov 2022 06:41:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1otSP3-0003i9-5j for qemu-devel@nongnu.org; Fri, 11 Nov 2022 06:40:57 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1otSP1-000278-1F for qemu-devel@nongnu.org; Fri, 11 Nov 2022 06:40:56 -0500 Received: by mail-pl1-x632.google.com with SMTP id k7so4049413pll.6 for ; Fri, 11 Nov 2022 03:40:54 -0800 (PST) Received: from stoup.lan (2001-44b8-2176-c800-0aef-59aa-1faf-7e61.static.ipv6.internode.on.net. [2001:44b8:2176:c800:aef:59aa:1faf:7e61]) by smtp.gmail.com with ESMTPSA id e29-20020a056a0000dd00b005668b26ade0sm1393933pfj.136.2022.11.11.03.40.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Nov 2022 03:40:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6M3iRFNhKVd0TwGrz26oDC6xvInu5XUK/efCOgi0W1w=; b=A1W0PGzkAswjLT1Hj9o4Tr0u53YU2BmOmXb0QYId2BLXv/D1hDZJXHcYbdtrB23kzj ht4s+pOEbASoZFk816G9yG15Ranly4CYwVHTd4gbVbcvDUgDlsrHz4+2aiybq2lanfgK 4zS+tiPMMhrJ/ymjTxrPgpnefZZAorOzxGenGLhWHMRDzG/xZNWi2kKafQ0WEmDaYmIM XIS6bAvpmyN7LIswi0aOUlMOxfV/C7fkBRthOoDlVjHRIDbyiJvBkjqZi7ozbxGlNeDa Nf7LV9NCkshMzm0ul28zV1mBjf9s3JWs2uIjc57sfwwCZsH7KqAe2IHbFTRqUFRGdhJw zUGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6M3iRFNhKVd0TwGrz26oDC6xvInu5XUK/efCOgi0W1w=; b=usGaHBfUGlBH3MfxxvFub4r2d3YI7smK570O3GI4aA989CVzGppqgLAFuJQIpyOyNs Iw9/alURvPwn+CwlaMNtUFBjo11tths1uFswiII1RanrL9nFpAnpkvMw5bYskkwQSFA7 XDd6oJSq62h7PhdrOlxDIFXFbcuwhbhx+Y4YqNrdx9Mxk7JonBwZFf5AjWRtKxvCvqc6 B4B2VTwv/6WfBV95cr79MqeyAZ4INIJxYdVmJ9cFgB1tyjI+S0WDs83zj9GypOssjxoL hgMij40DlTkMwAi0dhunTLcEMk81UB5jrPO5OOyzqEjemzjOICkHMrMPNSVRs7O+t5Cs TngQ== X-Gm-Message-State: ANoB5pl0D1d2ehqKyTRIeDY88/4Tk8iNGPyfTUzhQK3xXxtuf0omn5FS u1zmUpZ5hlpXXZUTjGunZC5GDzvP7JU/siZq X-Google-Smtp-Source: AA0mqf7/5Z0sEtxLbzD+X1AJ3DjyNUtXy4GsmHgXWAP3xu1CrvOqA4bbcKbpKNKPeLQit8L9atIo8Q== X-Received: by 2002:a17:903:41d0:b0:188:5e78:be0 with SMTP id u16-20020a17090341d000b001885e780be0mr2224882ple.18.1668166853578; Fri, 11 Nov 2022 03:40:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Paolo Bonzini Subject: [PATCH for-7.2 1/2] target/i386: fix cmpxchg with 32-bit register destination Date: Fri, 11 Nov 2022 21:40:43 +1000 Message-Id: <20221111114044.2510256-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111114044.2510256-1-richard.henderson@linaro.org> References: <20221111114044.2510256-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668166895000100001 Content-Type: text/plain; charset="utf-8" From: Paolo Bonzini Unlike the memory case, where "the destination operand receives a write cycle without regard to the result of the comparison", rm must not be touched altogether if the write fails, including not zero-extending it on 64-bit processors. This is not how the movcond currently works, because it is always followed by a gen_op_mov_reg_v to rm. To fix it, introduce a new function that is similar to gen_op_mov_reg_v but writes to a TCG temporary. Considering that gen_extu(ot, oldv) is not needed in the memory case either, the two cases for register and memory destinations are different enough that one might as well fuse the two "if (mod =3D=3D 3)" into one. So do that too. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/508 Signed-off-by: Paolo Bonzini [rth: Add a test case ] Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 82 ++++++++++++++++++++++---------- tests/tcg/x86_64/cmpxchg.c | 42 ++++++++++++++++ tests/tcg/x86_64/Makefile.target | 1 + 3 files changed, 99 insertions(+), 26 deletions(-) create mode 100644 tests/tcg/x86_64/cmpxchg.c diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 28a4e6dc1d..dbd6492778 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -439,32 +439,51 @@ static inline MemOp mo_b_d32(int b, MemOp ot) return b & 1 ? (ot =3D=3D MO_16 ? MO_16 : MO_32) : MO_8; } =20 -static void gen_op_mov_reg_v(DisasContext *s, MemOp ot, int reg, TCGv t0) +/* Compute the result of writing t0 to the OT-sized register REG. + * + * If DEST is NULL, store the result into the register and return the + * register's TCGv. + * + * If DEST is not NULL, store the result into DEST and return the + * register's TCGv. + */ +static TCGv gen_op_deposit_reg_v(DisasContext *s, MemOp ot, int reg, TCGv = dest, TCGv t0) { switch(ot) { case MO_8: - if (!byte_reg_is_xH(s, reg)) { - tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8); - } else { - tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8= , 8); + if (byte_reg_is_xH(s, reg)) { + dest =3D dest ? dest : cpu_regs[reg - 4]; + tcg_gen_deposit_tl(dest, cpu_regs[reg - 4], t0, 8, 8); + return cpu_regs[reg - 4]; } + dest =3D dest ? dest : cpu_regs[reg]; + tcg_gen_deposit_tl(dest, cpu_regs[reg], t0, 0, 8); break; case MO_16: - tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16); + dest =3D dest ? dest : cpu_regs[reg]; + tcg_gen_deposit_tl(dest, cpu_regs[reg], t0, 0, 16); break; case MO_32: /* For x86_64, this sets the higher half of register to zero. For i386, this is equivalent to a mov. */ - tcg_gen_ext32u_tl(cpu_regs[reg], t0); + dest =3D dest ? dest : cpu_regs[reg]; + tcg_gen_ext32u_tl(dest, t0); break; #ifdef TARGET_X86_64 case MO_64: - tcg_gen_mov_tl(cpu_regs[reg], t0); + dest =3D dest ? dest : cpu_regs[reg]; + tcg_gen_mov_tl(dest, t0); break; #endif default: tcg_abort(); } + return cpu_regs[reg]; +} + +static void gen_op_mov_reg_v(DisasContext *s, MemOp ot, int reg, TCGv t0) +{ + gen_op_deposit_reg_v(s, ot, reg, NULL, t0); } =20 static inline @@ -3747,7 +3766,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) case 0x1b0: case 0x1b1: /* cmpxchg Ev, Gv */ { - TCGv oldv, newv, cmpv; + TCGv oldv, newv, cmpv, dest; =20 ot =3D mo_b_d(b, dflag); modrm =3D x86_ldub_code(env, s); @@ -3758,7 +3777,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) cmpv =3D tcg_temp_new(); gen_op_mov_v_reg(s, ot, newv, reg); tcg_gen_mov_tl(cmpv, cpu_regs[R_EAX]); - + gen_extu(ot, cmpv); if (s->prefix & PREFIX_LOCK) { if (mod =3D=3D 3) { goto illegal_op; @@ -3766,32 +3785,43 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) gen_lea_modrm(env, s, modrm); tcg_gen_atomic_cmpxchg_tl(oldv, s->A0, cmpv, newv, s->mem_index, ot | MO_LE); - gen_op_mov_reg_v(s, ot, R_EAX, oldv); } else { if (mod =3D=3D 3) { rm =3D (modrm & 7) | REX_B(s); gen_op_mov_v_reg(s, ot, oldv, rm); + gen_extu(ot, oldv); + + /* + * Unlike the memory case, where "the destination oper= and receives + * a write cycle without regard to the result of the c= omparison", + * rm must not be touched altogether if the write fail= s, including + * not zero-extending it on 64-bit processors. So, pr= ecompute + * the result of a successful writeback and perform th= e movcond + * directly on cpu_regs. Also need to write accumulat= or first, in + * case rm is part of RAX too. + */ + dest =3D gen_op_deposit_reg_v(s, ot, rm, newv, newv); + tcg_gen_movcond_tl(TCG_COND_EQ, dest, oldv, cmpv, newv= , dest); } else { gen_lea_modrm(env, s, modrm); gen_op_ld_v(s, ot, oldv, s->A0); - rm =3D 0; /* avoid warning */ - } - gen_extu(ot, oldv); - gen_extu(ot, cmpv); - /* store value =3D (old =3D=3D cmp ? new : old); */ - tcg_gen_movcond_tl(TCG_COND_EQ, newv, oldv, cmpv, newv, ol= dv); - if (mod =3D=3D 3) { - gen_op_mov_reg_v(s, ot, R_EAX, oldv); - gen_op_mov_reg_v(s, ot, rm, newv); - } else { - /* Perform an unconditional store cycle like physical = cpu; - must be before changing accumulator to ensure - idempotency if the store faults and the instruction - is restarted */ + + /* + * Perform an unconditional store cycle like physical = cpu; + * must be before changing accumulator to ensure + * idempotency if the store faults and the instruction + * is restarted + */ + tcg_gen_movcond_tl(TCG_COND_EQ, newv, oldv, cmpv, newv= , oldv); gen_op_st_v(s, ot, newv, s->A0); - gen_op_mov_reg_v(s, ot, R_EAX, oldv); } } + /* + * Write EAX only if the cmpxchg fails; reuse newv as the destination, + * since it's dead here. + */ + dest =3D gen_op_deposit_reg_v(s, ot, R_EAX, newv, oldv); + tcg_gen_movcond_tl(TCG_COND_EQ, dest, oldv, cmpv, dest, newv); tcg_gen_mov_tl(cpu_cc_src, oldv); tcg_gen_mov_tl(s->cc_srcT, cmpv); tcg_gen_sub_tl(cpu_cc_dst, cmpv, oldv); diff --git a/tests/tcg/x86_64/cmpxchg.c b/tests/tcg/x86_64/cmpxchg.c new file mode 100644 index 0000000000..5891735161 --- /dev/null +++ b/tests/tcg/x86_64/cmpxchg.c @@ -0,0 +1,42 @@ +#include + +static int mem; + +static unsigned long test_cmpxchgb(unsigned long orig) +{ + unsigned long ret; + mem =3D orig; + asm("cmpxchgb %b[cmp],%[mem]" + : [ mem ] "+m"(mem), [ rax ] "=3Da"(ret) + : [ cmp ] "r"(0x77), "a"(orig)); + return ret; +} + +static unsigned long test_cmpxchgw(unsigned long orig) +{ + unsigned long ret; + mem =3D orig; + asm("cmpxchgw %w[cmp],%[mem]" + : [ mem ] "+m"(mem), [ rax ] "=3Da"(ret) + : [ cmp ] "r"(0x7777), "a"(orig)); + return ret; +} + +static unsigned long test_cmpxchgl(unsigned long orig) +{ + unsigned long ret; + mem =3D orig; + asm("cmpxchgl %[cmp],%[mem]" + : [ mem ] "+m"(mem), [ rax ] "=3Da"(ret) + : [ cmp ] "r"(0x77777777u), "a"(orig)); + return ret; +} + +int main() +{ + unsigned long test =3D 0xdeadbeef12345678ull; + assert(test =3D=3D test_cmpxchgb(test)); + assert(test =3D=3D test_cmpxchgw(test)); + assert(test =3D=3D test_cmpxchgl(test)); + return 0; +} diff --git a/tests/tcg/x86_64/Makefile.target b/tests/tcg/x86_64/Makefile.t= arget index 6895db1c43..4eac78293f 100644 --- a/tests/tcg/x86_64/Makefile.target +++ b/tests/tcg/x86_64/Makefile.target @@ -11,6 +11,7 @@ include $(SRC_PATH)/tests/tcg/i386/Makefile.target ifeq ($(filter %-linux-user, $(TARGET)),$(TARGET)) X86_64_TESTS +=3D vsyscall X86_64_TESTS +=3D noexec +X86_64_TESTS +=3D cmpxchg TESTS=3D$(MULTIARCH_TESTS) $(X86_64_TESTS) test-x86_64 else TESTS=3D$(MULTIARCH_TESTS) --=20 2.34.1 From nobody Thu May 16 00:53:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1668166895; cv=none; d=zohomail.com; s=zohoarc; b=NDuDtklaK9Pi8BCnVaQnVSAJWORvxSa3F81fNrCuC07EfXFVUHq+7q2JzSmqGRYBj9jGKyFjbTMCj+3IJIMaVvBvLSWUppQS0k7l3yJbNC0/VZd7v82OMJfJd98TC8Uq+Az8t371vRG10Q+bDBjO8LXiw2c6FAl0IX75sMs6hj4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1668166895; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HIjPHkRH18chkLBXKE8P4bOXjlUnO+BcLL5w7iG1TVY=; b=iCjbFRD8XQaD0zCdoemB8xEbFwmW46GNedHDQ0CGp3C3BGlYP+pUBKYyw9Pa80WgM75yYe+6qys07eBOmCTSZu2hq5WPN1OWFpQwdiS5XFdGP46c3yvKjvzUBffxam8af0s09cP632jiGKPZRZyjfS76mEZQB1TtdpdGuFKxPos= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1668166895044343.9344996750731; Fri, 11 Nov 2022 03:41:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1otSP9-0003pa-6O; Fri, 11 Nov 2022 06:41:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1otSP7-0003mw-D7 for qemu-devel@nongnu.org; Fri, 11 Nov 2022 06:41:01 -0500 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1otSP3-00027K-SE for qemu-devel@nongnu.org; Fri, 11 Nov 2022 06:40:59 -0500 Received: by mail-pf1-x430.google.com with SMTP id z26so4703640pff.1 for ; Fri, 11 Nov 2022 03:40:57 -0800 (PST) Received: from stoup.lan (2001-44b8-2176-c800-0aef-59aa-1faf-7e61.static.ipv6.internode.on.net. [2001:44b8:2176:c800:aef:59aa:1faf:7e61]) by smtp.gmail.com with ESMTPSA id e29-20020a056a0000dd00b005668b26ade0sm1393933pfj.136.2022.11.11.03.40.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Nov 2022 03:40:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HIjPHkRH18chkLBXKE8P4bOXjlUnO+BcLL5w7iG1TVY=; b=DYmCcan0eU1LjY6PFMYcSNEK4CKdYBQOpam1+8iLRDjZxvWmG+lKxqjvsROdIWhfvO MJOAv0Fe+krlMJj/5/xYqqHAK/zRX305f9EXlKdzTS339kNzyNHw8Ci69dkdvn7mpMlE IoIDVN6ur+XYbeNdwKreNDOSiyhrd7qr4ZatwmP1CSXamiPLoTqaqlvEOu8TD5rU2GYX Hw3S6YhOKHfjKkqZrt2DvCc9lpiOqyK6s9vlJPwcSstV95tX0o6eRwDljVU2Ll8Jl9UX J6V73Nz+64rJTSTsuJb94d3To+I/ciTKhPLMHsVXCVw522xTGgiwqt960Pa9VsTDR3wg hVvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HIjPHkRH18chkLBXKE8P4bOXjlUnO+BcLL5w7iG1TVY=; b=PEgjfOIUg/cuoGdClLqmg85381z/2gpErN/Aq8wdwqDFfDqfZz8xRiPRE5aOZDnui7 DvHQWFe6Dkvj0qwB1Vqp1sSxC/0AWw6Ah4ktBEh0JcIZdw7cSxMSLNSKKcMNhbFV7vgr 011eV7tjxDcKkgIzblMB5v8dE1g4PQARb+/iKFQ1lIwM1CPmvx/vBl6rrbmKJI4fpiWc yA3kDKVME/a6XEKMvPfQnzrMpFJvnv/Yh0oxNaxgMTT+oZEg4vL/ecS+yJ2uWDVajq4D HRZCZdIImnkpF/zWCXvVn8DgZRlfDsSf20VpyRo9yyD6RczoKi1rlbgaeES0EnWuSfGV WYVA== X-Gm-Message-State: ANoB5pm0v3bskoJN2s9uWbGaYhL566G1JxueDIfSfeavad7mu9tDsjvK FFP4GkZwAYOvb3KFZ5Cq0ev0tPwt/D0taZcz X-Google-Smtp-Source: AA0mqf4ONaiYT7GKRS6/iqFGcvWbey9OwqsKjGWdApJrAKzPXL5Uad2xm73S5ByvTJ0UnVdeYIeGqQ== X-Received: by 2002:a63:4d1c:0:b0:462:e0d0:2582 with SMTP id a28-20020a634d1c000000b00462e0d02582mr1331099pgb.48.1668166856057; Fri, 11 Nov 2022 03:40:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Paolo Bonzini Subject: [PATCH for-7.2 2/2] target/i386: hardcode R_EAX as destination register for LAHF/SAHF Date: Fri, 11 Nov 2022 21:40:44 +1000 Message-Id: <20221111114044.2510256-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111114044.2510256-1-richard.henderson@linaro.org> References: <20221111114044.2510256-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668166896863100005 Content-Type: text/plain; charset="utf-8" From: Paolo Bonzini When translating code that is using LAHF and SAHF in combination with the REX prefix, the instructions should not use any other register than AH; however, QEMU selects SPL (SP being register 4, just like AH) if the REX prefix is present. To fix this, use deposit directly without going through gen_op_mov_v_reg and gen_op_mov_reg_v. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/130 Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index dbd6492778..7e0b2a709a 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -5230,7 +5230,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) case 0x9e: /* sahf */ if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) goto illegal_op; - gen_op_mov_v_reg(s, MO_8, s->T0, R_AH); + tcg_gen_shri_tl(s->T0, cpu_regs[R_EAX], 8); gen_compute_eflags(s); tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O); tcg_gen_andi_tl(s->T0, s->T0, CC_S | CC_Z | CC_A | CC_P | CC_C); @@ -5242,7 +5242,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_compute_eflags(s); /* Note: gen_compute_eflags() only gives the condition codes */ tcg_gen_ori_tl(s->T0, cpu_cc_src, 0x02); - gen_op_mov_reg_v(s, MO_8, R_AH, s->T0); + tcg_gen_deposit_tl(cpu_regs[R_EAX], cpu_regs[R_EAX], s->T0, 8, 8); break; case 0xf5: /* cmc */ gen_compute_eflags(s); --=20 2.34.1