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[219.106.231.132]) by smtp.gmail.com with ESMTPSA id g139-20020a625291000000b0056d2797bf05sm3478385pfb.217.2022.10.31.01.46.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 01:46:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=igel-co-jp.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=4NC4CbXNET7QgKVIkEBX2g1Hrhwce2DSB/31NQyzbcs=; b=1hhwDUqKUQAV2Qk9F9ttMxXYnXky+Wl7FQkFWWE2SyhWrJ6IdUzGafxkSlIyc82hL7 I3zebG2xJDYo2JkOgOB8T+68HOBXD93iMYEm5EvlWwg7Qa0EHpQfEC+gHO0RoagBnbLe MfEmuj0FyhLksPTk2DKIOGyNA3lZzA5nTSU6w8tYuQEdq9GgVkkFfQMRSpTLcQoYs+0s P1mbDI/6Gnf220/1mFfHu5U5qyKTji5EvIgz5jLP3tvelqHEvkJnu3E0YCt5BNctPVMW cV02vovH7Lgnuxl1OTf0A8g8QxYBdj7VaPzyBEUOl9Hei03i5PouZZEjznjg1YnsmITI NgNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=4NC4CbXNET7QgKVIkEBX2g1Hrhwce2DSB/31NQyzbcs=; b=vGP54p9S4EI37ZFijUGk1huiPtNp6ihxvSBDfglF6Huar8qLPvJrATtcAhZoOuzKlf UqjSc9y8gbaGmf+zhg5udDoDO93jagTmBWyrG76WagPj5hAGPIV/7x9MBSR+B76x81S9 8l9nl5O3SPteNN6uLV/3XUiBuASkynlNNftAB4gEBWwpnFmYZTsw0LuzjGF/QpQN8Y8H 9plBuPOQoSkwMjlXJUp9TgcpVO38j7v8S4hgL7GkjazyYDTYVnULLw4rFpecUcDq0gs2 9+J9+Omvmv4V3bWWu3ahySSyAM3Xktpz0B8F916JdwKGiFbko32slCeHUr71Hk4lai8D Eb1A== X-Gm-Message-State: ACrzQf365Vy3tROFUEZvBi+1EwTLQBGDnrd2n17iDngEVI7mzKVdwQic qta2l+E5B9wfq40iPKDjx0nBWS7dA1pRMw== X-Google-Smtp-Source: AMsMyM6qZkl8oydeFTBRUUBL7h7HegoImY1+Odm0gRWHK4n2pHGbx3m6JxfMtGRxpYCd0xEUIT7abQ== X-Received: by 2002:a17:902:e54e:b0:187:ba9:4305 with SMTP id n14-20020a170902e54e00b001870ba94305mr10012405plf.167.1667205963312; Mon, 31 Oct 2022 01:46:03 -0700 (PDT) From: Ake Koomsin To: qemu-devel@nongnu.org Cc: Ake Koomsin , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v2] target/arm: honor HCR_E2H and HCR_TGE in ats_write64() Date: Mon, 31 Oct 2022 17:43:25 +0900 Message-Id: <20221031084324.844220-1-ake@igel.co.jp> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=ake@igel.co.jp; helo=mail-pl1-x633.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @igel-co-jp.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667206059028100003 Content-Type: text/plain; charset="utf-8" We need to check HCR_E2H and HCR_TGE to select the right MMU index for the correct translation regime. To check for EL2&0 translation regime: - For S1E0*, S1E1* and S12E* ops, check both HCR_E2H and HCR_TGE - For S1E2* ops, check only HCR_E2H Signed-off-by: Ake Koomsin --- v2: - Rebase with the latest upstream - It turns out that we need to check both HCR_E2H and HCR_TGE for S1E0*, S1E1* and S12E* address translation as well according to the Architecture Manual. v1: https://lists.gnu.org/archive/html/qemu-devel/2022-10/msg02627.html target/arm/helper.c | 38 ++++++++++++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b070a20f1a..f7b988395a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3501,19 +3501,33 @@ static void ats_write64(CPUARMState *env, const ARM= CPRegInfo *ri, MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; ARMMMUIdx mmu_idx; int secure =3D arm_is_secure_below_el3(env); + bool regime_e20 =3D (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) =3D= =3D + (HCR_E2H | HCR_TGE); =20 switch (ri->opc2 & 6) { case 0: switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ if (ri->crm =3D=3D 9 && (env->pstate & PSTATE_PAN)) { - mmu_idx =3D ARMMMUIdx_Stage1_E1_PAN; + if (regime_e20) { + mmu_idx =3D ARMMMUIdx_E20_2_PAN; + } else { + mmu_idx =3D ARMMMUIdx_Stage1_E1_PAN; + } } else { - mmu_idx =3D ARMMMUIdx_Stage1_E1; + if (regime_e20) { + mmu_idx =3D ARMMMUIdx_E20_2; + } else { + mmu_idx =3D ARMMMUIdx_Stage1_E1; + } } break; case 4: /* AT S1E2R, AT S1E2W */ - mmu_idx =3D ARMMMUIdx_E2; + if ((arm_hcr_el2_eff(env) & HCR_E2H) =3D=3D HCR_E2H) { + mmu_idx =3D ARMMMUIdx_E20_2; + } else { + mmu_idx =3D ARMMMUIdx_E2; + } break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx =3D ARMMMUIdx_E3; @@ -3524,13 +3538,25 @@ static void ats_write64(CPUARMState *env, const ARM= CPRegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx =3D ARMMMUIdx_Stage1_E0; + if (regime_e20) { + mmu_idx =3D ARMMMUIdx_E20_0; + } else { + mmu_idx =3D ARMMMUIdx_Stage1_E0; + } break; case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx =3D ARMMMUIdx_E10_1; + if (regime_e20) { + mmu_idx =3D ARMMMUIdx_E20_2; + } else { + mmu_idx =3D ARMMMUIdx_E10_1; + } break; case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx =3D ARMMMUIdx_E10_0; + if (regime_e20) { + mmu_idx =3D ARMMMUIdx_E20_0; + } else { + mmu_idx =3D ARMMMUIdx_E10_0; + } break; default: g_assert_not_reached(); --=20 2.25.1