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([172.58.176.235]) by smtp.gmail.com with ESMTPSA id u8-20020a9d4d88000000b006618586b850sm2473857otk.46.2022.10.30.22.40.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 22:40:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EMqq6JpAdSiINrhh1Op3DHiRWmeRId7cbYbvtmcfq9o=; b=O+sbb6jCLsmz3q4jD7nr9WKS7rorogyAaUegSS8yOJJ3e86AeL4LK0tKSDVGxaaNdh BapBiCNKA7xwW4gX7gIYV7TmvjP2OHZXoVnBvZYkZ6m9ODI0hwglUMSkeWCjhwkwG+Mi +vRtx76m8RlK9Ceojt3eolIqx2o0vZn+nvhZckZvRYWbTG6KJE3b0VdBsHemruk6L1lJ ohC1w4+ruG1ybrZ6rWXcbe6g6ZM3PVYRPseDNSPTck0bHAkhkGyy2SAK7Zl1l6ro+8dO 9d8JlDhwPfkMWkJ9y9J1YDlA6BEOTUSF604QBJUEp97V3xQ1Bl1iJuzBVlumA0o3Ojwb iShQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EMqq6JpAdSiINrhh1Op3DHiRWmeRId7cbYbvtmcfq9o=; b=kcHA24mti6x7Hk4Hi07R4+pl3MaHl4YvQQrmipZP/V0PnnhfkwSuzQvtUZ2k3A+N0A POpMM4EaifP5IB9yI+dLXhgW/b3PMnKJz/cef7UE4TLQF2rLRB65QjP+B1Ro196TnmKv V8UOzd/uvkfKH0NozEmYK6PU9NrUqDae6n7WAmOo4AssWvMQ2gF2FWxzHV20cEin3K2H 7+TiUD9/E6URIkaSh5Lv1xLs3zqAtSRFGJvuqX+Dy3jQFRKU5URwbcAOzd8lKWPNYKhr B5TdeWxBAf4ArYKw9DT5OWe1Sv/NogVn9f9EyuUFqKhp7lrzh+CtdOLIKpwE8soqroYj VNww== X-Gm-Message-State: ACrzQf0kg9o3Ow6qeCH5OhJtfoFR6jdNXel6492hgmLa+DYM8egGhRMj WBL4GQI0438loc4i8kV3HXLNZlXCX86WYw== X-Google-Smtp-Source: AMsMyM4wTy2uDuzf1+6K3Td77axnepb1xdOuOMXt88N8WfNr7gat8NiFU5kZXT2yMJbhL6pKoL82Zg== X-Received: by 2002:a05:6808:1889:b0:359:ad66:d42a with SMTP id bi9-20020a056808188900b00359ad66d42amr13032173oib.227.1667194805959; Sun, 30 Oct 2022 22:40:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 01/11] tcg/sparc: Remove support for sparc32plus Date: Mon, 31 Oct 2022 16:39:38 +1100 Message-Id: <20221031053948.3408-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221031053948.3408-1-richard.henderson@linaro.org> References: <20221031053948.3408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1667194992379100001 Since 9b9c37c36439, we have only supported sparc64 cpus. Debian and Gentoo now only support 64-bit sparc64 userland, so it is time to drop the 32-bit sparc64 userland: sparc32plus. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.h | 11 --- tcg/tcg.c | 75 +---------------- tcg/sparc/tcg-target.c.inc | 166 +++++++------------------------------ 3 files changed, 33 insertions(+), 219 deletions(-) diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index c050763049..8655acdbe5 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -25,8 +25,6 @@ #ifndef SPARC_TCG_TARGET_H #define SPARC_TCG_TARGET_H =20 -#define TCG_TARGET_REG_BITS 64 - #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 #define TCG_TARGET_NB_REGS 32 @@ -70,19 +68,10 @@ typedef enum { /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_O6 =20 -#ifdef __arch64__ #define TCG_TARGET_STACK_BIAS 2047 #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_CALL_STACK_OFFSET (128 + 6*8 + TCG_TARGET_STACK_BIAS) -#else -#define TCG_TARGET_STACK_BIAS 0 -#define TCG_TARGET_STACK_ALIGN 8 -#define TCG_TARGET_CALL_STACK_OFFSET (64 + 4 + 6*4) -#endif - -#ifdef __arch64__ #define TCG_TARGET_EXTEND_ARGS 1 -#endif =20 #if defined(__VIS__) && __VIS__ >=3D 0x300 #define use_vis3_instructions 1 diff --git a/tcg/tcg.c b/tcg/tcg.c index 612a12f58f..c9e664ee31 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1487,39 +1487,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nar= gs, TCGTemp **args) } #endif =20 -#if defined(__sparc__) && !defined(__arch64__) \ - && !defined(CONFIG_TCG_INTERPRETER) - /* We have 64-bit values in one register, but need to pass as two - separate parameters. Split them. */ - int orig_typemask =3D typemask; - int orig_nargs =3D nargs; - TCGv_i64 retl, reth; - TCGTemp *split_args[MAX_OPC_PARAM]; - - retl =3D NULL; - reth =3D NULL; - typemask =3D 0; - for (i =3D real_args =3D 0; i < nargs; ++i) { - int argtype =3D extract32(orig_typemask, (i + 1) * 3, 3); - bool is_64bit =3D (argtype & ~1) =3D=3D dh_typecode_i64; - - if (is_64bit) { - TCGv_i64 orig =3D temp_tcgv_i64(args[i]); - TCGv_i32 h =3D tcg_temp_new_i32(); - TCGv_i32 l =3D tcg_temp_new_i32(); - tcg_gen_extr_i64_i32(l, h, orig); - split_args[real_args++] =3D tcgv_i32_temp(h); - typemask |=3D dh_typecode_i32 << (real_args * 3); - split_args[real_args++] =3D tcgv_i32_temp(l); - typemask |=3D dh_typecode_i32 << (real_args * 3); - } else { - split_args[real_args++] =3D args[i]; - typemask |=3D argtype << (real_args * 3); - } - } - nargs =3D real_args; - args =3D split_args; -#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS =3D=3D 64 +#if defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS =3D=3D 64 for (i =3D 0; i < nargs; ++i) { int argtype =3D extract32(typemask, (i + 1) * 3, 3); bool is_32bit =3D (argtype & ~1) =3D=3D dh_typecode_i32; @@ -1542,22 +1510,6 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nar= gs, TCGTemp **args) =20 pi =3D 0; if (ret !=3D NULL) { -#if defined(__sparc__) && !defined(__arch64__) \ - && !defined(CONFIG_TCG_INTERPRETER) - if ((typemask & 6) =3D=3D dh_typecode_i64) { - /* The 32-bit ABI is going to return the 64-bit value in - the %o0/%o1 register pair. Prepare for this by using - two return temporaries, and reassemble below. */ - retl =3D tcg_temp_new_i64(); - reth =3D tcg_temp_new_i64(); - op->args[pi++] =3D tcgv_i64_arg(reth); - op->args[pi++] =3D tcgv_i64_arg(retl); - nb_rets =3D 2; - } else { - op->args[pi++] =3D temp_arg(ret); - nb_rets =3D 1; - } -#else if (TCG_TARGET_REG_BITS < 64 && (typemask & 6) =3D=3D dh_typecode_= i64) { #if HOST_BIG_ENDIAN op->args[pi++] =3D temp_arg(ret + 1); @@ -1571,7 +1523,6 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int narg= s, TCGTemp **args) op->args[pi++] =3D temp_arg(ret); nb_rets =3D 1; } -#endif } else { nb_rets =3D 0; } @@ -1634,29 +1585,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nar= gs, TCGTemp **args) tcg_debug_assert(TCGOP_CALLI(op) =3D=3D real_args); tcg_debug_assert(pi <=3D ARRAY_SIZE(op->args)); =20 -#if defined(__sparc__) && !defined(__arch64__) \ - && !defined(CONFIG_TCG_INTERPRETER) - /* Free all of the parts we allocated above. */ - for (i =3D real_args =3D 0; i < orig_nargs; ++i) { - int argtype =3D extract32(orig_typemask, (i + 1) * 3, 3); - bool is_64bit =3D (argtype & ~1) =3D=3D dh_typecode_i64; - - if (is_64bit) { - tcg_temp_free_internal(args[real_args++]); - tcg_temp_free_internal(args[real_args++]); - } else { - real_args++; - } - } - if ((orig_typemask & 6) =3D=3D dh_typecode_i64) { - /* The 32-bit ABI returned two 32-bit pieces. Re-assemble them. - Note that describing these as TCGv_i64 eliminates an unnecessary - zero-extension that tcg_gen_concat_i32_i64 would create. */ - tcg_gen_concat32_i64(temp_tcgv_i64(ret), retl, reth); - tcg_temp_free_i64(retl); - tcg_temp_free_i64(reth); - } -#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS =3D=3D 64 +#if defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS =3D=3D 64 for (i =3D 0; i < nargs; ++i) { int argtype =3D extract32(typemask, (i + 1) * 3, 3); bool is_32bit =3D (argtype & ~1) =3D=3D dh_typecode_i32; diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 72d9552fd0..097bcfcd12 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -22,6 +22,11 @@ * THE SOFTWARE. */ =20 +/* We only support generating code for 64-bit mode. */ +#ifndef __arch64__ +#error "unsupported code generation mode" +#endif + #include "../tcg-pool.c.inc" =20 #ifdef CONFIG_DEBUG_TCG @@ -61,12 +66,6 @@ static const char * const tcg_target_reg_names[TCG_TARGE= T_NB_REGS] =3D { }; #endif =20 -#ifdef __arch64__ -# define SPARC64 1 -#else -# define SPARC64 0 -#endif - #define TCG_CT_CONST_S11 0x100 #define TCG_CT_CONST_S13 0x200 #define TCG_CT_CONST_ZERO 0x400 @@ -91,11 +90,7 @@ static const char * const tcg_target_reg_names[TCG_TARGE= T_NB_REGS] =3D { * high bits of the %i and %l registers garbage at all times. */ #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) -#if SPARC64 # define ALL_GENERAL_REGS64 ALL_GENERAL_REGS -#else -# define ALL_GENERAL_REGS64 MAKE_64BIT_MASK(0, 16) -#endif #define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) #define ALL_QLDST_REGS64 (ALL_GENERAL_REGS64 & ~SOFTMMU_RESERVE_REGS) =20 @@ -306,11 +301,7 @@ static bool check_fit_i32(int32_t val, unsigned int bi= ts) } =20 #define check_fit_tl check_fit_i64 -#if SPARC64 -# define check_fit_ptr check_fit_i64 -#else -# define check_fit_ptr check_fit_i32 -#endif +#define check_fit_ptr check_fit_i64 =20 static bool patch_reloc(tcg_insn_unit *src_rw, int type, intptr_t value, intptr_t addend) @@ -573,11 +564,6 @@ static void tcg_out_sety(TCGContext *s, TCGReg rs) tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs)); } =20 -static void tcg_out_rdy(TCGContext *s, TCGReg rd) -{ - tcg_out32(s, RDY | INSN_RD(rd)); -} - static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1, int32_t val2, int val2const, int uns) { @@ -914,9 +900,7 @@ static void emit_extend(TCGContext *s, TCGReg r, int op) tcg_out_arithi(s, r, r, 16, SHIFT_SRL); break; case MO_32: - if (SPARC64) { - tcg_out_arith(s, r, r, 0, SHIFT_SRL); - } + tcg_out_arith(s, r, r, 0, SHIFT_SRL); break; case MO_64: break; @@ -948,7 +932,6 @@ static void build_trampolines(TCGContext *s) }; =20 int i; - TCGReg ra; =20 for (i =3D 0; i < ARRAY_SIZE(qemu_ld_helpers); ++i) { if (qemu_ld_helpers[i] =3D=3D NULL) { @@ -961,16 +944,8 @@ static void build_trampolines(TCGContext *s) } qemu_ld_trampoline[i] =3D tcg_splitwx_to_rx(s->code_ptr); =20 - if (SPARC64 || TARGET_LONG_BITS =3D=3D 32) { - ra =3D TCG_REG_O3; - } else { - /* Install the high part of the address. */ - tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O2, 32, SHIFT_SRLX); - ra =3D TCG_REG_O4; - } - /* Set the retaddr operand. */ - tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O3, TCG_REG_O7); /* Tail call. */ tcg_out_jmpl_const(s, qemu_ld_helpers[i], true, true); /* delay slot -- set the env argument */ @@ -988,37 +963,10 @@ static void build_trampolines(TCGContext *s) } qemu_st_trampoline[i] =3D tcg_splitwx_to_rx(s->code_ptr); =20 - if (SPARC64) { - emit_extend(s, TCG_REG_O2, i); - ra =3D TCG_REG_O4; - } else { - ra =3D TCG_REG_O1; - if (TARGET_LONG_BITS =3D=3D 64) { - /* Install the high part of the address. */ - tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX); - ra +=3D 2; - } else { - ra +=3D 1; - } - if ((i & MO_SIZE) =3D=3D MO_64) { - /* Install the high part of the data. */ - tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX); - ra +=3D 2; - } else { - emit_extend(s, ra, i); - ra +=3D 1; - } - /* Skip the oi argument. */ - ra +=3D 1; - } - =20 + emit_extend(s, TCG_REG_O2, i); + /* Set the retaddr operand. */ - if (ra >=3D TCG_REG_O6) { - tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK, - TCG_TARGET_CALL_STACK_OFFSET); - } else { - tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); - } + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O4, TCG_REG_O7); =20 /* Tail call. */ tcg_out_jmpl_const(s, qemu_st_helpers[i], true, true); @@ -1047,11 +995,6 @@ static void build_trampolines(TCGContext *s) qemu_unalign_st_trampoline =3D tcg_splitwx_to_rx(s->code_ptr); } =20 - if (!SPARC64 && TARGET_LONG_BITS =3D=3D 64) { - /* Install the high part of the address. */ - tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O2, 32, SHIFT_SRLX); - } - /* Tail call. */ tcg_out_jmpl_const(s, helper, true, true); /* delay slot -- set the env argument */ @@ -1182,7 +1125,7 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg = addr, int mem_index, tcg_out_cmp(s, r0, r2, 0); =20 /* If the guest address must be zero-extended, do so now. */ - if (SPARC64 && TARGET_LONG_BITS =3D=3D 32) { + if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_arithi(s, r0, addr, 0, SHIFT_SRL); return r0; } @@ -1231,7 +1174,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a, TCGReg addr, =20 #ifdef CONFIG_SOFTMMU unsigned memi =3D get_mmuidx(oi); - TCGReg addrz, param; + TCGReg addrz; const tcg_insn_unit *func; =20 addrz =3D tcg_out_tlb_load(s, addr, memi, memop, @@ -1251,12 +1194,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg da= ta, TCGReg addr, =20 /* TLB Miss. */ =20 - param =3D TCG_REG_O1; - if (!SPARC64 && TARGET_LONG_BITS =3D=3D 64) { - /* Skip the high-part; we'll perform the extract in the trampoline= . */ - param++; - } - tcg_out_mov(s, TCG_TYPE_REG, param++, addrz); + tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_O1, addrz); =20 /* We use the helpers to extend SB and SW data, leaving the case of SL needing explicit extending below. */ @@ -1268,30 +1206,13 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= ata, TCGReg addr, tcg_debug_assert(func !=3D NULL); tcg_out_call_nodelay(s, func, false); /* delay slot */ - tcg_out_movi(s, TCG_TYPE_I32, param, oi); + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_O2, oi); =20 - /* Recall that all of the helpers return 64-bit results. - Which complicates things for sparcv8plus. */ - if (SPARC64) { - /* We let the helper sign-extend SB and SW, but leave SL for here.= */ - if (is_64 && (memop & MO_SSIZE) =3D=3D MO_SL) { - tcg_out_arithi(s, data, TCG_REG_O0, 0, SHIFT_SRA); - } else { - tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0); - } + /* We let the helper sign-extend SB and SW, but leave SL for here. */ + if (is_64 && (memop & MO_SSIZE) =3D=3D MO_SL) { + tcg_out_arithi(s, data, TCG_REG_O0, 0, SHIFT_SRA); } else { - if ((memop & MO_SIZE) =3D=3D MO_64) { - tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, 32, SHIFT_SLLX); - tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O1, 0, SHIFT_SRL); - tcg_out_arith(s, data, TCG_REG_O0, TCG_REG_O1, ARITH_OR); - } else if (is_64) { - /* Re-extend from 32-bit rather than reassembling when we - know the high register must be an extension. */ - tcg_out_arithi(s, data, TCG_REG_O1, 0, - memop & MO_SIGN ? SHIFT_SRA : SHIFT_SRL); - } else { - tcg_out_mov(s, TCG_TYPE_I32, data, TCG_REG_O1); - } + tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0); } =20 *label_ptr |=3D INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); @@ -1301,7 +1222,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a, TCGReg addr, unsigned s_bits =3D memop & MO_SIZE; unsigned t_bits; =20 - if (SPARC64 && TARGET_LONG_BITS =3D=3D 32) { + if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); addr =3D TCG_REG_T1; } @@ -1337,10 +1258,9 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg da= ta, TCGReg addr, * operation in the delay slot, and failure need only invoke the * handler for SIGBUS. */ - TCGReg arg_low =3D TCG_REG_O1 + (!SPARC64 && TARGET_LONG_BITS =3D= =3D 64); tcg_out_call_nodelay(s, qemu_unalign_ld_trampoline, false); /* delay slot -- move to low part of argument reg */ - tcg_out_mov_delay(s, arg_low, addr); + tcg_out_mov_delay(s, TCG_REG_O1, addr); } else { /* Underalignment: load by pieces of minimum alignment. */ int ld_opc, a_size, s_size, i; @@ -1400,7 +1320,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= a, TCGReg addr, =20 #ifdef CONFIG_SOFTMMU unsigned memi =3D get_mmuidx(oi); - TCGReg addrz, param; + TCGReg addrz; const tcg_insn_unit *func; =20 addrz =3D tcg_out_tlb_load(s, addr, memi, memop, @@ -1418,23 +1338,14 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= ata, TCGReg addr, =20 /* TLB Miss. */ =20 - param =3D TCG_REG_O1; - if (!SPARC64 && TARGET_LONG_BITS =3D=3D 64) { - /* Skip the high-part; we'll perform the extract in the trampoline= . */ - param++; - } - tcg_out_mov(s, TCG_TYPE_REG, param++, addrz); - if (!SPARC64 && (memop & MO_SIZE) =3D=3D MO_64) { - /* Skip the high-part; we'll perform the extract in the trampoline= . */ - param++; - } - tcg_out_mov(s, TCG_TYPE_REG, param++, data); + tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_O1, addrz); + tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_O2, data); =20 func =3D qemu_st_trampoline[memop & (MO_BSWAP | MO_SIZE)]; tcg_debug_assert(func !=3D NULL); tcg_out_call_nodelay(s, func, false); /* delay slot */ - tcg_out_movi(s, TCG_TYPE_I32, param, oi); + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_O3, oi); =20 *label_ptr |=3D INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); #else @@ -1443,7 +1354,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= a, TCGReg addr, unsigned s_bits =3D memop & MO_SIZE; unsigned t_bits; =20 - if (SPARC64 && TARGET_LONG_BITS =3D=3D 32) { + if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); addr =3D TCG_REG_T1; } @@ -1479,10 +1390,9 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg da= ta, TCGReg addr, * operation in the delay slot, and failure need only invoke the * handler for SIGBUS. */ - TCGReg arg_low =3D TCG_REG_O1 + (!SPARC64 && TARGET_LONG_BITS =3D= =3D 64); tcg_out_call_nodelay(s, qemu_unalign_st_trampoline, false); /* delay slot -- move to low part of argument reg */ - tcg_out_mov_delay(s, arg_low, addr); + tcg_out_mov_delay(s, TCG_REG_O1, addr); } else { /* Underalignment: store by pieces of minimum alignment. */ int st_opc, a_size, s_size, i; @@ -1719,14 +1629,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_muls2_i32: c =3D ARITH_SMUL; do_mul2: - /* The 32-bit multiply insns produce a full 64-bit result. If the - destination register can hold it, we can avoid the slower RDY. = */ + /* The 32-bit multiply insns produce a full 64-bit result. */ tcg_out_arithc(s, a0, a2, args[3], const_args[3], c); - if (SPARC64 || a0 <=3D TCG_REG_O7) { - tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX); - } else { - tcg_out_rdy(s, a1); - } + tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX); break; =20 case INDEX_op_qemu_ld_i32: @@ -1984,16 +1889,11 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use = */ } =20 -#if SPARC64 -# define ELF_HOST_MACHINE EM_SPARCV9 -#else -# define ELF_HOST_MACHINE EM_SPARC32PLUS -# define ELF_HOST_FLAGS EF_SPARC_32PLUS -#endif +#define ELF_HOST_MACHINE EM_SPARCV9 =20 typedef struct { DebugFrameHeader h; - uint8_t fde_def_cfa[SPARC64 ? 4 : 2]; + uint8_t fde_def_cfa[4]; uint8_t fde_win_save; uint8_t fde_ret_save[3]; } DebugFrame; @@ -2010,12 +1910,8 @@ static const DebugFrame debug_frame =3D { .h.fde.len =3D sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_off= set), =20 .fde_def_cfa =3D { -#if SPARC64 12, 30, /* DW_CFA_def_cfa i6, 2047 */ (2047 & 0x7f) | 0x80, (2047 >> 7) -#else - 13, 30 /* DW_CFA_def_cfa_register i6 */ -#endif }, .fde_win_save =3D 0x2d, /* DW_CFA_GNU_window_save */ .fde_ret_save =3D { 9, 15, 31 }, /* DW_CFA_register o7, i7 */ --=20 2.34.1 From nobody Sat May 18 10:30:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1667194856; cv=none; d=zohomail.com; s=zohoarc; b=ZB+F7Mk4eclSWPFdKGA7P1cCTVtWKkLnsFZmpGUMXKef/gt+XZSEPUgtWvwQAKmqqN7sismSqRW7MKVgvdIXH2L1VLJo/CyD4hmFEavxof6mmCbuzMTr8UsTOWczFpgt6fIj35vqRaElrRhqZc+6jjSfnHEf/09w6DByXKyerGo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667194856; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wcxwX8W92JQ/vOBmXH0SG17huQWKX+Sq0YwofD1p00Q=; b=Qbs56xD74Dm2esR4uqbkLdWw7mG9NWtY2iCrnTfU46dahmZ/ED1CeMVRYnGus5r/GI+flhO/35YOq96GqxsfPYH47y4mZeYaK+G67MJQ8zfi4SqAkHfo0fL+yeEYmhthLMwdkkqhqJGLBK/S5jLvY+6sAeFWVFmlWLKfTsjU+T0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1667194856099599.1274600716334; Sun, 30 Oct 2022 22:40:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opNWx-0001aF-4q; Mon, 31 Oct 2022 01:40:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opNWv-0001a1-NQ for qemu-devel@nongnu.org; Mon, 31 Oct 2022 01:40:13 -0400 Received: from mail-oi1-x22e.google.com ([2607:f8b0:4864:20::22e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opNWu-0003k5-5J for qemu-devel@nongnu.org; Mon, 31 Oct 2022 01:40:13 -0400 Received: by mail-oi1-x22e.google.com with SMTP id r83so11895754oih.2 for ; Sun, 30 Oct 2022 22:40:11 -0700 (PDT) Received: from stoup.. ([172.58.176.235]) by smtp.gmail.com with ESMTPSA id u8-20020a9d4d88000000b006618586b850sm2473857otk.46.2022.10.30.22.40.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 22:40:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wcxwX8W92JQ/vOBmXH0SG17huQWKX+Sq0YwofD1p00Q=; b=ckTLVQzxbmOfb10Or51EvC6t6gyZXj+6PXzbukiT3K5+RpRew0xbTxhz8kY/hvPovU 1T7hUr4QeVSuwaFLhirR8hYwCf+pvdjWe8qMbcspTI6NN3+iPbnwmU7m5OcTO1RbEcNQ KSBEIN6lR+Qg4e4XvQCppRP6QTLtPuPvAmxTzu5abhGbciK7mAwaWmUd3rxMqCqO75tJ Q01lBsND8oqlY4GUdsxw6riRXh7yO/ZAiGrwGe9sahzfcuz1cCBKgd6wcqT1Qc0Ijhu+ g2zFFdqsJP80EC/gMc0gMNqWSZJ2B/H9aLGGXAJrAt63WAT5vM7Qcf11eLarUECjk/rb XYVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wcxwX8W92JQ/vOBmXH0SG17huQWKX+Sq0YwofD1p00Q=; b=ps9xcEqzIcfE+eWO9kqfAWeyLHiNKy8GO6XqLm+3qkCW5osRK2RJFPusrVDob0qqbr LXYo3S0FkqQBTQKOhSrodQ/ydLuGNwFNlloD5ERru/Pe4t7UUj1vG2SZuG+XjQizTr+V siq9n9HzcfjMhkIiWMvADvJ1HMCot8z80BHIFEgUTK/6pBnX6qnCk/g3TSIV4+09qwAc ShAhrDe8VkW3JOC44pCoBxWFlYjVePJzAOqfDNqv9cRAAMXhCVGpMaNRgh4tublmN3R9 3wHe9YWtCII33dpew+lmf90l52oUz8qc5hk1JQLMBMtADJOjGcnD7LMe745jVInTqsE7 9S5g== X-Gm-Message-State: ACrzQf01b/KEe/jW+E9Vuau4ZSCuwf+4VRhFi96pnIL5xDDTrrrkhLti fj6IKS5MOvWZ396cTur2+3Oew6ovtDIF6g== X-Google-Smtp-Source: AMsMyM5/Rdro3rUchIAXAULDcYn07KMvia36xiJe6J3yVocBXL5KtejsIV+6mY04BQ0MrGFEQ2vxCg== X-Received: by 2002:a05:6808:1b12:b0:354:e2c8:5e70 with SMTP id bx18-20020a0568081b1200b00354e2c85e70mr13729903oib.146.1667194810865; Sun, 30 Oct 2022 22:40:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 02/11] tcg/sparc64: Rename from tcg/sparc Date: Mon, 31 Oct 2022 16:39:39 +1100 Message-Id: <20221031053948.3408-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221031053948.3408-1-richard.henderson@linaro.org> References: <20221031053948.3408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1667194858064100006 Emphasize that we only support full 64-bit code generation. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- meson.build | 4 +--- tcg/{sparc =3D> sparc64}/tcg-target-con-set.h | 0 tcg/{sparc =3D> sparc64}/tcg-target-con-str.h | 0 tcg/{sparc =3D> sparc64}/tcg-target.h | 0 tcg/{sparc =3D> sparc64}/tcg-target.c.inc | 0 MAINTAINERS | 2 +- 6 files changed, 2 insertions(+), 4 deletions(-) rename tcg/{sparc =3D> sparc64}/tcg-target-con-set.h (100%) rename tcg/{sparc =3D> sparc64}/tcg-target-con-str.h (100%) rename tcg/{sparc =3D> sparc64}/tcg-target.h (100%) rename tcg/{sparc =3D> sparc64}/tcg-target.c.inc (100%) diff --git a/meson.build b/meson.build index 37737913df..e9853ad21a 100644 --- a/meson.build +++ b/meson.build @@ -49,7 +49,7 @@ qapi_trace_events =3D [] bsd_oses =3D ['gnu/kfreebsd', 'freebsd', 'netbsd', 'openbsd', 'dragonfly',= 'darwin'] supported_oses =3D ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', '= sunos', 'linux'] supported_cpus =3D ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64', - 'arm', 'aarch64', 'loongarch64', 'mips', 'mips64', 'sparc', 'sparc64'] + 'arm', 'aarch64', 'loongarch64', 'mips', 'mips64', 'sparc64'] =20 cpu =3D host_machine.cpu_family() =20 @@ -469,8 +469,6 @@ if get_option('tcg').allowed() endif if get_option('tcg_interpreter') tcg_arch =3D 'tci' - elif host_arch =3D=3D 'sparc64' - tcg_arch =3D 'sparc' elif host_arch =3D=3D 'x86_64' tcg_arch =3D 'i386' elif host_arch =3D=3D 'ppc64' diff --git a/tcg/sparc/tcg-target-con-set.h b/tcg/sparc64/tcg-target-con-se= t.h similarity index 100% rename from tcg/sparc/tcg-target-con-set.h rename to tcg/sparc64/tcg-target-con-set.h diff --git a/tcg/sparc/tcg-target-con-str.h b/tcg/sparc64/tcg-target-con-st= r.h similarity index 100% rename from tcg/sparc/tcg-target-con-str.h rename to tcg/sparc64/tcg-target-con-str.h diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc64/tcg-target.h similarity index 100% rename from tcg/sparc/tcg-target.h rename to tcg/sparc64/tcg-target.h diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc similarity index 100% rename from tcg/sparc/tcg-target.c.inc rename to tcg/sparc64/tcg-target.c.inc diff --git a/MAINTAINERS b/MAINTAINERS index 64893e36bc..1ab6962b0a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3379,7 +3379,7 @@ L: qemu-s390x@nongnu.org =20 SPARC TCG target S: Odd Fixes -F: tcg/sparc/ +F: tcg/sparc64/ F: disas/sparc.c =20 TCI TCG target --=20 2.34.1 From nobody Sat May 18 10:30:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1667194927; cv=none; d=zohomail.com; s=zohoarc; b=aTbTBcCJhUfJxOLQHs1lSO4Z3Ysn7FB/7VCfYdEYulbBuIDJxHwnE9TFiDKzZYqhOzt4x2W/7JDlgelK8kvHBcgr2MuwvNykyTqE/PkppwoDET+Ffh1rphuOF4mTLoPMGAJyi/SgTaUYTeK5+fMV4XlhbAds8R/Aeb9pQf9TFfg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667194927; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JOI9wCa8HkP733gcye6yWCLDNfK9DpfpzUVfiO5LUvs=; b=YQxQh8kRi+4UpBwSxQYBcjbHa40PVVkyduVQXWLti4zjT7L3ZA6Oq7MiqmSdR/52ZNcc0B6XEfWpOEAlxy8JWhly/0YoTP4ReQNTUontmxhQ4y0ORyokBH7mRWi0Shyj67qveZDtoIZ81Dn8dR7NrdJs8wKHcMhPxpmAXUmHyks= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16671949273161019.5310982163256; Sun, 30 Oct 2022 22:42:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opNX3-0001al-UO; Mon, 31 Oct 2022 01:40:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opNX1-0001ab-G7 for qemu-devel@nongnu.org; Mon, 31 Oct 2022 01:40:19 -0400 Received: from mail-ot1-x32d.google.com ([2607:f8b0:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opNWz-0003kQ-LE for qemu-devel@nongnu.org; Mon, 31 Oct 2022 01:40:19 -0400 Received: by mail-ot1-x32d.google.com with SMTP id k59-20020a9d19c1000000b0066c45cdfca5so1807823otk.10 for ; Sun, 30 Oct 2022 22:40:17 -0700 (PDT) Received: from stoup.. ([172.58.176.235]) by smtp.gmail.com with ESMTPSA id u8-20020a9d4d88000000b006618586b850sm2473857otk.46.2022.10.30.22.40.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 22:40:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JOI9wCa8HkP733gcye6yWCLDNfK9DpfpzUVfiO5LUvs=; b=J1V7LwUUNunw/Ooh+m4iYZnBuQ+PHGFi/VA/2+ieFR/uwf8oTSJd8hs50BG/OVn1Bz 9QWXElDnANIh7Tjqsd1eLw6Q+cMm/rsyFo4dfpkvVAJYaZxOzHiRNL6eZ/uOKcstxo4S mjt63p7g9ASztjjeqy9CX26uv7L/2MZJZnQ2PeFPU9mEVUqQOetYOSUgU1Gbob6CYzvW SH0Knltv+74k+Bf3QOZ1wq+nJY/7QAOkwNuhl05LKeil3lU8HywUttFD+lqp7Acj0tet pPoTJvmt1g53cO3ogoYBL7kdhZNAiekk1PPQStvUPI/esKF9+ntaGrQDqebYcnTh6bg6 Y9eQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JOI9wCa8HkP733gcye6yWCLDNfK9DpfpzUVfiO5LUvs=; b=YG0Czqc6zJmELqkU6f7zTBQ3r4PVm+7v+zrZLgi4zSCuREE1jmTxdvlCzJaZu7eYui Qjyz0I2iWniOxJ2bLxgz2viGhGgq8SBTUEAYYs6s+AIzJm7OZ40fZcP7l7WWAkGKKB2W McDxB9eONZ+OjONeAynJx1I18UaE20xRwHTzNLiKLBXHLtUsfr6fGD/gb5YRakU5YHPT /dLKAlaR1P4QkKMnvaXvn4X918er+G+w6f0jFCugZCS3jYVBr2r4HhxXH6NdC9mh8WrH iCnQYY/Gf2UJJ7/n+SNahoEipmK/FO0r1tuPpBEmciq2aLXbI0hwjkg6doQ0S9I+iK2N YHQQ== X-Gm-Message-State: ACrzQf30K0RCfJixKzbrHNgfTuLh0B1LcxJed2++q68U7exDd8Dn00F6 /9jVeqHuZQ1l5cq5fAP82/O10EMR3qYThA== X-Google-Smtp-Source: AMsMyM4ieS8HjECCNzS7otZR99wt+zHgGm8HDkEscqy6yY8cpc0sajAic3TVXlfTUG8C8lPUhGNDcQ== X-Received: by 2002:a9d:2909:0:b0:661:9cae:6f08 with SMTP id d9-20020a9d2909000000b006619cae6f08mr5816307otb.277.1667194816310; Sun, 30 Oct 2022 22:40:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 03/11] tcg/sparc64: Remove sparc32plus constraints Date: Mon, 31 Oct 2022 16:39:40 +1100 Message-Id: <20221031053948.3408-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221031053948.3408-1-richard.henderson@linaro.org> References: <20221031053948.3408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1667194928683100005 Content-Type: text/plain; charset="utf-8" With sparc64 we need not distinguish between registers that can hold 32-bit values and those that can hold 64-bit values. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target-con-set.h | 16 +---- tcg/sparc64/tcg-target-con-str.h | 3 - tcg/sparc64/tcg-target.c.inc | 109 ++++++++++++------------------- 3 files changed, 44 insertions(+), 84 deletions(-) diff --git a/tcg/sparc64/tcg-target-con-set.h b/tcg/sparc64/tcg-target-con-= set.h index 3b751dc3fb..31e6fea1fc 100644 --- a/tcg/sparc64/tcg-target-con-set.h +++ b/tcg/sparc64/tcg-target-con-set.h @@ -11,22 +11,12 @@ */ C_O0_I1(r) C_O0_I2(rZ, r) -C_O0_I2(RZ, r) C_O0_I2(rZ, rJ) -C_O0_I2(RZ, RJ) -C_O0_I2(sZ, A) -C_O0_I2(SZ, A) -C_O1_I1(r, A) -C_O1_I1(R, A) +C_O0_I2(sZ, s) +C_O1_I1(r, s) C_O1_I1(r, r) -C_O1_I1(r, R) -C_O1_I1(R, r) -C_O1_I1(R, R) -C_O1_I2(R, R, R) +C_O1_I2(r, r, r) C_O1_I2(r, rZ, rJ) -C_O1_I2(R, RZ, RJ) C_O1_I4(r, rZ, rJ, rI, 0) -C_O1_I4(R, RZ, RJ, RI, 0) C_O2_I2(r, r, rZ, rJ) -C_O2_I4(R, R, RZ, RZ, RJ, RI) C_O2_I4(r, r, rZ, rZ, rJ, rJ) diff --git a/tcg/sparc64/tcg-target-con-str.h b/tcg/sparc64/tcg-target-con-= str.h index fdb25d9313..8f5c7aef97 100644 --- a/tcg/sparc64/tcg-target-con-str.h +++ b/tcg/sparc64/tcg-target-con-str.h @@ -9,10 +9,7 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('R', ALL_GENERAL_REGS64) REGS('s', ALL_QLDST_REGS) -REGS('S', ALL_QLDST_REGS64) -REGS('A', TARGET_LONG_BITS =3D=3D 64 ? ALL_QLDST_REGS64 : ALL_QLDST_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 097bcfcd12..cb9453efdd 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -80,19 +80,8 @@ static const char * const tcg_target_reg_names[TCG_TARGE= T_NB_REGS] =3D { #else #define SOFTMMU_RESERVE_REGS 0 #endif - -/* - * Note that sparcv8plus can only hold 64 bit quantities in %g and %o - * registers. These are saved manually by the kernel in full 64-bit - * slots. The %i and %l registers are saved by the register window - * mechanism, which only allocates space for 32 bits. Given that this - * window spill/fill can happen on any signal, we must consider the - * high bits of the %i and %l registers garbage at all times. - */ #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) -# define ALL_GENERAL_REGS64 ALL_GENERAL_REGS #define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) -#define ALL_QLDST_REGS64 (ALL_GENERAL_REGS64 & ~SOFTMMU_RESERVE_REGS) =20 /* Define some temporary registers. T2 is used for constant generation. = */ #define TCG_REG_T1 TCG_REG_G1 @@ -1738,107 +1727,91 @@ static TCGConstraintSetIndex tcg_target_op_def(TCG= Opcode op) return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: case INDEX_op_ld_i32: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: case INDEX_op_neg_i32: + case INDEX_op_neg_i64: case INDEX_op_not_i32: + case INDEX_op_not_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: + case INDEX_op_extrh_i64_i32: return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: + case INDEX_op_st8_i64: case INDEX_op_st16_i32: + case INDEX_op_st16_i64: case INDEX_op_st_i32: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: return C_O0_I2(rZ, r); =20 case INDEX_op_add_i32: + case INDEX_op_add_i64: case INDEX_op_mul_i32: + case INDEX_op_mul_i64: case INDEX_op_div_i32: + case INDEX_op_div_i64: case INDEX_op_divu_i32: + case INDEX_op_divu_i64: case INDEX_op_sub_i32: + case INDEX_op_sub_i64: case INDEX_op_and_i32: + case INDEX_op_and_i64: case INDEX_op_andc_i32: + case INDEX_op_andc_i64: case INDEX_op_or_i32: + case INDEX_op_or_i64: case INDEX_op_orc_i32: + case INDEX_op_orc_i64: case INDEX_op_xor_i32: + case INDEX_op_xor_i64: case INDEX_op_shl_i32: + case INDEX_op_shl_i64: case INDEX_op_shr_i32: + case INDEX_op_shr_i64: case INDEX_op_sar_i32: + case INDEX_op_sar_i64: case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: return C_O1_I2(r, rZ, rJ); =20 case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: return C_O0_I2(rZ, rJ); case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: return C_O1_I4(r, rZ, rJ, rI, 0); case INDEX_op_add2_i32: + case INDEX_op_add2_i64: case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: return C_O2_I4(r, r, rZ, rZ, rJ, rJ); case INDEX_op_mulu2_i32: case INDEX_op_muls2_i32: return C_O2_I2(r, r, rZ, rJ); - - case INDEX_op_ld8u_i64: - case INDEX_op_ld8s_i64: - case INDEX_op_ld16u_i64: - case INDEX_op_ld16s_i64: - case INDEX_op_ld32u_i64: - case INDEX_op_ld32s_i64: - case INDEX_op_ld_i64: - case INDEX_op_ext_i32_i64: - case INDEX_op_extu_i32_i64: - return C_O1_I1(R, r); - - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: - return C_O0_I2(RZ, r); - - case INDEX_op_add_i64: - case INDEX_op_mul_i64: - case INDEX_op_div_i64: - case INDEX_op_divu_i64: - case INDEX_op_sub_i64: - case INDEX_op_and_i64: - case INDEX_op_andc_i64: - case INDEX_op_or_i64: - case INDEX_op_orc_i64: - case INDEX_op_xor_i64: - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - case INDEX_op_setcond_i64: - return C_O1_I2(R, RZ, RJ); - - case INDEX_op_neg_i64: - case INDEX_op_not_i64: - case INDEX_op_ext32s_i64: - case INDEX_op_ext32u_i64: - return C_O1_I1(R, R); - - case INDEX_op_extrl_i64_i32: - case INDEX_op_extrh_i64_i32: - return C_O1_I1(r, R); - - case INDEX_op_brcond_i64: - return C_O0_I2(RZ, RJ); - case INDEX_op_movcond_i64: - return C_O1_I4(R, RZ, RJ, RI, 0); - case INDEX_op_add2_i64: - case INDEX_op_sub2_i64: - return C_O2_I4(R, R, RZ, RZ, RJ, RI); case INDEX_op_muluh_i64: - return C_O1_I2(R, R, R); + return C_O1_I2(r, r, r); =20 case INDEX_op_qemu_ld_i32: - return C_O1_I1(r, A); case INDEX_op_qemu_ld_i64: - return C_O1_I1(R, A); + return C_O1_I1(r, s); case INDEX_op_qemu_st_i32: - return C_O0_I2(sZ, A); case INDEX_op_qemu_st_i64: - return C_O0_I2(SZ, A); + return C_O0_I2(sZ, s); =20 default: g_assert_not_reached(); @@ -1859,7 +1832,7 @@ static void tcg_target_init(TCGContext *s) #endif =20 tcg_target_available_regs[TCG_TYPE_I32] =3D ALL_GENERAL_REGS; - tcg_target_available_regs[TCG_TYPE_I64] =3D ALL_GENERAL_REGS64; + tcg_target_available_regs[TCG_TYPE_I64] =3D ALL_GENERAL_REGS; =20 tcg_target_call_clobber_regs =3D 0; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1); --=20 2.34.1 From nobody Sat May 18 10:30:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1667194859; cv=none; d=zohomail.com; s=zohoarc; b=lVU+mhnHmmTMVipwKW2kpO/iTqXG4z4qtQzxuL7YQ9Lwx1qaZWPVN2Cr2weuxRQsiTxaSx93JauIpt5Fx4K121R7BIt7d4+YJ+9L8Bdekn+RKzCFVY0CEqhOFfF8/uXEdAsYujcrhafTa3ZnAgGPhHTthMcxIOCv10L9a5ZZ5I0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667194859; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([172.58.176.235]) by smtp.gmail.com with ESMTPSA id u8-20020a9d4d88000000b006618586b850sm2473857otk.46.2022.10.30.22.40.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 22:40:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9OVsqAmyqPbTHmE3w0Zkzp7OCwHypnqZuwBCZ2+0TpM=; b=UNYOaaYZ3FhPCyRhkIlnn8n8h4/bd8c82EJGRZh2dFysSIB8j6Qf0RJNT2rTrqZ+JF K64r4P7PMYvGVm5JzHK09Mbx2N75sCJbHa2I5qNm7HfVtaOR2yBwTyWvXAQg9Rij2+nh KfM2EPjrlxx5twUoSXcdYMPiXicQTsvNtldzYCH0kanx5zEn8+3PFTvnsDL9Ea7vFCHP /fcIhCRPf+98/sx96Jk9aJ0T33/MQvgiUS1sZLb+cNABd832RLiI5k9sV01sNLKGNE51 S4mqaoCs2+lu3jjfRxwlnhO02BWozbOTIGQF8sznLG0e3LjJggMvI2m/4pxswlCtCqkZ 4VHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9OVsqAmyqPbTHmE3w0Zkzp7OCwHypnqZuwBCZ2+0TpM=; b=FxxRuDiZpopL04VyJ+lqeUS/lDFVATXXdUiNgjuBelGdPRAXRzHf4g7c0a1V4HJOOg Q/Fdlei+pxaadMF20pjsY7tUpm1wA453zoF+cFyZPvj+3g1vT0SqmYpsFQjafu9Vd3JI 8pbIDAlAC63azHMyQ3TTN040S7TlgEO7nmYwBZ+6ZCO+zppzkVGffgl6ZsZv8jblIAb2 3PXoOzX6lGleCAE2FF9SxSKAl1O3yQvM7rPDPbMaTqiLzp1QT2oz+7DQcRkA2n1k0O9p 7YbJOgA7uPApL/CsLKigvraXLqfsOvh/CTtLRP0I2RmlmXHqiNlmTsogceAJuVIoM/g5 MbiA== X-Gm-Message-State: ACrzQf3xIJJBzCQK0OUEZQfnS+bIS0a05yTmiBf9LHay31Y8gQ3CFtpq VbuMtKAMLzSUcYzdbvJb1Om9GIxa8SIeqg== X-Google-Smtp-Source: AMsMyM45LapvvE4Ut6NvzhxlNz/JV7ZgZwtgLDpGtdSbQMUw1tyXyeKNpXwj0q6Zm9pLz24/D/jm+A== X-Received: by 2002:a9d:5f82:0:b0:638:eab8:14a4 with SMTP id g2-20020a9d5f82000000b00638eab814a4mr5724758oti.71.1667194821777; Sun, 30 Oct 2022 22:40:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Icenowy Zheng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 04/11] tcg/tci: fix logic error when registering helpers via FFI Date: Mon, 31 Oct 2022 16:39:41 +1100 Message-Id: <20221031053948.3408-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221031053948.3408-1-richard.henderson@linaro.org> References: <20221031053948.3408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1667194860106100013 From: Icenowy Zheng When registering helpers via FFI for TCI, the inner loop that iterates parameters of the helper reuses (and thus pollutes) the same variable used by the outer loop that iterates all helpers, thus made some helpers unregistered. Fix this logic error by using a dedicated temporary variable for the inner loop. Fixes: 22f15579fa ("tcg: Build ffi data structures for helpers") Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Icenowy Zheng Message-Id: <20221028072145.1593205-1-uwu@icenowy.me> [rth: Move declaration of j to the for loop itself] Signed-off-by: Richard Henderson --- tcg/tcg.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index c9e664ee31..b6c46b7e25 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -634,9 +634,9 @@ static void tcg_context_init(unsigned max_cpus) =20 if (nargs !=3D 0) { ca->cif.arg_types =3D ca->args; - for (i =3D 0; i < nargs; ++i) { - int typecode =3D extract32(typemask, (i + 1) * 3, 3); - ca->args[i] =3D typecode_to_ffi[typecode]; + for (int j =3D 0; j < nargs; ++j) { + int typecode =3D extract32(typemask, (j + 1) * 3, 3); + ca->args[j] =3D typecode_to_ffi[typecode]; } } =20 --=20 2.34.1 From nobody Sat May 18 10:30:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1667194947; cv=none; d=zohomail.com; s=zohoarc; b=AxWCHjNzgISuMVFixsihD6b2Ay8fwrzp4T0WQvQi5Jzde5bdKxDmySpAo50G0wpXYrbkNpUPjzbtzZcSpoXNkwdQztigI+8yk1V/MPMeCw1nn5EDiiK2ps2p9yZKFIq2sZcl1aM3Mq6L++sElvj3nLY14KBiqchUZddQCJIOr3Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667194947; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CHYIC5asuArw95radfcZ/rVfrHssHUSuePR3hcbF0+I=; b=DO8kS0iSAxdptkEzzbgrEoxOxkopblY0heLmLYVwhmxfME9tqNoGwypskcQHrgSVRM6Tp8dI/Weq8CAYs84XwGg9RQa/LVR8Y+bjpLxBR/Sb7LC24S+SAayunmTFwLeNt34ECD45luScwNgEb5RewPRktxsGsEXd89PWND3rkp4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1667194947347802.5035931731439; Sun, 30 Oct 2022 22:42:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opNXG-0001c0-E1; Mon, 31 Oct 2022 01:40:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opNXB-0001br-JA for qemu-devel@nongnu.org; Mon, 31 Oct 2022 01:40:29 -0400 Received: from mail-ot1-x329.google.com ([2607:f8b0:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opNX9-0003oM-Od for qemu-devel@nongnu.org; Mon, 31 Oct 2022 01:40:29 -0400 Received: by mail-ot1-x329.google.com with SMTP id br15-20020a056830390f00b0061c9d73b8bdso6249833otb.6 for ; Sun, 30 Oct 2022 22:40:27 -0700 (PDT) Received: from stoup.. ([172.58.176.235]) by smtp.gmail.com with ESMTPSA id u8-20020a9d4d88000000b006618586b850sm2473857otk.46.2022.10.30.22.40.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 22:40:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CHYIC5asuArw95radfcZ/rVfrHssHUSuePR3hcbF0+I=; b=rXZI88JHIyPKKzulnhgYCMJlmE1ED8mkDCBJXdHhGhTAEluGTEOH5n+pBLThV9+dfx MfmlcLXjqah9Pg8S2/GjYkTDEY5Wa8lbwJy8FQ1dMrD653Xqyxnvfu5u0efJY7chlxxF GyrNVCpJZ8xtmV74pQ0TE8RCkQxpBjMUMnOeitspBFxjVbEIzlIjERKPedcp/XdAaaUC U7sA35SsnnrL3PN4vcDY9rA5EgnABlkF0F0dIAZkCvPMPY5FEQHtE3tmaij2EfW5/jGU wEBUnwy3+88i2Kt1ywFDvb/u13f/k3XiRJlbxoWG6vfzh+KIvC+jqMRW87eesMcf/Iux q4GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CHYIC5asuArw95radfcZ/rVfrHssHUSuePR3hcbF0+I=; b=x2lbjZEARgFfbzv+gkhqkzqTD2auehCcF6lYcsA6rMomUDaJD+mz9Vh3BGkigyiKFT +CrHo3yIxOgUP/CqUVq+c8PTUULOsmfmjtuiFzb7tTKGR6Yw+ni1lYoILTaEff3pgTsa eUDKwXRiVH0BL0pofyWzyLLxhqp/QfjRTs1IgxHK4o+G+16hAoptIedSHBdkMnxXYGmt NKwFzhaiJOtsNoOBr6Wl7LX3B3W8tzOX4e9bdgDR29K4JIdkm9UqRxJ/JmwZwYJYRCva yYbqbkmTnCplEcYJNpUhAqjmAOOv3cPis0OMmFchcltDKQAMM8WQHbcFL4xnmIcxds+Y DQXg== X-Gm-Message-State: ACrzQf3yfgkdiGt/s2w/4Sk4STrisOpiZchbdzTuuIQvNg7/I7nDyKdX J+FurtixyjMoDEuClv+ZTbUMZwzePjPhmg== X-Google-Smtp-Source: AMsMyM5fU64W/ocriClbQOTyBz5VeZFdGEWUS+ZEqYtDCX9ROoWsc1Ul41zFs/cFHtlOn+Q83D69Lw== X-Received: by 2002:a05:6830:1f58:b0:66c:3e5e:3ee8 with SMTP id u24-20020a0568301f5800b0066c3e5e3ee8mr4707792oth.45.1667194826042; Sun, 30 Oct 2022 22:40:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Claudio Fontana Subject: [PULL 05/11] accel/tcg: Introduce cpu_unwind_state_data Date: Mon, 31 Oct 2022 16:39:42 +1100 Message-Id: <20221031053948.3408-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221031053948.3408-1-richard.henderson@linaro.org> References: <20221031053948.3408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1667194948837100003 Content-Type: text/plain; charset="utf-8" Add a way to examine the unwind data without actually restoring the data back into env. Reviewed-by: Claudio Fontana Signed-off-by: Richard Henderson --- accel/tcg/internal.h | 4 +-- include/exec/exec-all.h | 21 ++++++++--- accel/tcg/translate-all.c | 74 ++++++++++++++++++++++++++------------- 3 files changed, 68 insertions(+), 31 deletions(-) diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h index 1227bb69bd..9c06b320b7 100644 --- a/accel/tcg/internal.h +++ b/accel/tcg/internal.h @@ -106,8 +106,8 @@ void tb_reset_jump(TranslationBlock *tb, int n); TranslationBlock *tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_p= c, tb_page_addr_t phys_page2); bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc); -int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, - uintptr_t searched_pc, bool reset_icount); +void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, + uintptr_t host_pc, bool reset_icount); =20 /* Return the current PC from CPU, which may be cached in TB. */ static inline target_ulong log_pc(CPUState *cpu, const TranslationBlock *t= b) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index e948992a80..7d851f5907 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -39,20 +39,33 @@ typedef ram_addr_t tb_page_addr_t; #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT #endif =20 +/** + * cpu_unwind_state_data: + * @cpu: the cpu context + * @host_pc: the host pc within the translation + * @data: output data + * + * Attempt to load the the unwind state for a host pc occurring in + * translated code. If @host_pc is not in translated code, the + * function returns false; otherwise @data is loaded. + * This is the same unwind info as given to restore_state_to_opc. + */ +bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *dat= a); + /** * cpu_restore_state: - * @cpu: the vCPU state is to be restore to - * @searched_pc: the host PC the fault occurred at + * @cpu: the cpu context + * @host_pc: the host pc within the translation * @will_exit: true if the TB executed will be interrupted after some cpu adjustments. Required for maintaining the correct icount valus * @return: true if state was restored, false otherwise * * Attempt to restore the state for a fault occurring in translated - * code. If the searched_pc is not in translated code no state is + * code. If @host_pc is not in translated code no state is * restored and the function returns false. */ -bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc, bool will_exi= t); +bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit); =20 G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu); G_NORETURN void cpu_loop_exit(CPUState *cpu); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index f185356a36..319becb698 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -247,52 +247,66 @@ static int encode_search(TranslationBlock *tb, uint8_= t *block) return p - block; } =20 -/* The cpu state corresponding to 'searched_pc' is restored. - * When reset_icount is true, current TB will be interrupted and - * icount should be recalculated. - */ -int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, - uintptr_t searched_pc, bool reset_icount) +static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc, + uint64_t *data) { - uint64_t data[TARGET_INSN_START_WORDS]; - uintptr_t host_pc =3D (uintptr_t)tb->tc.ptr; + uintptr_t iter_pc =3D (uintptr_t)tb->tc.ptr; const uint8_t *p =3D tb->tc.ptr + tb->tc.size; int i, j, num_insns =3D tb->icount; -#ifdef CONFIG_PROFILER - TCGProfile *prof =3D &tcg_ctx->prof; - int64_t ti =3D profile_getclock(); -#endif =20 - searched_pc -=3D GETPC_ADJ; + host_pc -=3D GETPC_ADJ; =20 - if (searched_pc < host_pc) { + if (host_pc < iter_pc) { return -1; } =20 - memset(data, 0, sizeof(data)); + memset(data, 0, sizeof(uint64_t) * TARGET_INSN_START_WORDS); if (!TARGET_TB_PCREL) { data[0] =3D tb_pc(tb); } =20 - /* Reconstruct the stored insn data while looking for the point at - which the end of the insn exceeds the searched_pc. */ + /* + * Reconstruct the stored insn data while looking for the point + * at which the end of the insn exceeds host_pc. + */ for (i =3D 0; i < num_insns; ++i) { for (j =3D 0; j < TARGET_INSN_START_WORDS; ++j) { data[j] +=3D decode_sleb128(&p); } - host_pc +=3D decode_sleb128(&p); - if (host_pc > searched_pc) { - goto found; + iter_pc +=3D decode_sleb128(&p); + if (iter_pc > host_pc) { + return num_insns - i; } } return -1; +} + +/* + * The cpu state corresponding to 'host_pc' is restored. + * When reset_icount is true, current TB will be interrupted and + * icount should be recalculated. + */ +void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, + uintptr_t host_pc, bool reset_icount) +{ + uint64_t data[TARGET_INSN_START_WORDS]; +#ifdef CONFIG_PROFILER + TCGProfile *prof =3D &tcg_ctx->prof; + int64_t ti =3D profile_getclock(); +#endif + int insns_left =3D cpu_unwind_data_from_tb(tb, host_pc, data); + + if (insns_left < 0) { + return; + } =20 - found: if (reset_icount && (tb_cflags(tb) & CF_USE_ICOUNT)) { assert(icount_enabled()); - /* Reset the cycle counter to the start of the block - and shift if to the number of actually executed instructions */ - cpu_neg(cpu)->icount_decr.u16.low +=3D num_insns - i; + /* + * Reset the cycle counter to the start of the block and + * shift if to the number of actually executed instructions. + */ + cpu_neg(cpu)->icount_decr.u16.low +=3D insns_left; } =20 cpu->cc->tcg_ops->restore_state_to_opc(cpu, tb, data); @@ -302,7 +316,6 @@ int cpu_restore_state_from_tb(CPUState *cpu, Translatio= nBlock *tb, prof->restore_time + profile_getclock() - ti); qatomic_set(&prof->restore_count, prof->restore_count + 1); #endif - return 0; } =20 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit) @@ -335,6 +348,17 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t host_p= c, bool will_exit) return false; } =20 +bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *dat= a) +{ + if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) { + TranslationBlock *tb =3D tcg_tb_lookup(host_pc); + if (tb) { + return cpu_unwind_data_from_tb(tb, host_pc, data) >=3D 0; + } + } + return false; +} + void page_init(void) { page_size_init(); --=20 2.34.1 From nobody Sat May 18 10:30:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([172.58.176.235]) by smtp.gmail.com with ESMTPSA id u8-20020a9d4d88000000b006618586b850sm2473857otk.46.2022.10.30.22.40.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 22:40:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r8ag8A++CsvWQPICCIPv2YWYP7CkxoK0jspe/zfPQ5Q=; b=c+dNSuQ/KuZEPIMBtk8TS2j5ASI3EKjYRhEPweq6GOUL0YYGWWoYh5y1Am+pBiZP+f yMgMsPov5UkiSTKmeUZGfQNmAHZD/dFqfbHGuwAh8uYYcyqFa3pzz6ikWDIusGZgkN5a dUItcWaDJAuh6gOBWd8Zu9OCclKHqafdeZ/yBh+MH/6YX3FnozUbM3jgK+Do6UZOiDBL PM0g2NSuu78J4XYaN6AXPSKDK/E/ZcSZyNsV5zFa6hLR7auZOyTB//H4UDUbRcvzYl7D TQ3AeSEuLhWZGdaquf26rzyf84HoDu/QTOKhITK3Kg8CvHbIJzNKxN3tX/CPnEw+QL1l a8yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r8ag8A++CsvWQPICCIPv2YWYP7CkxoK0jspe/zfPQ5Q=; b=Ln4h8z5Vu9E+1oBb5ZqhNQIoz29/LUXI8UqVRYq4feT8249mcDNpZhznKPPRD1r1lZ 0nyA/J6BISMqlKZlhFi5XQvo+AEVff/t4A+K3ZaaRIYIi/Nch9LF4ymuB6P9d6U4STpq fCjmS1KmBfo+fIt3kv5BW2xooXTNWKFzAr+VRkiPsKE3CUQR+VCUx+hu4JxopG86j/mu cwO0Wowpiqi0tQsUxrTt+lcpEhYVLRPFVG776Oz+orMfPSrBaoXz5Hkm2TT5/pE4BU4M GD05I49Fzq1T2MUPmytKVv8edGMAW6Rt2HsnQ6wkDT0chWWFeTf6dpywaRq4x77rWyWc x+5A== X-Gm-Message-State: ACrzQf0hirkB3l20DL1ngvMkpsqixaU/OE5upBXlH8bzll9MtGAuuu44 dWSzjH/4sxoh/kvGfbtxOT7aTHqPJOf3HQ== X-Google-Smtp-Source: AMsMyM5Dq0D1ujYhUBPrXHEBf0+aCH5dkbOrU3J37mQhba1WhNkQeWjgyt1H2ISgYCAoKnXkOk9aTw== X-Received: by 2002:a9d:64d9:0:b0:662:2e67:730a with SMTP id n25-20020a9d64d9000000b006622e67730amr6030793otl.369.1667194830276; Sun, 30 Oct 2022 22:40:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Claudio Fontana Subject: [PULL 06/11] target/i386: Use cpu_unwind_state_data for tpr access Date: Mon, 31 Oct 2022 16:39:43 +1100 Message-Id: <20221031053948.3408-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221031053948.3408-1-richard.henderson@linaro.org> References: <20221031053948.3408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1667194858075100007 Content-Type: text/plain; charset="utf-8" Avoid cpu_restore_state, and modifying env->eip out from underneath the translator with TARGET_TB_PCREL. There is some slight duplication from x86_restore_state_to_opc, but it's just a few lines. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1269 Reviewed-by: Claudio Fontana Signed-off-by: Richard Henderson --- target/i386/helper.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/target/i386/helper.c b/target/i386/helper.c index b62a1e48e2..2cd1756f1a 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -509,6 +509,23 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int= bank, } } =20 +static target_ulong get_memio_eip(CPUX86State *env) +{ + uint64_t data[TARGET_INSN_START_WORDS]; + CPUState *cs =3D env_cpu(env); + + if (!cpu_unwind_state_data(cs, cs->mem_io_pc, data)) { + return env->eip; + } + + /* Per x86_restore_state_to_opc. */ + if (TARGET_TB_PCREL) { + return (env->eip & TARGET_PAGE_MASK) | data[0]; + } else { + return data[0] - env->segs[R_CS].base; + } +} + void cpu_report_tpr_access(CPUX86State *env, TPRAccess access) { X86CPU *cpu =3D env_archcpu(env); @@ -519,9 +536,9 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess = access) =20 cpu_interrupt(cs, CPU_INTERRUPT_TPR); } else if (tcg_enabled()) { - cpu_restore_state(cs, cs->mem_io_pc, false); + target_ulong eip =3D get_memio_eip(env); =20 - apic_handle_tpr_access_report(cpu->apic_state, env->eip, access); + apic_handle_tpr_access_report(cpu->apic_state, eip, access); } } #endif /* !CONFIG_USER_ONLY */ --=20 2.34.1 From nobody Sat May 18 10:30:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1667194949; cv=none; d=zohomail.com; s=zohoarc; b=bMfKk3BO57Tdr/kVijf0a1ICMojVPTe4qC37T8oraKj14XzilE3DRLqySx2aTH//HsdhStug+ZmrIWRIph/DDxN3JJipoiHMav9wBMMOU7Bb+1hY26caTTg5RGVXai8oIl4KgIyl3IS4uKDxMiepdycSUI2A3XhQCaIHYFrb/bc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667194949; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HkiTDoffwuSaTr7ke0a+7yV5MGBGA3Q19sPSnhU1cq4=; b=IaAjdQcgWq/SHeXVpj/3EWzeW1Bf6NjgQW1RHGf/HIFtbHMa4VsSzxyBKTM1/uCB4oCpAkGd/Oi6NGUCIWkwaweaXQDpS+ssd54mxIc9R5b9jFrEAP2VulJxiCW0ry9XUwjBBL5bri1NlkTknUr63jTFMIAnyJrarXQJvq6h1k0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16671949490661019.5297049517944; Sun, 30 Oct 2022 22:42:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opNXL-0001g5-Uu; Mon, 31 Oct 2022 01:40:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opNXI-0001dw-MY for qemu-devel@nongnu.org; Mon, 31 Oct 2022 01:40:36 -0400 Received: from mail-oi1-x22e.google.com ([2607:f8b0:4864:20::22e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opNXH-0003yc-4C for qemu-devel@nongnu.org; Mon, 31 Oct 2022 01:40:36 -0400 Received: by mail-oi1-x22e.google.com with SMTP id p127so11863564oih.9 for ; Sun, 30 Oct 2022 22:40:34 -0700 (PDT) Received: from stoup.. ([172.58.176.235]) by smtp.gmail.com with ESMTPSA id u8-20020a9d4d88000000b006618586b850sm2473857otk.46.2022.10.30.22.40.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 22:40:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HkiTDoffwuSaTr7ke0a+7yV5MGBGA3Q19sPSnhU1cq4=; b=M7SAalJgVaK3xLz3SzTtnUQEPeKmWSRbyQNdAooO+muWiATuJLLfSpZb5R5aIVSz+i UJaM6RrNy4vfkJ3eUHqhxBFkiB/c5DZeEIP1POCfb2+D7k/EvSWYek5dWvSNvt8L5tK8 TddnrJr/8E1zoI+kD3kbcjSw5am7NeW7gqoPDTeirhssjgzoqnCOpXR5XU+QQvsoAtZR D2hJcMAwFR7+reuBSQlGshrXGUgC8B6+DGCVsJsuhpTJeaO1tnM+Tme3Y6v3RmXsGVQO Ntnss0G/f4EFnJ6afZXyXAsXCXfAeiNi8H+fZ9AW26nmFQLjkp/MNvQtCbIc5N1z8Pxm aIww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HkiTDoffwuSaTr7ke0a+7yV5MGBGA3Q19sPSnhU1cq4=; b=qkZOwRXgVYyW9ad6/LbZTpyyj4DchWBH3eKqGnl0nsp8KZtxq2nddNq5zq0dMWrSif Fvga+vSaJ55H4H615Jrhr7/zzF02JmtDjZRRHh/wIGmpTZpT8rJSUVj+xOKzveLtv4YU jLBLWg0M88S2em0ezCqwrcC0vQkguvtJGJ9yu/BgNtKGpTQ8hmz6C2jnFrF3kG/2fGVr 9lqdNlvv5jt2C537xi55v2rqileasvsRonb7UiKwLD5cw/G1i6H+ixU0I8vhV75zzf+m JJ8VfO9FZHQgumGcr4hbhYgl1uJZ3jmWY7Lr+s2XbYmIkxfL9UAGrvLIqmCp2DcYQIkQ Wjvg== X-Gm-Message-State: ACrzQf2t7SiyAZ4GR8BZZVkoJXpsCkujQNpDGRghZrBSFjZpP5odL8zX doIFnL2UTcXnWKpwjfZhrP6elmJxXP3ZZA== X-Google-Smtp-Source: AMsMyM6+Fnbz88ouSdWddfdOAm4I2KLZ+fqwsdK/SsDlT/1EVOUyxL8NVFy8DLBTWX2WzcmhDQ3M5g== X-Received: by 2002:aca:ded7:0:b0:359:dee9:7809 with SMTP id v206-20020acaded7000000b00359dee97809mr5736225oig.1.1667194834144; Sun, 30 Oct 2022 22:40:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 07/11] target/openrisc: Always exit after mtspr npc Date: Mon, 31 Oct 2022 16:39:44 +1100 Message-Id: <20221031053948.3408-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221031053948.3408-1-richard.henderson@linaro.org> References: <20221031053948.3408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1667194950781100006 We have called cpu_restore_state asserting will_exit. Do not go back on that promise. This affects icount. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/openrisc/sys_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 09b3c97d7c..a3508e421d 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -51,8 +51,8 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong sp= r, target_ulong rb) if (env->pc !=3D rb) { env->pc =3D rb; env->dflag =3D 0; - cpu_loop_exit(cs); } + cpu_loop_exit(cs); break; =20 case TO_SPR(0, 17): /* SR */ --=20 2.34.1 From nobody Sat May 18 10:30:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1667194927; cv=none; d=zohomail.com; s=zohoarc; b=FiffWCsPrRCET0oh6F1z99gx8t3hWBY/+AXf1cxnrZcumNwSbf4Ln29cYbmuCYdivuJngok/qFXdD4zEhR4Rm64ClXMu0SF1E91Y+5ahkMQEBoeBfeDEolmsPueNn0x+YnlzBV10uY37hi6Q/l3YtwFFqPQ7kbucgMDHJsVoBTc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667194927; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4EPNlPLvvaNZ49dHiEVCBrThmnHD1d1VYoHkcOJOcWA=; b=MH/bHmgKKj5+sB6fPjAgMd1CN8mQoJJGfq/QeLbZEneUQ4bKWjSvJVKx1yh0GTwArBcpVebtd+ulzmr/R9RmTVZv31L4XgudThHj9jjT8Z/BzLzK1wDjvKKpNzdSyhaFO+2vgtPqZs3qW0BL/7OSNVxNk3tn0GPs2J8rviYnvZk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1667194927871369.9648656595633; Sun, 30 Oct 2022 22:42:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opNXO-0001hI-VX; Mon, 31 Oct 2022 01:40:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opNXM-0001gE-Fp for qemu-devel@nongnu.org; Mon, 31 Oct 2022 01:40:40 -0400 Received: from mail-oi1-x22f.google.com ([2607:f8b0:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opNXK-00042A-Ty for qemu-devel@nongnu.org; Mon, 31 Oct 2022 01:40:40 -0400 Received: by mail-oi1-x22f.google.com with SMTP id l5so11883963oif.7 for ; Sun, 30 Oct 2022 22:40:38 -0700 (PDT) Received: from stoup.. ([172.58.176.235]) by smtp.gmail.com with ESMTPSA id u8-20020a9d4d88000000b006618586b850sm2473857otk.46.2022.10.30.22.40.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 22:40:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4EPNlPLvvaNZ49dHiEVCBrThmnHD1d1VYoHkcOJOcWA=; b=lP1bUtldjz9AmUUgqlpQQ0W7J+0otT/lOdE6kXkCSj1rYI6eyb/kmT1KCYlDVDBUQy B/Z+Q6+d/8R38bPfOD9s8yGf6kgPWARk7NZmL1PGb0th5z4DOpA2gToSD94M0ztutX5l jvD021wWWLoClh5ni+X00Bj6pv9lbFDYG5bOY8x45bNgdEp836LdfVL1BzpZjhVHsqqL Qy65JGL2f0COnqWVu3xSOc94GtUMKnz54JvqKZPyV3OJlES2RqDUrsi4hYY0Js3TL5qa BDsmSSBaZIoHoIIFHV0wiibNmWjueE0QKyFjhZ8myr9+dKIQFlXizg2owOFNUOlfS3Ge T39A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4EPNlPLvvaNZ49dHiEVCBrThmnHD1d1VYoHkcOJOcWA=; b=hyja+TyxMt2wjh4mawW9tJjuTz2Xm1Jgl4/cp3J5znlVUHG1nxqbd5PJ4ld+dIVtmB WOtpwPLfrfjgB4rnPi7kDEHSUkRrALL1cva3dNRqZeMiSuOxjYfOd20pT0giuFr1/o13 vYOJgeGpIMtERcElFdGUh1CmpWtMd8tScTLgJYIIiE0vx9zyJDyxGAwMjf21S7nzG8D2 Fe+SWYh/M9+RUHe16emugooeTAeh//wMC7FqBouaQ11RL/TXSxFWFnwcC3dmSxX+x9hU CCB2bwWwL4IuvdddqO+aOb43hdivDDVU6KJQOAqjLixMz2aF52CueS5BLYDtlq34L13J 2RyA== X-Gm-Message-State: ACrzQf2oPqyPjFUlkJfhOPvVW3rfHWnNEtaC7yJ5QW1bpu11mEEmFUwn f9+6SCL8mXCwDfSb3yynK3DExoMhjay3gg== X-Google-Smtp-Source: AMsMyM4OLncX4jkh4rEtFbjuqKjJO6wgStkEB6wxeMmJ6j1OCIrkaO7ksJxU3rMXVmexueuPjR1+EA== X-Received: by 2002:a05:6808:23c9:b0:359:b71b:459a with SMTP id bq9-20020a05680823c900b00359b71b459amr12135182oib.10.1667194837655; Sun, 30 Oct 2022 22:40:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 08/11] target/openrisc: Use cpu_unwind_state_data for mfspr Date: Mon, 31 Oct 2022 16:39:45 +1100 Message-Id: <20221031053948.3408-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221031053948.3408-1-richard.henderson@linaro.org> References: <20221031053948.3408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1667194928688100006 Content-Type: text/plain; charset="utf-8" Since we do not plan to exit, use cpu_unwind_state_data and extract exactly the data requested. This is a bug fix, in that we no longer clobber dflag. Consider: l.j L2 // branch l.mfspr r1, ppc // delay L1: boom L2: l.lwa r3, (r4) Here, dflag would be set by cpu_restore_state (because that is the current state of the cpu), but but not cleared by tb_stop on exiting the TB (because DisasContext has recorded the current value as zero). The next TB begins at L2 with dflag incorrectly set. If the load has a tlb miss, then the exception will be delivered as per a delay slot: with DSX set in the status register and PC decremented (delay slots restart by re-executing the branch). This will cause the return from interrupt to go to L1, and boom! Signed-off-by: Richard Henderson --- target/openrisc/sys_helper.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index a3508e421d..dde2fa1623 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -199,6 +199,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, targe= t_ulong rd, target_ulong spr) { #ifndef CONFIG_USER_ONLY + uint64_t data[TARGET_INSN_START_WORDS]; MachineState *ms =3D MACHINE(qdev_get_machine()); OpenRISCCPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); @@ -232,14 +233,20 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, tar= get_ulong rd, return env->evbar; =20 case TO_SPR(0, 16): /* NPC (equals PC) */ - cpu_restore_state(cs, GETPC(), false); + if (cpu_unwind_state_data(cs, GETPC(), data)) { + return data[0]; + } return env->pc; =20 case TO_SPR(0, 17): /* SR */ return cpu_get_sr(env); =20 case TO_SPR(0, 18): /* PPC */ - cpu_restore_state(cs, GETPC(), false); + if (cpu_unwind_state_data(cs, GETPC(), data)) { + if (data[1] & 2) { + return data[0] - 4; + } + } return env->ppc; =20 case TO_SPR(0, 32): /* EPCR */ --=20 2.34.1 From nobody Sat May 18 10:30:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1667194885; cv=none; d=zohomail.com; s=zohoarc; b=PkqTOdIXuPlUGU6fV4sYGF0sS/0SrLLB6k+hmmHX+dExcnXJJeWtbygXttLr9coOe1yVNcV486mHXAHKccKiBeCy36xQwZtXre53LCMVV7lkSDDbVwtehAaak3nyvYVbarUzZ/rJTz6MajdJMyjIZwPee3Fk4nVqOaFAI+KSbS4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667194885; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=C9qAXoDzlHGtWJjESxhzwvdwIiiEZj3DJdEKDv+hjRU=; b=Wb67yLoF5fif+HQ5LiMXTlUwFPh2yp8qNKXBQ4j4jI9zCxmVf4sBNF7UzrIYViSoXcpsYxx4bK0O/RJ0qlSmDdF+kBE4szPgnBgJNUr1dwTFKFOL6xgvlX1xhJw9M+S783e0ZEvNv4HBB35zJB4213xpLVr9qZdNIx2zV9BrKu8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1667194885816398.1587417830174; Sun, 30 Oct 2022 22:41:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opNXS-0001iv-MK; Mon, 31 Oct 2022 01:40:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opNXR-0001iY-NH for qemu-devel@nongnu.org; Mon, 31 Oct 2022 01:40:45 -0400 Received: from mail-oa1-x35.google.com ([2001:4860:4864:20::35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opNXP-00043k-Bj for qemu-devel@nongnu.org; Mon, 31 Oct 2022 01:40:45 -0400 Received: by mail-oa1-x35.google.com with SMTP id 586e51a60fabf-13be3ef361dso12446515fac.12 for ; Sun, 30 Oct 2022 22:40:42 -0700 (PDT) Received: from stoup.. ([172.58.176.235]) by smtp.gmail.com with ESMTPSA id u8-20020a9d4d88000000b006618586b850sm2473857otk.46.2022.10.30.22.40.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 22:40:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C9qAXoDzlHGtWJjESxhzwvdwIiiEZj3DJdEKDv+hjRU=; b=GoTiUtv4Umd2Pg7MHBmCNLmeJO3YuT/Q4PF/EXBZl8x3entzsZK49BH81hTq0Lorxi rvPJtLUE63ELAle7QseAaUGm+yLF9wmyjbG57NKBkRhcxre8duy0JfMMLTL8WsmbluhK IZJflPdAx504oiDQAqkjbQYUyCp5Y76xs9H31NHXcetRcCW8QhNuMTOF5okpXi+OHRcB fD9LZqCRcEGQvPKrGpvsNc3qjDoHMnYLAgC8B5VvVKdUOTjZFRG5b9CUmAz15afQRE0G xx5TG9VldwPLdaCW1U1ea7oJNkGAIZ9VAmadXcNWM/qKHlXE/ILATo0Y8PnNzc4M+BR5 cPnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C9qAXoDzlHGtWJjESxhzwvdwIiiEZj3DJdEKDv+hjRU=; b=MOr/1nhtrZ1jfq2EpBlLf8SahDss0p1YJJVQslOsovlDidc5/g70QhTX5hFj/onEgs O7cyyPbkMQOupagqWnk6NEqNMItezQ1K+NVTBnxG+DgvTmpfuTi9RvMtWKD/2i+VU4Vd RmmpN+uTquBCN6crWiff8KtVMgffdAULTbM1qtH0Y5liKLUO4nGePkvbfko31dl+38kW rB5BOHWGA6wiesPwu5pQwxh6RkqEpg6Xa+E3f+aZd3ux5JRgSz8iz3dTqP5dgqJKxTg4 b+6ErX1Mg+528VlSTxSCnU/Cj71+n6quvOey5eEA18ibNvcHFJquTtUrkW4mTELUdJZj vGHw== X-Gm-Message-State: ACrzQf1frGB8RNRGCRnMR9UT6PQ9ldMaNa/thvyuK8nsW3WegoP4M/J3 ilKbD4l57Kq7iM+Wo0F6Rd5GGMuAuAD7pw== X-Google-Smtp-Source: AMsMyM4InADtwdW6XvGxrtQf/zabyfmpuOjV+hnIjYU3zhmtBsYlnl9EJaZcfleQfFMpAUWe+QFcWw== X-Received: by 2002:a05:6870:424d:b0:13c:12cf:84d7 with SMTP id v13-20020a056870424d00b0013c12cf84d7mr16374284oac.281.1667194842024; Sun, 30 Oct 2022 22:40:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Claudio Fontana Subject: [PULL 09/11] accel/tcg: Remove will_exit argument from cpu_restore_state Date: Mon, 31 Oct 2022 16:39:46 +1100 Message-Id: <20221031053948.3408-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221031053948.3408-1-richard.henderson@linaro.org> References: <20221031053948.3408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::35; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1667194886524100007 Content-Type: text/plain; charset="utf-8" The value passed is always true, and if the target's synchronize_from_tb hook is non-trivial, not exiting may be erroneous. Reviewed-by: Claudio Fontana Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 5 +---- accel/tcg/cpu-exec-common.c | 2 +- accel/tcg/translate-all.c | 12 ++---------- target/alpha/helper.c | 2 +- target/alpha/mem_helper.c | 2 +- target/arm/op_helper.c | 2 +- target/arm/tlb_helper.c | 8 ++++---- target/cris/helper.c | 2 +- target/i386/tcg/sysemu/svm_helper.c | 2 +- target/m68k/op_helper.c | 4 ++-- target/microblaze/helper.c | 2 +- target/nios2/op_helper.c | 2 +- target/openrisc/sys_helper.c | 4 ++-- target/ppc/excp_helper.c | 2 +- target/s390x/tcg/excp_helper.c | 2 +- target/tricore/op_helper.c | 2 +- target/xtensa/helper.c | 6 +++--- 17 files changed, 25 insertions(+), 36 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 7d851f5907..9b7bfbf09a 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -56,16 +56,13 @@ bool cpu_unwind_state_data(CPUState *cpu, uintptr_t hos= t_pc, uint64_t *data); * cpu_restore_state: * @cpu: the cpu context * @host_pc: the host pc within the translation - * @will_exit: true if the TB executed will be interrupted after some - cpu adjustments. Required for maintaining the correct - icount valus * @return: true if state was restored, false otherwise * * Attempt to restore the state for a fault occurring in translated * code. If @host_pc is not in translated code no state is * restored and the function returns false. */ -bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit); +bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc); =20 G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu); G_NORETURN void cpu_loop_exit(CPUState *cpu); diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index be6fe45aa5..c7bc8c6efa 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -71,7 +71,7 @@ void cpu_loop_exit(CPUState *cpu) void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc) { if (pc) { - cpu_restore_state(cpu, pc, true); + cpu_restore_state(cpu, pc); } cpu_loop_exit(cpu); } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 319becb698..90997fed47 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -318,16 +318,8 @@ void cpu_restore_state_from_tb(CPUState *cpu, Translat= ionBlock *tb, #endif } =20 -bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit) +bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc) { - /* - * The pc update associated with restore without exit will - * break the relative pc adjustments performed by TARGET_TB_PCREL. - */ - if (TARGET_TB_PCREL) { - assert(will_exit); - } - /* * The host_pc has to be in the rx region of the code buffer. * If it is not we will not be able to resolve it here. @@ -341,7 +333,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc= , bool will_exit) if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) { TranslationBlock *tb =3D tcg_tb_lookup(host_pc); if (tb) { - cpu_restore_state_from_tb(cpu, tb, host_pc, will_exit); + cpu_restore_state_from_tb(cpu, tb, host_pc, true); return true; } } diff --git a/target/alpha/helper.c b/target/alpha/helper.c index a5a389b5a3..970c869771 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -532,7 +532,7 @@ G_NORETURN void dynamic_excp(CPUAlphaState *env, uintpt= r_t retaddr, cs->exception_index =3D excp; env->error_code =3D error; if (retaddr) { - cpu_restore_state(cs, retaddr, true); + cpu_restore_state(cs, retaddr); /* Floating-point exceptions (our only users) point to the next PC= . */ env->pc +=3D 4; } diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 47283a0612..a39b52c5dd 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -28,7 +28,7 @@ static void do_unaligned_access(CPUAlphaState *env, vaddr= addr, uintptr_t retadd uint64_t pc; uint32_t insn; =20 - cpu_restore_state(env_cpu(env), retaddr, true); + cpu_restore_state(env_cpu(env), retaddr); =20 pc =3D env->pc; insn =3D cpu_ldl_code(env, pc); diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c5bde1cfcc..70672bcd9f 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -78,7 +78,7 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, = uint32_t syndrome, * we must restore CPU state here before setting the syndrome * the caller passed us, and cannot use cpu_loop_exit_restore(). */ - cpu_restore_state(cs, ra, true); + cpu_restore_state(cs, ra); raise_exception(env, excp, syndrome, target_el); } =20 diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 69b0dc69df..0f4f4fc809 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -156,7 +156,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr va= ddr, ARMMMUFaultInfo fi =3D {}; =20 /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); + cpu_restore_state(cs, retaddr); =20 fi.type =3D ARMFault_Alignment; arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); @@ -196,7 +196,7 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr= physaddr, ARMMMUFaultInfo fi =3D {}; =20 /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); + cpu_restore_state(cs, retaddr); =20 fi.ea =3D arm_extabort_type(response); fi.type =3D ARMFault_SyncExternal; @@ -252,7 +252,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, return false; } else { /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); + cpu_restore_state(cs, retaddr); arm_deliver_fault(cpu, address, access_type, mmu_idx, fi); } } @@ -271,7 +271,7 @@ void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr, * We report both ESR and FAR to signal handlers. * For now, it's easiest to deliver the fault normally. */ - cpu_restore_state(cs, ra, true); + cpu_restore_state(cs, ra); arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi); } =20 diff --git a/target/cris/helper.c b/target/cris/helper.c index 91e4aeb178..81a72699b5 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -87,7 +87,7 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, cs->exception_index =3D EXCP_BUSFAULT; env->fault_vector =3D res.bf_vec; if (retaddr) { - if (cpu_restore_state(cs, retaddr, true)) { + if (cpu_restore_state(cs, retaddr)) { /* Evaluate flags after retranslation. */ helper_top_evaluate_flags(env); } diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/s= vm_helper.c index 8e88567399..2d27731b60 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -704,7 +704,7 @@ void cpu_vmexit(CPUX86State *env, uint32_t exit_code, u= int64_t exit_info_1, { CPUState *cs =3D env_cpu(env); =20 - cpu_restore_state(cs, retaddr, true); + cpu_restore_state(cs, retaddr); =20 qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmexit(%08x, %016" PRIx64 ", %016" PRIx64 ", " TARGET_FMT_lx ")!\n", diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 5da176d642..1ce850bbc5 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -460,7 +460,7 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr p= hysaddr, vaddr addr, M68kCPU *cpu =3D M68K_CPU(cs); CPUM68KState *env =3D &cpu->env; =20 - cpu_restore_state(cs, retaddr, true); + cpu_restore_state(cs, retaddr); =20 if (m68k_feature(env, M68K_FEATURE_M68040)) { env->mmu.mmusr =3D 0; @@ -558,7 +558,7 @@ raise_exception_format2(CPUM68KState *env, int tt, int = ilen, uintptr_t raddr) cs->exception_index =3D tt; =20 /* Recover PC and CC_OP for the beginning of the insn. */ - cpu_restore_state(cs, raddr, true); + cpu_restore_state(cs, raddr); =20 /* Flags are current in env->cc_*, or are undefined. */ env->cc_op =3D CC_OP_FLAGS; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index a607fe68e5..98bdb82de8 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -277,7 +277,7 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr add= r, uint32_t esr, iflags; =20 /* Recover the pc and iflags from the corresponding insn_start. */ - cpu_restore_state(cs, retaddr, true); + cpu_restore_state(cs, retaddr); iflags =3D cpu->env.iflags; =20 qemu_log_mask(CPU_LOG_INT, diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index 2e30d0a908..0aaf33ffc2 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -40,7 +40,7 @@ void nios2_cpu_loop_exit_advance(CPUNios2State *env, uint= ptr_t retaddr) * Do this here, rather than in restore_state_to_opc(), * lest we affect QEMU internal exceptions, like EXCP_DEBUG. */ - cpu_restore_state(cs, retaddr, true); + cpu_restore_state(cs, retaddr); env->pc +=3D 4; cpu_loop_exit(cs); } diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index dde2fa1623..ec145960e3 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -45,7 +45,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong sp= r, target_ulong rb) break; =20 case TO_SPR(0, 16): /* NPC */ - cpu_restore_state(cs, GETPC(), true); + cpu_restore_state(cs, GETPC()); /* ??? Mirror or1ksim in not trashing delayed branch state when "jumping" to the current instruction. */ if (env->pc !=3D rb) { @@ -131,7 +131,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong = spr, target_ulong rb) case TO_SPR(8, 0): /* PMR */ env->pmr =3D rb; if (env->pmr & PMR_DME || env->pmr & PMR_SME) { - cpu_restore_state(cs, GETPC(), true); + cpu_restore_state(cs, GETPC()); env->pc +=3D 4; cs->halted =3D 1; raise_exception(cpu, EXCP_HALTED); diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 43f2480e94..3ded309265 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -2414,7 +2414,7 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr = vaddr, uint32_t insn; =20 /* Restore state and reload the insn we executed, for filling in DSISR= . */ - cpu_restore_state(cs, retaddr, true); + cpu_restore_state(cs, retaddr); insn =3D cpu_ldl_code(env, env->nip); =20 switch (env->mmu_model) { diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 29ccf70df1..2cd6d062b9 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -39,7 +39,7 @@ G_NORETURN void tcg_s390_program_interrupt(CPUS390XState = *env, { CPUState *cs =3D env_cpu(env); =20 - cpu_restore_state(cs, ra, true); + cpu_restore_state(cs, ra); qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n", env->psw.addr); trigger_pgm_exception(env, code); diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index a79c838a92..532ae6b74c 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -31,7 +31,7 @@ void raise_exception_sync_internal(CPUTriCoreState *env, = uint32_t class, int tin { CPUState *cs =3D env_cpu(env); /* in case we come from a helper-call we need to restore the PC */ - cpu_restore_state(cs, pc, true); + cpu_restore_state(cs, pc); =20 /* Tin is loaded into d[15] */ env->gpr_d[15] =3D tin; diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index e0a9caab4b..2aa9777a8e 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -253,7 +253,7 @@ void xtensa_cpu_do_unaligned_access(CPUState *cs, =20 assert(xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION)); - cpu_restore_state(CPU(cpu), retaddr, true); + cpu_restore_state(CPU(cpu), retaddr); HELPER(exception_cause_vaddr)(env, env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr); @@ -284,7 +284,7 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, } else if (probe) { return false; } else { - cpu_restore_state(cs, retaddr, true); + cpu_restore_state(cs, retaddr); HELPER(exception_cause_vaddr)(env, env->pc, ret, address); } } @@ -297,7 +297,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, vaddr addr, XtensaCPU *cpu =3D XTENSA_CPU(cs); CPUXtensaState *env =3D &cpu->env; =20 - cpu_restore_state(cs, retaddr, true); + cpu_restore_state(cs, retaddr); HELPER(exception_cause_vaddr)(env, env->pc, access_type =3D=3D MMU_INST_FETCH ? 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([172.58.176.235]) by smtp.gmail.com with ESMTPSA id u8-20020a9d4d88000000b006618586b850sm2473857otk.46.2022.10.30.22.40.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 22:40:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=i4zXGhAahLgSXdO3U/esGQ4mxgb9DP6esDERUUVmeB4=; b=v690nMUk+aUOCBbF8KBNfMPy7DDyo1NIrel5zhYqBjxZf9MmF5cBB5Huc71fGiS/nc BwfQ0y12CqdO/0A8J9q3A9X9KVc+LBtz97XQLCc0TuUdQiNLf2yCLK4306WA+a/rI3Ig ueY8YqUeem7jp0+9HwjkS7O9UI6l9a6EcB+MfX/5q5XnA6UclZs5j6ZJ4YeAUbAh78Mv 37N8/WLUJXwAjfBYMk1XaWG1P6+865MFJCgP5Lqzm6Wircqp2RLwXLkfYCZk21Wje0Yb qxGcmLVsTIeTqshh+8ryhUW353+2HSTuDqMySoOocCfKVNWtNJDg/C8m8XsYjjy1kWy8 NdfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i4zXGhAahLgSXdO3U/esGQ4mxgb9DP6esDERUUVmeB4=; b=J35eT8RymXPVOiiORAk5BY5UO2YQBMIMgx90LiT9xXMMhqT2dmstVmi4JCAB58hUMy 77LdE4vzGxsXX4HNfA67p56gh4WdBlHmlU+ejjz/3IjgogxrLBfwqwqVGHKpaiSPr8n6 HaYt2hDSmrc5LHIsXxN2JbkCwhqsTUn76IZh5NoZQiplOkwHfvou5pYGYivCLekWuWXy GfOUY8e7TIG79aFLMJXotfxcXSJvHxhjhN0Xw3Je5NX+b/9frN4G4MeaPBa8Nj/ZY7oy IivoD3jkDoUmm1dNvi0AD8MJwCrgsfSYCYUEJbJjupIP9189y7/7i7y5g230T4f3zCp7 bAYw== X-Gm-Message-State: ACrzQf2Qi1jpozrd1sNtxwGa8GilE0JUkZh5Kcrc9sPIJuAdYg0oVcPf ny6QVIiE7OlfP9bHIPOyN3MMAdMyC6dodQ== X-Google-Smtp-Source: AMsMyM5bdwkBAK/whIIi+UT9skVv7lg0Im47bpMAnoAjU0vTJODKlZALyvLdgIBfFurdM0RK3hIk/A== X-Received: by 2002:a05:6870:970e:b0:13c:5da4:aeb0 with SMTP id n14-20020a056870970e00b0013c5da4aeb0mr11772929oaq.27.1667194846093; Sun, 30 Oct 2022 22:40:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Claudio Fontana Subject: [PULL 10/11] accel/tcg: Remove reset_icount argument from cpu_restore_state_from_tb Date: Mon, 31 Oct 2022 16:39:47 +1100 Message-Id: <20221031053948.3408-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221031053948.3408-1-richard.henderson@linaro.org> References: <20221031053948.3408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1667194902403100001 Content-Type: text/plain; charset="utf-8" The value passed is always true. Reviewed-by: Claudio Fontana Signed-off-by: Richard Henderson --- accel/tcg/internal.h | 2 +- accel/tcg/tb-maint.c | 4 ++-- accel/tcg/translate-all.c | 15 +++++++-------- 3 files changed, 10 insertions(+), 11 deletions(-) diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h index 9c06b320b7..cb13bade4f 100644 --- a/accel/tcg/internal.h +++ b/accel/tcg/internal.h @@ -107,7 +107,7 @@ TranslationBlock *tb_link_page(TranslationBlock *tb, tb= _page_addr_t phys_pc, tb_page_addr_t phys_page2); bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc); void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, - uintptr_t host_pc, bool reset_icount); + uintptr_t host_pc); =20 /* Return the current PC from CPU, which may be cached in TB. */ static inline target_ulong log_pc(CPUState *cpu, const TranslationBlock *t= b) diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index c8e921089d..0cdb35548c 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -536,7 +536,7 @@ tb_invalidate_phys_page_range__locked(struct page_colle= ction *pages, * restore the CPU state. */ current_tb_modified =3D true; - cpu_restore_state_from_tb(cpu, current_tb, retaddr, true); + cpu_restore_state_from_tb(cpu, current_tb, retaddr); } #endif /* TARGET_HAS_PRECISE_SMC */ tb_phys_invalidate__locked(tb); @@ -685,7 +685,7 @@ bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr= , uintptr_t pc) * function to partially restore the CPU state. */ current_tb_modified =3D true; - cpu_restore_state_from_tb(cpu, current_tb, pc, true); + cpu_restore_state_from_tb(cpu, current_tb, pc); } #endif /* TARGET_HAS_PRECISE_SMC */ tb_phys_invalidate(tb, addr); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 90997fed47..0089578f8f 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -282,12 +282,11 @@ static int cpu_unwind_data_from_tb(TranslationBlock *= tb, uintptr_t host_pc, } =20 /* - * The cpu state corresponding to 'host_pc' is restored. - * When reset_icount is true, current TB will be interrupted and - * icount should be recalculated. + * The cpu state corresponding to 'host_pc' is restored in + * preparation for exiting the TB. */ void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, - uintptr_t host_pc, bool reset_icount) + uintptr_t host_pc) { uint64_t data[TARGET_INSN_START_WORDS]; #ifdef CONFIG_PROFILER @@ -300,7 +299,7 @@ void cpu_restore_state_from_tb(CPUState *cpu, Translati= onBlock *tb, return; } =20 - if (reset_icount && (tb_cflags(tb) & CF_USE_ICOUNT)) { + if (tb_cflags(tb) & CF_USE_ICOUNT) { assert(icount_enabled()); /* * Reset the cycle counter to the start of the block and @@ -333,7 +332,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc) if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) { TranslationBlock *tb =3D tcg_tb_lookup(host_pc); if (tb) { - cpu_restore_state_from_tb(cpu, tb, host_pc, true); + cpu_restore_state_from_tb(cpu, tb, host_pc); return true; } } @@ -1032,7 +1031,7 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t ret= addr) tb =3D tcg_tb_lookup(retaddr); if (tb) { /* We can use retranslation to find the PC. */ - cpu_restore_state_from_tb(cpu, tb, retaddr, true); + cpu_restore_state_from_tb(cpu, tb, retaddr); tb_phys_invalidate(tb, -1); } else { /* The exception probably happened in a helper. The CPU state sho= uld @@ -1068,7 +1067,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retadd= r) cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=3D%p", (void *)retaddr); } - cpu_restore_state_from_tb(cpu, tb, retaddr, true); + cpu_restore_state_from_tb(cpu, tb, retaddr); =20 /* * Some guests must re-execute the branch when re-executing a delay --=20 2.34.1 From nobody Sat May 18 10:30:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1667194884; cv=none; d=zohomail.com; s=zohoarc; b=EJtsOlUTk5vF6aokFpSpHcR8RBY/dX1itC++YmfzSZfSxdur+Xp2K2bxCM6txpS1qFDwkGZAOl0gD8oPNEwUGm/PTLtQnELgA2gT3rU50+a+fZmCbO6cTDo2AWPC5dS1yofj10ulz7sYfE3K99kQbBaMUYzdKMzkGccqWomx9sg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667194884; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aw7jRTpy1iP2UJDNtDZiMejQvGcVoKkChHzFJ9QsKgc=; b=CYI04coHwm2WpOSdyNyzWXxZbZrJQNKh6RR3+lbOw6idyFK+9My4CAefAcGFgKgf7THtIBEvoCWmnWPvuxFBBKUC5eHmTBTfnoANf+gQ/KJkaRPzG4rLWlLVI96dWJhgG911wSFMVsXZeLrPKoPov437Zsr3sWRh8dcX6cjDh4M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1667194884805451.3891140817824; Sun, 30 Oct 2022 22:41:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opNXe-0001wz-Ol; Mon, 31 Oct 2022 01:40:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opNXZ-0001ri-N0 for qemu-devel@nongnu.org; Mon, 31 Oct 2022 01:40:54 -0400 Received: from mail-oi1-x22e.google.com ([2607:f8b0:4864:20::22e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opNXY-00048a-0f for qemu-devel@nongnu.org; Mon, 31 Oct 2022 01:40:53 -0400 Received: by mail-oi1-x22e.google.com with SMTP id v81so3208415oie.5 for ; Sun, 30 Oct 2022 22:40:51 -0700 (PDT) Received: from stoup.. ([172.58.176.235]) by smtp.gmail.com with ESMTPSA id u8-20020a9d4d88000000b006618586b850sm2473857otk.46.2022.10.30.22.40.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 22:40:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aw7jRTpy1iP2UJDNtDZiMejQvGcVoKkChHzFJ9QsKgc=; b=Un+AIRQPZN56Lav+uorxyAsutVxiJEdIXGcK+09Ren2aEYrLqyt23BK+5KxV5E7pLu E97QIM/l/2vI5k01FISxjjr2fm/EbRi8cEVYsg6u7DoiCN4kcnXuoNoyrNeK7LmY0bZa sC+c2M45a8JpOC7nrdQhfLATT+JdyEacVcYFDJrPvQ5skWZP5gtbVqT8b84WPj0Z4UIk 2b+1nkIZO3S7VjOMUPza+KuA+2DU7hqSXyacBhCbaHK8CDb3J9YxCubWCSovBg+SSA+m BKB9Q5YDpD1sefVP5absnfdVpgaFsfno8Hiq1yM3qGFFbkzd9fK5Ql2GCmMzcj95llNQ C0jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aw7jRTpy1iP2UJDNtDZiMejQvGcVoKkChHzFJ9QsKgc=; b=M9kIRpDRm02chY+bzS5hxmbQYaBx7wgJ5afjfLjF8zmAKVCGGceFxZSOQQKjRDjxz7 A7+o36tRFHrBfD/63cpLVf0kaDmFuWDOiUaBCSDK0rffizNXzVxAU4QDLShtM2env659 rKE1rolNpRTSejrwHJOeOMq6OCf4ZCS749Z4NCOTz2Zu6sPsfHpnuCwrvgFjlIWQz5Sj JVi82qCWNkIWTH4pN+f6sBnAroyF9f/DzdERDV9M2eB+MibGckIFR107VOEH7nILqjt1 apY39Xnds1KWTe1ihmq5Ud6AGEUQDRP0kzFLXINCr4XyDW9vKcdnPO9RRLYaolyf+UCv qNHg== X-Gm-Message-State: ACrzQf0yvTh3Z9Mjw+z1PnrS+bYqINxHPFGtN/iT/FVvQb+9wHu8lD8k BHz0GxeQdG148CWKl4US0h9hG1Hom9qIIQ== X-Google-Smtp-Source: AMsMyM4eG1Ra0CczidvMGuOyMGgccTl14UBwDd+CyS66g2zujwW9mhNT/xcQXNFCi0EDbF/HnG5DWw== X-Received: by 2002:a05:6808:2082:b0:359:f4e9:8f13 with SMTP id s2-20020a056808208200b00359f4e98f13mr3746976oiw.170.1667194850888; Sun, 30 Oct 2022 22:40:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 11/11] target/i386: Expand eflags updates inline Date: Mon, 31 Oct 2022 16:39:48 +1100 Message-Id: <20221031053948.3408-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221031053948.3408-1-richard.henderson@linaro.org> References: <20221031053948.3408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1667194886390100004 The helpers for reset_rf, cli, sti, clac, stac are completely trivial; implement them inline. Drop some nearby #if 0 code. Reviewed-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/i386/helper.h | 5 ----- target/i386/tcg/cc_helper.c | 41 ------------------------------------- target/i386/tcg/translate.c | 30 ++++++++++++++++++++++----- 3 files changed, 25 insertions(+), 51 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index 88143b2a24..b7de5429ef 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -56,13 +56,8 @@ DEF_HELPER_2(syscall, void, env, int) DEF_HELPER_2(sysret, void, env, int) #endif DEF_HELPER_FLAGS_2(pause, TCG_CALL_NO_WG, noreturn, env, int) -DEF_HELPER_1(reset_rf, void, env) DEF_HELPER_FLAGS_3(raise_interrupt, TCG_CALL_NO_WG, noreturn, env, int, in= t) DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, int) -DEF_HELPER_1(cli, void, env) -DEF_HELPER_1(sti, void, env) -DEF_HELPER_1(clac, void, env) -DEF_HELPER_1(stac, void, env) DEF_HELPER_3(boundw, void, env, tl, int) DEF_HELPER_3(boundl, void, env, tl, int) =20 diff --git a/target/i386/tcg/cc_helper.c b/target/i386/tcg/cc_helper.c index cc7ea9e8b9..6227dbb30b 100644 --- a/target/i386/tcg/cc_helper.c +++ b/target/i386/tcg/cc_helper.c @@ -346,44 +346,3 @@ void helper_clts(CPUX86State *env) env->cr[0] &=3D ~CR0_TS_MASK; env->hflags &=3D ~HF_TS_MASK; } - -void helper_reset_rf(CPUX86State *env) -{ - env->eflags &=3D ~RF_MASK; -} - -void helper_cli(CPUX86State *env) -{ - env->eflags &=3D ~IF_MASK; -} - -void helper_sti(CPUX86State *env) -{ - env->eflags |=3D IF_MASK; -} - -void helper_clac(CPUX86State *env) -{ - env->eflags &=3D ~AC_MASK; -} - -void helper_stac(CPUX86State *env) -{ - env->eflags |=3D AC_MASK; -} - -#if 0 -/* vm86plus instructions */ -void helper_cli_vm(CPUX86State *env) -{ - env->eflags &=3D ~VIF_MASK; -} - -void helper_sti_vm(CPUX86State *env) -{ - env->eflags |=3D VIF_MASK; - if (env->eflags & VIP_MASK) { - raise_exception_ra(env, EXCP0D_GPF, GETPC()); - } -} -#endif diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 546c427c23..0ee548ce56 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2746,6 +2746,26 @@ static void gen_reset_hflag(DisasContext *s, uint32_= t mask) } } =20 +static void gen_set_eflags(DisasContext *s, target_ulong mask) +{ + TCGv t =3D tcg_temp_new(); + + tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, eflags)); + tcg_gen_ori_tl(t, t, mask); + tcg_gen_st_tl(t, cpu_env, offsetof(CPUX86State, eflags)); + tcg_temp_free(t); +} + +static void gen_reset_eflags(DisasContext *s, target_ulong mask) +{ + TCGv t =3D tcg_temp_new(); + + tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, eflags)); + tcg_gen_andi_tl(t, t, ~mask); + tcg_gen_st_tl(t, cpu_env, offsetof(CPUX86State, eflags)); + tcg_temp_free(t); +} + /* Clear BND registers during legacy branches. */ static void gen_bnd_jmp(DisasContext *s) { @@ -2776,7 +2796,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool= recheck_tf, bool jr) } =20 if (s->base.tb->flags & HF_RF_MASK) { - gen_helper_reset_rf(cpu_env); + gen_reset_eflags(s, RF_MASK); } if (recheck_tf) { gen_helper_rechecking_single_step(cpu_env); @@ -5502,12 +5522,12 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) #endif case 0xfa: /* cli */ if (check_iopl(s)) { - gen_helper_cli(cpu_env); + gen_reset_eflags(s, IF_MASK); } break; case 0xfb: /* sti */ if (check_iopl(s)) { - gen_helper_sti(cpu_env); + gen_set_eflags(s, IF_MASK); /* interruptions are enabled only the first insn after sti */ gen_update_eip_next(s); gen_eob_inhibit_irq(s, true); @@ -5789,7 +5809,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) || CPL(s) !=3D 0) { goto illegal_op; } - gen_helper_clac(cpu_env); + gen_reset_eflags(s, AC_MASK); s->base.is_jmp =3D DISAS_EOB_NEXT; break; =20 @@ -5798,7 +5818,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) || CPL(s) !=3D 0) { goto illegal_op; } - gen_helper_stac(cpu_env); + gen_set_eflags(s, AC_MASK); s->base.is_jmp =3D DISAS_EOB_NEXT; break; =20 --=20 2.34.1