From nobody Sat May 11 15:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1666548231504202.80214622604; Sun, 23 Oct 2022 11:03:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omfAt-0001NC-FY for importer@patchew.org; Sun, 23 Oct 2022 13:54:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omd2S-0005zz-CN for qemu-devel@nongnu.org; Sun, 23 Oct 2022 11:37:25 -0400 Received: from mail-out-4.itc.rwth-aachen.de ([2a00:8a60:1:e501::5:49]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omd2N-0006L4-9C for qemu-devel@nongnu.org; Sun, 23 Oct 2022 11:37:24 -0400 Received: from rwthex-s2-b.rwth-ad.de ([134.130.26.155]) by mail-in-4.itc.rwth-aachen.de with ESMTP; 23 Oct 2022 17:37:11 +0200 Received: from localhost.localdomain (2a02:908:1088:5920:10a7:3a65:7c9d:55ef) by RWTHEX-S2-B.rwth-ad.de (2a00:8a60:1:e500::26:155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.15; Sun, 23 Oct 2022 17:37:12 +0200 X-IPAS-Result: =?us-ascii?q?A2CrAAC8Q0Vj/5sagoZaHAEBAQEBAQcBARIBAQQEAQFAg?= =?us-ascii?q?T4EAQELAYR9hE6RGIETngALAQEBAQEBAQEBCAFCBAEBhQECAgKEdSY3Bg4BA?= =?us-ascii?q?gQBAQEBAwIDAQEBAQEBAwEBBgEBAQEBAQYEgRyFL0aGQwIBAyMECwFGECAFA?= =?us-ascii?q?iYCAlcGDgWCfYMhrRR/M4EBhHCJcQkBgQcsAYhQgiuFNIJQgRWCc3WEYTCDC?= =?us-ascii?q?oJmBJo5HDgDCQMHBSwdQAMLHw0WNRgDFAMFIQcDGQ8jDQ0EHQwDAwUlAwICG?= =?us-ascii?q?wcCAgMCBhMFAgI1GDQIBAgEKyQPBQIHLwUELwIeBAUGEQgCFgIGBAQEBBUCE?= =?us-ascii?q?AgCCCYXBxMzGQEFMicOCSEcDhoNBQYTAyBvBQc7DygvaSsdGweBDCooFQMEB?= =?us-ascii?q?AMCBhMDIAINKTEUBCkTDy0HKXEJAgMiZQUDAwQoLAMJQAcoJDwHWDoFAwIQI?= =?us-ascii?q?jwGAwkDAiRZdDASFAUDDRcmCAU3GwQIPAIFBlITAgoSAxIPLUkPSj47FwicW?= =?us-ascii?q?IEOpAqhAgeCG6FqTJZ0ApIWlxGiBoEYhCgCBAIEBQIWgXeBf3GDNlEXAg+OL?= =?us-ascii?q?BYVjhtzOwIGAQoBAQMJiwoBAQ?= IronPort-Data: A9a23:Xshf86/AGzuE14Qrpfc5DrUD33+TJUtcMsCJ2f8bNWPcYEJGY0x3y mYeW2+Obv+KNDfxeIxyPI3i8k9U6MKBydBlTwdv+C1EQiMRo6IpJzg4wmTYYnnOdJ2TFCqLy +1EN7Es+ehtFie0Si+Fa+Sn9z8kvU2xbuKUIPbePSxsThNTRi4kiBZy88Y0mYcAbeKRWmthg vuv5ZyCULOZ82QsaDhNs/va8EkHUMna4Vv0gHRvPZing3eDzxH5PLpHTYmtIn3xRJVjH+LSb 44vG5ngows1Vz90Yj+Uuu6Tnn8iG9Y+DiDS4pZiYJVOtzAZzsAE+vthaKBMOR8/ZwKhxLidw P0V3XC5pJxA0qfkwIzxWDEAe81y0DEvFLLveRCCXcKvI0LuQ1DlyehICRENIog6y+xHUWhur vYBEWVYBvyDr7reLLOTcNZQpukTafKxealZoG58zXTQAbAqTPgvQY2TvoMehWxowJoQW6+DO qL1ahI2BPjESwFIMFYeE9Qkm+qog3T7WydHtFLQrKM842XVigB8uFToGIOLIobVGZQPxi50o Ero+0/bLRAFaeCjyAW/7kqonuLBgxzCDdd6+LqQs6QCbEeo7nUeDQBTWValrP2RjEm4VNRCb UsO9UIGtaUu+VbtS9DsUxC8pFaAvxgVQd0WFPc1gDxh0YLO/BqZC3hBVWQEYpo8q9M2ADUmk FOE9z/0OQFSXHSuYSr13t+pQfmaYED58Udqifc4cDY4 IronPort-HdrOrdr: A9a23:+5PIa6HArULrRPuJpLqE0ceALOsnbusQ8zAXPidKOHtom62j5q STdZEgvnXJYVkqNU3I5urwXpVoLUmyyXcN2/hyAV7AZniChILLFuFfBOLZqlXd8kvFmNK1vp 0AT0ERMrHN5CBB/KXHCQCDYq8d/OU= X-IronPort-Anti-Spam-Filtered: true X-IronPort-AV: E=Sophos;i="5.95,176,1661810400"; d="scan'208";a="160274920" From: To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH v4 1/7] target/arm: Don't add all MIDR aliases for cores that immplement PMSA Date: Sun, 23 Oct 2022 17:36:53 +0200 Message-ID: <20221023153659.121138-2-tobias.roehmel@rwth-aachen.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221023153659.121138-1-tobias.roehmel@rwth-aachen.de> References: <20221023153659.121138-1-tobias.roehmel@rwth-aachen.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [2a02:908:1088:5920:10a7:3a65:7c9d:55ef] X-ClientProxiedBy: rwthex-s4-b.rwth-ad.de (2a00:8a60:1:e500::26:165) To RWTHEX-S2-B.rwth-ad.de (2a00:8a60:1:e500::26:155) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:8a60:1:e501::5:49; envelope-from=tobias.roehmel@rwth-aachen.de; helo=mail-out-4.itc.rwth-aachen.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1666548232706100001 From: Tobias R=C3=B6hmel Cores with PMSA have the MPUIR register which has the same encoding as the MIDR alias with opc2=3D4. So we only add that alias if we are not realizing a core that implements PMSA. Signed-off-by: Tobias R=C3=B6hmel Reviewed-by: Richard Henderson --- target/arm/helper.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index db3b1ea72d..3c517356e1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8025,10 +8025,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, .resetvalue =3D = cpu->midr, .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), .readfn =3D midr_read }, - /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 4,7 : AArch32 aliases= of MIDR */ - { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, - .access =3D PL1_R, .resetvalue =3D cpu->midr }, + /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 7 : AArch32 aliases o= f MIDR */ { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 7, .access =3D PL1_R, .resetvalue =3D cpu->midr }, @@ -8038,6 +8035,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .accessfn =3D access_aa64_tid1, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->revidr }, }; + ARMCPRegInfo id_v8_midr_alias_cp_reginfo =3D { + .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, + .access =3D PL1_R, .resetvalue =3D cpu->midr + }; ARMCPRegInfo id_cp_reginfo[] =3D { /* These are common to v8 and pre-v8 */ { .name =3D "CTR", @@ -8101,8 +8103,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) id_mpuir_reginfo.access =3D PL1_RW; id_tlbtr_reginfo.access =3D PL1_RW; } + if (arm_feature(env, ARM_FEATURE_V8)) { define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); + if (!arm_feature(env, ARM_FEATURE_PMSA)) { + define_one_arm_cp_reg(cpu, &id_v8_midr_alias_cp_reginfo); + } } else { define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); } --=20 2.34.1 From nobody Sat May 11 15:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1666586257585871.6676264869296; Sun, 23 Oct 2022 21:37:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omfZY-0003S4-3i for importer@patchew.org; Sun, 23 Oct 2022 14:19:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omd2U-00061W-NB for qemu-devel@nongnu.org; Sun, 23 Oct 2022 11:37:27 -0400 Received: from mail-out-4.itc.rwth-aachen.de ([2a00:8a60:1:e501::5:49]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omd2S-0006L4-Pm for qemu-devel@nongnu.org; Sun, 23 Oct 2022 11:37:26 -0400 Received: from rwthex-s2-b.rwth-ad.de ([134.130.26.155]) by mail-in-4.itc.rwth-aachen.de with ESMTP; 23 Oct 2022 17:37:11 +0200 Received: from localhost.localdomain (2a02:908:1088:5920:10a7:3a65:7c9d:55ef) by RWTHEX-S2-B.rwth-ad.de (2a00:8a60:1:e500::26:155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.15; Sun, 23 Oct 2022 17:37:12 +0200 X-IPAS-Result: =?us-ascii?q?A2DQAgC8Q0Vj/5sagoZaHAEBAQEBAQcBARIBAQQEAQFAg?= =?us-ascii?q?U+EfoROkRUDnSuBaAsBAQEBAQEBAQEIAUIEAQGFAQICAoR1JjgTAQIEAQEBA?= =?us-ascii?q?QMCAwEBAQEBAQMBAQYBAQEBAQEGBIEchS9GhkMCAQMjBAsBRhAgBQImAgJXB?= =?us-ascii?q?g4Fgn2DIa0UfzOBAYRwiXEJAYEHLIhRgiuFNIJQglGBNwduhCs2MIMKgmYEk?= =?us-ascii?q?iKIFxw4AwkDBwUsHUADCx8NFjUYAxQDBSEHAxkPIw0NBB0MAwMFJQMCAhsHA?= =?us-ascii?q?gIDAgYTBQICNRg0CAQIBCskDwUCBy8FBC8CHgQFBhEIAhYCBgQEBAQVAhAIA?= =?us-ascii?q?ggmFwcTMxkBBTInDgkhHA4aDQUGEwMgbwUHOw8oL2krHRsHgQwqKBUDBAQDA?= =?us-ascii?q?gYTAyACDSkxFAQpEw8tBylxCQIDImUFAwMEKCwDCQQ8BygkPAdYOgUDAhAiP?= =?us-ascii?q?AYDCQMCJBhBdDASFAUDDRcmCAU3GwQIDi4CBQZHCxMCChIDEg8tSQcISj47F?= =?us-ascii?q?wibZnEBgQ+DMaBYoQIHghuhakyWdAKSFoIIhEgBkECiBoEYhCgCBAIEBQIWg?= =?us-ascii?q?XiBfnGDNlEXAg+OLBaOMHM7AgYBCgEBAwmLCgEB?= IronPort-Data: A9a23:4hHAoKLApjhidsoCFE+RjpQlxSXFcZb7ZxGr2PjKsXjdYENShjwGn GAcCmmFOKuPMWSmLdBwYdiy8BsPuJLdndBqHgsd+CA2RRqmiyZk6fexcx2sZXPCdqUvaGo9s q3yv/GZdJhcokf0/0vraP65xZVF/fngbqLmD+LZMTxGSwZhSSMw4TpugOdRbrRA2LBVOCvQ/ 4KvyyHjEAX9gWQtajtNs/jrRC5H5ZwehhtJ5jTSWtgW5Dcyp1FNZLoDKKe4KWfPQ4U8NoZWk M6akdlVVkuAl/scIovNfoTTKyXmcZaOVeS6sUe6boD56vR0jnFojvxrZKJ0hXB/0F1ll/gpo DlEWAfZpQ0BZsUgk8xFO/VU/r0X0aBuoNf6zXaDXcO7kGr0Ymf0ws5VFmITB6wX1OFvKGVF3 KlNQNwNRkjra+Oe+o2HasRcw/95aeOtJpwDujRpwXfVAJ7KQ7iaGPmMvIQAmm1uwJkTQJ4yZ OJAAdZrRAjHaRxGIREND58+meqsrmPgbz0doVuepacxpWTepOB0+OGzaICKJo3QH625mG67m ziBwWjoAyhAd/XC6BG89UyjmrLAyHaTtIU6UefQGuRRqESew3FWBBAIWF+Tp/6/hUijHdVFJ CQ84icyoLJ08UW6QtT5WzW8oXiNpBlaXMBfe9DW8ymX1bbU7hbcHTJBRHhbd8Am8cY6AzAnv rOUo+7U6fVUmOX9YRqgGn289Fte5QB9wbc+WBI5 IronPort-HdrOrdr: A9a23:TYJd/6PDbC3H0cBcTvijsMiBIKoaSvp037BN7TEXdfU1SL39qy nKpp9w6faaslsssQ4b6La90cW7Lk80jKQFg7X5Xo3SOTUO2lHJEGgK1+KL/9SHIUPDH4VmtJ uIHZITNDSJNykYsS/y2njAL+od X-IronPort-Anti-Spam-Filtered: true X-IronPort-AV: E=Sophos;i="5.95,176,1661810400"; d="scan'208";a="160274922" From: To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH v4 2/7] target/arm: Make RVBAR available for all ARMv8 CPUs Date: Sun, 23 Oct 2022 17:36:54 +0200 Message-ID: <20221023153659.121138-3-tobias.roehmel@rwth-aachen.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221023153659.121138-1-tobias.roehmel@rwth-aachen.de> References: <20221023153659.121138-1-tobias.roehmel@rwth-aachen.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [2a02:908:1088:5920:10a7:3a65:7c9d:55ef] X-ClientProxiedBy: rwthex-s4-b.rwth-ad.de (2a00:8a60:1:e500::26:165) To RWTHEX-S2-B.rwth-ad.de (2a00:8a60:1:e500::26:155) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:8a60:1:e501::5:49; envelope-from=tobias.roehmel@rwth-aachen.de; helo=mail-out-4.itc.rwth-aachen.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1666586259689100001 From: Tobias R=C3=B6hmel RVBAR shadows RVBAR_ELx where x is the highest exception level if the highest EL is not EL3. This patch also allows ARMv8 CPUs to change the reset address with the rvbar property. Signed-off-by: Tobias R=C3=B6hmel Reviewed-by: Peter Maydell --- target/arm/cpu.c | 6 +++++- target/arm/helper.c | 23 +++++++++++++++-------- 2 files changed, 20 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 94ca6f163f..b642749d6d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -281,6 +281,10 @@ static void arm_cpu_reset(DeviceState *dev) env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, CPACR, CP11, 3); #endif + if (arm_feature(env, ARM_FEATURE_V8)) { + env->cp15.rvbar =3D cpu->rvbar_prop; + env->regs[15] =3D cpu->rvbar_prop; + } } =20 #if defined(CONFIG_USER_ONLY) @@ -1306,7 +1310,7 @@ void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_proper= ty); } =20 - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { object_property_add_uint64_ptr(obj, "rvbar", &cpu->rvbar_prop, OBJ_PROP_FLAG_READWRITE); diff --git a/target/arm/helper.c b/target/arm/helper.c index 3c517356e1..2e9e420d4e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7768,8 +7768,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (!arm_feature(env, ARM_FEATURE_EL3) && !arm_feature(env, ARM_FEATURE_EL2)) { ARMCPRegInfo rvbar =3D { - .name =3D "RVBAR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc2 = =3D 1, + .name =3D "RVBAR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .cp =3D 15, .opc1 =3D 0, .crn =3D 12, .crm = =3D 0, .opc2 =3D 1, .access =3D PL1_R, .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar), }; @@ -7859,13 +7859,20 @@ void register_cp_regs_for_features(ARMCPU *cpu) } /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ if (!arm_feature(env, ARM_FEATURE_EL3)) { - ARMCPRegInfo rvbar =3D { - .name =3D "RVBAR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 = =3D 1, - .access =3D PL2_R, - .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar), + ARMCPRegInfo rvbar[] =3D { + { + .name =3D "RVBAR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .op= c2 =3D 1, + .access =3D PL2_R, + .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar), + }, + { .name =3D "RVBAR", .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc= 2 =3D 1, + .access =3D PL2_R, + .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar), + }, }; - define_one_arm_cp_reg(cpu, &rvbar); + define_arm_cp_regs(cpu, rvbar); } } =20 --=20 2.34.1 From nobody Sat May 11 15:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1666553492048361.7830289938843; Sun, 23 Oct 2022 12:31:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omg2O-0005eb-NL for importer@patchew.org; Sun, 23 Oct 2022 14:49:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omd2V-00062F-MP for qemu-devel@nongnu.org; Sun, 23 Oct 2022 11:37:27 -0400 Received: from mail-out-4.itc.rwth-aachen.de ([2a00:8a60:1:e501::5:49]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omd2T-0006NF-GF for qemu-devel@nongnu.org; Sun, 23 Oct 2022 11:37:27 -0400 Received: from rwthex-s2-b.rwth-ad.de ([134.130.26.155]) by mail-in-4.itc.rwth-aachen.de with ESMTP; 23 Oct 2022 17:37:12 +0200 Received: from localhost.localdomain (2a02:908:1088:5920:10a7:3a65:7c9d:55ef) by RWTHEX-S2-B.rwth-ad.de (2a00:8a60:1:e500::26:155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.15; Sun, 23 Oct 2022 17:37:12 +0200 X-IPAS-Result: =?us-ascii?q?A2DQAgC8Q0Vj/5sagoZaHAEBAQEBAQcBARIBAQQEAQFAg?= =?us-ascii?q?U+EfoROkRiBE54ACwEBAQEBAQEBAQgBQgQBAYUBAgIChHUmOBMBAgQBAQEBA?= =?us-ascii?q?wIDAQEBAQEBAwEBBgEBAQEBAQYEgRyFL0aGQwIBAyMPAUEFECAFAiYCAlcGD?= =?us-ascii?q?gWCfYMhrRSBMoEBhHCJcQkBgQcsiFGCK4U0glCBFYJzdYRhMIMKgmYEmjkcO?= =?us-ascii?q?AMJAwcFLB1AAwsfDRY1GAMUAwUhBwMZDyMNDQQdDAMDBSUDAgIbBwICAwIGE?= =?us-ascii?q?wUCAjUYNAgECAQrJA8FAgcvBQQvAh4EBQYRCAIWAgYEBAQEFQIQCAIIJhcHE?= =?us-ascii?q?zMZAQUyJw4JIRwOGg0FBhMDIG8FBzsPKC9pKx0bB4EMKigVAwQEAwIGEwMgA?= =?us-ascii?q?g0pMRQEKRMPLQcpcQkCAyJlBQMDBCgsAwlABygkPAdYOgUDAhAiPAYDCQMCJ?= =?us-ascii?q?BNGdDASFAUDDRcmCAU3GwQIPAIFBlITAgoSAxIPLUkPSj47FwicUQeBDoF5N?= =?us-ascii?q?sJdB4IboWpMlnQCkhYtlmSjHoQoAgQCBAUCFoF4gX5xgzZRFwIPnHJzOwIGA?= =?us-ascii?q?QoBAQMJiwoBAQ?= IronPort-Data: A9a23:0PWucarctJaZNGGQEqfyHiDTHJ5eBmJHZBIvgKrLsJaIsI4StFCzt garIBmEPq2KNmv0Kd4kPY+xpk5X6MDVnNdiGVY9rH1jEXlG8uPIVI+TRqvS04J+DeWeFh49v 5VGAjXkBJppJpMJjk71atANlVEliefSAOKU5NfsYkhZXRVjRDoqlSVtkus4hp8AqdWiCmthg /uryyHkEALjimMc3l48sfrZ8ko35a2q4lv0g3RnDRx1lA6G/5UqJM9HTU2BByOQapVZGOe8W 9HCwNmRlo8O105wYj8Nuu+TnnwiGtY+DyDX4pZlc/TKbix5m8AH+v1T2Mw0NB0L0WXZx7id/ /0W3XC4YV9B0qQhA43xWTEAe811FfUuFLMqvRFTvOTLp3AqfUcAzN13A2I/ELUjpdwrLlNM+ u4BCBoNdQ660rfeLLKTEoGAh+wZE/XLEbNagSsl53fDEuomBJnPBanHjTNa9G5r2oYXRq6YP ZRfMGcyBPjDS0Qn1lM/FJU0ne6zwGP4fj1dpVa9v7Ur4y3axQdx3b6rPNe9ltmiHJsNxBnE9 zidl4j/Ki9EOt2UwGecziK93qz/xTHkd6wfNrLto5aGh3XWnAT/EiY+TFa+vLy1h1CzX/pZL Eob/DdoqrI9nGSzQ8XwRVu9qW+IsxoYc95RFeQg70eK0KW83uqCLnIbUj5MeJk97oo8AyY1y l/Mlt+vCTEHXKCpdE9xP4y89VuaURX550dYDcPYZWPpO+Xenbw= IronPort-HdrOrdr: A9a23:98O7Ga2kTrup3Bnm093kEQqjBIMkLtp133Aq2lEZdPRUGvb1qy nIpoV96faUskd0ZJhOo7690cW7K080sKQFgrX5Xo3SOTUO2lHIEGgK1+KLqAEIWReOlNK1vZ 0QFZSWY+eeMbEVt6vHCF7SKadZ/DD+ysCVbLDlvg5QcT0= X-IronPort-Anti-Spam-Filtered: true X-IronPort-AV: E=Sophos;i="5.95,176,1661810400"; d="scan'208";a="160274923" From: To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH v4 3/7] target/arm: Make stage_2_format for cache attributes optional Date: Sun, 23 Oct 2022 17:36:55 +0200 Message-ID: <20221023153659.121138-4-tobias.roehmel@rwth-aachen.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221023153659.121138-1-tobias.roehmel@rwth-aachen.de> References: <20221023153659.121138-1-tobias.roehmel@rwth-aachen.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [2a02:908:1088:5920:10a7:3a65:7c9d:55ef] X-ClientProxiedBy: rwthex-s4-b.rwth-ad.de (2a00:8a60:1:e500::26:165) To RWTHEX-S2-B.rwth-ad.de (2a00:8a60:1:e500::26:155) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:8a60:1:e501::5:49; envelope-from=tobias.roehmel@rwth-aachen.de; helo=mail-out-4.itc.rwth-aachen.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1666553496073100001 From: Tobias R=C3=B6hmel The v8R PMSAv8 has a two-stage MPU translation process, but, unlike VMSAv8, the stage 2 attributes are in the same format as the stage 1 attributes (8-bit MAIR format). Rather than converting the MAIR format to the format used for VMSA stage 2 (bits [5:2] of a VMSA stage 2 descriptor) and then converting back to do the attribute combination, allow combined_attrs_nofwb() to accept s2 attributes that are already in the MAIR format. We move the assert() to combined_attrs_fwb(), because that function really does require a VMSA stage 2 attribute format. (We will never get there for v8R, because PMSAv8 does not implement FEAT_S2FWB.) Signed-off-by: Tobias R=C3=B6hmel Reviewed-by: Peter Maydell --- target/arm/ptw.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2ddfc028ab..db50715fa7 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2105,7 +2105,11 @@ static uint8_t combined_attrs_nofwb(CPUARMState *env, { uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs; =20 - s2_mair_attrs =3D convert_stage2_attrs(env, s2.attrs); + if (s2.is_s2_format) { + s2_mair_attrs =3D convert_stage2_attrs(env, s2.attrs); + } else { + s2_mair_attrs =3D s2.attrs; + } =20 s1lo =3D extract32(s1.attrs, 0, 4); s2lo =3D extract32(s2_mair_attrs, 0, 4); @@ -2163,6 +2167,8 @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr) static uint8_t combined_attrs_fwb(CPUARMState *env, ARMCacheAttrs s1, ARMCacheAttrs s2) { + assert(s2.is_s2_format && !s1.is_s2_format); + switch (s2.attrs) { case 7: /* Use stage 1 attributes */ @@ -2212,7 +2218,6 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *= env, ARMCacheAttrs ret; bool tagged =3D false; =20 - assert(s2.is_s2_format && !s1.is_s2_format); ret.is_s2_format =3D false; =20 if (s1.attrs =3D=3D 0xf0) { --=20 2.34.1 From nobody Sat May 11 15:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166654944848872.25915423540448; Sun, 23 Oct 2022 11:24:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omfNd-0002TG-AP for importer@patchew.org; Sun, 23 Oct 2022 14:07:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omd2U-00061K-DL for qemu-devel@nongnu.org; Sun, 23 Oct 2022 11:37:27 -0400 Received: from mail-out-3.itc.rwth-aachen.de ([2a00:8a60:1:e501::5:48]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omd2S-0006L3-Br for qemu-devel@nongnu.org; Sun, 23 Oct 2022 11:37:26 -0400 Received: from rwthex-s2-b.rwth-ad.de ([134.130.26.155]) by mail-in-3.itc.rwth-aachen.de with ESMTP; 23 Oct 2022 17:37:12 +0200 Received: from localhost.localdomain (2a02:908:1088:5920:10a7:3a65:7c9d:55ef) by RWTHEX-S2-B.rwth-ad.de (2a00:8a60:1:e500::26:155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.15; Sun, 23 Oct 2022 17:37:12 +0200 X-IPAS-Result: =?us-ascii?q?A2AUBAAhREVj/5sagoZaHQEBAQEJARIBBQUBQIFPhH6ET?= =?us-ascii?q?pEYnxMLAQEBAQEBAQEBCAFCBAEBhQECAgKEdSY4EwECBAEBAQEDAgMBAQEBA?= =?us-ascii?q?QEDAQEGAQEBAQEBBgSBHIUvRoZDAgEDIwQLAUYQHQMFAiYCAkkOBg4Fgn2DI?= =?us-ascii?q?a0UfzOBAYRwiXEJAYEHLIhRgiuFNIJQglGBN3WEYTCDCoJmBJIiUYdGHDgDC?= =?us-ascii?q?QMHBSwdQAMLHw0WNRgDFAMFIQcDGQ8jDQ0EHQwDAwUlAwICGwcCAgMCBhMFA?= =?us-ascii?q?gI1GDQIBAgEKyQPBQIHLwUELwIeBAUGEQgCFgIGBAQEBBUCEAgCCCYXBxMzG?= =?us-ascii?q?QEFMicOCSEcDhoNBQYTAyBvBQc7DygvaSsdGweBDCooFQMEBAMCBhMDIAINK?= =?us-ascii?q?TEUBCkTDy0HKXEJAgMiZQUDAwQoLAMJQAcoJDwHWDoFAwIQIjwGAwkDAiQTR?= =?us-ascii?q?nQwEhQFAw0XJggFNxsECDwCBQZSEwIKEgMSDy1JD0o+OxcInFiBD4F7wxAHg?= =?us-ascii?q?huhakyWdAKSFi2RMoUyox6EKAIEAgQFAhaBeIF+cYM2URcCD5xyczsCBgEKA?= =?us-ascii?q?QEDCYsKAQE?= IronPort-Data: A9a23:LQp5MKNqrgzcpPHvrR36lsFynXyQoLVcMsEvi/4bfWQNrUp312QOz mMeDT2Hb/jZNGWmc413boqx9RgHv5CBzodrHHM5pCpnJ55oRWspJvzEdBuqb3PKRiHnZBg6h ynLQoCYdKjYdleF+lH3dOCJQUBUjcmgXqD7BPPPJhd/TAplTDZJoR94kobVuKYx6TSCK17L6 I6aT/H3Ygf/gWcsaztMscpvlTs21BjMkGJA1rABTa0T1LPuvyF9JI4SI6i3M0z5TuF8dgJtb 7+epF0R1jqxEyYFUrtJoJ6iGqE5auK60Ty1t5Zjc/PKbi5q+3ZuiPZrbJLwXm8M49mBt4gZJ NygLvVcQy9xVkHHsLx1vxW1j0iSMIUekIIrL0RTvuTCwE39d2PT6slrCUMWNKoT+eNFLD1Ro KlwxDAlNnhvhsqM/46bZ9kpvZ5mBo/xI58f/3hsiz3UZRokacmYH+OTvocehml2350TdRrdT 5NxhT5HcBPKYhRUfE0QBZI7keOAnGbjc3hRoVmVqKxx72W7IAlZieewbIGMJoXbLSlTth6av VqFzXTHOTYxON+h9Qe/rCmggNaayEsXX6pXTtVU7MVCmVCW2ykfBQMbUXO9pv+2jFP4XMhQQ 2QM9zYjt+43/V2nQ935dxm5pneeuVgbQdU4LgEhwBuS1qrZ80OCXC0OCCRedNxjvcNwSTFCO kK1ou4FzAdH6NW9IU9xPJ/Oxd9uEUD59VM/WBI= IronPort-HdrOrdr: A9a23:Zd1V9aF1UHR9qEuApLqE0ceALOsnbusQ8zAXPidKOHtom62j5q STdZEgvnXJYVkqNU3I5urwXpVoLUmyyXcN2/hyAV7AZniChILLFuFfBOLZqlXd8kvFmNK1vp 0AT0ERMrHN5CBB/KXHCQCDYq8d/OU= X-IronPort-Anti-Spam-Filtered: true X-IronPort-AV: E=Sophos;i="5.95,176,1661810400"; d="scan'208";a="175431419" From: To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH v4 4/7] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32 Date: Sun, 23 Oct 2022 17:36:56 +0200 Message-ID: <20221023153659.121138-5-tobias.roehmel@rwth-aachen.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221023153659.121138-1-tobias.roehmel@rwth-aachen.de> References: <20221023153659.121138-1-tobias.roehmel@rwth-aachen.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [2a02:908:1088:5920:10a7:3a65:7c9d:55ef] X-ClientProxiedBy: rwthex-s4-b.rwth-ad.de (2a00:8a60:1:e500::26:165) To RWTHEX-S2-B.rwth-ad.de (2a00:8a60:1:e500::26:155) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:8a60:1:e501::5:48; envelope-from=tobias.roehmel@rwth-aachen.de; helo=mail-out-3.itc.rwth-aachen.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1666549450428100001 From: Tobias R=C3=B6hmel ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even tough they don't have the TTBCR register. See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R AArch32 architecture profile Version:A.c section C1.2. Signed-off-by: Tobias R=C3=B6hmel Reviewed-by: Peter Maydell --- target/arm/debug_helper.c | 3 +++ target/arm/internals.h | 4 ++++ target/arm/tlb_helper.c | 3 +++ 3 files changed, 10 insertions(+) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index c21739242c..73665f988b 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -437,6 +437,9 @@ static uint32_t arm_debug_exception_fsr(CPUARMState *en= v) =20 if (target_el =3D=3D 2 || arm_el_is_aa64(env, target_el)) { using_lpae =3D true; + } else if (arm_feature(env, ARM_FEATURE_PMSA) + && arm_feature(env, ARM_FEATURE_V8)) { + using_lpae =3D true; } else { if (arm_feature(env, ARM_FEATURE_LPAE) && (env->cp15.tcr_el[target_el] & TTBCR_EAE)) { diff --git a/target/arm/internals.h b/target/arm/internals.h index 307a596505..e3699421b0 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -253,6 +253,10 @@ unsigned int arm_pamax(ARMCPU *cpu); static inline bool extended_addresses_enabled(CPUARMState *env) { uint64_t tcr =3D env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; + if (arm_feature(env, ARM_FEATURE_PMSA) + && arm_feature(env, ARM_FEATURE_V8)) { + return true; + } return arm_el_is_aa64(env, 1) || (arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE)); } diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index ad225b1cb2..a2047b0bc6 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -18,6 +18,9 @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx= mmu_idx) int el =3D regime_el(env, mmu_idx); if (el =3D=3D 2 || arm_el_is_aa64(env, el)) { return true; + } else if (arm_feature(env, ARM_FEATURE_PMSA) + && arm_feature(env, ARM_FEATURE_V8)) { + return true; } if (arm_feature(env, ARM_FEATURE_LPAE) && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) { --=20 2.34.1 From nobody Sat May 11 15:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166654717425222.383424496579323; Sun, 23 Oct 2022 10:46:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omesv-0001k8-03 for importer@patchew.org; Sun, 23 Oct 2022 13:35:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omd2S-00060G-St for qemu-devel@nongnu.org; Sun, 23 Oct 2022 11:37:25 -0400 Received: from mail-out-1a.itc.rwth-aachen.de ([2a00:8a60:1:e501::5:44]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omd2N-0006L7-9M for qemu-devel@nongnu.org; Sun, 23 Oct 2022 11:37:24 -0400 Received: from rwthex-s2-b.rwth-ad.de ([134.130.26.155]) by mail-in-1a.itc.rwth-aachen.de with ESMTP; 23 Oct 2022 17:37:13 +0200 Received: from localhost.localdomain (2a02:908:1088:5920:10a7:3a65:7c9d:55ef) by RWTHEX-S2-B.rwth-ad.de (2a00:8a60:1:e500::26:155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.15; Sun, 23 Oct 2022 17:37:13 +0200 X-IPAS-Result: =?us-ascii?q?A2DRAgC8Q0Vj/5sagoZaHAEBAQEBAQcBARIBAQQEAQFAg?= =?us-ascii?q?U+EfoROkRUDgROcGIFoCwEBAQEBAQEBAQgBQgQBAYUBAgIChHUmOBMBAgQBA?= =?us-ascii?q?QEBAwIDAQEBAQEBAwEBBgEBAQEBAQYEgRyFL0aGQwIBAyMECwFGECAFAiYCA?= =?us-ascii?q?lcGDgWCfYMhrRR/M4EBhHCJcQkBgQcsiFGCK4U0glCBFYE8gTd1hCs2gzqCZ?= =?us-ascii?q?gSSIlGHRhw4AwkDBwUsHUADCx8NFjUYAxQDBSEHAxkPIw0NBB0MAwMFJQMCA?= =?us-ascii?q?hsHAgIDAgYTBQICNRg0CAQIBCskDwUCBy8FBC8CHgQFBhEIAhYCBgQEBAQVA?= =?us-ascii?q?hAIAggmFwcTMxkBBTInDgkhHA4aDQUGEwMgbwUHOw8oL2krHRsHgQwqKBUDB?= =?us-ascii?q?AQDAgYTAyACDSkxFAQpEw8tBylxCQIDImUFAwMEKCwDCUAHKCQ8B1g6BQMCE?= =?us-ascii?q?CI8BgMJAwIkWXQwEhQFAw0XJggFNxsECDwCBQZSEwIKEgMSDy1JD0o+OxcIm?= =?us-ascii?q?2ZyexQvE25LfpJJAo5FoQIHghuhakyWdAKSFpcRogaBGIQoAgQCBAUCFoF4g?= =?us-ascii?q?X5xgzZRFwIPgRuNERaOMHM7AgYBCgEBAwmLCgEB?= IronPort-Data: A9a23:Ekt5fqpEgV/9mROkzJu2mShuq9BeBmJEZBIvgKrLsJaIsI4StFCzt garIBmBbveNa2vyf4hza4mx8k9T6pSAytFqTFQ6pC0yEy5G8OPIVI+TRqvS04J+DeWeFh49v 5VGAjXkBJppJpMJjk71atANlVEliefSAOKU5NfsYkhZXRVjRDoqlSVtkus4hp8AqdWiCmthg /uryyHkEALjimMc3l48sfrZ8ko35a2q4lv0g3RnDRx1lA6G/5UqJM9HTU2BByOQapVZGOe8W 9HCwNmRlo8O105wYj8Nuu+TnnwiGtY+DyDX4pZlc/TKbix5m8AH+v1T2Mw0NB0L0WXZx7id/ /0W3XC4YV9B0qQhA43xWTEAe811FfUuFLMqvRFTvOTLp3AqfUcAzN1oKEQaDac62dp1GGNFz 909ECwWbimM0rfeLLKTEoGAh+wZE/XLEbNagSsl53fDEuomBJnPBanHjTNa9G5r2oYXRq6YP ZRfMGcyBPjDS0Qn1lM/FJU0ne6zwGP4fj1dpVa9v7Ur4y3axQdx3b6rPNe9ltmiH5gEwx/I/ T6uE2LRAg0bZYW55We57iyiobT/wDq8ALA0C+jtnhJtqBjJroAJMzUPWF6m5PW0lEO6c9RYL UMS52wpt6da3FSmUtTnGRixsXKJuho0X9tWGvc9rgaXxcLpDx2xHHcYTjNRLcd88cVwXyM21 hqAk5XlCFSDrYGodJ5UzZ/MxRvaBMTfBTRqifMsJefd3+TenQ== IronPort-HdrOrdr: A9a23:bYICSqv3w3KaOqQDG8rb/iPW7skDZNV00zEX/kB9WHVpm62j9/ xG88516faZslsssRIb+OxoWpPvfZq0z/ccirX5VY3SPzUO01HFEGgN1+HfK2qKIVyaygcL79 YDT5RD X-IronPort-Anti-Spam-Filtered: true X-IronPort-AV: E=Sophos;i="5.95,176,1661810400"; d="scan'208";a="25951834" From: To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH v4 5/7] target/arm: Add PMSAv8r registers Date: Sun, 23 Oct 2022 17:36:57 +0200 Message-ID: <20221023153659.121138-6-tobias.roehmel@rwth-aachen.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221023153659.121138-1-tobias.roehmel@rwth-aachen.de> References: <20221023153659.121138-1-tobias.roehmel@rwth-aachen.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [2a02:908:1088:5920:10a7:3a65:7c9d:55ef] X-ClientProxiedBy: rwthex-s4-b.rwth-ad.de (2a00:8a60:1:e500::26:165) To RWTHEX-S2-B.rwth-ad.de (2a00:8a60:1:e500::26:155) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:8a60:1:e501::5:44; envelope-from=tobias.roehmel@rwth-aachen.de; helo=mail-out-1a.itc.rwth-aachen.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1666547176135100001 From: Tobias R=C3=B6hmel Signed-off-by: Tobias R=C3=B6hmel --- target/arm/cpu.c | 26 +++- target/arm/cpu.h | 12 ++ target/arm/helper.c | 290 +++++++++++++++++++++++++++++++++++++++++++ target/arm/machine.c | 28 +++++ target/arm/ptw.c | 9 +- 5 files changed, 363 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b642749d6d..468150ad6c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -463,6 +463,16 @@ static void arm_cpu_reset(DeviceState *dev) sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); } } + + if (cpu->pmsav8r_hdregion > 0) { + memset(env->pmsav8.hprbar[M_REG_NS], 0, + sizeof(*env->pmsav8.hprbar[M_REG_NS]) + * cpu->pmsav8r_hdregion); + memset(env->pmsav8.hprlar[M_REG_NS], 0, + sizeof(*env->pmsav8.hprlar[M_REG_NS]) + * cpu->pmsav8r_hdregion); + } + env->pmsav7.rnr[M_REG_NS] =3D 0; env->pmsav7.rnr[M_REG_S] =3D 0; env->pmsav8.mair0[M_REG_NS] =3D 0; @@ -1965,8 +1975,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) */ if (!cpu->has_mpu) { cpu->pmsav7_dregion =3D 0; + cpu->pmsav8r_hdregion =3D 0; } - if (cpu->pmsav7_dregion =3D=3D 0) { + if ((cpu->pmsav7_dregion =3D=3D 0) && (cpu->pmsav8r_hdregion =3D=3D 0)= ) { cpu->has_mpu =3D false; } =20 @@ -1994,6 +2005,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) env->pmsav7.dracr =3D g_new0(uint32_t, nr); } } + + if (cpu->pmsav8r_hdregion > 0xFF) { + error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, + cpu->pmsav8r_hdregion); + return; + } + + if (cpu->pmsav8r_hdregion) { + env->pmsav8.hprbar[M_REG_NS] =3D g_new0(uint32_t, + cpu->pmsav8r_hdregion); + env->pmsav8.hprlar[M_REG_NS] =3D g_new0(uint32_t, + cpu->pmsav8r_hdregion); + } } =20 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 429ed42eec..1bb3c24db1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -307,6 +307,13 @@ typedef struct CPUArchState { }; uint64_t sctlr_el[4]; }; + union { /* Virtualization System control register. */ + struct { + uint32_t vsctlr_ns; + uint32_t vsctlr_s; + }; + uint32_t vsctlr_el[2]; + }; uint64_t cpacr_el1; /* Architectural feature access control regist= er */ uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ @@ -740,8 +747,11 @@ typedef struct CPUArchState { */ uint32_t *rbar[M_REG_NUM_BANKS]; uint32_t *rlar[M_REG_NUM_BANKS]; + uint32_t *hprbar[M_REG_NUM_BANKS]; + uint32_t *hprlar[M_REG_NUM_BANKS]; uint32_t mair0[M_REG_NUM_BANKS]; uint32_t mair1[M_REG_NUM_BANKS]; + uint32_t hprselr[M_REG_NUM_BANKS]; } pmsav8; =20 /* v8M SAU */ @@ -901,6 +911,8 @@ struct ArchCPU { bool has_mpu; /* PMSAv7 MPU number of supported regions */ uint32_t pmsav7_dregion; + /* PMSAv8 MPU number of supported hyp regions */ + uint32_t pmsav8r_hdregion; /* v8M SAU number of supported regions */ uint32_t sau_sregion; =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 2e9e420d4e..6a27a618bc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3607,6 +3607,215 @@ static void pmsav7_rgnr_write(CPUARMState *env, con= st ARMCPRegInfo *ri, raw_write(env, ri, value); } =20 +static void prbar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] =3D value; +} + +static uint64_t prbar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; +} + +static void prlar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] =3D value; +} + +static uint64_t prlar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; +} + +static void prselr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + /* Ignore writes that would select not implemented region */ + if (value >=3D cpu->pmsav7_dregion) { + return; + } + + env->pmsav7.rnr[M_REG_NS] =3D value; +} + +static void hprbar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + env->pmsav8.hprbar[M_REG_NS][env->pmsav8.hprselr[M_REG_NS]] =3D value; +} + +static uint64_t hprbar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.hprbar[M_REG_NS][env->pmsav8.hprselr[M_REG_NS]]; +} + +static void hprlar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + env->pmsav8.hprlar[M_REG_NS][env->pmsav8.hprselr[M_REG_NS]] =3D value; +} + +static uint64_t hprlar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.hprlar[M_REG_NS][env->pmsav8.hprselr[M_REG_NS]]; +} + +static void hprenr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint32_t n; + uint32_t bit; + ARMCPU *cpu =3D env_archcpu(env); + + /* Ignore writes to unimplemented regions */ + value &=3D (1 << cpu->pmsav8r_hdregion) - 1; + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + + /* Register alias is only valid for first 32 indexes */ + for (n =3D 0; n < (cpu->pmsav8r_hdregion & 0x1F); ++n) { + bit =3D extract32(value, n, 1); + env->pmsav8.hprlar[M_REG_NS][n] =3D deposit32( + env->pmsav8.hprlar[M_REG_NS][n], 0, 1, bit); + } +} + +static uint64_t hprenr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint32_t n; + uint32_t result =3D 0x0; + ARMCPU *cpu =3D env_archcpu(env); + + /* Register alias is only valid for first 32 indexes */ + for (n =3D 0; n < (cpu->pmsav8r_hdregion & 0x1F); ++n) { + if (env->pmsav8.hprlar[M_REG_NS][n] & 0x1) { + result |=3D (0x1 << n); + } + } + return result; +} + +static void hprselr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + /* Ignore writes that would select not implemented region */ + if (value >=3D cpu->pmsav8r_hdregion) { + return; + } + + env->pmsav8.hprselr[M_REG_NS] =3D value; +} + +static void pmsav8r_regn_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint8_t index =3D (ri->crm & 0b111) << 1; + index |=3D (ri->opc2 & 1 << 2) >> 2; + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + + if (ri->opc1 =3D=3D 4) { + if (index >=3D cpu->pmsav8r_hdregion) { + return; + } + if (ri->opc2 & 0x1) { + env->pmsav8.hprlar[M_REG_NS][index] =3D value; + } else { + env->pmsav8.hprbar[M_REG_NS][index] =3D value; + } + } else { + if (index >=3D cpu->pmsav7_dregion) { + return; + } + if (ri->opc2 & 0x1) { + env->pmsav8.rlar[M_REG_NS][index] =3D value; + } else { + env->pmsav8.rbar[M_REG_NS][index] =3D value; + } + } +} + +static uint64_t pmsav8r_regn_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint8_t index =3D (ri->crm & 0b111) << 1; + index |=3D (ri->opc2 & 1 << 2) >> 2; + + if (ri->opc1 =3D=3D 4) { + if (index >=3D cpu->pmsav8r_hdregion) { + return 0x0; + } + if (ri->opc2 & 0x1) { + return env->pmsav8.hprlar[M_REG_NS][index]; + } else { + return env->pmsav8.hprbar[M_REG_NS][index]; + } + } else { + if (index >=3D cpu->pmsav7_dregion) { + return 0x0; + } + if (ri->opc2 & 0x1) { + return env->pmsav8.rlar[M_REG_NS][index]; + } else { + return env->pmsav8.rbar[M_REG_NS][index]; + } + } +} + +static const ARMCPRegInfo pmsav8r_cp_reginfo[] =3D { + { .name =3D "PRBAR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, + .accessfn =3D access_tvm_trvm, + .readfn =3D prbar_read, .writefn =3D prbar_write}, + { .name =3D "PRLAR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 3, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, + .accessfn =3D access_tvm_trvm, + .readfn =3D prlar_read, .writefn =3D prlar_write}, + { .name =3D "PRSELR", .resetvalue =3D 0, + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .writefn =3D prselr_write, + .fieldoffset =3D offsetof(CPUARMState, pmsav7.rnr[M_REG_NS])}, + { .name =3D "HPRBAR", .resetvalue =3D 0, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 3, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_ALIAS, + .readfn =3D hprbar_read, .writefn =3D hprbar_write}, + { .name =3D "HPRLAR", + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 3, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_ALIAS, + .readfn =3D hprlar_read, .writefn =3D hprlar_write}, + { .name =3D "HPRSELR", .resetvalue =3D 0, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_RW, + .writefn =3D hprselr_write, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.hprselr[M_REG_NS])}, + { .name =3D "HPRENR", + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_ALIAS, + .readfn =3D hprenr_read, .writefn =3D hprenr_write}, +}; + static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { /* Reset for all these registers is handled in arm_cpu_reset(), * because the PMSAv7 is also used by M-profile CPUs, which do @@ -8079,6 +8288,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->pmsav7_dregion << 8 }; + /* HMPUIR is specific to PMSA V8 */ + ARMCPRegInfo id_hmpuir_reginfo =3D { + .name =3D "HMPUIR", + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 4, .opc2 =3D 4, + .access =3D PL2_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->pmsav8r_hdregion + }; static const ARMCPRegInfo crn0_wi_reginfo =3D { .name =3D "CRN0_WI", .cp =3D 15, .crn =3D 0, .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_W, @@ -8122,6 +8338,67 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, id_cp_reginfo); if (!arm_feature(env, ARM_FEATURE_PMSA)) { define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); + } else if (arm_feature(env, ARM_FEATURE_PMSA) + && !arm_feature(env, ARM_FEATURE_M) + && arm_feature(env, ARM_FEATURE_V8)) { + uint32_t i =3D 0; + g_autofree char *tmp_string; + + define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); + define_one_arm_cp_reg(cpu, &id_hmpuir_reginfo); + define_arm_cp_regs(cpu, pmsav8r_cp_reginfo); + + /* Register alias is only valid for first 32 indexes */ + for (i =3D 0; i < (cpu->pmsav7_dregion & 0x1F); ++i) { + uint8_t crm =3D 0b1000 | ((i & 0b1110) >> 1); + uint8_t opc2 =3D (i & 0x1) << 2; + + tmp_string =3D g_strdup_printf("PRBAR%u", i); + ARMCPRegInfo tmp_prbarn_reginfo =3D { + .name =3D tmp_string, .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D crm, .op= c2 =3D opc2, + .access =3D PL1_RW, .resetvalue =3D 0, + .accessfn =3D access_tvm_trvm, + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + }; + define_one_arm_cp_reg(cpu, &tmp_prbarn_reginfo); + + opc2 =3D (i & 0x1) << 2 | 0x1; + tmp_string =3D g_strdup_printf("PRLAR%u", i); + ARMCPRegInfo tmp_prlarn_reginfo =3D { + .name =3D tmp_string, .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D crm, .op= c2 =3D opc2, + .access =3D PL1_RW, .resetvalue =3D 0, + .accessfn =3D access_tvm_trvm, + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + }; + define_one_arm_cp_reg(cpu, &tmp_prlarn_reginfo); + } + + /* Register alias is only valid for first 32 indexes */ + for (i =3D 0; i < (cpu->pmsav8r_hdregion & 0x1F); ++i) { + uint8_t crm =3D 0b1000 | ((i & 0b1110) >> 1); + uint8_t opc2 =3D (i & 0x1) << 2; + + tmp_string =3D g_strdup_printf("HPRBAR%u", i); + ARMCPRegInfo tmp_hprbarn_reginfo =3D { + .name =3D tmp_string, .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D crm, .op= c2 =3D opc2, + .access =3D PL2_RW, .resetvalue =3D 0, + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + }; + define_one_arm_cp_reg(cpu, &tmp_hprbarn_reginfo); + + opc2 =3D (i & 0x1) << 2 | 0x1; + tmp_string =3D g_strdup_printf("HPRLAR%u", i); + ARMCPRegInfo tmp_hprlarn_reginfo =3D { + .name =3D tmp_string, .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D crm, .op= c2 =3D opc2, + .access =3D PL2_RW, .resetvalue =3D 0, + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + }; + define_one_arm_cp_reg(cpu, &tmp_hprlarn_reginfo); + } } else if (arm_feature(env, ARM_FEATURE_V7)) { define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); } @@ -8243,6 +8520,19 @@ void register_cp_regs_for_features(ARMCPU *cpu) sctlr.type |=3D ARM_CP_SUPPRESS_TB_END; } define_one_arm_cp_reg(cpu, &sctlr); + + if (arm_feature(env, ARM_FEATURE_PMSA) + && !arm_feature(env, ARM_FEATURE_M) + && arm_feature(env, ARM_FEATURE_V8)) { + ARMCPRegInfo vsctlr =3D { + .name =3D "VSCTLR", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D= 0, + .access =3D PL2_RW, .resetvalue =3D 0x0, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.vsctlr= _s), + offsetof(CPUARMState, cp15.vsctlr_ns) = }, + }; + define_one_arm_cp_reg(cpu, &vsctlr); + } } =20 if (cpu_isar_feature(aa64_lor, cpu)) { diff --git a/target/arm/machine.c b/target/arm/machine.c index 54c5c62433..923da8d0bc 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -487,6 +487,30 @@ static bool pmsav8_needed(void *opaque) arm_feature(env, ARM_FEATURE_V8); } =20 +static bool pmsav8r_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + + return arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V8) && + !arm_feature(env, ARM_FEATURE_M); +} + +static const VMStateDescription vmstate_pmsav8r =3D { + .name =3D "cpu/pmsav8/pmsav8r", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pmsav8r_needed, + .fields =3D (VMStateField[]) { + VMSTATE_VARRAY_UINT32(env.pmsav8.hprbar[M_REG_NS], ARMCPU, + pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t= ), + VMSTATE_VARRAY_UINT32(env.pmsav8.hprlar[M_REG_NS], ARMCPU, + pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t= ), + VMSTATE_END_OF_LIST() + }, +}; + static const VMStateDescription vmstate_pmsav8 =3D { .name =3D "cpu/pmsav8", .version_id =3D 1, @@ -500,6 +524,10 @@ static const VMStateDescription vmstate_pmsav8 =3D { VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription * []) { + &vmstate_pmsav8r, + NULL } }; =20 diff --git a/target/arm/ptw.c b/target/arm/ptw.c index db50715fa7..4bd7389fa9 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1718,6 +1718,13 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t ad= dress, bool hit =3D false; uint32_t addr_page_base =3D address & TARGET_PAGE_MASK; uint32_t addr_page_limit =3D addr_page_base + (TARGET_PAGE_SIZE - 1); + int region_counter; + + if (regime_el(env, mmu_idx) =3D=3D 2) { + region_counter =3D cpu->pmsav8r_hdregion; + } else { + region_counter =3D cpu->pmsav7_dregion; + } =20 result->page_size =3D TARGET_PAGE_SIZE; result->phys =3D address; @@ -1742,7 +1749,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, hit =3D true; } =20 - for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { + for (n =3D region_counter - 1; n >=3D 0; n--) { /* region search */ /* * Note that the base address is bits [31:5] from the register --=20 2.34.1 From nobody Sat May 11 15:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1666569728548388.80899253195855; Sun, 23 Oct 2022 17:02:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omfpA-0004Y9-6h for importer@patchew.org; Sun, 23 Oct 2022 14:35:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omd2V-00061x-AZ for qemu-devel@nongnu.org; Sun, 23 Oct 2022 11:37:27 -0400 Received: from mail-out-1a.itc.rwth-aachen.de ([2a00:8a60:1:e501::5:44]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omd2T-0006L7-9X for qemu-devel@nongnu.org; Sun, 23 Oct 2022 11:37:27 -0400 Received: from rwthex-s2-b.rwth-ad.de ([134.130.26.155]) by mail-in-1a.itc.rwth-aachen.de with ESMTP; 23 Oct 2022 17:37:13 +0200 Received: from localhost.localdomain (2a02:908:1088:5920:10a7:3a65:7c9d:55ef) by RWTHEX-S2-B.rwth-ad.de (2a00:8a60:1:e500::26:155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.15; Sun, 23 Oct 2022 17:37:13 +0200 X-IPAS-Result: =?us-ascii?q?A2D6AAC8Q0Vj/5sagoZaHQEBAQEJARIBBQUBQIE+BQELA?= =?us-ascii?q?YR9hE6RFQOfEwsBAQEBAQEBAQEIAUIEAQGFAQICAoR1JjcGDgECBAEBAQEDA?= =?us-ascii?q?gMBAQEBAQEDAQEGAQEBAQEBBgSBHIUvRoZDAgEDIwQLAUEFECAFAiYCAlcGD?= =?us-ascii?q?gWCfYMhrRR/M4EBhHCJcQkBgQcsAYhQgiuFNIJQglGBN3WEHEWDOoJmBJIii?= =?us-ascii?q?BccOAMJAwcFLB1AAwsfDRY1GAMUAwUhBwMZDyMNDQQdDAMDBSUDAgIbBwICA?= =?us-ascii?q?wIGEwUCAjUYNAgECAQrJA8FAgcvBQQvAh4EBQYRCAIWAgYEBAQEFQIQCAIIJ?= =?us-ascii?q?hcHEzMZAQUyJw4JIRwOGg0FBhMDIG8FBzsPKC9pKx0bB4EMKigVAwQEAwIGE?= =?us-ascii?q?wMgAg0pMRQEKRMPLQcpcQkCAyJlBQMDBCgsAwlABygkPAdYOgUDAhAiPAYDC?= =?us-ascii?q?QMCJFl0MBIUBQMNFyYIBTcbBAg8AgUGUhMCChIDEg8tSQ9KPjsXCJtmcgEsL?= =?us-ascii?q?TSCU68GkzMHghuhakyDdpJ+AjaRYJcRox6EKAIEAgQFAhaBd4F/cYM2URcCD?= =?us-ascii?q?5xyczsCBgEKAQEDCYhDgkcBAQ?= IronPort-Data: A9a23:6Ag0r6tBwZAh/v8CqBGgQ+vZsufnVApfMUV32f8akzHdYApBsoF/q tZmKWqGafbZMTT1co8lPo7npEsCsZXWyd9hQAY9rCFjHnwSgMeUXt7xwmUcns+xBpCZEBg3v 512hv3odp1coqr0/0/1WlTZhSAgk/vOHtIQMcacUghpXwhoVSw9vhxqnu89k+ZAjMOwa++3k YqaT/b3ZRn0hlaYDkpOs/jZ8Us25ayo0N8llgVWic5j7Qe2e0Y9Ucp3yZGZdxPQXoRSF+imc OfPpJnRErTxpkpF5nuNy94XQ2VSKlLgFVHmZkl+B8BOtiN/Shkaic7XAtJBMxsN22XR9zxG4 I4lWZSYEW/FN0BX8QgXe0Ew/ypWZcWq9FJbSJSymZT78qHIT5fj69dXImdoDa4Ywf0tH0xt9 KIoMAwjVynW0opawJrjIgVtrv4cEOnGDMYk4DRKiyvGEfZjSJyFT6iiCd1whWxswJkVRbCEO YxANGcHgBfoOnWjPn8LD5g/lfzunH7yczhVrHqPurY3pmHaxwx81v7hPbI5f/TQGJQIxxbD+ Aoq+UzlGD44MvDYwwOs0Un0jeXdvB3jWb8rQejQGvlCxQf7KnYoIAQbUEb+rfSnh0qWXdVZJ EoJvC00osAa7EG3Q8O7WhSprHOAujYYWtxZCep87xuCopc4+C6DGXQEQy4Ec4ZjvoksWiAqk 1aF2d/kbdByjICopbum3u/8hVuP1eI9cQfuuQdsodM53uTe IronPort-HdrOrdr: A9a23:6qQrhqFon9xA+ZSmpLqE2ceALOsnbusQ8zAXP0AYc3Bom6uj5q eTdZUgpHvJYVkqNk3I9errBEDEewK+yXcX2/h1AV7BZmjbUQKTRekI0WKh+UyDJ8SXzJ866U 4KScdD4bPLYGST2q3BkXGF+q4boOVvp5rY/Nvj8w== X-IronPort-Anti-Spam-Filtered: true X-IronPort-AV: E=Sophos;i="5.95,176,1661810400"; d="scan'208";a="25951836" From: To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH v4 6/7] target/arm: Add PMSAv8r functionality Date: Sun, 23 Oct 2022 17:36:58 +0200 Message-ID: <20221023153659.121138-7-tobias.roehmel@rwth-aachen.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221023153659.121138-1-tobias.roehmel@rwth-aachen.de> References: <20221023153659.121138-1-tobias.roehmel@rwth-aachen.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [2a02:908:1088:5920:10a7:3a65:7c9d:55ef] X-ClientProxiedBy: rwthex-s4-b.rwth-ad.de (2a00:8a60:1:e500::26:165) To RWTHEX-S2-B.rwth-ad.de (2a00:8a60:1:e500::26:155) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:8a60:1:e501::5:44; envelope-from=tobias.roehmel@rwth-aachen.de; helo=mail-out-1a.itc.rwth-aachen.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1666569732723100001 From: Tobias R=C3=B6hmel Add PMSAv8r translation. Signed-off-by: Tobias R=C3=B6hmel --- target/arm/ptw.c | 130 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 110 insertions(+), 20 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4bd7389fa9..a5d890c09a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1503,6 +1503,23 @@ static bool pmsav7_use_background_region(ARMCPU *cpu= , ARMMMUIdx mmu_idx, =20 if (arm_feature(env, ARM_FEATURE_M)) { return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MA= SK; + } else if (arm_feature(env, ARM_FEATURE_PMSA)) { + if (regime_el(env, mmu_idx) =3D=3D 2) { + if (mmu_idx !=3D ARMMMUIdx_E2) { + return false; + } else if ((mmu_idx =3D=3D ARMMMUIdx_E2) + &&!(regime_sctlr(env, mmu_idx) & SCTLR_BR)) { + return false; + } + } else { + if (mmu_idx !=3D ARMMMUIdx_Stage1_E1) { + return false; + } else if ((mmu_idx =3D=3D ARMMMUIdx_Stage1_E1) + &&!(regime_sctlr(env, mmu_idx) & SCTLR_BR)) { + return false; + } + } + return true; } else { return regime_sctlr(env, mmu_idx) & SCTLR_BR; } @@ -1696,6 +1713,26 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, u= int32_t address, return !(result->prot & (1 << access_type)); } =20 +static uint32_t *regime_rbar(CPUARMState *env, ARMMMUIdx mmu_idx, + uint32_t secure) +{ + if (regime_el(env, mmu_idx) =3D=3D 2) { + return env->pmsav8.hprbar[secure]; + } else { + return env->pmsav8.rbar[secure]; + } +} + +static uint32_t *regime_rlar(CPUARMState *env, ARMMMUIdx mmu_idx, + uint32_t secure) +{ + if (regime_el(env, mmu_idx) =3D=3D 2) { + return env->pmsav8.hprlar[secure]; + } else { + return env->pmsav8.rlar[secure]; + } +} + bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, bool secure, GetPhysAddrResult *result, @@ -1733,6 +1770,10 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t ad= dress, *mregion =3D -1; } =20 + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + fi->stage2 =3D true; + } + /* * Unlike the ARM ARM pseudocode, we don't need to check whether this * was an exception vector read from the vector table (which is always @@ -1749,17 +1790,27 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, hit =3D true; } =20 + uint32_t bitmask; + if (arm_feature(env, ARM_FEATURE_M)) { + bitmask =3D 0x1f; + fi->level =3D 1; + } else { + bitmask =3D 0x3f; + fi->level =3D 0; + } + for (n =3D region_counter - 1; n >=3D 0; n--) { /* region search */ /* - * Note that the base address is bits [31:5] from the register - * with bits [4:0] all zeroes, but the limit address is bits - * [31:5] from the register with bits [4:0] all ones. + * Note that the base address is bits [31:x] from the register + * with bits [x-1:0] all zeroes, but the limit address is bits + * [31:x] from the register with bits [x:0] all ones. Where x = is + * 5 for Cortex-M and 6 for Cortex-R */ - uint32_t base =3D env->pmsav8.rbar[secure][n] & ~0x1f; - uint32_t limit =3D env->pmsav8.rlar[secure][n] | 0x1f; + uint32_t base =3D regime_rbar(env, mmu_idx, secure)[n] & ~bitm= ask; + uint32_t limit =3D regime_rlar(env, mmu_idx, secure)[n] | bitm= ask; =20 - if (!(env->pmsav8.rlar[secure][n] & 0x1)) { + if (!(regime_rlar(env, mmu_idx, secure)[n] & 0x1)) { /* Region disabled */ continue; } @@ -1793,7 +1844,6 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, * PMSAv7 where highest-numbered-region wins) */ fi->type =3D ARMFault_Permission; - fi->level =3D 1; return true; } =20 @@ -1803,8 +1853,11 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t ad= dress, } =20 if (!hit) { - /* background fault */ - fi->type =3D ARMFault_Background; + if (arm_feature(env, ARM_FEATURE_M)) { + fi->type =3D ARMFault_Background; + } else { + fi->type =3D ARMFault_Permission; + } return true; } =20 @@ -1812,12 +1865,14 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, /* hit using the background region */ get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot); } else { - uint32_t ap =3D extract32(env->pmsav8.rbar[secure][matchregion], 1= , 2); - uint32_t xn =3D extract32(env->pmsav8.rbar[secure][matchregion], 0= , 1); + uint32_t matched_rbar =3D regime_rbar(env, mmu_idx, secure)[matchr= egion]; + uint32_t matched_rlar =3D regime_rlar(env, mmu_idx, secure)[matchr= egion]; + uint32_t ap =3D extract32(matched_rbar, 1, 2); + uint32_t xn =3D extract32(matched_rbar, 0, 1); bool pxn =3D false; =20 if (arm_feature(env, ARM_FEATURE_V8_1M)) { - pxn =3D extract32(env->pmsav8.rlar[secure][matchregion], 4, 1); + pxn =3D extract32(matched_rlar, 4, 1); } =20 if (m_is_system_region(env, address)) { @@ -1825,21 +1880,49 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, xn =3D 1; } =20 - result->prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); + if (arm_feature(env, ARM_FEATURE_M)) { + /* + * We don't need to look the attribute up in the MAIR0/MAIR1 + * registers because that only tells us about cacheability. + */ + result->prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); + } else { + if (regime_el(env, mmu_idx) =3D=3D 2) { + result->prot =3D simple_ap_to_rw_prot_is_user(ap, + mmu_idx !=3D ARMMMUIdx_E2); + } else { + result->prot =3D simple_ap_to_rw_prot_is_user(ap, + mmu_idx !=3D ARMMMUIdx_Sta= ge1_E1); + } + + if (regime_sctlr(env, mmu_idx) & SCTLR_WXN + && (result->prot & PAGE_WRITE)) { + xn =3D 0x1; + } + + if ((regime_el(env, mmu_idx) =3D=3D 1) && regime_sctlr(env, mm= u_idx) + & SCTLR_UWXN && (ap =3D=3D 0x1)) { + xn =3D 0x1; + } + + uint8_t attrindx =3D extract32(matched_rlar, 1, 3); + uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; + uint8_t sh =3D extract32(matched_rlar, 3, 2); + result->cacheattrs.is_s2_format =3D false; + result->cacheattrs.attrs =3D extract64(mair, attrindx * 8, 8); + result->cacheattrs.shareability =3D sh; + } + if (result->prot && !xn && !(pxn && !is_user)) { result->prot |=3D PAGE_EXEC; } - /* - * We don't need to look the attribute up in the MAIR0/MAIR1 - * registers because that only tells us about cacheability. - */ + if (mregion) { *mregion =3D matchregion; } } =20 fi->type =3D ARMFault_Permission; - fi->level =3D 1; return !(result->prot & (1 << access_type)); } =20 @@ -2348,8 +2431,15 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, cacheattrs1 =3D result->cacheattrs; memset(result, 0, sizeof(*result)); =20 - ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, - is_el0, result, fi); + /* S1 is done. Now do S2 translation. */ + if (arm_feature(env, ARM_FEATURE_PMSA)) { + ret =3D get_phys_addr_pmsav8(env, ipa, access_type, s2_mmu= _idx, + is_secure, result, fi); + } else { + ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_i= dx, + is_el0, result, fi); + } + fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ --=20 2.34.1 From nobody Sat May 11 15:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1666546810833381.14552633182814; Sun, 23 Oct 2022 10:40:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omeRT-00052K-5L for importer@patchew.org; Sun, 23 Oct 2022 13:07:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omd2Q-0005yl-8n for qemu-devel@nongnu.org; Sun, 23 Oct 2022 11:37:22 -0400 Received: from mail-out-2a.itc.rwth-aachen.de ([2a00:8a60:1:e501::5:45]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omd2N-0006L8-9B for qemu-devel@nongnu.org; Sun, 23 Oct 2022 11:37:21 -0400 Received: from rwthex-s2-b.rwth-ad.de ([134.130.26.155]) by mail-in-2a.itc.rwth-aachen.de with ESMTP; 23 Oct 2022 17:37:14 +0200 Received: from localhost.localdomain (2a02:908:1088:5920:10a7:3a65:7c9d:55ef) by RWTHEX-S2-B.rwth-ad.de (2a00:8a60:1:e500::26:155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.15; Sun, 23 Oct 2022 17:37:13 +0200 X-IPAS-Result: =?us-ascii?q?A2CrAAAhREVj/5sagoZaHAEBAQEBAQcBARIBAQQEAQFAg?= =?us-ascii?q?T4EAQELAYR9hE6RGJ8TCwEBAQEBAQEBAQgBQgQBAYUBAgIChHUmNwYOAQIEA?= =?us-ascii?q?QEBAQMCAwEBAQEBAQMBAQYBAQEBAQEGBIEchS9GhkMCAQMjBAsBRhAgBQImA?= =?us-ascii?q?gJXBg4Fgn2DIa0UfzOBAYRwiXEJAYEHLAGIUIIrhTSCUIJRgTd1hGEwgwqCZ?= =?us-ascii?q?gSSIogXHDgDCQMHBSwdQAMLHw0WNRgDFAMFIQcDGQ8jDQ0EHQwDAwUlAwICG?= =?us-ascii?q?wcCAgMCBhMFAgI1GDQIBAgEKyQPBQIHLwUELwIeBAUGEQgCFgIGBAQEBBUCE?= =?us-ascii?q?AgCCCYXBxMzGQEFMicOCSEcDhoNBQYTAyBvBQc7DygvaSsdGweBDCooFQMEB?= =?us-ascii?q?AMCBhMDIAINKTEUBCkTDy0HKXEJAgMiZQUDAwQoLAMJQAcoJDwHWDoFAwIQI?= =?us-ascii?q?jwGAwkDAiRZdDASFAUDDRcmCAU3GwQIPAIFBlITAgoSAxIPLUkPSj47FwicW?= =?us-ascii?q?IEOlUSORqECB4IboWpMlnQCkhaXEaMehCgCBAIEBQIWgXeBf3GDNlEXAg+OL?= =?us-ascii?q?BaOMHM7AgYBCgEBAwmLCgEB?= IronPort-Data: A9a23:QGOtkKnZNwlSvSZMdENr+gvo5gzdJ0RdPkR7XQ2eYbSJt1+Wr1Gzt xJKDTuOa/iMMGXxetAkPI+x904OsZ6HyN9gT1E4/C48FltH+JHPbTi7wuYcHAvPdJGZHBI/h yk6QoOdRCzhZiaE/n9BCpC48T8mk/ngqoPUUIbsIjp2SRJvVBAvgBdin/9RqoNziLBVOSvU0 T/Ji5CZaQLNNwJcaDpOsfvb8Uo35pwehRtB1rAATaET1LPhvyRNZH4vDfnZB2f1RIBSAtm7S 47rpF1u1jqEl/uFIorNfofTKiXmcJaLVeS9oiY+t5yZv/R3jndaPpATaaBAMxcH011lqPgqo DlFncTYpQ7EpcQgksxFO/VTO3kW0aGrZNYrLFDn2fF/wXEqfFO24P9FT3EoBrcBpPZWAFxe2 tgICGEkO0Xra+KemNpXS8FWufgDAfmuB9lakDd60i3ZSP8qB5zOK0nIzYYDgHFp3ZgIR6iYP pdEAdZsRE2ojxlnJlAdCZsl2v2vi3n6fjlwsk2Jpe8+6mPTwQo33LWF3N/9IIHbG5UPxxvwS mTuxF7GMCMcCsOm5z/C/HST2KzQgBnQcddHfFG/3rsw6LGJ/UQKBRgLEFe2v/S9oki5Xd1ZN goT4CVGhbA/6EGxCNz0ThG1pHqsuh8aUsBXVeog52mwJrH8+RmFBmUUCyUbLdZgrtAqRXkj2 hmFkrsFGABSjVFcclrFnp/8kN94EXJ9wbMqDcPccTY43g== IronPort-HdrOrdr: A9a23:G9yLHKkce29JgC+1yo4PWU7+OivpDfI+3DAbv31ZSRFFG/Fw9v rPoB1173DJYVoqNU3I+urgBEDjex3hHPdOiOF7AV7LZniEhILCFu1fBOXZqQEJTEbFh4tgPP BbAspDNOE= X-IronPort-Anti-Spam-Filtered: true X-IronPort-AV: E=Sophos;i="5.95,176,1661810400"; d="scan'208";a="25968215" From: To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH v4 7/7] target/arm: Add ARM Cortex-R52 CPU Date: Sun, 23 Oct 2022 17:36:59 +0200 Message-ID: <20221023153659.121138-8-tobias.roehmel@rwth-aachen.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221023153659.121138-1-tobias.roehmel@rwth-aachen.de> References: <20221023153659.121138-1-tobias.roehmel@rwth-aachen.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [2a02:908:1088:5920:10a7:3a65:7c9d:55ef] X-ClientProxiedBy: rwthex-s4-b.rwth-ad.de (2a00:8a60:1:e500::26:165) To RWTHEX-S2-B.rwth-ad.de (2a00:8a60:1:e500::26:155) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:8a60:1:e501::5:45; envelope-from=tobias.roehmel@rwth-aachen.de; helo=mail-out-2a.itc.rwth-aachen.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1666546812730100001 From: Tobias R=C3=B6hmel All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3 Signed-off-by: Tobias R=C3=B6hmel Reviewed-by: Peter Maydell --- target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 98b5ba2160..52b9d671f7 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -851,6 +851,47 @@ static void cortex_r5_initfn(Object *obj) define_arm_cp_regs(cpu, cortexr5_cp_reginfo); } =20 +static void cortex_r52_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_PMSA); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + cpu->midr =3D 0x411fd133; /* r1p3 */ + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034023; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x8144c004; + cpu->reset_sctlr =3D 0x30c50838; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x10111001; + cpu->isar.id_dfr0 =3D 0x03010006; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00211040; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01200000; + cpu->isar.id_mmfr3 =3D 0xf0102211; + cpu->isar.id_mmfr4 =3D 0x00000010; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232142; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x00010001; + cpu->isar.dbgdidr =3D 0x77168000; + cpu->clidr =3D (1 << 27) | (1 << 24) | 0x3; + cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe00a; /* 32KB L1 icache */ + + cpu->pmsav7_dregion =3D 16; + cpu->pmsav8r_hdregion =3D 16; +} + static void cortex_r5f_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -1159,6 +1200,7 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn }, { .name =3D "cortex-r5f", .initfn =3D cortex_r5f_initfn }, + { .name =3D "cortex-r52", .initfn =3D cortex_r52_initfn }, { .name =3D "ti925t", .initfn =3D ti925t_initfn }, { .name =3D "sa1100", .initfn =3D sa1100_initfn }, { .name =3D "sa1110", .initfn =3D sa1110_initfn }, --=20 2.34.1