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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.15.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:15:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ROIaR2/2j+a5heyURGySBxjwOTFvMLYqmlHWrVr1ZCs=; b=UqFq1/TVBNhb5c6+fH4hnMe/83viqNxKg4+zV/SzExDiHGApEDwulsois1HrtFeYVj 9CQPdoGjcBhfJOeeDF+s8TzY6WJfogWWGcw2PaM1BGO2vdS7lw7+i16yHi0i5zNFBhs0 RzgrEFP3G/KOO0mlzVrzeeBNlafsEEMf1pnSUl6JyHS1yrd3lYY6jUlwP8s/s5oR5Ux5 wqKs8lI8rP39U2lxdnaTmmBi/qaaXd3KPY4hv4cQhFKPgFFrJ+bgDWKo2vJU2tFH8tFB Lw1biauhMlSqalUF9elGyX9MozDGe7ur3uBICA0akQObjZFUKECTN0qfB/WS8rRu2O2z ZCww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ROIaR2/2j+a5heyURGySBxjwOTFvMLYqmlHWrVr1ZCs=; b=dzEA0RdEHLq4SDIqA6UGjxe8hus4LolHWgU46gnHBEUj7lCDjOyYIZ6fGXOR/x8rXl YQvDwu+cMMUbJX/Tkz7DuwrYEFfHaytG2/Z7yrraVyooROWpbXKGc5IbCGYgG4LZU6BS 4LBKxxNolDk0w/Oqk1G03dLjbAeBGslS9+ITLy8ixUg2sGgtXZasypxKDhSg4agJYS/b yGBeVRKMA4vih9FV5AYh30mUOp6el1kvHluDfwDswvTszIfWEnzjzaMlbWCZEJcP8vGj WDquBKDRrrkloejgfA55tmqKbOqsElBVZ4ujyzNI2aO7ZZbwqcQViAnTdc+McCNz9M2M d0ag== X-Gm-Message-State: AJIora+j5yZEb9Bi6zwlbrSdZA2zOWEosnVJJCEPdgl9nxB++CbiMNVk w2k2xKY5exGdobbPyMGhelQionieaxJojNks X-Google-Smtp-Source: AGRyM1sOiqn3tFwfWfcNh2WQVUQkmDUX/+xb9BIgSAbly0f4kOBeSYMljygV7e4HdPeF/fJkCnNVMw== X-Received: by 2002:a17:903:32c4:b0:16a:4227:cd68 with SMTP id i4-20020a17090332c400b0016a4227cd68mr4070860plr.173.1657293349602; Fri, 08 Jul 2022 08:15:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 01/45] target/arm: Handle SME in aarch64_cpu_dump_state Date: Fri, 8 Jul 2022 20:44:56 +0530 Message-Id: <20220708151540.18136-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657293514342100003 Content-Type: text/plain; charset="utf-8" Dump SVCR, plus use the correct access check for Streaming Mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ae6dca2f01..9c58be8b14 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -878,6 +878,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *= f, int flags) int i; int el =3D arm_current_el(env); const char *ns_status; + bool sve; =20 qemu_fprintf(f, " PC=3D%016" PRIx64 " ", env->pc); for (i =3D 0; i < 32; i++) { @@ -904,6 +905,12 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE = *f, int flags) el, psr & PSTATE_SP ? 'h' : 't'); =20 + if (cpu_isar_feature(aa64_sme, cpu)) { + qemu_fprintf(f, " SVCR=3D%08" PRIx64 " %c%c", + env->svcr, + (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), + (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); + } if (cpu_isar_feature(aa64_bti, cpu)) { qemu_fprintf(f, " BTYPE=3D%d", (psr & PSTATE_BTYPE) >> 10); } @@ -918,7 +925,15 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE = *f, int flags) qemu_fprintf(f, " FPCR=3D%08x FPSR=3D%08x\n", vfp_get_fpcr(env), vfp_get_fpsr(env)); =20 - if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) =3D= =3D 0) { + if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)= ) { + sve =3D sme_exception_el(env, el) =3D=3D 0; + } else if (cpu_isar_feature(aa64_sve, cpu)) { + sve =3D sve_exception_el(env, el) =3D=3D 0; + } else { + sve =3D false; + } + + if (sve) { int j, zcr_len =3D sve_vqm1_for_el(env, el); =20 for (i =3D 0; i <=3D FFR_PRED_NUM; i++) { --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657293511; cv=none; d=zohomail.com; s=zohoarc; b=OHaowRC+yWbXKUqi24MU+RX00YVCyFciJ1kU0Je4tzo9XF6FML+p+LZXlNHDbV92vXYe3WHtrF94uMhAQoug4G95KaJnfPnWg9wKq4SKs3OCEZWDzdSXNfl0UVEaO3Pl91g06qmLnVnfV5RkDBqE+A4c5PZZW2G2ld1i4D7oiWY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657293511; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Zt0iFWR3qz21z3bSyJ1iuT1OyELXtc2hbyVwv56j1M4=; b=L4WoNaWCJtjv+FJA1BQLBLaNuN9lT3yOqpHU5ZQExIuvwO3hUHs4FWzcjLabYwXugeki1dhuv2C3SB7dlKpEsbpIRjPdaN/ZS0IE9jJDsFatdDFcnQdEM2ALa+T5qJbFgOG3/+kEKjjjmfKmXqNLikrJaODr/8NViqmom2s15FI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657293511153128.4520551995505; Fri, 8 Jul 2022 08:18:31 -0700 (PDT) Received: from localhost ([::1]:48388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9pkT-0005KS-Ha for importer@patchew.org; Fri, 08 Jul 2022 11:18:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36612) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pi6-00027r-Ap for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:02 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:33399) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pi0-000256-M9 for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:02 -0400 Received: by mail-pj1-x102a.google.com with SMTP id j1-20020a17090aeb0100b001ef777a7befso1839728pjz.0 for ; Fri, 08 Jul 2022 08:15:53 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.15.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:15:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Zt0iFWR3qz21z3bSyJ1iuT1OyELXtc2hbyVwv56j1M4=; b=r1il2+o3ugblql6EWta8flVXEwTReZW7f/a30BLJ9P94aEumoCWLym/GL8pkesWTA5 yP41MNabkthP6f3GbOFe6yG3M6DniiFpG/+91GJllmwpUu6PmG80qNit8E32RG4TshLH C/G3f5jrIAIw8EWND8Vnv0st3ZMhoztS+N4arhM5A5z3OD1jTO94BjfWi5C+hXbEglIc VGY/HXwqct1/Ia2HjH8zKk4vS3Uo43SwYULZsEjydo0Z22b8VnH3BEv/6FL4sq0ADgDj aoIokctejPwacTK3wFuYYCAQBSUlvItub75xd8DfizU5egowfbC+WOCn5xj8S3LJ48Iw fYKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Zt0iFWR3qz21z3bSyJ1iuT1OyELXtc2hbyVwv56j1M4=; b=6SXNRxOgYlPevW/FrKwkLZAhIwS7VLZsLGhqjFSU2oZwzwuHP4e8TSmIm8Oiz4KHzs yVv2FUwyp0p5jC5TurLaDjGFoxh0wJ3sxcoboVVvywEMyKbcgbVfKTbgn0zqIXCstKH3 +LrE4jPLnWtXDZbkJY9Wr3CYf9ygTB12icuB7mOwfqtIDquWcg5NaXvnCwsJpiPVxQuR EPhuQWN300O7ldsZ4FHcT4z/mhvtm4s2VmOgqsKcvXSuaGCtfljUSq/HQ/PPDHsVCyG/ S1rSmj0vTggNvQpigj9y40LoD51Q4MtGgLITZ+sv0f3XePa/a7NIq/g+rK/pVP5iGdX+ lqTQ== X-Gm-Message-State: AJIora8yoHmpgwRwRdKEgcjSuxL+mTfk+RBkuR4HaXut2DYZfA7xfeNK bX5Tc4VcJoG1XlVs3bExB1LBwq9Zjmn47y2w X-Google-Smtp-Source: AGRyM1svWMNAHdyezOYeQPM3CFAr2WEocJTkfixwo2HroYw2r9UrRxCdYakjpFq7PU/0UJDdLninPA== X-Received: by 2002:a17:902:e752:b0:16a:4515:b2f2 with SMTP id p18-20020a170902e75200b0016a4515b2f2mr4187537plf.140.1657293352716; Fri, 08 Jul 2022 08:15:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 02/45] target/arm: Add infrastructure for disas_sme Date: Fri, 8 Jul 2022 20:44:57 +0530 Message-Id: <20220708151540.18136-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657293512495100001 Content-Type: text/plain; charset="utf-8" This includes the build rules for the decoder, and the new file for translation, but excludes any instructions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 1 + target/arm/sme.decode | 20 ++++++++++++++++++++ target/arm/translate-a64.c | 7 ++++++- target/arm/translate-sme.c | 35 +++++++++++++++++++++++++++++++++++ target/arm/meson.build | 2 ++ 5 files changed, 64 insertions(+), 1 deletion(-) create mode 100644 target/arm/sme.decode create mode 100644 target/arm/translate-sme.c diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index f0970c6b8c..789b6e8e78 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -146,6 +146,7 @@ static inline int pred_gvec_reg_size(DisasContext *s) } =20 bool disas_sve(DisasContext *, uint32_t); +bool disas_sme(DisasContext *, uint32_t); =20 void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); diff --git a/target/arm/sme.decode b/target/arm/sme.decode new file mode 100644 index 0000000000..c25c031a71 --- /dev/null +++ b/target/arm/sme.decode @@ -0,0 +1,20 @@ +# AArch64 SME instruction descriptions +# +# Copyright (c) 2022 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c86b97b1d4..a5f8a6c771 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14806,7 +14806,12 @@ static void aarch64_tr_translate_insn(DisasContext= Base *dcbase, CPUState *cpu) } =20 switch (extract32(insn, 25, 4)) { - case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ + case 0x0: + if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) { + unallocated_encoding(s); + } + break; + case 0x1: case 0x3: /* UNALLOCATED */ unallocated_encoding(s); break; case 0x2: diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c new file mode 100644 index 0000000000..786c93fb2d --- /dev/null +++ b/target/arm/translate-sme.c @@ -0,0 +1,35 @@ +/* + * AArch64 SME translation + * + * Copyright (c) 2022 Linaro, Ltd + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" +#include "tcg/tcg-gvec-desc.h" +#include "translate.h" +#include "exec/helper-gen.h" +#include "translate-a64.h" +#include "fpu/softfloat.h" + + +/* + * Include the generated decoder. + */ + +#include "decode-sme.c.inc" diff --git a/target/arm/meson.build b/target/arm/meson.build index 43dc600547..6dd7e93643 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,5 +1,6 @@ gen =3D [ decodetree.process('sve.decode', extra_args: '--decode=3Ddisas_sve'), + decodetree.process('sme.decode', extra_args: '--decode=3Ddisas_sme'), decodetree.process('neon-shared.decode', extra_args: '--decode=3Ddisas_n= eon_shared'), decodetree.process('neon-dp.decode', extra_args: '--decode=3Ddisas_neon_= dp'), decodetree.process('neon-ls.decode', extra_args: '--decode=3Ddisas_neon_= ls'), @@ -50,6 +51,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'sme_helper.c', 'translate-a64.c', 'translate-sve.c', + 'translate-sme.c', )) =20 arm_softmmu_ss =3D ss.source_set() --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657293515; cv=none; d=zohomail.com; s=zohoarc; b=j3YHeE2cwFHMbOzCzM0MHnHESq5mWNPmFz0OIZvmQQ0hgIAa2FNPZW4fdCldckRzhg17IekpzY8xBTU/rBIVmYbUejxwzVfSDsVEQRcDLXiNRH36kcz1xAnKSameWFCMhbSYYbuuHvoe/emPi2mEo7lnygrdIfvGJimETUIbJb4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657293515; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TCGRYaM9CMo/9aFeB3/W5WDfDKYHUGdwXwE5N2wq+aM=; b=iXM+ElyeLqWeSWk53FN3a+imjkFDUDiku2vqXPaVV4rlkQhb/+fhckFOfNAldp6QCdGoCol6OoqEuHWUSBaY3jkqGbf1w99Jp/+r3qUn2V1yzuKNH2Vgwq8W+H/8E4DWRygWYTDI8fbXFmd685Y+qHg4Leep5OxWk9LhgqqonBg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657293515260743.7387482497725; Fri, 8 Jul 2022 08:18:35 -0700 (PDT) Received: from localhost ([::1]:48638 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9pkX-0005UL-48 for importer@patchew.org; Fri, 08 Jul 2022 11:18:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36634) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pi7-00028U-6K for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:03 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:34616) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pi2-00025Y-9F for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:02 -0400 Received: by mail-pl1-x630.google.com with SMTP id z1so10806582plb.1 for ; Fri, 08 Jul 2022 08:15:57 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.15.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:15:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TCGRYaM9CMo/9aFeB3/W5WDfDKYHUGdwXwE5N2wq+aM=; b=xhrrwgLbr4SHQKd4EHCEbLL3Qyx4MBX/QJd1HsTS1NEyMYUEBAXQfgW0m+6lpoMQSt QgGfmgztvQEc7pKEJknsq6/mDtEKaXsjNwzSbosC+B+bzhGBy/ctETZs7brCu2TfLBOn mp7CqQldjrnrrEOTzpSAZd6830+teJsk8X+8GZwJqQsI5yhAzsWhn/oqs8YBi+jXuaP4 cd3eIiro2gtV3xfwMhsU/e11U5h8c2eo+6cMUtH9LOIJhO+ogCn/ywG07XMJHQkqtbQa pQZ3YRGRXX6PHxBa3+A7gDGk4bNJWHkbLSU4iUdLAz8Ii/0jU8iVN4d3pE9j1fWstG9L LU7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TCGRYaM9CMo/9aFeB3/W5WDfDKYHUGdwXwE5N2wq+aM=; b=inRwa7K2alxLDEJ1u1BZZeggLxP4N8uxOI8D4hAwqmgQQxm7Pngnkw5ijHmOH72ssq C25hSyDfUD0D4Zhtv1kHIZL1TZSm1N4aLoAsGeMctHohgRfNOiIjtf3kxD8Vp5RDYeEF RDTrVk/mM82BGA/GlHxpmXbtYj01MnadgF3amFlXybzWG9JnSWdk2OAl8C0M9uRKPGex TW7ak7LU85LIC5XF8XjkOS/XD2CX1aDq/QfNYuc8Btc3elzisXQJCIGfqYZRQyFqXWnz P/CAZMHvopsCGKwT77ABWz2ckQObRkxyiGUcHB7KXFGFeNMeH1ez/ee+RPomCWeGhUJh 0HEQ== X-Gm-Message-State: AJIora9acGLyimnOkDqpEj2gP9vMaH4WXlqo7oeJLncSgRxycf4WQyff qB1tAWws3YrA3EhnH0nsIKiZp/tpUoac+AzI X-Google-Smtp-Source: AGRyM1sa1JeE2FnX81oUhXi2uDdM9MJAn/p9r8xUtrK0vYaw/UbzobBT0Npem0H7Z8Zip6JRhURV+A== X-Received: by 2002:a17:902:ef50:b0:16b:e2de:1c24 with SMTP id e16-20020a170902ef5000b0016be2de1c24mr4284954plx.99.1657293356212; Fri, 08 Jul 2022 08:15:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active Date: Fri, 8 Jul 2022 20:44:58 +0530 Message-Id: <20220708151540.18136-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657293516320100005 Content-Type: text/plain; charset="utf-8" This new behaviour is in the ARM pseudocode function AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32 via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which the trap would be delivered is in AArch64 mode. Given that ARMv9 drops support for AArch32 outside EL0, the trap EL detection ought to be trivially true, but the pseudocode still contains a number of conditions, and QEMU has not yet committed to dropping A32 support for EL[12] when v9 features are present. Since the computation of SME_TRAP_NONSTREAMING is necessarily different for the two modes, we might as well preserve bits within TBFLAG_ANY and allocate separate bits within TBFLAG_A32 and TBFLAG_A64 instead. Note that DDI0616A.a has typos for bits [22:21] of LD1RO in the table of instructions illegal in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 7 +++ target/arm/translate.h | 4 ++ target/arm/sme-fa64.decode | 90 ++++++++++++++++++++++++++++++++++++++ target/arm/helper.c | 41 +++++++++++++++++ target/arm/translate-a64.c | 40 ++++++++++++++++- target/arm/translate-vfp.c | 12 +++++ target/arm/translate.c | 2 + target/arm/meson.build | 1 + 8 files changed, 195 insertions(+), 2 deletions(-) create mode 100644 target/arm/sme-fa64.decode diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1f4f3e0485..1e36a839ee 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3158,6 +3158,11 @@ FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) * the same thing as the current security state of the processor! */ FIELD(TBFLAG_A32, NS, 10, 1) +/* + * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. + * This requires an SME trap from AArch32 mode when using NEON. + */ +FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) =20 /* * Bit usage when in AArch32 state, for M-profile only. @@ -3195,6 +3200,8 @@ FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) FIELD(TBFLAG_A64, SVL, 24, 4) +/* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. = */ +FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) =20 /* * Helpers for using the above. diff --git a/target/arm/translate.h b/target/arm/translate.h index 22fd882368..cbc907c751 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -102,6 +102,10 @@ typedef struct DisasContext { bool pstate_sm; /* True if PSTATE.ZA is set. */ bool pstate_za; + /* True if non-streaming insns should raise an SME Streaming exception= . */ + bool sme_trap_nonstreaming; + /* True if the current instruction is non-streaming. */ + bool is_nonstreaming; /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ bool mve_no_pred; /* diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode new file mode 100644 index 0000000000..3d90837fc7 --- /dev/null +++ b/target/arm/sme-fa64.decode @@ -0,0 +1,90 @@ +# AArch64 SME allowed instruction decoding +# +# Copyright (c) 2022 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# + +# These patterns are taken from Appendix E1.1 of DDI0616 A.a, +# Arm Architecture Reference Manual Supplement, +# The Scalable Matrix Extension (SME), for Armv9-A + +{ + [ + OK 0-00 1110 0000 0001 0010 11-- ---- ---- # SMOV W|Xd,Vn.B[0] + OK 0-00 1110 0000 0010 0010 11-- ---- ---- # SMOV W|Xd,Vn.H[0] + OK 0100 1110 0000 0100 0010 11-- ---- ---- # SMOV Xd,Vn.S[0] + OK 0000 1110 0000 0001 0011 11-- ---- ---- # UMOV Wd,Vn.B[0] + OK 0000 1110 0000 0010 0011 11-- ---- ---- # UMOV Wd,Vn.H[0] + OK 0000 1110 0000 0100 0011 11-- ---- ---- # UMOV Wd,Vn.S[0] + OK 0100 1110 0000 1000 0011 11-- ---- ---- # UMOV Xd,Vn.D[0] + ] + FAIL 0--0 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD vector o= perations +} + +{ + [ + OK 0101 1110 --1- ---- 11-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (= scalar) + OK 0101 1110 -10- ---- 00-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (= scalar, FP16) + OK 01-1 1110 1-10 0001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX = (scalar) + OK 01-1 1110 1111 1001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX = (scalar, FP16) + ] + FAIL 01-1 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD single-e= lement operations +} + +FAIL 0-00 110- ---- ---- ---- ---- ---- ---- # Advanced SIMD structur= e load/store +FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptogr= aphy extensions +FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS + +# These are the "avoidance of doubt" final table of Illegal Advanced SIMD = instructions +# We don't actually need to include these, as the default is OK. +# -001 111- ---- ---- ---- ---- ---- ---- # Scalar floating-point = operations +# --10 110- ---- ---- ---- ---- ---- ---- # Load/store pair of FP = registers +# --01 1100 ---- ---- ---- ---- ---- ---- # Load FP register (PC-r= elative literal) +# --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register= (unscaled imm) +# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) +# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) + +FAIL 0000 0100 --1- ---- 1010 ---- ---- ---- # ADR +FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA +FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT +FAIL 0010 0101 --01 100- 1111 000- ---0 ---- # RDFFR, RDFFRS +FAIL 0010 0101 --10 1--- 1001 ---- ---- ---- # WRFFR, SETFFR +FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP +FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b r= esult) +FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA +FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL +FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD +FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA +FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA +FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/cryp= to instructions +FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT = load (vector+scalar) +FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather pref= etch (vector+imm) +FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather pref= etch (scalar+vector) +FAIL 1000 010- -01- ---- 1--- ---- ---- ---- # SVE 32-bit gather load= (vector+imm) +FAIL 1000 0100 0-0- ---- 0--- ---- ---- ---- # SVE 32-bit gather load= byte (scalar+vector) +FAIL 1000 0100 1--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load= half (scalar+vector) +FAIL 1000 0101 0--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load= word (scalar+vector) +FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load= (scalar+scalar) +FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load= (scalar+imm) +FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+scalar) +FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+imm) +FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load= /prefetch +FAIL 1110 010- -00- ---- 001- ---- ---- ---- # SVE2 64-bit scatter NT= store (vector+scalar) +FAIL 1110 010- -10- ---- 001- ---- ---- ---- # SVE2 32-bit scatter NT= store (vector+scalar) +FAIL 1110 010- ---- ---- 1-0- ---- ---- ---- # SVE scatter store (sca= lar+32-bit vector) +FAIL 1110 010- ---- ---- 101- ---- ---- ---- # SVE scatter store (mis= c) diff --git a/target/arm/helper.c b/target/arm/helper.c index e6f37e160f..73a5b2b86d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6098,6 +6098,32 @@ int sme_exception_el(CPUARMState *env, int el) return 0; } =20 +/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */ +static bool sme_fa64(CPUARMState *env, int el) +{ + if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) { + return false; + } + + if (el <=3D 1 && !el_is_in_host(env, el)) { + if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) { + return false; + } + } + if (el <=3D 2 && arm_is_el2_enabled(env)) { + if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) { + return false; + } + } + if (arm_feature(env, ARM_FEATURE_EL3)) { + if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) { + return false; + } + } + + return true; +} + /* * Given that SVE is enabled, return the vector length for EL. */ @@ -10801,6 +10827,20 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMStat= e *env, int fp_el, DP_TBFLAG_ANY(flags, PSTATE__IL, 1); } =20 + /* + * The SME exception we are testing for is raised via + * AArch64.CheckFPAdvSIMDEnabled(), as called from + * AArch32.CheckAdvSIMDOrFPEnabled(). + */ + if (el =3D=3D 0 + && FIELD_EX64(env->svcr, SVCR, SM) + && (!arm_is_el2_enabled(env) + || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE))) + && arm_el_is_aa64(env, 1) + && !sme_fa64(env, el)) { + DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1); + } + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } =20 @@ -10850,6 +10890,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState= *env, int el, int fp_el, } if (FIELD_EX64(env->svcr, SVCR, SM)) { DP_TBFLAG_A64(flags, PSTATE_SM, 1); + DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el)= ); } DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a5f8a6c771..7fab7f64f8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1155,7 +1155,7 @@ static void do_vec_ld(DisasContext *s, int destidx, i= nt element, * unallocated-encoding checks (otherwise the syndrome information * for the resulting exception will be incorrect). */ -static bool fp_access_check(DisasContext *s) +static bool fp_access_check_only(DisasContext *s) { if (s->fp_excp_el) { assert(!s->fp_access_checked); @@ -1170,6 +1170,19 @@ static bool fp_access_check(DisasContext *s) return true; } =20 +static bool fp_access_check(DisasContext *s) +{ + if (!fp_access_check_only(s)) { + return false; + } + if (s->sme_trap_nonstreaming && s->is_nonstreaming) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_Streaming, false)); + return false; + } + return true; +} + /* Check that SVE access is enabled. If it is, return true. * If not, emit code to generate an appropriate exception and return false. */ @@ -1994,7 +2007,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, default: g_assert_not_reached(); } - if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { + if ((ri->type & ARM_CP_FPU) && !fp_access_check_only(s)) { return; } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { return; @@ -14530,6 +14543,23 @@ static void disas_data_proc_simd_fp(DisasContext *= s, uint32_t insn) } } =20 +/* + * Include the generated SME FA64 decoder. + */ + +#include "decode-sme-fa64.c.inc" + +static bool trans_OK(DisasContext *s, arg_OK *a) +{ + return true; +} + +static bool trans_FAIL(DisasContext *s, arg_OK *a) +{ + s->is_nonstreaming =3D true; + return true; +} + /** * is_guarded_page: * @env: The cpu environment @@ -14657,6 +14687,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->mte_active[1] =3D EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE); dc->pstate_sm =3D EX_TBFLAG_A64(tb_flags, PSTATE_SM); dc->pstate_za =3D EX_TBFLAG_A64(tb_flags, PSTATE_ZA); + dc->sme_trap_nonstreaming =3D EX_TBFLAG_A64(tb_flags, SME_TRAP_NONSTRE= AMING); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; @@ -14805,6 +14836,11 @@ static void aarch64_tr_translate_insn(DisasContext= Base *dcbase, CPUState *cpu) } } =20 + s->is_nonstreaming =3D false; + if (s->sme_trap_nonstreaming) { + disas_sme_fa64(s, insn); + } + switch (extract32(insn, 25, 4)) { case 0x0: if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) { diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 82fdbcae53..bd5ae27d09 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -234,6 +234,18 @@ static bool vfp_access_check_a(DisasContext *s, bool i= gnore_vfp_enabled) return false; } =20 + /* + * Note that rebuild_hflags_a32 has already accounted for being in EL0 + * and the higher EL in A64 mode, etc. Unlike A64 mode, there do not + * appear to be any insns which touch VFP which are allowed. + */ + if (s->sme_trap_nonstreaming) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_Streaming, + s->base.pc_next - s->pc_curr =3D=3D= 2)); + return false; + } + if (!s->vfp_enabled && !ignore_vfp_enabled) { assert(!arm_dc_feature(s, ARM_FEATURE_M)); unallocated_encoding(s); diff --git a/target/arm/translate.c b/target/arm/translate.c index 6617de775f..4ffb095c73 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9378,6 +9378,8 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) dc->vec_len =3D EX_TBFLAG_A32(tb_flags, VECLEN); dc->vec_stride =3D EX_TBFLAG_A32(tb_flags, VECSTRIDE); } + dc->sme_trap_nonstreaming =3D + EX_TBFLAG_A32(tb_flags, SME_TRAP_NONSTREAMING); } dc->cp_regs =3D cpu->cp_regs; dc->features =3D env->features; diff --git a/target/arm/meson.build b/target/arm/meson.build index 6dd7e93643..87e911b27f 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,6 +1,7 @@ gen =3D [ decodetree.process('sve.decode', extra_args: '--decode=3Ddisas_sve'), decodetree.process('sme.decode', extra_args: '--decode=3Ddisas_sme'), + decodetree.process('sme-fa64.decode', extra_args: '--static-decode=3Ddis= as_sme_fa64'), decodetree.process('neon-shared.decode', extra_args: '--decode=3Ddisas_n= eon_shared'), decodetree.process('neon-dp.decode', extra_args: '--decode=3Ddisas_neon_= dp'), decodetree.process('neon-ls.decode', extra_args: '--decode=3Ddisas_neon_= ls'), --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.15.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:15:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4m+iHIMfbnBsMZ3ri5BagDQ5TJ6WuhbAqlKM6iP5vPw=; b=nmANE5U35j25gFU7ETbeA1uxSVgTzLBgebsI/S2YU3LSnW6FpoIa3Lip7EFmCmycic I2Rrt53oH6gN40isCMojFtcDgwq74vsHj/S4yljs9fha30k5MY0L/G34BsBcbkjA2GTp PMmaMCTzVKs1cOHM8I4enO5WY2Po7Gz1Jam3FNgmujVCuL9IV+JURnL7gZtAXEteR+/S cEvyjcHoqNqNZqYea01pXAObC9A3I8ueYdDCIcOdyb4qanhAxQRwFD4QmkdqhYSVQCls Wj3uiFJhEMUndB06nycx9PABLaQsJGiOOm1fsQ4KOHshmwRXhF4TvxdgVtTqEhBh7dKW uYWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4m+iHIMfbnBsMZ3ri5BagDQ5TJ6WuhbAqlKM6iP5vPw=; b=O2eMMM7aJTNwZwoM/PksF066Np5zfHdLoOjrPI7jin/D6lEdYrHPnADTiPwFX1Dc4f B8wFk6nsXBVVOvrbgT8xncWr6QEtsS8H+jXwBkTSfomC/O154equgbPO7T21TGybBTxf 10emUmKHbnjF9yam8v3BDgIUL88aipgPMQTKlO+tBZPQf/4YuiE81WDS78RGJ9rG5T8Q Y+kd0l925pEB2MI6AhWJpRsLvIfsQkgQaYwBfRzPSRbMLZllrORdS7U9py0uyhpRp9rM W28Nmad+qS2wLoRZkFlpKSeKwA4POvinJXnby8ZaXSGU34/Ll59PyCcAyr4B5VKlPS7r IgOA== X-Gm-Message-State: AJIora+ekMg0kC9EiJGyynFzwYnQVpKJjhqW/WGEF+BcVOpJRbNVuKqI DqWV0hU/61C7YtteOm0EJC3tJafTDKTpTdUV X-Google-Smtp-Source: AGRyM1s4/YHs/RDBXCgJIGhd6knp9kLjFPKuZUBiYzLWL6weMWwRGa9AwJTl68h+gjCoHHUk9u7tZA== X-Received: by 2002:a17:90a:fe4:b0:1ef:8564:4f4 with SMTP id 91-20020a17090a0fe400b001ef856404f4mr382248pjz.118.1657293358766; Fri, 08 Jul 2022 08:15:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 04/45] target/arm: Mark ADR as non-streaming Date: Fri, 8 Jul 2022 20:44:59 +0530 Message-Id: <20220708151540.18136-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657293818605100001 Content-Type: text/plain; charset="utf-8" Mark ADR as a non-streaming instruction, which should trap if full a64 support is not enabled in streaming mode. Removing entries from sme-fa64.decode is an easy way to see what remains to be done. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.h | 7 +++++++ target/arm/sme-fa64.decode | 1 - target/arm/translate-sve.c | 8 ++++---- 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index cbc907c751..e2e619dab2 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -566,4 +566,11 @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int = op); static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); } =20 +#define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...) \ + static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ + { \ + s->is_nonstreaming =3D true; \ + return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \ + } + #endif /* TARGET_ARM_TRANSLATE_H */ diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 3d90837fc7..73c71abc46 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -59,7 +59,6 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVT= ZS # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) =20 -FAIL 0000 0100 --1- ---- 1010 ---- ---- ---- # ADR FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT FAIL 0010 0101 --01 100- 1111 000- ---0 ---- # RDFFR, RDFFRS diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 62b5f3040c..5d1db0d3ff 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1320,10 +1320,10 @@ static bool do_adr(DisasContext *s, arg_rrri *a, ge= n_helper_gvec_3 *fn) return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm); } =20 -TRANS_FEAT(ADR_p32, aa64_sve, do_adr, a, gen_helper_sve_adr_p32) -TRANS_FEAT(ADR_p64, aa64_sve, do_adr, a, gen_helper_sve_adr_p64) -TRANS_FEAT(ADR_s32, aa64_sve, do_adr, a, gen_helper_sve_adr_s32) -TRANS_FEAT(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u32) +TRANS_FEAT_NONSTREAMING(ADR_p32, aa64_sve, do_adr, a, gen_helper_sve_adr_p= 32) +TRANS_FEAT_NONSTREAMING(ADR_p64, aa64_sve, do_adr, a, gen_helper_sve_adr_p= 64) +TRANS_FEAT_NONSTREAMING(ADR_s32, aa64_sve, do_adr, a, gen_helper_sve_adr_s= 32) +TRANS_FEAT_NONSTREAMING(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u= 32) =20 /* *** SVE Integer Misc - Unpredicated Group --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657293682; cv=none; d=zohomail.com; s=zohoarc; b=U29XpBFdEgz4LSscdlsVKqA+aHBynFUauu43IqFPf0IsFOzVA8sM4QfnmaOECYyzsJOWYWwtbXTab9p+qrEplJ/j1N2adT6WB5+1nhL2WLShLHTjZ65Mz3H+fyqZjVzo6QPaHQPFCnmntzlLkHK7esuJ6osPOqFRU4vEwv8gOek= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657293682; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pHHLspKH8W4B5YilQ8WrGPBQ+uTIDLVeEbSmBurKp7U=; b=cN0sjgUpFYQpHPDLgoB989wvb/xULyG1McdH3F6Mvg+F2O1O0k945X6z8dQPeC7q2wSm1lFgYq5YhPO9K8IwavesB7SFrVRlIhEaxRLWe5QJ2mNuCqQ1DOsDV4dgkLHLZdydTJQZAaAVFATTKTH56yThyQoKJAI895N1sJpNTaE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657293682365557.1628375930915; Fri, 8 Jul 2022 08:21:22 -0700 (PDT) Received: from localhost ([::1]:58034 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9pnF-0003He-6Y for importer@patchew.org; Fri, 08 Jul 2022 11:21:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36670) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pi8-0002Ap-Ld for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:05 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:39448) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pi7-00026i-1G for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:04 -0400 Received: by mail-pf1-x42b.google.com with SMTP id j3so11128631pfb.6 for ; Fri, 08 Jul 2022 08:16:02 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.15.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pHHLspKH8W4B5YilQ8WrGPBQ+uTIDLVeEbSmBurKp7U=; b=LymeUmereyzsWgRmarJbmGBzZH0FYFvLJpiuGxJzP7qhTADbJGJx4ohnYrI9DyDmDn fAhoCLjdIAIp/L9AbN7d+RSWI8Rpa1y6rD0F5naxbIof+zgNEmZhgBsDtvimWNUSZ106 NIr9AzSlae4cghM9W3RqRqQEEa5365cwtKpmFChLSTOGSDAycF0lziNjYQ0GSLmx6+S/ 3Swwc4PAJZq8088nEysmWcyuwdVmQglkgZ/ufWyBdHceJ29NPavDzuWaOslIhSWvNOYK 5Z4NJo8PkUrRS8fKIcJm6q83VhvskP0G//lOr6jwF5RzkMJAyT5ecUyAQlCzbK7FmA+E We4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pHHLspKH8W4B5YilQ8WrGPBQ+uTIDLVeEbSmBurKp7U=; b=V9L9Ks1bHe+PbgR3gnrXTOt9ZvrujiDa+86DWPVlsWvyCyKBNUV8g/UGlFyBYBfDW5 N3bQluy5Z40Z3ACeeeHEp3yFs9fgiQLf5eIDjIRhpA/VNMXi5/MFbv0N/sPn0c90dYNa zIb8D/CiB6oY9wbVI4aKXKU63HE33JxdYyver5xWbH0+Er5mIayhSJHDcd1F/5DF3r6+ VRqvIW1Q4fQwAc4V14WxHOzZIXH49eTAzz5L2vHeRKoPfFAZEhJG4WmfRSQtjlau1Rfl 1qEDR/G7Ey6ufecbEiZqFoYv0trKn1p7fMezp0SzckZvgQtnVDbotD72b7W0y8BUihhA X7Nw== X-Gm-Message-State: AJIora/Uj5oJxsTligaL/IVrpqAYQSG3DBCwS0enncXYOdxhjVM5NtNz +aQe4Mk9Z/1mZ6uCg6QB273t+x4yohds9+2f X-Google-Smtp-Source: AGRyM1tALuRNY8SBqjNwza8h783NMt5ff0HQw4KSW0G4G/m+Jp7rTVGHhxRVDPzWFcVJ3bLTOMaNOg== X-Received: by 2002:a65:6048:0:b0:412:73c7:cca9 with SMTP id a8-20020a656048000000b0041273c7cca9mr3873181pgp.257.1657293361529; Fri, 08 Jul 2022 08:16:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 05/45] target/arm: Mark RDFFR, WRFFR, SETFFR as non-streaming Date: Fri, 8 Jul 2022 20:45:00 +0530 Message-Id: <20220708151540.18136-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657293683417100001 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 2 -- target/arm/translate-sve.c | 9 ++++++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 73c71abc46..fa2b5cbf1a 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -61,8 +61,6 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVT= ZS =20 FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT -FAIL 0010 0101 --01 100- 1111 000- ---0 ---- # RDFFR, RDFFRS -FAIL 0010 0101 --10 1--- 1001 ---- ---- ---- # WRFFR, SETFFR FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b r= esult) FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 5d1db0d3ff..d6faec15fe 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1785,7 +1785,8 @@ static bool do_predset(DisasContext *s, int esz, int = rd, int pat, bool setflag) TRANS_FEAT(PTRUE, aa64_sve, do_predset, a->esz, a->rd, a->pat, a->s) =20 /* Note pat =3D=3D 31 is #all, to set all elements. */ -TRANS_FEAT(SETFFR, aa64_sve, do_predset, 0, FFR_PRED_NUM, 31, false) +TRANS_FEAT_NONSTREAMING(SETFFR, aa64_sve, + do_predset, 0, FFR_PRED_NUM, 31, false) =20 /* Note pat =3D=3D 32 is #unimp, to set no elements. */ TRANS_FEAT(PFALSE, aa64_sve, do_predset, 0, a->rd, 32, false) @@ -1799,11 +1800,13 @@ static bool trans_RDFFR_p(DisasContext *s, arg_RDFF= R_p *a) .rd =3D a->rd, .pg =3D a->pg, .s =3D a->s, .rn =3D FFR_PRED_NUM, .rm =3D FFR_PRED_NUM, }; + + s->is_nonstreaming =3D true; return trans_AND_pppp(s, &alt_a); } =20 -TRANS_FEAT(RDFFR, aa64_sve, do_mov_p, a->rd, FFR_PRED_NUM) -TRANS_FEAT(WRFFR, aa64_sve, do_mov_p, FFR_PRED_NUM, a->rn) +TRANS_FEAT_NONSTREAMING(RDFFR, aa64_sve, do_mov_p, a->rd, FFR_PRED_NUM) +TRANS_FEAT_NONSTREAMING(WRFFR, aa64_sve, do_mov_p, FFR_PRED_NUM, a->rn) =20 static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a, void (*gen_fn)(TCGv_i32, TCGv_ptr, --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657293847; cv=none; d=zohomail.com; s=zohoarc; b=gGd0rCjFbkjQcFJu0eeqqVv2bM1TgGjbC1ie2xL4ZUQxMuPKtnhgVgy3npi3FLJ2nJadrokA7FaViJHkri2Xc5cEMGBQXht6Cc6/lWzJRF4DjPe2Uy2gjh3kf7E+7iuHGHLtxw/Dx7jK96j2N9KmGzqbuDnJqOWRjAF8rzb32K4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657293847; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hqPebj8e+A/slNwJFXKTlqvHw3rlOVkEOFZ7HeJe4nE=; b=BbyJczgFL3Wuy/rbFzHNiDP5LUHJdmrDdvZ3pQFB05bkQeuXdgBa2f+uuZz3RERTJWQxOijOEXVLGc1NEBn0IfsJvqIpdFEp5XIpuHDvnt38FxU+IGhIKQcyVbsFSKcAscamOvSJwS2De8iSArw2A7qNgxYXFNNcxuZBGM5wpls= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657293847113553.3353231740807; Fri, 8 Jul 2022 08:24:07 -0700 (PDT) Received: from localhost ([::1]:39294 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9ppt-0001De-33 for importer@patchew.org; Fri, 08 Jul 2022 11:24:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36714) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9piC-0002Cs-4e for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:08 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:37718) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9piA-00027j-Il for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:07 -0400 Received: by mail-pf1-x42c.google.com with SMTP id w185so20054379pfb.4 for ; Fri, 08 Jul 2022 08:16:06 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hqPebj8e+A/slNwJFXKTlqvHw3rlOVkEOFZ7HeJe4nE=; b=kXgJ9LljZCm79DFXUXbuhkRulo8yv+p8i3+9PHDQv6J0cHJIJV4ExvhaI2on95XwVx Yfuly0cxUh9SOzHGYIXeCqLPSqgIX2di/iR2yn52keYIIbUfaKthCZXbnd/LNXlSySwI qSeXA8WOBRyXq4qHNJ7Nw51p1gQVvzgkjQ2Qe97HjD4U4z1bH2B54gWq6jCXJJ61Gw8T pGdTMDio/RkCcXPIDqECMPIj4E5XKZzJHKDHnAxnKcXP1S0UE0on0XMfOnZS2PsanNtG bPNKB8QwUgjIT08+EvMgmv88h3KzTny4mS3JK70ILoRbVHvpyXOJiK5owhoRaCOR1udU gVNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hqPebj8e+A/slNwJFXKTlqvHw3rlOVkEOFZ7HeJe4nE=; b=JEmNOaQDXoxT9oZbHP+4pmctiu5B2Vl+kTedkZK9oiP9aOSit5tKdbBDL3Xd4wR91m m/C7AKDz3kOQYSIMiVRyTpVqfE8wDDiFBn4S/VhLk1CWjE0W1jAePWaH0eht+cdNkMjb pa/Q4mROhNIIOMDJ2ZVk+aSspRIfWb29hgFDttL15Sossyg9z8PbrHBxTk3AUfDZz+FZ pVl+ILcFu0tSuUfnHKoS3B4aWPfFqJqn3qjrPiT21Tlx8cbrToanUdcDevv+uXd6vw+a 9EMFksX+TzMdQwLSnwwk4preY+gAyrN/gqC6uxqbHaK+GT58eFVOMZATSITQ/lnRjduV 0BVQ== X-Gm-Message-State: AJIora9CmmwqzNhh9ZfzuCx3FnAcEf9mI9pBVnkN7jykIvmJ1IxWRjkd o5UTGF8pDBzPvppk7iGWH7fEUCCcp5maCwUW X-Google-Smtp-Source: AGRyM1uWqDt4uZ+y+i3b/StG5sO5CP3NHBjpuyW1ihj+8JFJL5azmEgX9xVBXltx4Cm0vR240h0FXg== X-Received: by 2002:a63:150:0:b0:412:acfc:b6bf with SMTP id 77-20020a630150000000b00412acfcb6bfmr3742308pgb.377.1657293365192; Fri, 08 Jul 2022 08:16:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streaming Date: Fri, 8 Jul 2022 20:45:01 +0530 Message-Id: <20220708151540.18136-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657293848679100001 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 22 ++++++++++++---------- 2 files changed, 12 insertions(+), 13 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index fa2b5cbf1a..4f515939d9 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -59,9 +59,6 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVT= ZS # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) =20 -FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA -FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT -FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b r= esult) FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index d6faec15fe..ae48040aa4 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1333,14 +1333,15 @@ static gen_helper_gvec_2 * const fexpa_fns[4] =3D { NULL, gen_helper_sve_fexpa_h, gen_helper_sve_fexpa_s, gen_helper_sve_fexpa_d, }; -TRANS_FEAT(FEXPA, aa64_sve, gen_gvec_ool_zz, - fexpa_fns[a->esz], a->rd, a->rn, 0) +TRANS_FEAT_NONSTREAMING(FEXPA, aa64_sve, gen_gvec_ool_zz, + fexpa_fns[a->esz], a->rd, a->rn, 0) =20 static gen_helper_gvec_3 * const ftssel_fns[4] =3D { NULL, gen_helper_sve_ftssel_h, gen_helper_sve_ftssel_s, gen_helper_sve_ftssel_d, }; -TRANS_FEAT(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz, ftssel_fns[a->esz], a, = 0) +TRANS_FEAT_NONSTREAMING(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz, + ftssel_fns[a->esz], a, 0) =20 /* *** SVE Predicate Logical Operations Group @@ -2536,7 +2537,8 @@ TRANS_FEAT(TRN2_q, aa64_sve_f64mm, gen_gvec_ool_arg_z= zz, static gen_helper_gvec_3 * const compact_fns[4] =3D { NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d }; -TRANS_FEAT(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz, compact_fns[a->esz], a= , 0) +TRANS_FEAT_NONSTREAMING(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz, + compact_fns[a->esz], a, 0) =20 /* Call the helper that computes the ARM LastActiveElement pseudocode * function, scaled by the element size. This includes the not found @@ -6374,22 +6376,22 @@ static gen_helper_gvec_3 * const bext_fns[4] =3D { gen_helper_sve2_bext_b, gen_helper_sve2_bext_h, gen_helper_sve2_bext_s, gen_helper_sve2_bext_d, }; -TRANS_FEAT(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, - bext_fns[a->esz], a, 0) +TRANS_FEAT_NONSTREAMING(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, + bext_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const bdep_fns[4] =3D { gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h, gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d, }; -TRANS_FEAT(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, - bdep_fns[a->esz], a, 0) +TRANS_FEAT_NONSTREAMING(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, + bdep_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const bgrp_fns[4] =3D { gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h, gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d, }; -TRANS_FEAT(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, - bgrp_fns[a->esz], a, 0) +TRANS_FEAT_NONSTREAMING(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, + bgrp_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const cadd_fns[4] =3D { gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h, --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657293640; cv=none; d=zohomail.com; s=zohoarc; b=VKVdu0y1mBbSqfj1Q28hpybDiCAEPmWQDLc895QDcjkvLSJQD6YFgSnfKBhd/a7H+HJrwkggUTJBjlGuipGUBB/KDiAeHBrG/V1vpevcUnCuAJi/Otwd27/bSM+N4J91M1kzrcsFhQRJI5yUK9ytWZ2xlDTtMJoI6c3ZSEqTLBQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657293640; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1btQdC+wS4/yxekRBbxVZ7KHECPJ8mO9wBrq6XRLd5o=; b=P2opyhPCaIFd2s/2Z8ik06IJiguKH8mBQU4dVv/gLyxQ/lKw1QJRNwcRYfV7XPyTWxlA4tgyCNJZGcE87dZfLqTOzrpwo7diRCZfwlIQGKmKU4Sp+T/F510xRuME9UDcnqMRyduS6P0/juA5YVX9DL8d4zjXpqb/TpUVBrowlgY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657293640835416.5966914092361; Fri, 8 Jul 2022 08:20:40 -0700 (PDT) Received: from localhost ([::1]:54922 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9pmZ-0001DO-LW for importer@patchew.org; Fri, 08 Jul 2022 11:20:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9piL-0002Gx-4d for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:17 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:43696) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9piJ-00028O-DK for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:16 -0400 Received: by mail-pl1-x634.google.com with SMTP id r1so16579535plo.10 for ; Fri, 08 Jul 2022 08:16:08 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1btQdC+wS4/yxekRBbxVZ7KHECPJ8mO9wBrq6XRLd5o=; b=Y2cqkqQprZjZ+NYRn8GL83vhWWxcMj3hSnUxtktqdGKMj1lqrMnXMkpbOHpFrwPEKy /2eOovz4LK/p+CTAExvCORH344VxMemi0l7e397ocTXBUFyveLvtsv5aEk0J3zJsE8o6 1wZjf4pXFE/ZvIomvriwt+tTYk/gknA+71ge8fYJOTlSKIkt4+2HmWThScQwSx5nPZrD +pFX7mHWwFk8joLyg3uJPg8/0mcnvf1lnYun9Z+4XLjYqxvzM5KVvePoPJ4/e8wzjhNN wHpRbkGakvoPTrQzUOzxcSDpQLg+dcBwuU3qTRYJ71SMNlBTo5oeLNJxkyI2Axy9ex7j 5Jwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1btQdC+wS4/yxekRBbxVZ7KHECPJ8mO9wBrq6XRLd5o=; b=IFQ0jCe+/Zy0CZnelIUtTn4BFoVB1ORJQt+8MVX/g/lg6N+suc2mtSaG1rM8iMfljh E0ohxjrRzzimsO52mmLZHxfoaSJhLzYVxdzpjwXtKh3lSe6nBmnTNgk9OjwxgV5MuBjG rslnuFmnzu7cevB6acN7Z3ZAywHZIAbZnWXn5L9ZSVXA6GGLYqVPFEEIlA0gjajNVjuS L9Gzw0SVUJ6AsukWp9YIu4FcyR89jNv91P3Kec9JyMAoIjttAeuSisykQoRSt1GzAjK6 hoDrYWkuH8muSdfCFjvmpOOn1wrOwk57jV4ovyH3RDhTkBuHf2rOaFFYkavFzaEeOZwz esew== X-Gm-Message-State: AJIora9bx2huyYTshA/5AQYM8/Dpcb0hHTSv4INuM27EW+zLiajIQNUU I9vzJ8kkv9Y0nJz0Z14sfuB6r6FUOzSIA48K X-Google-Smtp-Source: AGRyM1uXVLsidLDsKHRKlZwECTR+RJi26d7Udry4GwXIjsLZz478J+34+hv3vj66YY4Qjf5jLZWGDw== X-Received: by 2002:a17:90a:9411:b0:1ef:9c3f:9a07 with SMTP id r17-20020a17090a941100b001ef9c3f9a07mr379692pjo.150.1657293367862; Fri, 08 Jul 2022 08:16:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 07/45] target/arm: Mark PMULL, FMMLA as non-streaming Date: Fri, 8 Jul 2022 20:45:02 +0530 Message-Id: <20220708151540.18136-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657293641191100001 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 2 -- target/arm/translate-sve.c | 24 +++++++++++++++--------- 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 4f515939d9..4ff2df82e5 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -59,8 +59,6 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVT= ZS # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) =20 -FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b r= esult) -FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index ae48040aa4..4ff2102fc8 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -6186,9 +6186,13 @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_= esz *a, bool sel) gen_helper_gvec_pmull_q, gen_helper_sve2_pmull_h, NULL, gen_helper_sve2_pmull_d, }; - if (a->esz =3D=3D 0 - ? !dc_isar_feature(aa64_sve2_pmull128, s) - : !dc_isar_feature(aa64_sve, s)) { + + if (a->esz =3D=3D 0) { + if (!dc_isar_feature(aa64_sve2_pmull128, s)) { + return false; + } + s->is_nonstreaming =3D true; + } else if (!dc_isar_feature(aa64_sve, s)) { return false; } return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel); @@ -7125,10 +7129,12 @@ DO_ZPZZ_FP(FMINP, aa64_sve2, sve2_fminp_zpzz) * SVE Integer Multiply-Add (unpredicated) */ =20 -TRANS_FEAT(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_s, - a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR) -TRANS_FEAT(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_d, - a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR) +TRANS_FEAT_NONSTREAMING(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, + gen_helper_fmmla_s, a->rd, a->rn, a->rm, a->ra, + 0, FPST_FPCR) +TRANS_FEAT_NONSTREAMING(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, + gen_helper_fmmla_d, a->rd, a->rn, a->rm, a->ra, + 0, FPST_FPCR) =20 static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] =3D { NULL, gen_helper_sve2_sqdmlal_zzzw_h, @@ -7301,8 +7307,8 @@ TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_ar= g_zzzz, TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_ool_arg_zzxz, gen_helper_gvec_bfdot_idx, a) =20 -TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, - gen_helper_gvec_bfmmla, a, 0) +TRANS_FEAT_NONSTREAMING(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, + gen_helper_gvec_bfmmla, a, 0) =20 static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) { --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657294032; cv=none; d=zohomail.com; s=zohoarc; b=WMchlPO2ZvzevL7UGr8THmLQQ+0FWp4JDCIQXrg+9qNcD0wuiZ4gj4OLawuV/8J1Himvb5r08OK6C9ElyprEosvNkjFXieIOp3YtYEtIIQuDnPhLDvBVb16fe3v0EXofRqSMJ1I5+449aTDvO7buWGhsFxfFwt23yBonme0TjGs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657294032; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dcHardhOi3ouG3QD1ZaU/LIrZV5tMarYA0PaEYIlrzQ=; b=g4LyznXd1R0mSpLRa1xeuo/OelLEWEuWQD07Bd8zVXr3ZESnDXolVZavX/S49Io3oo9XTOALWeJ7jPl0wLJps4Tcfj9F59qnUcrnaDT8vqQPlUkmPmUY6zlUyQDjmcTkeWmwl3sFZ5LpH2NIOJPR80SY7p8CdKPZVyMbeYBXZ/0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657294032761821.5210769104372; Fri, 8 Jul 2022 08:27:12 -0700 (PDT) Received: from localhost ([::1]:47982 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9pst-00070X-8q for importer@patchew.org; Fri, 08 Jul 2022 11:27:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9piM-0002Je-Qv for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:18 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:46800) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9piJ-00028f-Hc for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:18 -0400 Received: by mail-pl1-x635.google.com with SMTP id l12so11242826plk.13 for ; Fri, 08 Jul 2022 08:16:11 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dcHardhOi3ouG3QD1ZaU/LIrZV5tMarYA0PaEYIlrzQ=; b=Kwr26iqkjCDtSmnm+ohn3gHMOyDhs7H0tYEA5l2ola5RLrJmRAj62eXplKATYlO+Mm vyld0L2tA622ErAF27HRjpnMZVV3Bmpt8exBkjP7uCbNX8aXQWXrKESJD3+UJC+l+kqj J1cGc8fmNoOqnIUf0fHG3o57/CEU/Nv8o9ElBaLPGnN2mvwH0hBP7FV0jDuWQvwmpD67 79Tpyv72hU2xwOf3lbBneuucrpfU3DwqU9UajnwNP89RSBX9bv620n2gGwEWHo6XEK3n dzv80kzwM5HgAqy8wWhCrOSH00/R/zOMOOmXM1sknvrcG1+kISWUckbxvoYZS/zGqDt3 nI3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dcHardhOi3ouG3QD1ZaU/LIrZV5tMarYA0PaEYIlrzQ=; b=Khl9REw/B3hv62dPcPq+amWvqVEyMAiY1u8Ha4VXqu16HJxl2TnwbuSpL2z7Lsioj4 pTAmfmDoqo7ZdQZihFBB1o429VY6z8EO8R2W8jhTdotWvrKkvUc21GejXyKTPlPHqwQn ufEqN+9WNiW10DYdJ8MXjnIo3Z+0JxBdE5IRcOgs/BnCK1tv7qG0pXL46NMzNXYJEMQw cQtwOnxrvGCv9w5GZrzgxMxgRUIT3qynRDN94tj0BPxVYywrrqvUjjrfgePVuVP9NS98 Gc1Iak9dBd22xRpxl2DbHBfLaBZ5d2gCPgIgAa59vRBfHTlPhazLH9qN6rRnRxOGmmui JTow== X-Gm-Message-State: AJIora9B0MtXgxcrrCdM/fdX4bn3MdnfLebCCwlKd59/BuchU+E5ATVE bAdQv9fiXXiJAMG4pXOPXNm7vMQhKhBHcMXD X-Google-Smtp-Source: AGRyM1ui1MhCX79xPfUtef6Y7Ni5xwcq5j8IwhJH/XPmgvgGU9WQntxlNi03AUry1bMNYd0ZTTl1uw== X-Received: by 2002:a17:902:d2c8:b0:16c:58d:7278 with SMTP id n8-20020a170902d2c800b0016c058d7278mr4189287plc.45.1657293370509; Fri, 08 Jul 2022 08:16:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 08/45] target/arm: Mark FTSMUL, FTMAD, FADDA as non-streaming Date: Fri, 8 Jul 2022 20:45:03 +0530 Message-Id: <20220708151540.18136-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657294034212100001 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 15 +++++++++++---- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 4ff2df82e5..b5eaa2d0fa 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -59,9 +59,6 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVT= ZS # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) =20 -FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL -FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD -FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/cryp= to instructions FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT = load (vector+scalar) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 4ff2102fc8..d5aad53923 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3861,9 +3861,9 @@ static gen_helper_gvec_3_ptr * const ftmad_fns[4] =3D= { NULL, gen_helper_sve_ftmad_h, gen_helper_sve_ftmad_s, gen_helper_sve_ftmad_d, }; -TRANS_FEAT(FTMAD, aa64_sve, gen_gvec_fpst_zzz, - ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm, - a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_FPCR) +TRANS_FEAT_NONSTREAMING(FTMAD, aa64_sve, gen_gvec_fpst_zzz, + ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm, + a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_FPCR) =20 /* *** SVE Floating Point Accumulating Reduction Group @@ -3886,6 +3886,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz= *a) if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming =3D true; if (!sve_access_check(s)) { return true; } @@ -3923,12 +3924,18 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_e= sz *a) DO_FP3(FADD_zzz, fadd) DO_FP3(FSUB_zzz, fsub) DO_FP3(FMUL_zzz, fmul) -DO_FP3(FTSMUL, ftsmul) DO_FP3(FRECPS, recps) DO_FP3(FRSQRTS, rsqrts) =20 #undef DO_FP3 =20 +static gen_helper_gvec_3_ptr * const ftsmul_fns[4] =3D { + NULL, gen_helper_gvec_ftsmul_h, + gen_helper_gvec_ftsmul_s, gen_helper_gvec_ftsmul_d +}; +TRANS_FEAT_NONSTREAMING(FTSMUL, aa64_sve, gen_gvec_fpst_arg_zzz, + ftsmul_fns[a->esz], a, 0) + /* *** SVE Floating Point Arithmetic - Predicated Group */ --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657293999; cv=none; d=zohomail.com; s=zohoarc; b=CS5fOxBGyFvvGJNYyl5rIVgj4wZWKg5h5Ial2Y32gd5h+fUGuu0cy8lykmvMXYVQqAG6JeP0X7CsfdNtKuiGGswlzJuQi9GJWx24TGQCJ7p7HFlMvzQ01fLeNCZondn7ami4M24kmc1BsUpzphNK0E4Rv9oFzTMcPupGdwLhucI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657293999; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5diXjDkZ8lDduwnyqU3jDTWthnVlvOOyK5gnN0aC3a8=; b=ZMHvDQyfBKpGT4hS2Ggzzb7sz6RYrAzGLABiiuMM0ug0GbqE3rm4akrjoAbew0L7/rjcKSNNExcybQnv7/uAcpaJIGcTVYBdKGsSSDbiPUeIdd0fPR6e0iDd6XA7Jd5N1rXDYmkVtXd1YBtxqkA3w9YxJXh0WImeP9Y7v6MuFvU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657293999010718.1385244804923; Fri, 8 Jul 2022 08:26:39 -0700 (PDT) Received: from localhost ([::1]:47416 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9psL-0006cB-Pj for importer@patchew.org; Fri, 08 Jul 2022 11:26:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36852) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9piM-0002JL-Lq for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:18 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:41565) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9piJ-00028v-HE for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:18 -0400 Received: by mail-pj1-x1032.google.com with SMTP id o31-20020a17090a0a2200b001ef7bd037bbso2077454pjo.0 for ; Fri, 08 Jul 2022 08:16:14 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5diXjDkZ8lDduwnyqU3jDTWthnVlvOOyK5gnN0aC3a8=; b=Xs3H7pLUVLv3IoFcOon/LnA0jyYXOtIP3GG0z5bduOSK+/4xR6NraKw3xYUIV7FQJv 4LiUjycXwmCFTnB1seIu8ult4nKMsQH7edhVNKeN50mCwDLJys4JFOraULBTvmLbgHuJ sAlsknEevjBqTLzX7/RG+2ijUsBes8oVWjtgPKiuExUylfqHlgDFH5EojSOgOBJoxRAj HAfgKRGtIIiGt3N9oxjkNOjhivcvd9+bUpNdg/0Xa0xgy+rYxDaYCjLVx8YBGrmkBZuv hc+oyz4jrrPKkRbINfy1UcDJaJNBS7KfV4tQh09YhHdxUVsfsMxoHPKGIslvCZRyIkJP r8Eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5diXjDkZ8lDduwnyqU3jDTWthnVlvOOyK5gnN0aC3a8=; b=dtlUnM97XXKE385RAgnc7MV68GZuoLFGWvtLENqlZEQE3no7/hTJP0AEpK7kfB6TX7 +p06NfpJpk48IXgHnlOeqwtPwA+i4Cd53VY5868/bhy1E7pgUzEVW2x5AtImyb7OMwEb zIFCg6KF7436PDkDEhXseeiPBhFHd/YqrIPcA1AE7DCoAERVXECy7RsouLHjs4FxHgh8 STBS2PCqxF7ffnmF1XWcGljpYADv0JzH6jyNbvtI7CW+KsfJnBOD+SBqi5/0MWMslWrB Ptpa4KRtvAahK/fgYefW0eEPZ9nFYJPYcem2dQE+euYOwm5Plr0eKpIIpgkcHO27C2/f SZMQ== X-Gm-Message-State: AJIora+fHl1OTup0FvPlBFN0MehFhzzBxI3nBdVVIwHcJLBijFHHK2Ot fbPP1eVFh+27PlRrGYW10MXbu2aTUXmT4OOE X-Google-Smtp-Source: AGRyM1uYZKvvrVrVV7Dhd3fT8IP4/ZZjIR90JRf64CMeFoRTE2dQ7sCCJYQkutgystlu9Xoe5AFkJg== X-Received: by 2002:a17:902:aa47:b0:16b:8e4c:93d2 with SMTP id c7-20020a170902aa4700b0016b8e4c93d2mr4211237plr.27.1657293373640; Fri, 08 Jul 2022 08:16:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 09/45] target/arm: Mark SMMLA, UMMLA, USMMLA as non-streaming Date: Fri, 8 Jul 2022 20:45:04 +0530 Message-Id: <20220708151540.18136-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657294000024100001 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 1 - target/arm/translate-sve.c | 12 ++++++------ 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index b5eaa2d0fa..3260ea2d64 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -59,7 +59,6 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVT= ZS # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) =20 -FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/cryp= to instructions FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT = load (vector+scalar) FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather pref= etch (vector+imm) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index d5aad53923..9bbf44f008 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7302,12 +7302,12 @@ TRANS_FEAT(FMLALT_zzxw, aa64_sve2, do_FMLAL_zzxw, a= , false, true) TRANS_FEAT(FMLSLB_zzxw, aa64_sve2, do_FMLAL_zzxw, a, true, false) TRANS_FEAT(FMLSLT_zzxw, aa64_sve2, do_FMLAL_zzxw, a, true, true) =20 -TRANS_FEAT(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, - gen_helper_gvec_smmla_b, a, 0) -TRANS_FEAT(USMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, - gen_helper_gvec_usmmla_b, a, 0) -TRANS_FEAT(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, - gen_helper_gvec_ummla_b, a, 0) +TRANS_FEAT_NONSTREAMING(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, + gen_helper_gvec_smmla_b, a, 0) +TRANS_FEAT_NONSTREAMING(USMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, + gen_helper_gvec_usmmla_b, a, 0) +TRANS_FEAT_NONSTREAMING(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, + gen_helper_gvec_ummla_b, a, 0) =20 TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, gen_helper_gvec_bfdot, a, 0) --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657293747; cv=none; d=zohomail.com; s=zohoarc; b=nxbLwZlIOgfM5SahmBdSIWVSc/0ayEwZ3/Tj35O9MspEPNhLXaRLEr5P3053QOj5gSYE1PbrKrOU9+rO6c32dkgpxbfUE++YX6nk2yNZeoXHwiEi6vbyiB5eOHoz8PfEheoZKjnvD6r2P8SwiIgHtFfP+IDThujEqdRj1CQXRSo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657293747; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eMDZljSMa7lgcdxc4v8wiBGe99d03Zr6CetA/Z+JkFo=; b=TWAkmN5z8rMjfpJxcjkSCJcp4vVJF05iLrAX2TS5GtUr7EsgPVzHSIJ+GuEPMR/Wd2PQv9b4sWzzVK9Nw5rHQaNzTFUGVY7rJpREdvPlhXZHjrDN5l4BqruvtlA7g2R0xxxuhJsHmUe4cVqzeSYHhc7Oh4dUwfb+/73vlpYO1LA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657293747384282.76519968129287; Fri, 8 Jul 2022 08:22:27 -0700 (PDT) Received: from localhost ([::1]:32962 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9poH-0005OG-7u for importer@patchew.org; Fri, 08 Jul 2022 11:22:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36896) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9piO-0002Mf-8z for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:20 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:40667) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9piL-0002C5-UN for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:19 -0400 Received: by mail-pg1-x533.google.com with SMTP id i190so10003669pge.7 for ; Fri, 08 Jul 2022 08:16:17 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eMDZljSMa7lgcdxc4v8wiBGe99d03Zr6CetA/Z+JkFo=; b=bBknTnwsvdYJ4IH1HT01E84YxRPB2fwfykMBOcWty8HM9jm8/FtapVvikPFxogSODI qg0kbuSeoj83xAJg9Vijff0IAhikgXw/XFNBwCV5uczREBnl4vMUAqGffZWjJxwjN/qN jWwortGJt+JzqKMTA6mr5hqeo2FoMmt24MFEEb5BWOe7fG7KiN76cjheNASg5ztBPpwL hOd5zh+boO+IFM6eiczMQPm1b1gzWdQN9XeeeETW7wIm1vmS9MCDyixbhmOZ2pyu8TmD hXXELyQ111U8O9KdW/DyCKn5nCPxWuRQkZCfoxOaDhRxSEO7ze8d6mXXE0AP5zJPC5cs ZFXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eMDZljSMa7lgcdxc4v8wiBGe99d03Zr6CetA/Z+JkFo=; b=JCmxNgqYx1435T/75bZX5Zlcv0OI1hnpQMwhwl9mhSFQpZh6+DiW9bZPGWuEdj4+r0 XVISpjzd/gPyVyb6tAdTL2bCK8/ekdqOnIdafHZDBo0fhK3EbKWCNQOJtWJQoCZO0erH NdG4t52+0UwdkaEDRjBCgqzttqz4oW6CLAFriytUBJNJdWJ/f9gvlcyE+NmcamfJyyWT ACfcRWZ1AHGZiP5dG8xaVnJRyOzm45M49M4NzhXrUmml+FxUzC07yE7MelNl/jYiMSWD bRwEbcZcHsLzrmjp3pe7GR4prRYli+ascMR39hpHeVx0pxLKacr1mtpSlUFS0PhA1q5b IxiQ== X-Gm-Message-State: AJIora9ep/HFOW4Omikko3Nce/QElvjv2oH5zl+h5XCxumlzJhJ3q16B hT6uSHS+eiKsbMXgKe6mjwQcPqUGmNWYcEbl X-Google-Smtp-Source: AGRyM1t2GnmiOauwwo1umLM5kzWGq0hXaBFHmMjJz/T48Py69c31erlErFGvFiiRLFMZyHmxAeS9jA== X-Received: by 2002:a63:1a09:0:b0:3fd:ac2b:3876 with SMTP id a9-20020a631a09000000b003fdac2b3876mr3728690pga.457.1657293376465; Fri, 08 Jul 2022 08:16:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 10/45] target/arm: Mark string/histo/crypto as non-streaming Date: Fri, 8 Jul 2022 20:45:05 +0530 Message-Id: <20220708151540.18136-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657293747975100001 Content-Type: text/plain; charset="utf-8" Mark these as non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 1 - target/arm/translate-sve.c | 35 ++++++++++++++++++----------------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 3260ea2d64..fe462d2ccc 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -59,7 +59,6 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVT= ZS # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) =20 -FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/cryp= to instructions FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT = load (vector+scalar) FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather pref= etch (vector+imm) FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather pref= etch (scalar+vector) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 9bbf44f008..f8e0716474 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7110,21 +7110,21 @@ DO_SVE2_ZZZ_NARROW(RSUBHNT, rsubhnt) static gen_helper_gvec_flags_4 * const match_fns[4] =3D { gen_helper_sve2_match_ppzz_b, gen_helper_sve2_match_ppzz_h, NULL, NULL }; -TRANS_FEAT(MATCH, aa64_sve2, do_ppzz_flags, a, match_fns[a->esz]) +TRANS_FEAT_NONSTREAMING(MATCH, aa64_sve2, do_ppzz_flags, a, match_fns[a->e= sz]) =20 static gen_helper_gvec_flags_4 * const nmatch_fns[4] =3D { gen_helper_sve2_nmatch_ppzz_b, gen_helper_sve2_nmatch_ppzz_h, NULL, NU= LL }; -TRANS_FEAT(NMATCH, aa64_sve2, do_ppzz_flags, a, nmatch_fns[a->esz]) +TRANS_FEAT_NONSTREAMING(NMATCH, aa64_sve2, do_ppzz_flags, a, nmatch_fns[a-= >esz]) =20 static gen_helper_gvec_4 * const histcnt_fns[4] =3D { NULL, NULL, gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d }; -TRANS_FEAT(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz, - histcnt_fns[a->esz], a, 0) +TRANS_FEAT_NONSTREAMING(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz, + histcnt_fns[a->esz], a, 0) =20 -TRANS_FEAT(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz, - a->esz =3D=3D 0 ? gen_helper_sve2_histseg : NULL, a, 0) +TRANS_FEAT_NONSTREAMING(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz, + a->esz =3D=3D 0 ? gen_helper_sve2_histseg : NULL, = a, 0) =20 DO_ZPZZ_FP(FADDP, aa64_sve2, sve2_faddp_zpzz) DO_ZPZZ_FP(FMAXNMP, aa64_sve2, sve2_fmaxnmp_zpzz) @@ -7238,20 +7238,21 @@ TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sve2, gen_gvec_ool_= zzzz, TRANS_FEAT(USDOT_zzzz, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, a->esz =3D=3D 2 ? gen_helper_gvec_usdot_b : NULL, a, 0) =20 -TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz, - gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt) +TRANS_FEAT_NONSTREAMING(AESMC, aa64_sve2_aes, gen_gvec_ool_zz, + gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt) =20 -TRANS_FEAT(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz, - gen_helper_crypto_aese, a, false) -TRANS_FEAT(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz, - gen_helper_crypto_aese, a, true) +TRANS_FEAT_NONSTREAMING(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz, + gen_helper_crypto_aese, a, false) +TRANS_FEAT_NONSTREAMING(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz, + gen_helper_crypto_aese, a, true) =20 -TRANS_FEAT(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, - gen_helper_crypto_sm4e, a, 0) -TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, - gen_helper_crypto_sm4ekey, a, 0) +TRANS_FEAT_NONSTREAMING(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, + gen_helper_crypto_sm4e, a, 0) +TRANS_FEAT_NONSTREAMING(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, + gen_helper_crypto_sm4ekey, a, 0) =20 -TRANS_FEAT(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a) +TRANS_FEAT_NONSTREAMING(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, + gen_gvec_rax1, a) =20 TRANS_FEAT(FCVTNT_sh, aa64_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_sh, a, 0, FPST_FPCR) --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657293811; cv=none; d=zohomail.com; s=zohoarc; b=lonvld1tumz5bHtJKk0PwdXc/4bnLzrh+Wz4enUJeFSB2OKOi3inbUaFUjzk7ktX5fEifZjoXnCrvp0DFmC3yFTNBfgRdK/u1OpJSfoY1OMU6VSBFl8LujQXzsMQH1UqZkjKChcDcN8RNPD7x2FtdkfX7Rt9DizQN7oyHJE+2tA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657293811; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BY/R+8YJ5Dv/43YfnL4nTrVKxj1X4wUM5az+kdRyBN4=; b=J0R7PkoYg1ZD8hfkfyN+yDO93Q79hQm+6DcoCtJXhl0qZoq0vuPirKzC0YeuZdZ1jb0cqB9Yt2SrTjAxjBh3OAnMmTf2d5spcw6b2RoRGmiXIwZunTdMwNqsV3xAW6LRNeEPJQQn6rU7x19LZPwZCowFSfcToa6aORY+sf0vNDo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657293811582689.6626177322174; Fri, 8 Jul 2022 08:23:31 -0700 (PDT) Received: from localhost ([::1]:36672 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9ppK-0007uA-B1 for importer@patchew.org; Fri, 08 Jul 2022 11:23:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36954) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9piQ-0002Sz-Tt for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:23 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:55830) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9piP-0002Du-8V for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:22 -0400 Received: by mail-pj1-x102a.google.com with SMTP id w24so18317607pjg.5 for ; Fri, 08 Jul 2022 08:16:20 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BY/R+8YJ5Dv/43YfnL4nTrVKxj1X4wUM5az+kdRyBN4=; b=H3aB0a6KQ/oxNS6+VxJ2W2ligNKt2LX2wkhV2j44tZ098um3bYJgmsSyJGrOnDhFHU sLEKp65rzwNc7a+s3SM8F9nsbHtgMJbkqhVPLjRQEF0rrjeKxtXpivB9A0Flchr+r7jX YcUaog0zhi3e5JJEJtmEf5aACfmAyZcmCX3DB04ypx6JZVsqkyjBV2nWoHWfhko1t2pe L1Xxwtm/wqqrVF/wqDhn+h1KO4+1subSO9QsAO/tS8Lmn57M+IFa7nI77BokOKg02YTX 7uyBlMf3h/sZ3sdeUzLRNftHBKxIdqmfGEVzo1565qi+ndJJoBB8m0XUo5jnd8pCKYlt OtmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BY/R+8YJ5Dv/43YfnL4nTrVKxj1X4wUM5az+kdRyBN4=; b=0AmlzQ76bV2s+xg9viVhUcJFB9I2h77xVi/QBIHltaa91KfW+hJFUTnz4sm5Ex6z/T H0RZgNgxYh7wv4+nF3P9vbQOnCRpePVIX/iAYGMbGfL0Ms1LAAShJ63y5kv5f4BuZ9jg HnQwMyza+f45NoTfvqMICFNgE1fws28KnAocM9ySNgmSde5WuV0UEo1Gs8fFtOZXqBL0 H2Vrovmw3zyEwueWPX3DSQrEA2RID88keycFV0i9yhAesB0oKClctnEAGbG7AFw/Sg8/ tOxaobfR5CHPPFaNExAEJrix6wHYTcboo8gZk3l+161sOlcPoX0Dcn7/m/RdO2Jsfkt6 Ob/w== X-Gm-Message-State: AJIora/FvWyQPWhM58u96+PIvWA6/SHTsU0T381ob503tSxMVDQ9CNEC WlwgqNY6EumAcS4E9Bk9sHUTWJ1AoY/QldgC X-Google-Smtp-Source: AGRyM1tOkKvfCd1k6lruEaFoJGc7edh56YCgSinXOo3k2E/B6aZk2TXQJxIpdMTkwShMxpOIhCfFRA== X-Received: by 2002:a17:90b:4f81:b0:1ef:acca:2d6b with SMTP id qe1-20020a17090b4f8100b001efacca2d6bmr305078pjb.243.1657293379067; Fri, 08 Jul 2022 08:16:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 11/45] target/arm: Mark gather/scatter load/store as non-streaming Date: Fri, 8 Jul 2022 20:45:06 +0530 Message-Id: <20220708151540.18136-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657293812634100001 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 9 --------- target/arm/translate-sve.c | 6 ++++++ 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index fe462d2ccc..1acc3ae080 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -59,19 +59,10 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJC= VTZS # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) =20 -FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT = load (vector+scalar) FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather pref= etch (vector+imm) FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather pref= etch (scalar+vector) -FAIL 1000 010- -01- ---- 1--- ---- ---- ---- # SVE 32-bit gather load= (vector+imm) -FAIL 1000 0100 0-0- ---- 0--- ---- ---- ---- # SVE 32-bit gather load= byte (scalar+vector) -FAIL 1000 0100 1--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load= half (scalar+vector) -FAIL 1000 0101 0--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load= word (scalar+vector) FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load= (scalar+scalar) FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load= (scalar+imm) FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+scalar) FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+imm) FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load= /prefetch -FAIL 1110 010- -00- ---- 001- ---- ---- ---- # SVE2 64-bit scatter NT= store (vector+scalar) -FAIL 1110 010- -10- ---- 001- ---- ---- ---- # SVE2 32-bit scatter NT= store (vector+scalar) -FAIL 1110 010- ---- ---- 1-0- ---- ---- ---- # SVE scatter store (sca= lar+32-bit vector) -FAIL 1110 010- ---- ---- 101- ---- ---- ---- # SVE scatter store (mis= c) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index f8e0716474..b23c6aa0bf 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5669,6 +5669,7 @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1_z= prz *a) if (!dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming =3D true; if (!sve_access_check(s)) { return true; } @@ -5700,6 +5701,7 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_z= piz *a) if (!dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming =3D true; if (!sve_access_check(s)) { return true; } @@ -5734,6 +5736,7 @@ static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1= _zprz *a) if (!dc_isar_feature(aa64_sve2, s)) { return false; } + s->is_nonstreaming =3D true; if (!sve_access_check(s)) { return true; } @@ -5857,6 +5860,7 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_z= prz *a) if (!dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming =3D true; if (!sve_access_check(s)) { return true; } @@ -5887,6 +5891,7 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_z= piz *a) if (!dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming =3D true; if (!sve_access_check(s)) { return true; } @@ -5921,6 +5926,7 @@ static bool trans_STNT1_zprz(DisasContext *s, arg_ST1= _zprz *a) if (!dc_isar_feature(aa64_sve2, s)) { return false; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EEUaOkhoazNVf18b04XDY+SiXA3h6+AppArsj54fhkI=; b=yiW3pQ1RIvcf7Phuds5BBKVzqbum3+ox4rTtGLkPCzm4LushjfdL1X6EBUjFJIeCxS xBoDglVXFb5BigURyKq22Ngh07WVYQCYS7vjy+HSejB7pIKxiSGgwZuLyWnIMV8r6qqU HJNasp3KVx/ktpwWsWdemOG+7nlMVgdLH+o50rP7kgDi5SZundv0FO7trdZ3oxorz2/o XzMUFPOu6ENl0I6LNKlAdinm2c79POy9gTNoFmt98cl44bBQTgjbwsTzeFvzkV1vseC+ zmbKnDlEwfNNyCc5vGXuygLFEWk0x5hcMv5U/P5m296M9/DJBEhGQC6lCOMBYcmmzTnd RpgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EEUaOkhoazNVf18b04XDY+SiXA3h6+AppArsj54fhkI=; b=XxtpxSkD1H4hEfLjhA15VIqlhqW3zkKjdLIQM9HLp1Z/cKHDRtmmR8B7GVdvb60I61 bdvSIbvS1jH8+UlBWm+lSaMrJNGUar/anS2EbY4twB19B2zMBEP/KzoYi3dicCh6jYmc l5q+XxDNNc/yWTRxeHYCbBt/lOiGShIyPIfMFmSJZm/FM80o4ypCU11Hd81RaF4jIOu2 qz6FOd9UWI2tQf4QgrhbJ7QiVJx4xpE8S+BBSiI6NB5R+TPaqPKC3SVPESFYI75rWfDF oGO6OKL/5W+QMbFTHC9LF4jGUVdaKDMSGA/QhOqTfmUdj5cZE5pbCkmtcDehx/5eY7S2 WtGQ== X-Gm-Message-State: AJIora/QULwlvJLkgz28J1finVYXXeecHBlAWVGFBBI0imbR4acGVlZg +vhuY9gVmLMudR1ND6J5zERUdu/2oRvx0Wxc X-Google-Smtp-Source: AGRyM1v/u2lXofykaivCNQHOIy1Gn05eBl/2+deePc8VngB1EckoJVZZ53XuDq/gNEdX7zqwfNEv6g== X-Received: by 2002:a17:902:b218:b0:168:de55:dfba with SMTP id t24-20020a170902b21800b00168de55dfbamr4272859plr.134.1657293381856; Fri, 08 Jul 2022 08:16:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 12/45] target/arm: Mark gather prefetch as non-streaming Date: Fri, 8 Jul 2022 20:45:07 +0530 Message-Id: <20220708151540.18136-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657293979843100001 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. In this case, introduce PRF_ns (prefetch non-streaming) to handle the checks. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/sve.decode | 10 +++++----- target/arm/translate-sve.c | 11 +++++++++++ 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 1acc3ae080..7d4c33fb5b 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -59,10 +59,7 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCV= TZS # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) =20 -FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather pref= etch (vector+imm) -FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather pref= etch (scalar+vector) FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load= (scalar+scalar) FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load= (scalar+imm) FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+scalar) FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+imm) -FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load= /prefetch diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a54feb2f61..908643d7d9 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1183,10 +1183,10 @@ LD1RO_zpri 1010010 .. 01 0.... 001 ... ..... .= .... \ @rpri_load_msz nreg=3D0 =20 # SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets) -PRF 1000010 00 -1 ----- 0-- --- ----- 0 ---- +PRF_ns 1000010 00 -1 ----- 0-- --- ----- 0 ---- =20 # SVE 32-bit gather prefetch (vector plus immediate) -PRF 1000010 -- 00 ----- 111 --- ----- 0 ---- +PRF_ns 1000010 -- 00 ----- 111 --- ----- 0 ---- =20 # SVE contiguous prefetch (scalar plus immediate) PRF 1000010 11 1- ----- 0-- --- ----- 0 ---- @@ -1223,13 +1223,13 @@ LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... .= .... \ @rpri_g_load esz=3D3 =20 # SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets) -PRF 1100010 00 11 ----- 1-- --- ----- 0 ---- +PRF_ns 1100010 00 11 ----- 1-- --- ----- 0 ---- =20 # SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets) -PRF 1100010 00 -1 ----- 0-- --- ----- 0 ---- +PRF_ns 1100010 00 -1 ----- 0-- --- ----- 0 ---- =20 # SVE 64-bit gather prefetch (vector plus immediate) -PRF 1100010 -- 00 ----- 111 --- ----- 0 ---- +PRF_ns 1100010 -- 00 ----- 111 --- ----- 0 ---- =20 ### SVE Memory Store Group =20 diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index b23c6aa0bf..bbf3bf2119 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5971,6 +5971,17 @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr= *a) return true; } =20 +static bool trans_PRF_ns(DisasContext *s, arg_PRF_ns *a) +{ + if (!dc_isar_feature(aa64_sve, s)) { + return false; + } + /* Prefetch is a nop within QEMU. */ + s->is_nonstreaming =3D true; + (void)sve_access_check(s); + return true; +} + /* * Move Prefix * --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657294164; cv=none; d=zohomail.com; s=zohoarc; b=Sr02g6Sld69HyZnZlO0m1pMpCbGh+BM4eUsoq6ku1yJOcaLQyar84L3PYpVdH+EAUhIpR3uHqPv3bDAvO1Qojaf+Fhe/Oxd0K+Qa0obFNmp6AyEWHxlwmAsPOgoc1NyCD6yRXHgN12XQDlNPT6YaJmEbX2jx3mwMtTdGPffkXc8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657294164; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3fycTpR631CAyDn0p7xxlDZ9oFm740riIb23T+ghRkc=; b=KlqFeacpPikz8VlCkQC8zAM6eV6tmOBIgQcStlKRUSVfF8K7WzNlgrcN/WiPETLfN+ ndWnSoUvH9msmc8ffLen0nZECoMK4JNcitWt3Wab88mFabLKgY6Vv3VyNXRG3pOh+Sdp zhfqGhpGoXthYzt24zTqjbEAUhR3hRG62mtY8qh1NhsaPmKJCQux8DSIY921e1S401wv xAlmq5neMSmnnWw80itX2n20uCm76bSENpEqrC8CjYdoEkKcl5cXKdvenxAbo5Xb67JT Y6HfQEBfMAjJfl0wsputEBachvP8rzbXE5lR8zgB5aiBoOxLHWFytatItiNTzj6tfHlg /ZlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3fycTpR631CAyDn0p7xxlDZ9oFm740riIb23T+ghRkc=; b=EmPCSh2WYOB1+OfVV1GUu9Lq4Ib87z3sdAWShLKAr8HOQoNOKp4aVjLDyo1SYWKjtO tkfqBrNMPckORWXBjik0A2ak2IL3NYNFghPil6aAHzIJQjGWU6N6UpgDeW9+/kyKxHD8 GeByrWhZR4O5RwgXPr9lr8S07EOnqTRTH2kG9tzIIHw5PL135Dk+Y9WW6qxNNuicglwX sv9R2oYbyKGuwUDpC/eTbU5fXfTKYT4DvDBJcHynPTlZiJPs3ebbm8cS9Vv+N0OCSDKj Fj66P17Z4oTUbi1JRpUapyjR/IempV3gq2Gh7bULkkAPfBhS5Ssy/EVcSwwrdaTkawh6 VxlQ== X-Gm-Message-State: AJIora9IQS2aV/3HHnVnRBedQs0lDJ1ccVGVq/qMmZryQV/K5v5gAL2V tOqcqMjJqvqI7JMzKSU3jhsQ8F04uBkmRU4f X-Google-Smtp-Source: AGRyM1sLULJidU4fzwcq7p9Vq99XqYQHAi4zdbebRNEB6XLLWpP/kThHoxhqCW9nshhjlWt39BY9+Q== X-Received: by 2002:a17:90a:f415:b0:1ef:8811:e0c7 with SMTP id ch21-20020a17090af41500b001ef8811e0c7mr373534pjb.130.1657293385095; Fri, 08 Jul 2022 08:16:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 13/45] target/arm: Mark LDFF1 and LDNF1 as non-streaming Date: Fri, 8 Jul 2022 20:45:08 +0530 Message-Id: <20220708151540.18136-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657294165151100001 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 2 -- target/arm/translate-sve.c | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 7d4c33fb5b..2b5432bf85 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -59,7 +59,5 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVT= ZS # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) =20 -FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load= (scalar+scalar) -FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load= (scalar+imm) FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+scalar) FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+imm) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index bbf3bf2119..5182ee4c06 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4805,6 +4805,7 @@ static bool trans_LDFF1_zprr(DisasContext *s, arg_rpr= r_load *a) if (!dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming =3D true; if (sve_access_check(s)) { TCGv_i64 addr =3D new_tmp_a64(s); tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); @@ -4906,6 +4907,7 @@ static bool trans_LDNF1_zpri(DisasContext *s, arg_rpr= i_load *a) if (!dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming =3D true; if (sve_access_check(s)) { int vsz =3D vec_full_reg_size(s); int elements =3D vsz >> dtype_esz[a->dtype]; --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657294139; cv=none; d=zohomail.com; s=zohoarc; b=CBktLeWor8o9Ud1wbubvBxmCQphC1AVkfoCsYUZ64s7EyU432DjT+so4W7NICpZynAw+Z6y/i3qJ4cw//30CxojzwlNyJmYq3ixog9aRY2lm0HIbAsTfkzb4vYefcGddwwgmbzvkXgOd3SDxWpJKlY/Vjy3YGHBb7T1CREO9ICs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657294139; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Eedjnu3eOCixQFi7+Gzy6ksLbMXPKA3RAkF+Pv5QpfE=; b=lgjVn8a7naxeAaKo+GLFN9a+UaUsApQe3e0UKUKdsPhEoM4NeeHI6NC6NYlpS+ihpw4GjyVzuwwleuxN/t3jlZJVD8wyAwJZH9REJPY6aE2+K179k4QcbMzbz7VOSRS/ZsJncYT4WP162WGh38eL5sg7Nt6d3bgkDtWvX9VI4DU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657294139328174.96535165700323; Fri, 8 Jul 2022 08:28:59 -0700 (PDT) Received: from localhost ([::1]:54288 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9pub-0003A4-JU for importer@patchew.org; Fri, 08 Jul 2022 11:28:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37092) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pia-0002a3-2T for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:33 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:36817) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9piX-0002IT-BQ for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:31 -0400 Received: by mail-pf1-x436.google.com with SMTP id g126so9355557pfb.3 for ; Fri, 08 Jul 2022 08:16:28 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Eedjnu3eOCixQFi7+Gzy6ksLbMXPKA3RAkF+Pv5QpfE=; b=RLRqYk0b4m+zHsufuHYy7XOLtTeQ7v56+VvEl5yg+lSfw6qbJ4ilGk7ZYhdn32RK5M pr0wasqrkSGUrSYVhAhZxQMc7QE2B6xQFOSSDr/aapx5k/21I265MGfmvty9TLYMmGmJ 2czn5Rj2eJlWml1W4DVmrh8dCYnyGWgPBBTWYOjKbDOqodo2HUwpSiYy4/pIqjevV6W1 /R9tAWpvvDN0yTLjfGDmJ8aHW2ynInnTso9T/tLEt+PqA/A84CU8BbWZfo0odlCylN36 T0AXt6IHEilZ1yYS+hndgmBcRWvT9iyA0GqOx3RzTnzqlNU2gMaeDrCSVhuzlpcINCWw Tx+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Eedjnu3eOCixQFi7+Gzy6ksLbMXPKA3RAkF+Pv5QpfE=; b=SNozmfF/FnvicNSGxda3bZ3jpgLlFFZHOwB34RV+BOq7ed5eTe+4Pgk54uiTB4StaR oMUwAKtXwOfZgQJIaP8tg8wHUnydYa3YXJC1AmdBW54sa8PQeH0ajsJeTyVwggBQ0BBg fAGkJ9Vbe3yXQIM62ZHu0YomQZ0uJ1UBsdwpG/Rk5dgzFJ4qGn8eeiQhA0veFXoQv4M4 HprJLorDhGF1wYJl7BoMc6nv5cYYpCVUan8/khfLFPLS7XxpSze3DJV3zelVv+P9Uu0G V4+DfLhNmjh70XpiDgj4ndZslG4JDdAUmEWH5dAfzCiUs0U2JqdBUJ5WYj082ERedag/ 7lGw== X-Gm-Message-State: AJIora/GiiG5s69tXV2/Kly6hs3R/szKuO8lzlR9+O4hlPjQd/Ox1/zg KN46S/1i9T2gRVDXTnCvugjw+EQ7O8V4WqM3 X-Google-Smtp-Source: AGRyM1tCdFyfjZNs3sbLOhkVQ7+vrJ8XADT2MURr0Akb/GcYly/bQukI2NkPQM+L0AFdnAK5gDZXRg== X-Received: by 2002:a05:6a00:124a:b0:525:894b:7924 with SMTP id u10-20020a056a00124a00b00525894b7924mr4324990pfi.31.1657293387932; Fri, 08 Jul 2022 08:16:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 14/45] target/arm: Mark LD1RO as non-streaming Date: Fri, 8 Jul 2022 20:45:09 +0530 Message-Id: <20220708151540.18136-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657294140811100001 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 2b5432bf85..47708ccc8d 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -58,6 +58,3 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVT= ZS # --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register= (unscaled imm) # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) - -FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+scalar) -FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+imm) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 5182ee4c06..96e934c1ea 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5062,6 +5062,7 @@ static bool trans_LD1RO_zprr(DisasContext *s, arg_rpr= r_load *a) if (a->rm =3D=3D 31) { return false; } + s->is_nonstreaming =3D true; if (sve_access_check(s)) { TCGv_i64 addr =3D new_tmp_a64(s); tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); @@ -5076,6 +5077,7 @@ static bool trans_LD1RO_zpri(DisasContext *s, arg_rpr= i_load *a) if (!dc_isar_feature(aa64_sve_f64mm, s)) { return false; } + s->is_nonstreaming =3D true; if (sve_access_check(s)) { TCGv_i64 addr =3D new_tmp_a64(s); tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 32); --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657294415; cv=none; d=zohomail.com; s=zohoarc; b=BPGIjPTxJQqGUBCCbB6Be5zfDckp6NnlTeEdxtiwqMRwjrgiEL9evoxukL8aiIw1wsaxmMrpv8IApMA2HlkPVB9SNlUC1NAyX2XwGojmo5k4sqh1O10aHUypK6kgji1GcPfoXDRm7qEdsnUDKojn7E2hDI3qSmaRJO9YbB3ZXoU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657294415; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PhJtFSrquOFUVO5QY9Q5zh4pNEWnYjCw2RgtobhuW2s=; b=JnV3LufqA4NQe+FZgj7ZSNBdHvGDs9134J588p+aJ4oUIRkFGzgWwcMOSxpWZOMyumcLV+cHM6fO3K/tjJHDEP3ZEK57szzqp86lsDbws/QEn9YkFROiOzTBBWGY7kC0ak1cXlZaAzfqRdW3zpsBipe1lRop2POElv/NkgJTJns= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657294415989583.3140049429942; Fri, 8 Jul 2022 08:33:35 -0700 (PDT) Received: from localhost ([::1]:37948 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9pz4-0002rj-QW for importer@patchew.org; Fri, 08 Jul 2022 11:33:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37146) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pid-0002b8-1o for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:36 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:38884) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pia-0002J7-Qd for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:34 -0400 Received: by mail-pf1-x435.google.com with SMTP id o12so10217842pfp.5 for ; Fri, 08 Jul 2022 08:16:32 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PhJtFSrquOFUVO5QY9Q5zh4pNEWnYjCw2RgtobhuW2s=; b=lWMF37XJ1jJ0MLY6VWKtYw/pp9ZqCPFDYoUDGnTqI6tvWpYlox6HKjlbtbjvpK0d+C rWWjUSmZrEEICbn/tVKAxOBnfU+ws2kR1YK2qf+hPqFCaB0+I6Fg+Pu5enn4HDoY2Vfn 9YFcS2FTz5lTyTYZDb+QsB1YqGfIDiHpDSN74bJoeKqk1pb1bnCgJxlNBtRvrz/WQ50e Rjco1rdq8GO8YZ9pZWBLny5j77IV0OjXG9ua/lQloW1YOtZzqM45PCQrGOSWnsv4e53R IRMNASxmT6a5TR1hNBLZZSu3lAea+0K5UkOTisqiUpABrKAfCHITMprcJMy4ZA1399HQ r77A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PhJtFSrquOFUVO5QY9Q5zh4pNEWnYjCw2RgtobhuW2s=; b=lQWbh8NJ7VxwUCHkDejljFizWrHCZ4vVfxRVH7KILiRnnzHIQXfCWLhyI+Lk3iQSFf Q4NYoQpVBqDKkTrJDNGtqaMpcNW7NPzgSzx2rX1zB0/xS8OyFlCSkGOh/upuCq9XYYH4 ss9FYbCRpzaSK74KrBqYKXqDYdGJshrZNdd74o54eIP1WdShQQaeNNlBisImi5/z7zek +SJQgzeb0SHCuDwMBXJuf1qHtF6+7XCLT5LNcTpPZluYhgpmqNqda/Y8Eqbl5qOIwU6n Ird2p1VeYNnroDSDNtgVGJQvXAIuR+tT2UlSdB/I08GVtvWJWUatg7Zwjkejm9IeHJoX tjow== X-Gm-Message-State: AJIora/6oQgzxkz/d3neDr7IpgvAwhNaYy4u4bNpdzQyaCh98FVSrS9s f9N+NYdVY84QUZFJit0zAXDixVoOl54kFrHp X-Google-Smtp-Source: AGRyM1vpNq5G6cl1W2tlRC6yiRM2vuQC5TOlD/nmNttKUGJkTUGoAV9nOzgcpNemD+vxekWjiO7OUw== X-Received: by 2002:a63:6703:0:b0:413:1f40:6cb5 with SMTP id b3-20020a636703000000b004131f406cb5mr3771235pgc.614.1657293391467; Fri, 08 Jul 2022 08:16:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 15/45] target/arm: Add SME enablement checks Date: Fri, 8 Jul 2022 20:45:10 +0530 Message-Id: <20220708151540.18136-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657294417822100001 Content-Type: text/plain; charset="utf-8" These functions will be used to verify that the cpu is in the correct state for a given instruction. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 21 +++++++++++++++++++++ target/arm/translate-a64.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 789b6e8e78..02fb95e019 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -29,6 +29,27 @@ void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v); bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, unsigned int imms, unsigned int immr); bool sve_access_check(DisasContext *s); +bool sme_enabled_check(DisasContext *s); +bool sme_enabled_check_with_svcr(DisasContext *s, unsigned); + +/* This function corresponds to CheckStreamingSVEEnabled. */ +static inline bool sme_sm_enabled_check(DisasContext *s) +{ + return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK); +} + +/* This function corresponds to CheckSMEAndZAEnabled. */ +static inline bool sme_za_enabled_check(DisasContext *s) +{ + return sme_enabled_check_with_svcr(s, R_SVCR_ZA_MASK); +} + +/* Note that this function corresponds to CheckStreamingSVEAndZAEnabled. */ +static inline bool sme_smza_enabled_check(DisasContext *s) +{ + return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK | R_SVCR_ZA_MASK); +} + TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, int log2_size); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7fab7f64f8..b16d81bf19 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1216,6 +1216,40 @@ static bool sme_access_check(DisasContext *s) return true; } =20 +/* This function corresponds to CheckSMEEnabled. */ +bool sme_enabled_check(DisasContext *s) +{ + /* + * Note that unlike sve_excp_el, we have not constrained sme_excp_el + * to be zero when fp_excp_el has priority. This is because we need + * sme_excp_el by itself for cpregs access checks. + */ + if (!s->fp_excp_el || s->sme_excp_el < s->fp_excp_el) { + s->fp_access_checked =3D true; + return sme_access_check(s); + } + return fp_access_check_only(s); +} + +/* Common subroutine for CheckSMEAnd*Enabled. */ +bool sme_enabled_check_with_svcr(DisasContext *s, unsigned req) +{ + if (!sme_enabled_check(s)) { + return false; + } + if (FIELD_EX64(req, SVCR, SM) && !s->pstate_sm) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_NotStreaming, false)); + return false; + } + if (FIELD_EX64(req, SVCR, ZA) && !s->pstate_za) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_InactiveZA, false)); + return false; + } + return true; +} + /* * This utility function is for doing register extension with an * optional shift. You will likely want to pass a temporary for the --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657294307; cv=none; d=zohomail.com; s=zohoarc; b=SzB4MRVNpl8ISr4zlP5TZbfem3Ws+9sQdxHFeKDd/EcHOLG4tvArfsLclGJVmqbg3KMjKddaX29H9TRnH3iKjI0j9FWzJHF4rgzLzQZMu1LR7wFwc6rsL1ZXSTbJcAIbbMBSe2yJBl1u7U0c3xEeYeFu9ng7lPmbV1ds5ruLG/g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657294307; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0yTWCJ1DktZzYQTXntYaiEXNGmdccKtN6uvynpzt0IU=; b=ha2dtUguN6YVdnH6JDyEk/Slc7p51IKa1AKmFjH9NnJubLW8IDYTd+NsXqGKKYMiCZh9Qk5bC4E7QAT3VlnZ7tMmGqLw+P35TWY6azU2tFXXDziPJxCNwk0W77/6c8PNgHrFhK+LvqrHw9wiBwP83Hph9obgk+zPf6O00oTVBW8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657294307569454.65364850196727; Fri, 8 Jul 2022 08:31:47 -0700 (PDT) Received: from localhost ([::1]:34608 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9pxK-0000WT-Az for importer@patchew.org; Fri, 08 Jul 2022 11:31:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37188) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pif-0002dv-C3 for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:37 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:55830) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pid-0002Du-RG for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:37 -0400 Received: by mail-pj1-x102a.google.com with SMTP id w24so18318330pjg.5 for ; Fri, 08 Jul 2022 08:16:35 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0yTWCJ1DktZzYQTXntYaiEXNGmdccKtN6uvynpzt0IU=; b=ykcqy5iL8i8pOvOURorfK4XajYxKOyu/nILzzejoGJJTomorraf8K0UoY66N4a03Ho EraPgnG9p4j39gAKdGJIb6cx3pOQoXGsYSyqE0Bxo6uuTYepuUYOJclouaOBUDio4Nby 4mto7YjrmTJelbSupIdr/D8rvrJ3XqIZbGhlVhzkDD3hHfuZDtceJEQfaVPzXxUZCpBT IHpotTu/1b75bzRuYAWDegrm5Fifay3T/+DC1OFCU6ZgW9Bw0RvUSX/Vhulp8DoDXNuu D/OaTvGfgTTGHvhbEeh3eFWkTOwRB060RnFAPoISBBNHCeyfRKxwjvpE+9F4wUpGl73r 2ZHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0yTWCJ1DktZzYQTXntYaiEXNGmdccKtN6uvynpzt0IU=; b=MWujfKMPoLk2yBL95Dc62ertaoHXwoRxdKu5Q6+L9ahcpF16bCiQ5qIWF11znf/qOU 7ywRq3ueM4YAVjlPEsP+jdkFDReEs2mOEcaM922VyJsKGGGjL1ZsQF8nKr++2P0/ovG5 atv7UncpM/gdzMhBdoqLC8gd7HLAq1/arsC8RXUPjOC3rp+2+yj2lPFuuyQvp86P2Q+t vokq/LZKMxNUMi8xU+Z1zN2+pRKc0pZjmtSeQKfZBtCY8s2C8iIaXKcsX5sjrV7TgeqP +LsioNFoBrWdWxIlrIHwmwxNC4AuiotqO7fxc+hdJShxToQdHzl/OnmPHEgIVC+QSyEF ivHg== X-Gm-Message-State: AJIora8vUFEQyAEYj+hLls3PTF9gjGWtAwFThviVgoFDuDLapZzaKbJx pZyAhlm4Tzyj+czgdyAbmLU/O4vCf5zrJINp X-Google-Smtp-Source: AGRyM1stKrh+FGTLaKzYH6FfAOVqrN3sSYiX0B4eeK5G2yzfxvd74TDXgS7WlfIyEuFByM81bQIiog== X-Received: by 2002:a17:90b:2c4a:b0:1ef:8f70:e125 with SMTP id rw10-20020a17090b2c4a00b001ef8f70e125mr401199pjb.50.1657293395076; Fri, 08 Jul 2022 08:16:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 16/45] target/arm: Handle SME in sve_access_check Date: Fri, 8 Jul 2022 20:45:11 +0530 Message-Id: <20220708151540.18136-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657294309181100001 Content-Type: text/plain; charset="utf-8" The pseudocode for CheckSVEEnabled gains a check for Streaming SVE mode, and for SME present but SVE absent. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b16d81bf19..b7b64f7358 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1183,21 +1183,31 @@ static bool fp_access_check(DisasContext *s) return true; } =20 -/* Check that SVE access is enabled. If it is, return true. +/* + * Check that SVE access is enabled. If it is, return true. * If not, emit code to generate an appropriate exception and return false. + * This function corresponds to CheckSVEEnabled(). */ bool sve_access_check(DisasContext *s) { - if (s->sve_excp_el) { - assert(!s->sve_access_checked); - s->sve_access_checked =3D true; - + if (s->pstate_sm || !dc_isar_feature(aa64_sve, s)) { + assert(dc_isar_feature(aa64_sme, s)); + if (!sme_sm_enabled_check(s)) { + goto fail_exit; + } + } else if (s->sve_excp_el) { gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn_sve_access_trap(), s->sve_excp_el); - return false; + goto fail_exit; } s->sve_access_checked =3D true; return fp_access_check(s); + + fail_exit: + /* Assert that we only raise one exception per instruction. */ + assert(!s->sve_access_checked); + s->sve_access_checked =3D true; + return false; } =20 /* --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657294564; cv=none; d=zohomail.com; s=zohoarc; b=U/ERwv2n03ye7S9jF24jxrXK9+dwaHFDWL5Jl8bQZ1Gk7z0VmurC0bInk6LJ70rSkfjpZi+w1k7pkDSOlqCjYRXS99k/5wDy5fQWNQ/N6UlbJJgr4ZF1KFNsMupZrTTm3o6d2OXcp0ED7jYEQL2L8Sb8aPRyJaDUDxSfgfesv9s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657294564; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KwsMd3cs1kMRtBrVlO0pZElFPRsZqBMQRBB6JbUzQes=; b=NdE4ZUPM5FbuhuoxJcdfEoV2ksR6M/cWHkoiZFg02CnRkLkvflZDs6ARUwF30xwoEjWqoo/HwG7LDNvCIYYkPYcrbUX/HxhmpGimUTh9n6HbDPVqw+7ue0e/lN0H286LeHNo7FSbFaAcQGnGF+CT/b24VHEg5Rnq2l5iUT28mqc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16572945648261014.9430443731849; Fri, 8 Jul 2022 08:36:04 -0700 (PDT) Received: from localhost ([::1]:42852 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9q1T-0006E1-00 for importer@patchew.org; Fri, 08 Jul 2022 11:36:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37218) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pij-0002h4-1c for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:41 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:43639) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pih-0002K8-9i for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:40 -0400 Received: by mail-pj1-x1034.google.com with SMTP id o5-20020a17090a3d4500b001ef76490983so2077186pjf.2 for ; Fri, 08 Jul 2022 08:16:38 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KwsMd3cs1kMRtBrVlO0pZElFPRsZqBMQRBB6JbUzQes=; b=cRKGy8VKMm6AEnV91tsqYTPXNOzh/LNtyRIm40ACejW5oOd4AWkbwXXKw6U8U0zzPP luWp1GU3qtKFfjBYXQz7T5UCTuRN86F7Cnbe8YjZk2GtEc0zKxCz/VjMoqzRyqb9S5nR yZTGeGDOrLXF6gVIgVYWMPHRbU8LZVahuIJxrd2rTqekCnKtKO7AJ0TEK1U2DUmWquwV 7MULD1XdXZq9x06zEiBcPb3RRlBCwjCgvsJSRGMhmP/3gpZ0ClP4ZmOaaTAcmoLkUoYf h0ZtGUysSA9cR922Uq0asXeMp9DN++d78ocyYccroLFYASIqKoyqIfB+XiNCK410dq8T A+9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KwsMd3cs1kMRtBrVlO0pZElFPRsZqBMQRBB6JbUzQes=; b=ipU/0XDm1mavJ3ML1PouH+Y7mOgB5zVdmXjLpJeQREEFKIiSH06k7ydSzkt8j2PNXk 3wenY7fAcCM3moFcQDZR3QMDz8aGwsqJ9qW/eiE58rQehL7tS7jWJ2djVKPnSMY6vgtN i0EjxEaoC3O776G5zviCzbBW7k3hftEf9tlMoEJ758w1xYDufjPESmiB6j5fndpVJ5Sw Evix1uuf7PjUnNHHTxgQO0R2Xs9tRUCzq7gdyDObk2nA3cbS8EizGlU0AtBYX6bVRlhx g++/6S9961a5LjFIzC9iC6ndHqHvWGi7xzCJlNVwUOK2fyp71uwLlwApacfTFAF/RlZT PVvA== X-Gm-Message-State: AJIora+HwdqkZPaCz4qCv/zzAmm5uTTlQ/OjP36mikR+PokWIcYHEK7R dBxAWVRhqDasF8Om565f1kLdh4FkcrtQARxR X-Google-Smtp-Source: AGRyM1tfk2AY+8wskYh8SWkwOwiEaSQi0zJI2OhqHRmlfkDcj5RSdMkT0cOVZmJAzgl1w1fl7kS13g== X-Received: by 2002:a17:902:d708:b0:16b:d655:e15a with SMTP id w8-20020a170902d70800b0016bd655e15amr4157317ply.34.1657293398047; Fri, 08 Jul 2022 08:16:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 17/45] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL Date: Fri, 8 Jul 2022 20:45:12 +0530 Message-Id: <20220708151540.18136-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657294566789100001 Content-Type: text/plain; charset="utf-8" These SME instructions are nominally within the SVE decode space, so we add them to sve.decode and translate-sve.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v4: Add streaming_{vec,pred}_reg_size. --- target/arm/translate-a64.h | 12 ++++++++++++ target/arm/sve.decode | 5 ++++- target/arm/translate-sve.c | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 54 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 02fb95e019..099d3d11d6 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -128,6 +128,12 @@ static inline int vec_full_reg_size(DisasContext *s) return s->vl; } =20 +/* Return the byte size of the vector register, SVL / 8. */ +static inline int streaming_vec_reg_size(DisasContext *s) +{ + return s->svl; +} + /* * Return the offset info CPUARMState of the predicate vector register Pn. * Note for this purpose, FFR is P16. @@ -143,6 +149,12 @@ static inline int pred_full_reg_size(DisasContext *s) return s->vl >> 3; } =20 +/* Return the byte size of the predicate register, SVL / 64. */ +static inline int streaming_pred_reg_size(DisasContext *s) +{ + return s->svl >> 3; +} + /* * Round up the size of a register to a size allowed by * the tcg vector infrastructure. Any operation which uses this diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 908643d7d9..95af08c139 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -449,14 +449,17 @@ INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 r= d:5 # SVE index generation (register start, register increment) INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm =20 -### SVE Stack Allocation Group +### SVE / Streaming SVE Stack Allocation Group =20 # SVE stack frame adjustment ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 +ADDSVL 00000100 001 ..... 01011 ...... ..... @rd_rn_i6 ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 +ADDSPL 00000100 011 ..... 01011 ...... ..... @rd_rn_i6 =20 # SVE stack frame size RDVL 00000100 101 11111 01010 imm:s6 rd:5 +RDSVL 00000100 101 11111 01011 imm:s6 rd:5 =20 ### SVE Bitwise Shift - Unpredicated Group =20 diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 96e934c1ea..95016e49e9 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1286,6 +1286,19 @@ static bool trans_ADDVL(DisasContext *s, arg_ADDVL *= a) return true; } =20 +static bool trans_ADDSVL(DisasContext *s, arg_ADDSVL *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_enabled_check(s)) { + TCGv_i64 rd =3D cpu_reg_sp(s, a->rd); + TCGv_i64 rn =3D cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(rd, rn, a->imm * streaming_vec_reg_size(s)); + } + return true; +} + static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) { if (!dc_isar_feature(aa64_sve, s)) { @@ -1299,6 +1312,19 @@ static bool trans_ADDPL(DisasContext *s, arg_ADDPL *= a) return true; } =20 +static bool trans_ADDSPL(DisasContext *s, arg_ADDSPL *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_enabled_check(s)) { + TCGv_i64 rd =3D cpu_reg_sp(s, a->rd); + TCGv_i64 rn =3D cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(rd, rn, a->imm * streaming_pred_reg_size(s)); + } + return true; +} + static bool trans_RDVL(DisasContext *s, arg_RDVL *a) { if (!dc_isar_feature(aa64_sve, s)) { @@ -1311,6 +1337,18 @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a) return true; } =20 +static bool trans_RDSVL(DisasContext *s, arg_RDSVL *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_enabled_check(s)) { + TCGv_i64 reg =3D cpu_reg(s, a->rd); + tcg_gen_movi_i64(reg, a->imm * streaming_vec_reg_size(s)); + } + return true; +} + /* *** SVE Compute Vector Address Group */ --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657294761; cv=none; d=zohomail.com; s=zohoarc; b=TlmhjZtoarEMX4ldnL86x2YQbvi44t7Cngj9lmhNQJIX1Myu0rwCUChiSEf9A2ppi+lBBhv6vx78Fljeiy6WAxTT7ZQTub+xuxh+4ovI/VCQoabzYsjB7uuziWForbIjeHHYlsyK/GAw6cXvv7CKJU2WRxNAMrHciyvW+1G0fjo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657294761; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8q6UgHZNxgLAwjYyD3emx4pnHnGEMm3xg5CqdRKZ5yA=; b=PgSWJ5KkBrSAA1mff0oEZ1DaejEpoWlQUV3Q40mI7/zQV4pyxJyuESn/OHK4bWc4pjlHOOMVYcFqLKe8iuVn5+5qkXVc+tCE+EHSXGJYRtQBtCi5gd2HMly6g0DuiZz4tBqwsFsKTRBlcntwHb1Z03w/wyYLtK2s9uFx3Bk6kS4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657294761571924.6451167914371; Fri, 8 Jul 2022 08:39:21 -0700 (PDT) Received: from localhost ([::1]:51242 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9q4d-0003yJ-Go for importer@patchew.org; Fri, 08 Jul 2022 11:39:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37272) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pin-0002ok-1b for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:45 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:34620) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pil-0002Kd-7U for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:16:44 -0400 Received: by mail-pl1-x630.google.com with SMTP id z1so10808198plb.1 for ; Fri, 08 Jul 2022 08:16:41 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8q6UgHZNxgLAwjYyD3emx4pnHnGEMm3xg5CqdRKZ5yA=; b=Rlh1uGi31mr+nppIEi5f5Iw+0CqYnLlsV5W4Y9htIKl857meuFaODi5r42vJqjvFMa 64UddTFV0Pck0r52ey0INwG+wvNrmZzcFJ25fA6gRSh/66FJwigzMwuAlmmQ4z2klcjX Jz8UbWO38MuTX0HYp18aLscwUdPNanyfiBqgSOcvHvx+rSobpm9f2Qrs8jYYR/AIdByh YdeK1EdS/axxGRrnQXVktLudanqfxfQ5vYf1yIkieF6XfBoN44+x2ZBb5e6v7W+6Kuk/ X0RsYx7y3K8TDTg1yJBgwRt+3142+Xe/3FI1HPNn1yno4qD49Z/2USXyvjZL9LbQrO9i TnCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657294763747100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v4: Fix ZA[] comment in helper_sme_zero. --- target/arm/helper-sme.h | 2 ++ target/arm/sme.decode | 4 ++++ target/arm/sme_helper.c | 25 +++++++++++++++++++++++++ target/arm/translate-sme.c | 13 +++++++++++++ 4 files changed, 44 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 3bd48c235f..c4ee1f09e4 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -19,3 +19,5 @@ =20 DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32) + +DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index c25c031a71..6e4483fdce 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -18,3 +18,7 @@ # # This file is processed by scripts/decodetree.py # + +### SME Misc + +ZERO 11000000 00 001 00000000000 imm:8 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index b215725594..eef2df73e1 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -59,3 +59,28 @@ void helper_set_pstate_za(CPUARMState *env, uint32_t i) memset(env->zarray, 0, sizeof(env->zarray)); } } + +void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl) +{ + uint32_t i; + + /* + * Special case clearing the entire ZA space. + * This falls into the CONSTRAINED UNPREDICTABLE zeroing of any + * parts of the ZA storage outside of SVL. + */ + if (imm =3D=3D 0xff) { + memset(env->zarray, 0, sizeof(env->zarray)); + return; + } + + /* + * Recall that ZAnH.D[m] is spread across ZA[n+8*m], + * so each row is discontiguous within ZA[]. + */ + for (i =3D 0; i < svl; i++) { + if (imm & (1 << (i % 8))) { + memset(&env->zarray[i], 0, svl); + } + } +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 786c93fb2d..971504559b 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -33,3 +33,16 @@ */ =20 #include "decode-sme.c.inc" + + +static bool trans_ZERO(DisasContext *s, arg_ZERO *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_za_enabled_check(s)) { + gen_helper_sme_zero(cpu_env, tcg_constant_i32(a->imm), + tcg_constant_i32(streaming_vec_reg_size(s))); + } + return true; +} --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657294703; cv=none; d=zohomail.com; s=zohoarc; b=UPYXXT7htdSURrTbsurusR9y4I9XsayeBQVJw0UUcA8re6tdRZHuTUMkZQbOpnt4X7/FRjTf9ZE6lUwatNvnlz4JS90ywfYkp0O6Nb/hyooBAhi622ImYPSsYBZlCGUXhnpQnXnt59VVSDcOVYIjqnp8YXU7sG9TYc2TLjbDRJs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657294703; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FIJZTJDsU3bwgxqkNI4PQQPdcbVgY9UEzpNtvLgVDjw=; b=MgKts0c+nWiblZHInWcvEbMvO9e+3ySMCJGxKDUI51+CknDGfhFG06K0q5o9hE0awc28ctMpVYs/u22GMncIVokn6klqyG0fq8KHQ+fuVLxBYdUV07EqcpzhzY5NCVAKfkSScjVxShGW45ayDDpTOqTH/p05t80URAAUmBjxIIk= ARC-Authentication-Results: i=1; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FIJZTJDsU3bwgxqkNI4PQQPdcbVgY9UEzpNtvLgVDjw=; b=QhM4tWZf/oA0nuWtfa++/biM8vIVag09ndJrhygQYNwfDf3VuXYXantnOf+XS79/nU ql+EB17xFQjNCKf2qzhfbA0MIA8vqOqUluW7ztTQC9+eTBFDHosGftQ+aFSVA7Aa9w2z ZKTG3lyTdLAekmlW+cZnC6sCA/qF0ksTyS/ThGQew14pZUU05dW3jtFDEqDiy8PWrymK +KIIGfZbpm0ZRJAO7NZgdHZks0doA86GY0e8gSJUYFIhW3jttaAzt5xSdYPRBj9ntBuH akEKa/yPnzcdG95AI6VL3oJLmMSzQg/DayntwtBsEvP/fjvkZYmBiBJTK6DaC+OY9rC8 46/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FIJZTJDsU3bwgxqkNI4PQQPdcbVgY9UEzpNtvLgVDjw=; b=veivWArH2Oee/QD0Zu/l1ORVYrvkkmnAoKdZPH/XkWuxT/R2bLezNJaehUKP/QIdmM 29HL72uuHFNgae6xlT7308SBbGdjMRF6Q2FYG/VYqytMpISNbSNrLnZjYcJPtNMvwlz/ WdcRxKoqv8fcR9FzWaS3dsmNvYNjUUPL8RgFWzMx9UOiHOqxT4tmem7ABi4hb2E4jOqU fMvuXt2medI6fSe9n4ImAq4TbSqGdEtAlb2VLTv0xRTl7EOrAhL0y1WM0s9THzyjsf5u Ywrh/HSJ8FY7MnOABxK7GiGV4CKMqTYrP/XMnWAkvauppbaNb9/hO23qb4NWKMpm5MwG eqVA== X-Gm-Message-State: AJIora9UHilWUIbxnffLu2NB2KbynuOmJFGY6fu8lyntU+zzS9OFh0Je IpqOAbpv6KzIZ1hzzouXxCTac1LBkriUn926 X-Google-Smtp-Source: AGRyM1s4rgcwRSPpItFxnuDBWHytQeV4DRsp5pgfExVfsprJ/qRcj83cJU5mJMF+XVP9gw0eip9TVg== X-Received: by 2002:a17:90a:e7c6:b0:1ee:fed1:60a4 with SMTP id kb6-20020a17090ae7c600b001eefed160a4mr376174pjb.100.1657293404536; Fri, 08 Jul 2022 08:16:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 19/45] target/arm: Implement SME MOVA Date: Fri, 8 Jul 2022 20:45:14 +0530 Message-Id: <20220708151540.18136-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657294703601100001 Content-Type: text/plain; charset="utf-8" We can reuse the SVE functions for implementing moves to/from horizontal tile slices, but we need new ones for moves to/from vertical tile slices. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 12 +++ target/arm/helper-sve.h | 2 + target/arm/translate-a64.h | 8 ++ target/arm/translate.h | 5 ++ target/arm/sme.decode | 15 ++++ target/arm/sme_helper.c | 151 ++++++++++++++++++++++++++++++++++++- target/arm/sve_helper.c | 12 +++ target/arm/translate-sme.c | 127 +++++++++++++++++++++++++++++++ 8 files changed, 331 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index c4ee1f09e4..154bc73d2e 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -21,3 +21,15 @@ DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void,= env, i32) DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32) =20 DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32) + +/* Move to/from vertical array slices, i.e. columns, so 'c'. */ +DEF_HELPER_FLAGS_4(sme_mova_cz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sme_mova_zc_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sme_mova_cz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sme_mova_zc_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sme_mova_cz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sme_mova_zc_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sme_mova_cz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sme_mova_zc_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sme_mova_cz_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sme_mova_zc_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index dc629f851a..ab0333400f 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -325,6 +325,8 @@ DEF_HELPER_FLAGS_5(sve_sel_zpzz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve_sel_zpzz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_sel_zpzz_q, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_5(sve2_addp_zpzz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 099d3d11d6..2a7fe6e9e7 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -178,6 +178,14 @@ static inline int pred_gvec_reg_size(DisasContext *s) return size_for_gvec(pred_full_reg_size(s)); } =20 +/* Return a newly allocated pointer to the predicate register. */ +static inline TCGv_ptr pred_full_reg_ptr(DisasContext *s, int regno) +{ + TCGv_ptr ret =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ret, cpu_env, pred_full_reg_offset(s, regno)); + return ret; +} + bool disas_sve(DisasContext *, uint32_t); bool disas_sme(DisasContext *, uint32_t); =20 diff --git a/target/arm/translate.h b/target/arm/translate.h index e2e619dab2..af5d4a7086 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -156,6 +156,11 @@ static inline int plus_2(DisasContext *s, int x) return x + 2; } =20 +static inline int plus_12(DisasContext *s, int x) +{ + return x + 12; +} + static inline int times_2(DisasContext *s, int x) { return x * 2; diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 6e4483fdce..241b4895b7 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -22,3 +22,18 @@ ### SME Misc =20 ZERO 11000000 00 001 00000000000 imm:8 + +### SME Move into/from Array + +%mova_rs 13:2 !function=3Dplus_12 +&mova esz rs pg zr za_imm v:bool to_vec:bool + +MOVA 11000000 esz:2 00000 0 v:1 .. pg:3 zr:5 0 za_imm:4 \ + &mova to_vec=3D0 rs=3D%mova_rs +MOVA 11000000 11 00000 1 v:1 .. pg:3 zr:5 0 za_imm:4 \ + &mova to_vec=3D0 rs=3D%mova_rs esz=3D4 + +MOVA 11000000 esz:2 00001 0 v:1 .. pg:3 0 za_imm:4 zr:5 \ + &mova to_vec=3D1 rs=3D%mova_rs +MOVA 11000000 11 00001 1 v:1 .. pg:3 0 za_imm:4 zr:5 \ + &mova to_vec=3D1 rs=3D%mova_rs esz=3D4 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index eef2df73e1..e88244423d 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -19,8 +19,10 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "internals.h" +#include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" +#include "qemu/int128.h" +#include "vec_internal.h" =20 /* ResetSVEState */ void arm_reset_sve_state(CPUARMState *env) @@ -84,3 +86,150 @@ void helper_sme_zero(CPUARMState *env, uint32_t imm, ui= nt32_t svl) } } } + + +/* + * When considering the ZA storage as an array of elements of + * type T, the index within that array of the Nth element of + * a vertical slice of a tile can be calculated like this, + * regardless of the size of type T. This is because the tiles + * are interleaved, so if type T is size N bytes then row 1 of + * the tile is N rows away from row 0. The division by N to + * convert a byte offset into an array index and the multiplication + * by N to convert from vslice-index-within-the-tile to + * the index within the ZA storage cancel out. + */ +#define tile_vslice_index(i) ((i) * sizeof(ARMVectorReg)) + +/* + * When doing byte arithmetic on the ZA storage, the element + * byteoff bytes away in a tile vertical slice is always this + * many bytes away in the ZA storage, regardless of the + * size of the tile element, assuming that byteoff is a multiple + * of the element size. Again this is because of the interleaving + * of the tiles. For instance if we have 1 byte per element then + * each row of the ZA storage has one byte of the vslice data, + * and (counting from 0) byte 8 goes in row 8 of the storage + * at offset (8 * row-size-in-bytes). + * If we have 8 bytes per element then each row of the ZA storage + * has 8 bytes of the data, but there are 8 interleaved tiles and + * so byte 8 of the data goes into row 1 of the tile, + * which is again row 8 of the storage, so the offset is still + * (8 * row-size-in-bytes). Similarly for other element sizes. + */ +#define tile_vslice_offset(byteoff) ((byteoff) * sizeof(ARMVectorReg)) + + +/* + * Move Zreg vector to ZArray column. + */ +#define DO_MOVA_C(NAME, TYPE, H) \ +void HELPER(NAME)(void *za, void *vn, void *vg, uint32_t desc) \ +{ \ + int i, oprsz =3D simd_oprsz(desc); \ + for (i =3D 0; i < oprsz; ) { \ + uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); \ + do { \ + if (pg & 1) { \ + *(TYPE *)(za + tile_vslice_offset(i)) =3D *(TYPE *)(vn + H= (i)); \ + } \ + i +=3D sizeof(TYPE); \ + pg >>=3D sizeof(TYPE); \ + } while (i & 15); \ + } \ +} + +DO_MOVA_C(sme_mova_cz_b, uint8_t, H1) +DO_MOVA_C(sme_mova_cz_h, uint16_t, H1_2) +DO_MOVA_C(sme_mova_cz_s, uint32_t, H1_4) + +void HELPER(sme_mova_cz_d)(void *za, void *vn, void *vg, uint32_t desc) +{ + int i, oprsz =3D simd_oprsz(desc) / 8; + uint8_t *pg =3D vg; + uint64_t *n =3D vn; + uint64_t *a =3D za; + + for (i =3D 0; i < oprsz; i++) { + if (pg[H1(i)] & 1) { + a[tile_vslice_index(i)] =3D n[i]; + } + } +} + +void HELPER(sme_mova_cz_q)(void *za, void *vn, void *vg, uint32_t desc) +{ + int i, oprsz =3D simd_oprsz(desc) / 16; + uint16_t *pg =3D vg; + Int128 *n =3D vn; + Int128 *a =3D za; + + /* + * Int128 is used here simply to copy 16 bytes, and to simplify + * the address arithmetic. + */ + for (i =3D 0; i < oprsz; i++) { + if (pg[H2(i)] & 1) { + a[tile_vslice_index(i)] =3D n[i]; + } + } +} + +#undef DO_MOVA_C + +/* + * Move ZArray column to Zreg vector. + */ +#define DO_MOVA_Z(NAME, TYPE, H) \ +void HELPER(NAME)(void *vd, void *za, void *vg, uint32_t desc) \ +{ \ + int i, oprsz =3D simd_oprsz(desc); \ + for (i =3D 0; i < oprsz; ) { \ + uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); \ + do { \ + if (pg & 1) { \ + *(TYPE *)(vd + H(i)) =3D *(TYPE *)(za + tile_vslice_offset= (i)); \ + } \ + i +=3D sizeof(TYPE); \ + pg >>=3D sizeof(TYPE); \ + } while (i & 15); \ + } \ +} + +DO_MOVA_Z(sme_mova_zc_b, uint8_t, H1) +DO_MOVA_Z(sme_mova_zc_h, uint16_t, H1_2) +DO_MOVA_Z(sme_mova_zc_s, uint32_t, H1_4) + +void HELPER(sme_mova_zc_d)(void *vd, void *za, void *vg, uint32_t desc) +{ + int i, oprsz =3D simd_oprsz(desc) / 8; + uint8_t *pg =3D vg; + uint64_t *d =3D vd; + uint64_t *a =3D za; + + for (i =3D 0; i < oprsz; i++) { + if (pg[H1(i)] & 1) { + d[i] =3D a[tile_vslice_index(i)]; + } + } +} + +void HELPER(sme_mova_zc_q)(void *vd, void *za, void *vg, uint32_t desc) +{ + int i, oprsz =3D simd_oprsz(desc) / 16; + uint16_t *pg =3D vg; + Int128 *d =3D vd; + Int128 *a =3D za; + + /* + * Int128 is used here simply to copy 16 bytes, and to simplify + * the address arithmetic. + */ + for (i =3D 0; i < oprsz; i++, za +=3D sizeof(ARMVectorReg)) { + if (pg[H2(i)] & 1) { + d[i] =3D a[tile_vslice_index(i)]; + } + } +} + +#undef DO_MOVA_Z diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 0c6379e6e8..df16170469 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -3565,6 +3565,18 @@ void HELPER(sve_sel_zpzz_d)(void *vd, void *vn, void= *vm, } } =20 +void HELPER(sve_sel_zpzz_q)(void *vd, void *vn, void *vm, + void *vg, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 16; + Int128 *d =3D vd, *n =3D vn, *m =3D vm; + uint16_t *pg =3D vg; + + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D (pg[H2(i)] & 1 ? n : m)[i]; + } +} + /* Two operand comparison controlled by a predicate. * ??? It is very tempting to want to be able to expand this inline * with x86 instructions, e.g. diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 971504559b..79c33d35c2 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -35,6 +35,74 @@ #include "decode-sme.c.inc" =20 =20 +/* + * Resolve tile.size[index] to a host pointer, where tile and index + * are always decoded together, dependent on the element size. + */ +static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs, + int tile_index, bool vertical) +{ + int tile =3D tile_index >> (4 - esz); + int index =3D esz =3D=3D MO_128 ? 0 : extract32(tile_index, 0, 4 - esz= ); + int pos, len, offset; + TCGv_i32 tmp; + TCGv_ptr addr; + + /* Compute the final index, which is Rs+imm. */ + tmp =3D tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(tmp, cpu_reg(s, rs)); + tcg_gen_addi_i32(tmp, tmp, index); + + /* Prepare a power-of-two modulo via extraction of @len bits. */ + len =3D ctz32(streaming_vec_reg_size(s)) - esz; + + if (vertical) { + /* + * Compute the byte offset of the index within the tile: + * (index % (svl / size)) * size + * =3D (index % (svl >> esz)) << esz + * Perform the power-of-two modulo via extraction of the low @len = bits. + * Perform the multiply by shifting left by @pos bits. + * Perform these operations simultaneously via deposit into zero. + */ + pos =3D esz; + tcg_gen_deposit_z_i32(tmp, tmp, pos, len); + + /* + * For big-endian, adjust the indexed column byte offset within + * the uint64_t host words that make up env->zarray[]. + */ + if (HOST_BIG_ENDIAN && esz < MO_64) { + tcg_gen_xori_i32(tmp, tmp, 8 - (1 << esz)); + } + } else { + /* + * Compute the byte offset of the index within the tile: + * (index % (svl / size)) * (size * sizeof(row)) + * =3D (index % (svl >> esz)) << (esz + log2(sizeof(row))) + */ + pos =3D esz + ctz32(sizeof(ARMVectorReg)); + tcg_gen_deposit_z_i32(tmp, tmp, pos, len); + + /* Row slices are always aligned and need no endian adjustment. */ + } + + /* The tile byte offset within env->zarray is the row. */ + offset =3D tile * sizeof(ARMVectorReg); + + /* Include the byte offset of zarray to make this relative to env. */ + offset +=3D offsetof(CPUARMState, zarray); + tcg_gen_addi_i32(tmp, tmp, offset); + + /* Add the byte offset to env to produce the final pointer. */ + addr =3D tcg_temp_new_ptr(); + tcg_gen_ext_i32_ptr(addr, tmp); + tcg_temp_free_i32(tmp); + tcg_gen_add_ptr(addr, addr, cpu_env); + + return addr; +} + static bool trans_ZERO(DisasContext *s, arg_ZERO *a) { if (!dc_isar_feature(aa64_sme, s)) { @@ -46,3 +114,62 @@ static bool trans_ZERO(DisasContext *s, arg_ZERO *a) } return true; } + +static bool trans_MOVA(DisasContext *s, arg_MOVA *a) +{ + static gen_helper_gvec_4 * const h_fns[5] =3D { + gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h, + gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d, + gen_helper_sve_sel_zpzz_q + }; + static gen_helper_gvec_3 * const cz_fns[5] =3D { + gen_helper_sme_mova_cz_b, gen_helper_sme_mova_cz_h, + gen_helper_sme_mova_cz_s, gen_helper_sme_mova_cz_d, + gen_helper_sme_mova_cz_q, + }; + static gen_helper_gvec_3 * const zc_fns[5] =3D { + gen_helper_sme_mova_zc_b, gen_helper_sme_mova_zc_h, + gen_helper_sme_mova_zc_s, gen_helper_sme_mova_zc_d, + gen_helper_sme_mova_zc_q, + }; + + TCGv_ptr t_za, t_zr, t_pg; + TCGv_i32 t_desc; + int svl; + + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (!sme_smza_enabled_check(s)) { + return true; + } + + t_za =3D get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v); + t_zr =3D vec_full_reg_ptr(s, a->zr); + t_pg =3D pred_full_reg_ptr(s, a->pg); + + svl =3D streaming_vec_reg_size(s); + t_desc =3D tcg_constant_i32(simd_desc(svl, svl, 0)); + + if (a->v) { + /* Vertical slice -- use sme mova helpers. */ + if (a->to_vec) { + zc_fns[a->esz](t_zr, t_za, t_pg, t_desc); + } else { + cz_fns[a->esz](t_za, t_zr, t_pg, t_desc); + } + } else { + /* Horizontal slice -- reuse sve sel helpers. */ + if (a->to_vec) { + h_fns[a->esz](t_zr, t_za, t_zr, t_pg, t_desc); + } else { + h_fns[a->esz](t_za, t_zr, t_za, t_pg, t_desc); + } + } + + tcg_temp_free_ptr(t_za); + tcg_temp_free_ptr(t_zr); + tcg_temp_free_ptr(t_pg); + + return true; +} --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657294967; cv=none; d=zohomail.com; s=zohoarc; b=O8zOxPYZtLFEbCsZwWRQHO3IWOI+p5P+EBrYaaIHloA7J96GbfPIbLERSZiWpuWXcSqdUpk5MxpouBphQXyLU0zCbhwIKfXBedjB9OYdBxNVqCfrx2tlnMEGYQMqbUBDyd5we6b3Ct27v1xXh2abuwGGhqHsiDXqd6srM/YFqyU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657294967; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8YQB6LeLt+3Ny30LNBUdLIOFN4107DYb/ESLNKv6Buo=; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8YQB6LeLt+3Ny30LNBUdLIOFN4107DYb/ESLNKv6Buo=; b=Zrm146tvGH49hpRCLcPwnds+ETUbYyvbbvET9jpZ3y2U2XvPIyqSkH5VgrPPyIRbjc 4naT05yAnDBY4ToKU2xhlM232T+xCQ5o83lk6YMCfCmpFzsEzhHFt/bPwRSbeGJ6Rdtu H/SVaN23f59RWFhWMAnwnp8nighzN+0l9YcNp4mcI/7IQERgbOk/P0AimYTkhN0E4+Zl +EkYKzm8upfm4TQ2XGyLpE5RSS7JxMtt5rRB9M6QapGTx9kI7T/30s7RlsANmCuf7o3y 5h1Dyhw03fR1RmRZnKJEPPQ8snuYfNPn27Ewr5y9wNgDnBh+3owO5cGloS2UKtZRl4Tn ZzNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8YQB6LeLt+3Ny30LNBUdLIOFN4107DYb/ESLNKv6Buo=; b=e2g96ObpVR/WMv/0+BpcKYLAbi7urRnvrEdJGRmBwhqKK0BiEPolDWszvM6ogIn4UN UdhHZ7a3FtpP+5HUqmW9acSqGhRoZJz5fMN6awtnU0zTEVuEKBAnhyxNdkIejeJcVAW/ 9d8B71Q8YYGrdCMTHsnAG7OByxQus9Z4KYIPtKR01K8tp3scxOTFO8OEyaL25ltI7ohK +TsWPCvr7xVM4JjK2ml4eQyd8Ke9CM1InKJzHrPw/K7mvO/MP+ugONvxBvb8ah00CJ79 zI6eY2boWJmZRNijRKjMG0nCAjza2W566Y5pf/OdqDcgFDcVF35L7IIV+KyuadWMgIeR ftig== X-Gm-Message-State: AJIora8tiIHe/5irGqsj55KAo0qEgaiqKJA7K+PElkDcaLE0s7AUsglm KCKd9GjjZtdVMaLxTNR9YkerIk7SXKRlokc/ X-Google-Smtp-Source: AGRyM1uejRe2ezy8PYso0q8EF4MJBV0B13jloqNRp/vOvrSpodH9ZvUea70lBPIYkSUCcl1n9UDgYw== X-Received: by 2002:a17:90b:4c86:b0:1ec:cc0f:32da with SMTP id my6-20020a17090b4c8600b001eccc0f32damr393184pjb.66.1657293408683; Fri, 08 Jul 2022 08:16:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 20/45] target/arm: Implement SME LD1, ST1 Date: Fri, 8 Jul 2022 20:45:15 +0530 Message-Id: <20220708151540.18136-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657294967757100001 Content-Type: text/plain; charset="utf-8" We cannot reuse the SVE functions for LD[1-4] and ST[1-4], because those functions accept only a Zreg register number. For SME, we want to pass a pointer into ZA storage. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 82 +++++ target/arm/sme.decode | 9 + target/arm/sme_helper.c | 595 +++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 70 +++++ 4 files changed, 756 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 154bc73d2e..95f6e88bdd 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -33,3 +33,85 @@ DEF_HELPER_FLAGS_4(sme_mova_cz_d, TCG_CALL_NO_RWG, void,= ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sme_mova_zc_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) DEF_HELPER_FLAGS_4(sme_mova_cz_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) DEF_HELPER_FLAGS_4(sme_mova_zc_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) + +DEF_HELPER_FLAGS_5(sme_ld1b_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_5(sme_ld1b_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_5(sme_ld1b_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl= , i32) +DEF_HELPER_FLAGS_5(sme_ld1b_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl= , i32) + +DEF_HELPER_FLAGS_5(sme_ld1h_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1h_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1h_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_ld1s_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1s_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1s_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_ld1d_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1d_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1d_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_ld1q_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1q_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1b_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_5(sme_st1b_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_5(sme_st1b_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl= , i32) +DEF_HELPER_FLAGS_5(sme_st1b_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl= , i32) + +DEF_HELPER_FLAGS_5(sme_st1h_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1h_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1h_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1s_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1s_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1s_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1d_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1d_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1d_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1q_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1q_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 241b4895b7..900e3f2a07 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -37,3 +37,12 @@ MOVA 11000000 esz:2 00001 0 v:1 .. pg:3 0 za_= imm:4 zr:5 \ &mova to_vec=3D1 rs=3D%mova_rs MOVA 11000000 11 00001 1 v:1 .. pg:3 0 za_imm:4 zr:5 \ &mova to_vec=3D1 rs=3D%mova_rs esz=3D4 + +### SME Memory + +&ldst esz rs pg rn rm za_imm v:bool st:bool + +LDST1 1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ + &ldst rs=3D%mova_rs +LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ + &ldst esz=3D4 rs=3D%mova_rs diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index e88244423d..10fd1ed910 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -19,10 +19,14 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "internals.h" #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" +#include "exec/cpu_ldst.h" +#include "exec/exec-all.h" #include "qemu/int128.h" #include "vec_internal.h" +#include "sve_ldst_internal.h" =20 /* ResetSVEState */ void arm_reset_sve_state(CPUARMState *env) @@ -233,3 +237,594 @@ void HELPER(sme_mova_zc_q)(void *vd, void *za, void *= vg, uint32_t desc) } =20 #undef DO_MOVA_Z + +/* + * Clear elements in a tile slice comprising len bytes. + */ + +typedef void ClearFn(void *ptr, size_t off, size_t len); + +static void clear_horizontal(void *ptr, size_t off, size_t len) +{ + memset(ptr + off, 0, len); +} + +static void clear_vertical_b(void *vptr, size_t off, size_t len) +{ + for (size_t i =3D 0; i < len; ++i) { + *(uint8_t *)(vptr + tile_vslice_offset(i + off)) =3D 0; + } +} + +static void clear_vertical_h(void *vptr, size_t off, size_t len) +{ + for (size_t i =3D 0; i < len; i +=3D 2) { + *(uint16_t *)(vptr + tile_vslice_offset(i + off)) =3D 0; + } +} + +static void clear_vertical_s(void *vptr, size_t off, size_t len) +{ + for (size_t i =3D 0; i < len; i +=3D 4) { + *(uint32_t *)(vptr + tile_vslice_offset(i + off)) =3D 0; + } +} + +static void clear_vertical_d(void *vptr, size_t off, size_t len) +{ + for (size_t i =3D 0; i < len; i +=3D 8) { + *(uint64_t *)(vptr + tile_vslice_offset(i + off)) =3D 0; + } +} + +static void clear_vertical_q(void *vptr, size_t off, size_t len) +{ + for (size_t i =3D 0; i < len; i +=3D 16) { + memset(vptr + tile_vslice_offset(i + off), 0, 16); + } +} + +/* + * Copy elements from an array into a tile slice comprising len bytes. + */ + +typedef void CopyFn(void *dst, const void *src, size_t len); + +static void copy_horizontal(void *dst, const void *src, size_t len) +{ + memcpy(dst, src, len); +} + +static void copy_vertical_b(void *vdst, const void *vsrc, size_t len) +{ + const uint8_t *src =3D vsrc; + uint8_t *dst =3D vdst; + size_t i; + + for (i =3D 0; i < len; ++i) { + dst[tile_vslice_index(i)] =3D src[i]; + } +} + +static void copy_vertical_h(void *vdst, const void *vsrc, size_t len) +{ + const uint16_t *src =3D vsrc; + uint16_t *dst =3D vdst; + size_t i; + + for (i =3D 0; i < len / 2; ++i) { + dst[tile_vslice_index(i)] =3D src[i]; + } +} + +static void copy_vertical_s(void *vdst, const void *vsrc, size_t len) +{ + const uint32_t *src =3D vsrc; + uint32_t *dst =3D vdst; + size_t i; + + for (i =3D 0; i < len / 4; ++i) { + dst[tile_vslice_index(i)] =3D src[i]; + } +} + +static void copy_vertical_d(void *vdst, const void *vsrc, size_t len) +{ + const uint64_t *src =3D vsrc; + uint64_t *dst =3D vdst; + size_t i; + + for (i =3D 0; i < len / 8; ++i) { + dst[tile_vslice_index(i)] =3D src[i]; + } +} + +static void copy_vertical_q(void *vdst, const void *vsrc, size_t len) +{ + for (size_t i =3D 0; i < len; i +=3D 16) { + memcpy(vdst + tile_vslice_offset(i), vsrc + i, 16); + } +} + +/* + * Host and TLB primitives for vertical tile slice addressing. + */ + +#define DO_LD(NAME, TYPE, HOST, TLB) = \ +static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host)= \ +{ = \ + TYPE val =3D HOST(host); = \ + *(TYPE *)(za + tile_vslice_offset(off)) =3D val; = \ +} = \ +static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za, = \ + intptr_t off, target_ulong addr, uintptr_t ra) = \ +{ = \ + TYPE val =3D TLB(env, useronly_clean_ptr(addr), ra); = \ + *(TYPE *)(za + tile_vslice_offset(off)) =3D val; = \ +} + +#define DO_ST(NAME, TYPE, HOST, TLB) = \ +static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host)= \ +{ = \ + TYPE val =3D *(TYPE *)(za + tile_vslice_offset(off)); = \ + HOST(host, val); = \ +} = \ +static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za, = \ + intptr_t off, target_ulong addr, uintptr_t ra) = \ +{ = \ + TYPE val =3D *(TYPE *)(za + tile_vslice_offset(off)); = \ + TLB(env, useronly_clean_ptr(addr), val, ra); = \ +} + +/* + * The ARMVectorReg elements are stored in host-endian 64-bit units. + * For 128-bit quantities, the sequence defined by the Elem[] pseudocode + * corresponds to storing the two 64-bit pieces in little-endian order. + */ +#define DO_LDQ(HNAME, VNAME, BE, HOST, TLB) = \ +static inline void HNAME##_host(void *za, intptr_t off, void *host) = \ +{ = \ + uint64_t val0 =3D HOST(host), val1 =3D HOST(host + 8); = \ + uint64_t *ptr =3D za + off; = \ + ptr[0] =3D BE ? val1 : val0, ptr[1] =3D BE ? val0 : val1; = \ +} = \ +static inline void VNAME##_v_host(void *za, intptr_t off, void *host) = \ +{ = \ + HNAME##_host(za, tile_vslice_offset(off), host); = \ +} = \ +static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, = \ + target_ulong addr, uintptr_t ra) = \ +{ = \ + uint64_t val0 =3D TLB(env, useronly_clean_ptr(addr), ra); = \ + uint64_t val1 =3D TLB(env, useronly_clean_ptr(addr + 8), ra); = \ + uint64_t *ptr =3D za + off; = \ + ptr[0] =3D BE ? val1 : val0, ptr[1] =3D BE ? val0 : val1; = \ +} = \ +static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off,= \ + target_ulong addr, uintptr_t ra) = \ +{ = \ + HNAME##_tlb(env, za, tile_vslice_offset(off), addr, ra); = \ +} + +#define DO_STQ(HNAME, VNAME, BE, HOST, TLB) = \ +static inline void HNAME##_host(void *za, intptr_t off, void *host) = \ +{ = \ + uint64_t *ptr =3D za + off; = \ + HOST(host, ptr[BE]); = \ + HOST(host + 1, ptr[!BE]); = \ +} = \ +static inline void VNAME##_v_host(void *za, intptr_t off, void *host) = \ +{ = \ + HNAME##_host(za, tile_vslice_offset(off), host); = \ +} = \ +static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, = \ + target_ulong addr, uintptr_t ra) = \ +{ = \ + uint64_t *ptr =3D za + off; = \ + TLB(env, useronly_clean_ptr(addr), ptr[BE], ra); = \ + TLB(env, useronly_clean_ptr(addr + 8), ptr[!BE], ra); = \ +} = \ +static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off,= \ + target_ulong addr, uintptr_t ra) = \ +{ = \ + HNAME##_tlb(env, za, tile_vslice_offset(off), addr, ra); = \ +} + +DO_LD(ld1b, uint8_t, ldub_p, cpu_ldub_data_ra) +DO_LD(ld1h_be, uint16_t, lduw_be_p, cpu_lduw_be_data_ra) +DO_LD(ld1h_le, uint16_t, lduw_le_p, cpu_lduw_le_data_ra) +DO_LD(ld1s_be, uint32_t, ldl_be_p, cpu_ldl_be_data_ra) +DO_LD(ld1s_le, uint32_t, ldl_le_p, cpu_ldl_le_data_ra) +DO_LD(ld1d_be, uint64_t, ldq_be_p, cpu_ldq_be_data_ra) +DO_LD(ld1d_le, uint64_t, ldq_le_p, cpu_ldq_le_data_ra) + +DO_LDQ(sve_ld1qq_be, sme_ld1q_be, 1, ldq_be_p, cpu_ldq_be_data_ra) +DO_LDQ(sve_ld1qq_le, sme_ld1q_le, 0, ldq_le_p, cpu_ldq_le_data_ra) + +DO_ST(st1b, uint8_t, stb_p, cpu_stb_data_ra) +DO_ST(st1h_be, uint16_t, stw_be_p, cpu_stw_be_data_ra) +DO_ST(st1h_le, uint16_t, stw_le_p, cpu_stw_le_data_ra) +DO_ST(st1s_be, uint32_t, stl_be_p, cpu_stl_be_data_ra) +DO_ST(st1s_le, uint32_t, stl_le_p, cpu_stl_le_data_ra) +DO_ST(st1d_be, uint64_t, stq_be_p, cpu_stq_be_data_ra) +DO_ST(st1d_le, uint64_t, stq_le_p, cpu_stq_le_data_ra) + +DO_STQ(sve_st1qq_be, sme_st1q_be, 1, stq_be_p, cpu_stq_be_data_ra) +DO_STQ(sve_st1qq_le, sme_st1q_le, 0, stq_le_p, cpu_stq_le_data_ra) + +#undef DO_LD +#undef DO_ST +#undef DO_LDQ +#undef DO_STQ + +/* + * Common helper for all contiguous predicated loads. + */ + +static inline QEMU_ALWAYS_INLINE +void sme_ld1(CPUARMState *env, void *za, uint64_t *vg, + const target_ulong addr, uint32_t desc, const uintptr_t ra, + const int esz, uint32_t mtedesc, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn, + ClearFn *clr_fn, + CopyFn *cpy_fn) +{ + const intptr_t reg_max =3D simd_oprsz(desc); + const intptr_t esize =3D 1 << esz; + intptr_t reg_off, reg_last; + SVEContLdSt info; + void *host; + int flags; + + /* Find the active elements. */ + if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, esize)) { + /* The entire predicate was false; no load occurs. */ + clr_fn(za, 0, reg_max); + return; + } + + /* Probe the page(s). Exit with exception for any invalid page. */ + sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, ra); + + /* Handle watchpoints for all active elements. */ + sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize, + BP_MEM_READ, ra); + + /* + * Handle mte checks for all active elements. + * Since TBI must be set for MTE, !mtedesc =3D> !mte_active. + */ + if (mtedesc) { + sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize, + mtedesc, ra); + } + + flags =3D info.page[0].flags | info.page[1].flags; + if (unlikely(flags !=3D 0)) { +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + /* + * At least one page includes MMIO. + * Any bus operation can fail with cpu_transaction_failed, + * which for ARM will raise SyncExternal. Perform the load + * into scratch memory to preserve register state until the end. + */ + ARMVectorReg scratch =3D { }; + + reg_off =3D info.reg_off_first[0]; + reg_last =3D info.reg_off_last[1]; + if (reg_last < 0) { + reg_last =3D info.reg_off_split; + if (reg_last < 0) { + reg_last =3D info.reg_off_last[0]; + } + } + + do { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + tlb_fn(env, &scratch, reg_off, addr + reg_off, ra); + } + reg_off +=3D esize; + } while (reg_off & 63); + } while (reg_off <=3D reg_last); + + cpy_fn(za, &scratch, reg_max); + return; +#endif + } + + /* The entire operation is in RAM, on valid pages. */ + + reg_off =3D info.reg_off_first[0]; + reg_last =3D info.reg_off_last[0]; + host =3D info.page[0].host; + + if (!vertical) { + memset(za, 0, reg_max); + } else if (reg_off) { + clr_fn(za, 0, reg_off); + } + + while (reg_off <=3D reg_last) { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } else if (vertical) { + clr_fn(za, reg_off, esize); + } + reg_off +=3D esize; + } while (reg_off <=3D reg_last && (reg_off & 63)); + } + + /* + * Use the slow path to manage the cross-page misalignment. + * But we know this is RAM and cannot trap. + */ + reg_off =3D info.reg_off_split; + if (unlikely(reg_off >=3D 0)) { + tlb_fn(env, za, reg_off, addr + reg_off, ra); + } + + reg_off =3D info.reg_off_first[1]; + if (unlikely(reg_off >=3D 0)) { + reg_last =3D info.reg_off_last[1]; + host =3D info.page[1].host; + + do { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } else if (vertical) { + clr_fn(za, reg_off, esize); + } + reg_off +=3D esize; + } while (reg_off & 63); + } while (reg_off <=3D reg_last); + } +} + +static inline QEMU_ALWAYS_INLINE +void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg, + target_ulong addr, uint32_t desc, uintptr_t ra, + const int esz, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn, + ClearFn *clr_fn, + CopyFn *cpy_fn) +{ + uint32_t mtedesc =3D desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + int bit55 =3D extract64(addr, 55, 1); + + /* Remove mtedesc from the normal sve descriptor. */ + desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + + /* Perform gross MTE suppression early. */ + if (!tbi_check(desc, bit55) || + tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { + mtedesc =3D 0; + } + + sme_ld1(env, za, vg, addr, desc, ra, esz, mtedesc, vertical, + host_fn, tlb_fn, clr_fn, cpy_fn); +} + +#define DO_LD(L, END, ESZ) = \ +void HELPER(sme_ld1##L##END##_h)(CPUARMState *env, void *za, void *vg, = \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_ld1(env, za, vg, addr, desc, GETPC(), ESZ, 0, false, = \ + sve_ld1##L##L##END##_host, sve_ld1##L##L##END##_tlb, = \ + clear_horizontal, copy_horizontal); = \ +} = \ +void HELPER(sme_ld1##L##END##_v)(CPUARMState *env, void *za, void *vg, = \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_ld1(env, za, vg, addr, desc, GETPC(), ESZ, 0, true, = \ + sme_ld1##L##END##_v_host, sme_ld1##L##END##_v_tlb, = \ + clear_vertical_##L, copy_vertical_##L); = \ +} = \ +void HELPER(sme_ld1##L##END##_h_mte)(CPUARMState *env, void *za, void *vg,= \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_ld1_mte(env, za, vg, addr, desc, GETPC(), ESZ, false, = \ + sve_ld1##L##L##END##_host, sve_ld1##L##L##END##_tlb, = \ + clear_horizontal, copy_horizontal); = \ +} = \ +void HELPER(sme_ld1##L##END##_v_mte)(CPUARMState *env, void *za, void *vg,= \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_ld1_mte(env, za, vg, addr, desc, GETPC(), ESZ, true, = \ + sme_ld1##L##END##_v_host, sme_ld1##L##END##_v_tlb, = \ + clear_vertical_##L, copy_vertical_##L); = \ +} + +DO_LD(b, , MO_8) +DO_LD(h, _be, MO_16) +DO_LD(h, _le, MO_16) +DO_LD(s, _be, MO_32) +DO_LD(s, _le, MO_32) +DO_LD(d, _be, MO_64) +DO_LD(d, _le, MO_64) +DO_LD(q, _be, MO_128) +DO_LD(q, _le, MO_128) + +#undef DO_LD + +/* + * Common helper for all contiguous predicated stores. + */ + +static inline QEMU_ALWAYS_INLINE +void sme_st1(CPUARMState *env, void *za, uint64_t *vg, + const target_ulong addr, uint32_t desc, const uintptr_t ra, + const int esz, uint32_t mtedesc, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn) +{ + const intptr_t reg_max =3D simd_oprsz(desc); + const intptr_t esize =3D 1 << esz; + intptr_t reg_off, reg_last; + SVEContLdSt info; + void *host; + int flags; + + /* Find the active elements. */ + if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, esize)) { + /* The entire predicate was false; no store occurs. */ + return; + } + + /* Probe the page(s). Exit with exception for any invalid page. */ + sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_STORE, ra); + + /* Handle watchpoints for all active elements. */ + sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize, + BP_MEM_WRITE, ra); + + /* + * Handle mte checks for all active elements. + * Since TBI must be set for MTE, !mtedesc =3D> !mte_active. + */ + if (mtedesc) { + sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize, + mtedesc, ra); + } + + flags =3D info.page[0].flags | info.page[1].flags; + if (unlikely(flags !=3D 0)) { +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + /* + * At least one page includes MMIO. + * Any bus operation can fail with cpu_transaction_failed, + * which for ARM will raise SyncExternal. We cannot avoid + * this fault and will leave with the store incomplete. + */ + reg_off =3D info.reg_off_first[0]; + reg_last =3D info.reg_off_last[1]; + if (reg_last < 0) { + reg_last =3D info.reg_off_split; + if (reg_last < 0) { + reg_last =3D info.reg_off_last[0]; + } + } + + do { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + tlb_fn(env, za, reg_off, addr + reg_off, ra); + } + reg_off +=3D esize; + } while (reg_off & 63); + } while (reg_off <=3D reg_last); + return; +#endif + } + + reg_off =3D info.reg_off_first[0]; + reg_last =3D info.reg_off_last[0]; + host =3D info.page[0].host; + + while (reg_off <=3D reg_last) { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } + reg_off +=3D 1 << esz; + } while (reg_off <=3D reg_last && (reg_off & 63)); + } + + /* + * Use the slow path to manage the cross-page misalignment. + * But we know this is RAM and cannot trap. + */ + reg_off =3D info.reg_off_split; + if (unlikely(reg_off >=3D 0)) { + tlb_fn(env, za, reg_off, addr + reg_off, ra); + } + + reg_off =3D info.reg_off_first[1]; + if (unlikely(reg_off >=3D 0)) { + reg_last =3D info.reg_off_last[1]; + host =3D info.page[1].host; + + do { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } + reg_off +=3D 1 << esz; + } while (reg_off & 63); + } while (reg_off <=3D reg_last); + } +} + +static inline QEMU_ALWAYS_INLINE +void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong ad= dr, + uint32_t desc, uintptr_t ra, int esz, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn) +{ + uint32_t mtedesc =3D desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + int bit55 =3D extract64(addr, 55, 1); + + /* Remove mtedesc from the normal sve descriptor. */ + desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + + /* Perform gross MTE suppression early. */ + if (!tbi_check(desc, bit55) || + tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { + mtedesc =3D 0; + } + + sme_st1(env, za, vg, addr, desc, ra, esz, mtedesc, + vertical, host_fn, tlb_fn); +} + +#define DO_ST(L, END, ESZ) = \ +void HELPER(sme_st1##L##END##_h)(CPUARMState *env, void *za, void *vg, = \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_st1(env, za, vg, addr, desc, GETPC(), ESZ, 0, false, = \ + sve_st1##L##L##END##_host, sve_st1##L##L##END##_tlb); = \ +} = \ +void HELPER(sme_st1##L##END##_v)(CPUARMState *env, void *za, void *vg, = \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_st1(env, za, vg, addr, desc, GETPC(), ESZ, 0, true, = \ + sme_st1##L##END##_v_host, sme_st1##L##END##_v_tlb); = \ +} = \ +void HELPER(sme_st1##L##END##_h_mte)(CPUARMState *env, void *za, void *vg,= \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_st1_mte(env, za, vg, addr, desc, GETPC(), ESZ, false, = \ + sve_st1##L##L##END##_host, sve_st1##L##L##END##_tlb); = \ +} = \ +void HELPER(sme_st1##L##END##_v_mte)(CPUARMState *env, void *za, void *vg,= \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_st1_mte(env, za, vg, addr, desc, GETPC(), ESZ, true, = \ + sme_st1##L##END##_v_host, sme_st1##L##END##_v_tlb); = \ +} + +DO_ST(b, , MO_8) +DO_ST(h, _be, MO_16) +DO_ST(h, _le, MO_16) +DO_ST(s, _be, MO_32) +DO_ST(s, _le, MO_32) +DO_ST(d, _be, MO_64) +DO_ST(d, _le, MO_64) +DO_ST(q, _be, MO_128) +DO_ST(q, _le, MO_128) + +#undef DO_ST diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 79c33d35c2..42d14b883a 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -173,3 +173,73 @@ static bool trans_MOVA(DisasContext *s, arg_MOVA *a) =20 return true; } + +static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) +{ + typedef void GenLdSt1(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv, TCGv_i32); + + /* + * Indexed by [esz][be][v][mte][st], which is (except for load/store) + * also the order in which the elements appear in the function names, + * and so how we must concatenate the pieces. + */ + +#define FN_LS(F) { gen_helper_sme_ld1##F, gen_helper_sme_st1##F } +#define FN_MTE(F) { FN_LS(F), FN_LS(F##_mte) } +#define FN_HV(F) { FN_MTE(F##_h), FN_MTE(F##_v) } +#define FN_END(L, B) { FN_HV(L), FN_HV(B) } + + static GenLdSt1 * const fns[5][2][2][2][2] =3D { + FN_END(b, b), + FN_END(h_le, h_be), + FN_END(s_le, s_be), + FN_END(d_le, d_be), + FN_END(q_le, q_be), + }; + +#undef FN_LS +#undef FN_MTE +#undef FN_HV +#undef FN_END + + TCGv_ptr t_za, t_pg; + TCGv_i64 addr; + int svl, desc =3D 0; + bool be =3D s->be_data =3D=3D MO_BE; + bool mte =3D s->mte_active[0]; + + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (!sme_smza_enabled_check(s)) { + return true; + } + + t_za =3D get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v); + t_pg =3D pred_full_reg_ptr(s, a->pg); + addr =3D tcg_temp_new_i64(); + + tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz); + tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); + + if (mte) { + desc =3D FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); + desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); + desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); + desc =3D FIELD_DP32(desc, MTEDESC, WRITE, a->st); + desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1); + desc <<=3D SVE_MTEDESC_SHIFT; + } else { + addr =3D clean_data_tbi(s, addr); + } + svl =3D streaming_vec_reg_size(s); + desc =3D simd_desc(svl, svl, desc); + + fns[a->esz][be][a->v][mte][a->st](cpu_env, t_za, t_pg, addr, + tcg_constant_i32(desc)); + + tcg_temp_free_ptr(t_za); + tcg_temp_free_ptr(t_pg); + tcg_temp_free_i64(addr); + return true; +} --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657295103; cv=none; d=zohomail.com; s=zohoarc; b=BgapA+6SSWGJ7/DhoWEZqoAIHii3lyFWMnl0s9fwtGcV2XpknX7hAM4Qb3bi8t3v8qY8ZXbxA40HTQXP0PMA5zlSTqOz7skPahOL0MeNusEBzILd0tarj+HAzwCSg1hcrcI637jkaj2ROqutMOW3+ph/Cp7MJBscRfnLRHJCpp0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657295103; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WXFOydNqWu4pd209lRdohDlcMY8B614kNt2CpuhFxBg=; b=vjokr42DkLjycxKd0gRZFbjH7r5W/ojBDlhKecp1yUpRtx95O3IdJQlpe3x4dZw1Ww ryObICQ4LnsmVmBM4XQfBbSoX4rPi6s8OV4z2qL7HNyFlg6514SWB2C2W4RAdcVPspmr hS2fXZv8LENn0ZZFfU6hXDQ6bluDVhr8fuvEZu+uYZ4pvxD5Uvf2AssWmtc6F+FnFzIC 4IapOeS9CcHgIh2MjA6geiBGvFgQUbD3j6peoj+E1tORFa0R+adP/w6XkADU4NjAcmAK ufS/77LDNISBrswksUlMg80Z3lSS+DnYyEpZWML+tCvXLjpAlEtcePZUv3l2pUpXgRU/ c7Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WXFOydNqWu4pd209lRdohDlcMY8B614kNt2CpuhFxBg=; b=W1OdzTjfhgIT7oI6Fxae9h4rKD2cu+0MAIx+vWWM6mCFmjy4udZLp3A4Z1ybgEM6bU aMyj6Uvy2IKp21KR1ZQMhucTC7+xTvhAUrSM3sNzO+krP2Xqfm6CCNmnku6bsYvT2IDp 9s08BconhqvvRrSuK+qbQzJwox+5LXhSRYKlW2Yl1vYi7z0DmRNNagwpxaJXAtRVzTVR trGyKrSuDmekkzjgdGi/IpNbo4N5NEl+d5n0Z804r/Sv9CZ6G57tLcC3nUitLSUVeAyo ltSI4PUInptrN6i/qJdq84uwasGAwcrcpQE2L/psREJ7E4MD1HmQHvD4YsnN9ZLj96zU DfxA== X-Gm-Message-State: AJIora9ZtS6WDaG3zsiejZviaK/P2yLuXhTpSMx0JjQ+IEI7We2Kt4+p ZFWItIzydh9YtabLyEX7aIyoZ85Tgsegr7jl X-Google-Smtp-Source: AGRyM1uj6dVdZeQyX1BvEgnMfjPS300ISgqbacZlYTX0azhcG2EIyCghQH9v8U/tITfWgnngO0P0Pg== X-Received: by 2002:a17:903:32c4:b0:16a:4227:cd68 with SMTP id i4-20020a17090332c400b0016a4227cd68mr4075185plr.173.1657293411712; Fri, 08 Jul 2022 08:16:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 21/45] target/arm: Export unpredicated ld/st from translate-sve.c Date: Fri, 8 Jul 2022 20:45:16 +0530 Message-Id: <20220708151540.18136-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657295105113100001 Content-Type: text/plain; charset="utf-8" Add a TCGv_ptr base argument, which will be cpu_env for SVE. We will reuse this for SME save and restore array insns. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 3 +++ target/arm/translate-sve.c | 48 ++++++++++++++++++++++++++++---------- 2 files changed, 39 insertions(+), 12 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 2a7fe6e9e7..ad3762d1ac 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -195,4 +195,7 @@ void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint3= 2_t rn_ofs, uint32_t rm_ofs, int64_t shift, uint32_t opr_sz, uint32_t max_sz); =20 +void gen_sve_ldr(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int= imm); +void gen_sve_str(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int= imm); + #endif /* TARGET_ARM_TRANSLATE_A64_H */ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 95016e49e9..fd1a173637 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4306,7 +4306,8 @@ TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz, * The load should begin at the address Rn + IMM. */ =20 -static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int im= m) +void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs, + int len, int rn, int imm) { int len_align =3D QEMU_ALIGN_DOWN(len, 8); int len_remain =3D len % 8; @@ -4332,7 +4333,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, in= t len, int rn, int imm) t0 =3D tcg_temp_new_i64(); for (i =3D 0; i < len_align; i +=3D 8) { tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ); - tcg_gen_st_i64(t0, cpu_env, vofs + i); + tcg_gen_st_i64(t0, base, vofs + i); tcg_gen_addi_i64(clean_addr, clean_addr, 8); } tcg_temp_free_i64(t0); @@ -4345,6 +4346,12 @@ static void do_ldr(DisasContext *s, uint32_t vofs, i= nt len, int rn, int imm) clean_addr =3D new_tmp_a64_local(s); tcg_gen_mov_i64(clean_addr, t0); =20 + if (base !=3D cpu_env) { + TCGv_ptr b =3D tcg_temp_local_new_ptr(); + tcg_gen_mov_ptr(b, base); + base =3D b; + } + gen_set_label(loop); =20 t0 =3D tcg_temp_new_i64(); @@ -4352,7 +4359,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, in= t len, int rn, int imm) tcg_gen_addi_i64(clean_addr, clean_addr, 8); =20 tp =3D tcg_temp_new_ptr(); - tcg_gen_add_ptr(tp, cpu_env, i); + tcg_gen_add_ptr(tp, base, i); tcg_gen_addi_ptr(i, i, 8); tcg_gen_st_i64(t0, tp, vofs); tcg_temp_free_ptr(tp); @@ -4360,6 +4367,11 @@ static void do_ldr(DisasContext *s, uint32_t vofs, i= nt len, int rn, int imm) =20 tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); tcg_temp_free_ptr(i); + + if (base !=3D cpu_env) { + tcg_temp_free_ptr(base); + assert(len_remain =3D=3D 0); + } } =20 /* @@ -4388,13 +4400,14 @@ static void do_ldr(DisasContext *s, uint32_t vofs, = int len, int rn, int imm) default: g_assert_not_reached(); } - tcg_gen_st_i64(t0, cpu_env, vofs + len_align); + tcg_gen_st_i64(t0, base, vofs + len_align); tcg_temp_free_i64(t0); } } =20 /* Similarly for stores. */ -static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int im= m) +void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs, + int len, int rn, int imm) { int len_align =3D QEMU_ALIGN_DOWN(len, 8); int len_remain =3D len % 8; @@ -4420,7 +4433,7 @@ static void do_str(DisasContext *s, uint32_t vofs, in= t len, int rn, int imm) =20 t0 =3D tcg_temp_new_i64(); for (i =3D 0; i < len_align; i +=3D 8) { - tcg_gen_ld_i64(t0, cpu_env, vofs + i); + tcg_gen_ld_i64(t0, base, vofs + i); tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); tcg_gen_addi_i64(clean_addr, clean_addr, 8); } @@ -4434,11 +4447,17 @@ static void do_str(DisasContext *s, uint32_t vofs, = int len, int rn, int imm) clean_addr =3D new_tmp_a64_local(s); tcg_gen_mov_i64(clean_addr, t0); =20 + if (base !=3D cpu_env) { + TCGv_ptr b =3D tcg_temp_local_new_ptr(); + tcg_gen_mov_ptr(b, base); + base =3D b; + } + gen_set_label(loop); =20 t0 =3D tcg_temp_new_i64(); tp =3D tcg_temp_new_ptr(); - tcg_gen_add_ptr(tp, cpu_env, i); + tcg_gen_add_ptr(tp, base, i); tcg_gen_ld_i64(t0, tp, vofs); tcg_gen_addi_ptr(i, i, 8); tcg_temp_free_ptr(tp); @@ -4449,12 +4468,17 @@ static void do_str(DisasContext *s, uint32_t vofs, = int len, int rn, int imm) =20 tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); tcg_temp_free_ptr(i); + + if (base !=3D cpu_env) { + tcg_temp_free_ptr(base); + assert(len_remain =3D=3D 0); + } } =20 /* Predicate register stores can be any multiple of 2. */ if (len_remain) { t0 =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(t0, cpu_env, vofs + len_align); + tcg_gen_ld_i64(t0, base, vofs + len_align); =20 switch (len_remain) { case 2: @@ -4486,7 +4510,7 @@ static bool trans_LDR_zri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D vec_full_reg_size(s); int off =3D vec_full_reg_offset(s, a->rd); - do_ldr(s, off, size, a->rn, a->imm * size); + gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } @@ -4499,7 +4523,7 @@ static bool trans_LDR_pri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D pred_full_reg_size(s); int off =3D pred_full_reg_offset(s, a->rd); - do_ldr(s, off, size, a->rn, a->imm * size); + gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } @@ -4512,7 +4536,7 @@ static bool trans_STR_zri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D vec_full_reg_size(s); int off =3D vec_full_reg_offset(s, a->rd); - do_str(s, off, size, a->rn, a->imm * size); + gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } @@ -4525,7 +4549,7 @@ static bool trans_STR_pri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D pred_full_reg_size(s); int off =3D pred_full_reg_offset(s, a->rd); - do_str(s, off, size, a->rn, a->imm * size); + gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657294972; cv=none; d=zohomail.com; s=zohoarc; b=UBshXkigVlAiigah/jbI9d69md+GebcrK4tbnjWxy56sxIslKlqqx2EhiBC+NNoXPUYIeNd0HX8Bs16+htaOTduGYa4sIqF3Yaf8cr7jJA+nKLVtgJPtbOzLmYEbJwWyugJViXAcZ374F193JVfB0fYHQ1qaVfNaZGiZe/GNSPc= ARC-Message-Signature: i=1; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xubRGg1CD554iutFjuAkV3ppcjr54S3DVLv86vq5+4E=; b=d1lcWU4msMV/mYIrhgTmQ68/IBzQpR+Vbm61k0JJD9exf3MzTaihbPKBI0VmXsOXAo JWyb3iMPm5D2NgbzwbzNLRzEQ8d/5V2qDogKlXxtoEvoordgcTCaUMEQ82uC86KYcBMO 5ihL9NmJfqW+/V1BF8RUIc50uFo4enT1zpUks9Kpj/ZOwqmDREaZ2bWirpIm7xYsNleu DMXwCR9ZOS5U7cZemWyx4/FS9UELMTmglOQrj6dWpV2apCwddB8MxdNt25fGrWxIChY8 m6pRFG+NmbVkfUGUN/seFFK/Hinw0YQdVXei5FFCTO12tj5GV0WA3OcH0XrbxghIhRyA QwRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xubRGg1CD554iutFjuAkV3ppcjr54S3DVLv86vq5+4E=; b=KIB59d0LbjfJSy+EaTKkq4QDvaiw4qQomxFZMkSX6By546uBde5sf+/CzYmJr7F5wS kgs2R2BIrBc0t6hc3TxFAbl8TWhnxsEtvYHwDK2aA8/5sGb1B8EaRmI+2ikHHivthhNT Se9guGh5F6+s3xZvSgcyEsTkgTfZotW6vEdTW/LefMTz2/f0tMSqnDBUN19gHfG2j13J WiSygLdzzGU7gcb21X1a5W+SBrOaJUIVQoivdHJodylS6pLdxt8l/J+i0a4rYh8O4u31 xip04LsRBa7CIe9Rdzts4THcroNiXDk6itt+HtoUOAgOPjy2O5vW0rOO9Leoy9MkgklV yOmA== X-Gm-Message-State: AJIora+aJ+pbA9s8uWZOMboBLc/u2jElFgRiIYfhaiCx1YuVtJDCqpZ5 +Gli/7kfucpD715rVoNoHdkiX3DlcFGpHInD X-Google-Smtp-Source: AGRyM1vhutM/kWDIwfcxhHQ6iRCrGGeUJfL1un39OnP6bhX9+mE3CCw1x/F/i3+gyH7Jl5FNmjZeEQ== X-Received: by 2002:a17:90b:3c0c:b0:1ef:e647:ff48 with SMTP id pb12-20020a17090b3c0c00b001efe647ff48mr321935pjb.173.1657293414536; Fri, 08 Jul 2022 08:16:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 22/45] target/arm: Implement SME LDR, STR Date: Fri, 8 Jul 2022 20:45:17 +0530 Message-Id: <20220708151540.18136-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657294973652100001 Content-Type: text/plain; charset="utf-8" We can reuse the SVE functions for LDR and STR, passing in the base of the ZA vector and a zero offset. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme.decode | 7 +++++++ target/arm/translate-sme.c | 24 ++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 900e3f2a07..f1ebd857a5 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -46,3 +46,10 @@ LDST1 1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn= :5 0 za_imm:4 \ &ldst rs=3D%mova_rs LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ &ldst esz=3D4 rs=3D%mova_rs + +&ldstr rv rn imm +@ldstr ....... ... . ...... .. ... rn:5 . imm:4 \ + &ldstr rv=3D%mova_rs + +LDR 1110000 100 0 000000 .. 000 ..... 0 .... @ldstr +STR 1110000 100 1 000000 .. 000 ..... 0 .... @ldstr diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 42d14b883a..35c2644812 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -243,3 +243,27 @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) tcg_temp_free_i64(addr); return true; } + +typedef void GenLdStR(DisasContext *, TCGv_ptr, int, int, int, int); + +static bool do_ldst_r(DisasContext *s, arg_ldstr *a, GenLdStR *fn) +{ + int svl =3D streaming_vec_reg_size(s); + int imm =3D a->imm; + TCGv_ptr base; + + if (!sme_za_enabled_check(s)) { + return true; + } + + /* ZA[n] equates to ZA0H.B[n]. */ + base =3D get_tile_rowcol(s, MO_8, a->rv, imm, false); + + fn(s, base, 0, svl, a->rn, imm * svl); + + tcg_temp_free_ptr(base); + return true; +} + +TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr) +TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str) --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657295125; cv=none; d=zohomail.com; s=zohoarc; b=DnsgDFZhYFs9gjUkj98vNQFkpD6UzqeSE+MwnIWx+rF0BbjmjWpTetzlpL57daxlrS9ZLjMcu+H+h7F7BJ6wfLiVT0SI9H71uQeTvU1dMqxzk01v1gXUnQg59iB2QxfssLEUmVRiq19YYTBacfQ/eSKTKh6l2uLx0rxP+gCdN5o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657295125; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1nuOMyOTVmZTm/vLrdu3i09qThjbDYLsicba1sLQlZY=; b=V/eQGGo45UA/zCoPeDnWsTr5t6+TFhKLskWcMQf1bETTObyJeL3uoahKbBDZ1N9wfX6Kl4GBpvzESfIhKAp2bJqngb+8j+hqfc8HkB+gSSCOOo2Z/SujuupOdhXTmKP8MEMPqnqeuFefmAW4qSh3CfIdsNDOkgr9pzjFQM9x9+Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657295125758212.33918556675303; Fri, 8 Jul 2022 08:45:25 -0700 (PDT) Received: from localhost ([::1]:40618 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9qAW-0000LG-Dk for importer@patchew.org; Fri, 08 Jul 2022 11:45:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37486) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pj2-0003ZO-SD for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:02 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:39791) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pj0-0002NI-L5 for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:00 -0400 Received: by mail-pl1-x633.google.com with SMTP id c13so12852210pla.6 for ; Fri, 08 Jul 2022 08:16:58 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1nuOMyOTVmZTm/vLrdu3i09qThjbDYLsicba1sLQlZY=; b=DdERSY0vftKcVgPGjo0AXBTsCHdsz+ybd0agPcOBZt/oAwunKuxlKhjq7sO4vsCfJz jyeR9V1qfR32fgRJ438zWLRPVN7icka1LqrEKQ1dBuGlQOk0fhrOxhN6CKpH1CAuIfUT 8RTAqlzaZQu/wtJ6QWqUtAeAjUHZ4DluOWaB3LywpIWyHbgfsttFKo17VnE/XH04fdEv zgGgM5IjPV9kTjIg4kdY1LAJWnm0isSXYxCwtiiqGkys56GH29uuMPrHjiAeBFwSj+uy oUu6aq56qljFKzae7E6Ld4SiG1isvhGK1sf1oi2U4LcguX/MFeArA3yUKNQtHjtfsDtc NQnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657295127465100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 5 +++ target/arm/sme.decode | 11 +++++ target/arm/sme_helper.c | 90 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 31 +++++++++++++ 4 files changed, 137 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 95f6e88bdd..753e9e624c 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -115,3 +115,8 @@ DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, v= oid, env, ptr, ptr, tl, i DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) +DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) +DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) +DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index f1ebd857a5..8cb6c4053c 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -53,3 +53,14 @@ LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn= :5 0 za_imm:4 \ =20 LDR 1110000 100 0 000000 .. 000 ..... 0 .... @ldstr STR 1110000 100 1 000000 .. 000 ..... 0 .... @ldstr + +### SME Add Vector to Array + +&adda zad zn pm pn +@adda_32 ........ .. ..... . pm:3 pn:3 zn:5 ... zad:2 &adda +@adda_64 ........ .. ..... . pm:3 pn:3 zn:5 .. zad:3 &adda + +ADDHA_s 11000000 10 01000 0 ... ... ..... 000 .. @adda_32 +ADDVA_s 11000000 10 01000 1 ... ... ..... 000 .. @adda_32 +ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64 +ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 10fd1ed910..f1e924db74 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -828,3 +828,93 @@ DO_ST(q, _be, MO_128) DO_ST(q, _le, MO_128) =20 #undef DO_ST + +void HELPER(sme_addha_s)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 4; + uint64_t *pn =3D vpn, *pm =3D vpm; + uint32_t *zda =3D vzda, *zn =3D vzn; + + for (row =3D 0; row < oprsz; ) { + uint64_t pa =3D pn[row >> 4]; + do { + if (pa & 1) { + for (col =3D 0; col < oprsz; ) { + uint64_t pb =3D pm[col >> 4]; + do { + if (pb & 1) { + zda[tile_vslice_index(row) + H4(col)] +=3D zn[= H4(col)]; + } + pb >>=3D 4; + } while (++col & 15); + } + } + pa >>=3D 4; + } while (++row & 15); + } +} + +void HELPER(sme_addha_d)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8; + uint8_t *pn =3D vpn, *pm =3D vpm; + uint64_t *zda =3D vzda, *zn =3D vzn; + + for (row =3D 0; row < oprsz; ++row) { + if (pn[H1(row)] & 1) { + for (col =3D 0; col < oprsz; ++col) { + if (pm[H1(col)] & 1) { + zda[tile_vslice_index(row) + col] +=3D zn[col]; + } + } + } + } +} + +void HELPER(sme_addva_s)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 4; + uint64_t *pn =3D vpn, *pm =3D vpm; + uint32_t *zda =3D vzda, *zn =3D vzn; + + for (row =3D 0; row < oprsz; ) { + uint64_t pa =3D pn[row >> 4]; + do { + if (pa & 1) { + uint32_t zn_row =3D zn[H4(row)]; + for (col =3D 0; col < oprsz; ) { + uint64_t pb =3D pm[col >> 4]; + do { + if (pb & 1) { + zda[tile_vslice_index(row) + H4(col)] +=3D zn_= row; + } + pb >>=3D 4; + } while (++col & 15); + } + } + pa >>=3D 4; + } while (++row & 15); + } +} + +void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8; + uint8_t *pn =3D vpn, *pm =3D vpm; + uint64_t *zda =3D vzda, *zn =3D vzn; + + for (row =3D 0; row < oprsz; ++row) { + if (pn[H1(row)] & 1) { + uint64_t zn_row =3D zn[row]; + for (col =3D 0; col < oprsz; ++col) { + if (pm[H1(col)] & 1) { + zda[tile_vslice_index(row) + col] +=3D zn_row; + } + } + } + } +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 35c2644812..d3b9cdd5c4 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -267,3 +267,34 @@ static bool do_ldst_r(DisasContext *s, arg_ldstr *a, G= enLdStR *fn) =20 TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr) TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str) + +static bool do_adda(DisasContext *s, arg_adda *a, MemOp esz, + gen_helper_gvec_4 *fn) +{ + int svl =3D streaming_vec_reg_size(s); + uint32_t desc =3D simd_desc(svl, svl, 0); + TCGv_ptr za, zn, pn, pm; + + if (!sme_smza_enabled_check(s)) { + return true; + } + + /* Sum XZR+zad to find ZAd. */ + za =3D get_tile_rowcol(s, esz, 31, a->zad, false); + zn =3D vec_full_reg_ptr(s, a->zn); + pn =3D pred_full_reg_ptr(s, a->pn); + pm =3D pred_full_reg_ptr(s, a->pm); + + fn(za, zn, pn, pm, tcg_constant_i32(desc)); + + tcg_temp_free_ptr(za); + tcg_temp_free_ptr(zn); + tcg_temp_free_ptr(pn); + tcg_temp_free_ptr(pm); + return true; +} + +TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addha_s) +TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s) +TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= ha_d) +TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= va_d) --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657294260928100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 5 +++ target/arm/sme.decode | 9 +++++ target/arm/sme_helper.c | 69 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 32 ++++++++++++++++++ 4 files changed, 115 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 753e9e624c..f50d0fe1d6 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -120,3 +120,8 @@ DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) + +DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 8cb6c4053c..ba4774d174 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -64,3 +64,12 @@ ADDHA_s 11000000 10 01000 0 ... ... ..... 000 ..= @adda_32 ADDVA_s 11000000 10 01000 1 ... ... ..... 000 .. @adda_32 ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64 ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64 + +### SME Outer Product + +&op zad zn zm pm pn sub:bool +@op_32 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 .. zad:2 &op +@op_64 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 . zad:3 &op + +FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32 +FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index f1e924db74..7dc76b6a1c 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -25,6 +25,7 @@ #include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "qemu/int128.h" +#include "fpu/softfloat.h" #include "vec_internal.h" #include "sve_ldst_internal.h" =20 @@ -918,3 +919,71 @@ void HELPER(sme_addva_d)(void *vzda, void *vzn, void *= vpn, } } } + +void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, void *vst, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_maxsz(desc); + uint32_t neg =3D simd_data(desc) << 31; + uint16_t *pn =3D vpn, *pm =3D vpm; + float_status fpst; + + /* + * Make a copy of float_status because this operation does not + * update the cumulative fp exception status. It also produces + * default nans. + */ + fpst =3D *(float_status *)vst; + set_default_nan_mode(true, &fpst); + + for (row =3D 0; row < oprsz; ) { + uint16_t pa =3D pn[H2(row >> 4)]; + do { + if (pa & 1) { + void *vza_row =3D vza + tile_vslice_offset(row); + uint32_t n =3D *(uint32_t *)(vzn + H1_4(row)) ^ neg; + + for (col =3D 0; col < oprsz; ) { + uint16_t pb =3D pm[H2(col >> 4)]; + do { + if (pb & 1) { + uint32_t *a =3D vza_row + H1_4(col); + uint32_t *m =3D vzm + H1_4(col); + *a =3D float32_muladd(n, *m, *a, 0, vst); + } + col +=3D 4; + pb >>=3D 4; + } while (col & 15); + } + } + row +=3D 4; + pa >>=3D 4; + } while (row & 15); + } +} + +void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, void *vst, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8; + uint64_t neg =3D (uint64_t)simd_data(desc) << 63; + uint64_t *za =3D vza, *zn =3D vzn, *zm =3D vzm; + uint8_t *pn =3D vpn, *pm =3D vpm; + float_status fpst =3D *(float_status *)vst; + + set_default_nan_mode(true, &fpst); + + for (row =3D 0; row < oprsz; ++row) { + if (pn[H1(row)] & 1) { + uint64_t *za_row =3D &za[tile_vslice_index(row)]; + uint64_t n =3D zn[row] ^ neg; + + for (col =3D 0; col < oprsz; ++col) { + if (pm[H1(col)] & 1) { + uint64_t *a =3D &za_row[col]; + *a =3D float64_muladd(n, zm[col], *a, 0, &fpst); + } + } + } + } +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index d3b9cdd5c4..fa8f343a7d 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -298,3 +298,35 @@ TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_h= elper_sme_addha_s) TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s) TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= ha_d) TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= va_d) + +static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, + gen_helper_gvec_5_ptr *fn) +{ + int svl =3D streaming_vec_reg_size(s); + uint32_t desc =3D simd_desc(svl, svl, a->sub); + TCGv_ptr za, zn, zm, pn, pm, fpst; + + if (!sme_smza_enabled_check(s)) { + return true; + } + + /* Sum XZR+zad to find ZAd. */ + za =3D get_tile_rowcol(s, esz, 31, a->zad, false); + zn =3D vec_full_reg_ptr(s, a->zn); + zm =3D vec_full_reg_ptr(s, a->zm); + pn =3D pred_full_reg_ptr(s, a->pn); + pm =3D pred_full_reg_ptr(s, a->pm); + fpst =3D fpstatus_ptr(FPST_FPCR); + + fn(za, zn, zm, pn, pm, fpst, tcg_constant_i32(desc)); + + tcg_temp_free_ptr(za); + tcg_temp_free_ptr(zn); + tcg_temp_free_ptr(pn); + tcg_temp_free_ptr(pm); + tcg_temp_free_ptr(fpst); + return true; +} + +TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fm= opa_s) +TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper= _sme_fmopa_d) --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657294080472100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 2 ++ target/arm/sme.decode | 2 ++ target/arm/sme_helper.c | 56 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 30 ++++++++++++++++++++ 4 files changed, 90 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index f50d0fe1d6..1d68fb8c74 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -125,3 +125,5 @@ DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index ba4774d174..afd9c0dffd 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -73,3 +73,5 @@ ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... = @adda_64 =20 FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32 FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 + +BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 7dc76b6a1c..690a53eee2 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -987,3 +987,59 @@ void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *v= zm, void *vpn, } } } + +/* + * Alter PAIR as needed for controlling predicates being false, + * and for NEG on an enabled row element. + */ +static inline uint32_t f16mop_adj_pair(uint32_t pair, uint32_t pg, uint32_= t neg) +{ + /* + * The pseudocode uses a conditional negate after the conditional zero. + * It is simpler here to unconditionally negate before conditional zer= o. + */ + pair ^=3D neg; + if (!(pg & 1)) { + pair &=3D 0xffff0000u; + } + if (!(pg & 4)) { + pair &=3D 0x0000ffffu; + } + return pair; +} + +void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_maxsz(desc); + uint32_t neg =3D simd_data(desc) * 0x80008000u; + uint16_t *pn =3D vpn, *pm =3D vpm; + + for (row =3D 0; row < oprsz; ) { + uint16_t prow =3D pn[H2(row >> 4)]; + do { + void *vza_row =3D vza + tile_vslice_offset(row); + uint32_t n =3D *(uint32_t *)(vzn + H1_4(row)); + + n =3D f16mop_adj_pair(n, prow, neg); + + for (col =3D 0; col < oprsz; ) { + uint16_t pcol =3D pm[H2(col >> 4)]; + do { + if (prow & pcol & 0b0101) { + uint32_t *a =3D vza_row + H1_4(col); + uint32_t m =3D *(uint32_t *)(vzm + H1_4(col)); + + m =3D f16mop_adj_pair(m, pcol, 0); + *a =3D bfdotadd(*a, n, m); + + col +=3D 4; + pcol >>=3D 4; + } + } while (col & 15); + } + row +=3D 4; + prow >>=3D 4; + } while (row & 15); + } +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index fa8f343a7d..ecb7583c55 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -299,6 +299,33 @@ TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_h= elper_sme_addva_s) TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= ha_d) TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= va_d) =20 +static bool do_outprod(DisasContext *s, arg_op *a, MemOp esz, + gen_helper_gvec_5 *fn) +{ + int svl =3D streaming_vec_reg_size(s); + uint32_t desc =3D simd_desc(svl, svl, a->sub); + TCGv_ptr za, zn, zm, pn, pm; + + if (!sme_smza_enabled_check(s)) { + return true; + } + + /* Sum XZR+zad to find ZAd. */ + za =3D get_tile_rowcol(s, esz, 31, a->zad, false); + zn =3D vec_full_reg_ptr(s, a->zn); + zm =3D vec_full_reg_ptr(s, a->zm); + pn =3D pred_full_reg_ptr(s, a->pn); + pm =3D pred_full_reg_ptr(s, a->pm); + + fn(za, zn, zm, pn, pm, tcg_constant_i32(desc)); + + tcg_temp_free_ptr(za); + tcg_temp_free_ptr(zn); + tcg_temp_free_ptr(pn); + tcg_temp_free_ptr(pm); + return true; +} + static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, gen_helper_gvec_5_ptr *fn) { @@ -330,3 +357,6 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a,= MemOp esz, =20 TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fm= opa_s) TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper= _sme_fmopa_d) + +/* TODO: FEAT_EBF16 */ +TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa) --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657295315520100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 2 ++ target/arm/sme.decode | 1 + target/arm/sme_helper.c | 74 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 1 + 4 files changed, 78 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 1d68fb8c74..4d5d05db3a 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -121,6 +121,8 @@ DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) =20 +DEF_HELPER_FLAGS_7(sme_fmopa_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, diff --git a/target/arm/sme.decode b/target/arm/sme.decode index afd9c0dffd..e8d27fd8a0 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -75,3 +75,4 @@ FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. = @op_32 FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 =20 BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 +FMOPA_h 10000001 101 ..... ... ... ..... . 00 .. @op_32 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 690a53eee2..302f89c30b 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -1008,6 +1008,80 @@ static inline uint32_t f16mop_adj_pair(uint32_t pair= , uint32_t pg, uint32_t neg) return pair; } =20 +static float32 f16_dotadd(float32 sum, uint32_t e1, uint32_t e2, + float_status *s_std, float_status *s_odd) +{ + float64 e1r =3D float16_to_float64(e1 & 0xffff, true, s_std); + float64 e1c =3D float16_to_float64(e1 >> 16, true, s_std); + float64 e2r =3D float16_to_float64(e2 & 0xffff, true, s_std); + float64 e2c =3D float16_to_float64(e2 >> 16, true, s_std); + float64 t64; + float32 t32; + + /* + * The ARM pseudocode function FPDot performs both multiplies + * and the add with a single rounding operation. Emulate this + * by performing the first multiply in round-to-odd, then doing + * the second multiply as fused multiply-add, and rounding to + * float32 all in one step. + */ + t64 =3D float64_mul(e1r, e2r, s_odd); + t64 =3D float64r32_muladd(e1c, e2c, t64, 0, s_std); + + /* This conversion is exact, because we've already rounded. */ + t32 =3D float64_to_float32(t64, s_std); + + /* The final accumulation step is not fused. */ + return float32_add(sum, t32, s_std); +} + +void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, void *vst, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_maxsz(desc); + uint32_t neg =3D simd_data(desc) * 0x80008000u; + uint16_t *pn =3D vpn, *pm =3D vpm; + float_status fpst_odd, fpst_std; + + /* + * Make a copy of float_status because this operation does not + * update the cumulative fp exception status. It also produces + * default nans. Make a second copy with round-to-odd -- see above. + */ + fpst_std =3D *(float_status *)vst; + set_default_nan_mode(true, &fpst_std); + fpst_odd =3D fpst_std; + set_float_rounding_mode(float_round_to_odd, &fpst_odd); + + for (row =3D 0; row < oprsz; ) { + uint16_t prow =3D pn[H2(row >> 4)]; + do { + void *vza_row =3D vza + tile_vslice_offset(row); + uint32_t n =3D *(uint32_t *)(vzn + H1_4(row)); + + n =3D f16mop_adj_pair(n, prow, neg); + + for (col =3D 0; col < oprsz; ) { + uint16_t pcol =3D pm[H2(col >> 4)]; + do { + if (prow & pcol & 0b0101) { + uint32_t *a =3D vza_row + H1_4(col); + uint32_t m =3D *(uint32_t *)(vzm + H1_4(col)); + + m =3D f16mop_adj_pair(m, pcol, 0); + *a =3D f16_dotadd(*a, n, m, &fpst_std, &fpst_odd); + + col +=3D 4; + pcol >>=3D 4; + } + } while (col & 15); + } + row +=3D 4; + prow >>=3D 4; + } while (row & 15); + } +} + void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, void *vpm, uint32_t desc) { diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index ecb7583c55..c2953b22ce 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -355,6 +355,7 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a,= MemOp esz, return true; } =20 +TRANS_FEAT(FMOPA_h, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fm= opa_h) TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fm= opa_s) TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper= _sme_fmopa_d) =20 --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657294518; cv=none; d=zohomail.com; s=zohoarc; b=EB8QRQWfzk1PHJB/Zzh9dc9lXWufoJH9OSQSMvhNX2sc4P3E55rweHSek1R3qQjpDepz3SL8jOMGPYn6X6VsitCGZlpR5xT7cOAhrCKNvKYRrd4WMkAv32X0EGpju5dNfC8zlJNGQkb6x+W966ATWiNhm6QSNeSJtJncf9JajAI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657294518; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hXhGi/aw89RWj52AXFgmx3W0yCI8A/e6P49IWgiTRQs=; b=eId3czS1MFsKghhC+SDRoIe0v/ldkMERig+t63DVk1rpqJovtaYArufYrKyk4XrA3FnzhspjkLNjfvJ3oTwiAIZqasdOO9fO6EFOsCxHP7tnG79PPW8OSh5ecy5oyJW/EIQ4bBrulHic9H8lGqh9pS4/oKrqIRiE/jpSYsoGiVA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657294518860846.6204482088355; Fri, 8 Jul 2022 08:35:18 -0700 (PDT) Received: from localhost ([::1]:41838 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9q0j-0005YR-Ja for importer@patchew.org; Fri, 08 Jul 2022 11:35:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37626) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pjE-000404-7E for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:12 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:40939) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pjB-00028w-Be for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:11 -0400 Received: by mail-pj1-x102d.google.com with SMTP id g16-20020a17090a7d1000b001ea9f820449so2220799pjl.5 for ; Fri, 08 Jul 2022 08:17:08 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hXhGi/aw89RWj52AXFgmx3W0yCI8A/e6P49IWgiTRQs=; b=gycKuKBNDGdn/L/F+HJe7jaTxLzUgscs6OKVzhsE2VIAwLCRcFcxJG8OKcgt0kcuoh cXAUCSQRAQl1XUprJxk6YaHjXYUpBWuF1Ldbb7w1cTgEFUxj+dCkjQwi6QwwlwO2dL9z 0L27mU6wdBHGZ210ArakrbGj7puC3LoJBvS0rqPxmxtjq99oQuGX5CilkAakAdiVkjtS QrZGtqJg4mjh1J9nyYb79n0rSii4nUWJAriQR9LkBrTmwfKFhJLIpQkZ5uR/R6FhbtSP qjB49pJq1sVrQt9jvjE9OSlkIds00GbxJirSRYKsvA+/piqnSr9Gi5ZjTDceHuzP/ETc 1/Ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hXhGi/aw89RWj52AXFgmx3W0yCI8A/e6P49IWgiTRQs=; b=3Uazxysok2vvHLb2gbj0AryViEHNhX9jg4tASr9+xFNOvWg+WWLSLVjNjW4oux3XaR Q6owjBQbXBGc3+O+/dtWZbdyR1HU7LX3LzQ30E62Kk17UvCu5OfdkDxuRfLoVbLE8WqQ ETfqbBtqI1zuniHEqyPRhQYkSHak0KsM4pvOCPl63cqSUC/ReinJYGwqfLEXZEK4ulxT lJuOMhN/C/r+hcKwGXcrNLqIjul65cPXrS/X5qe/g42/WhKU6pV7l7u2bGXo3ln1alp7 DesyEOo+1S2M8gV6mU0OThjl3TQfcvhELF678q2dla8LYuVjO5FJ8GhIYYeWbcXPIpCv a/xA== X-Gm-Message-State: AJIora8sQsFTzATrFn8ZjpLbVjSwFZjugZVmNR3oUNELvceOtVz7cDHl /8R962ctICa/o5RqwaX6YAc4lu3/KABaWd/W X-Google-Smtp-Source: AGRyM1tBSahVEVI4we8qfJBVXjw50MnfsGcg7VWvESOPLdR3YL2w7yJY+nSgq5kcgArQLwJeFUJ9bw== X-Received: by 2002:a17:902:d542:b0:16c:8ac:f471 with SMTP id z2-20020a170902d54200b0016c08acf471mr4387311plf.39.1657293428558; Fri, 08 Jul 2022 08:17:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 27/45] target/arm: Implement SME integer outer product Date: Fri, 8 Jul 2022 20:45:22 +0530 Message-Id: <20220708151540.18136-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657294520426100001 Content-Type: text/plain; charset="utf-8" This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 16 ++++++++ target/arm/sme.decode | 10 +++++ target/arm/sme_helper.c | 82 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 10 +++++ 4 files changed, 118 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 4d5d05db3a..d2d544a696 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -129,3 +129,19 @@ DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_smopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_umopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_sumopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_usmopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_smopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_umopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_sumopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_usmopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index e8d27fd8a0..628804e37a 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -76,3 +76,13 @@ FMOPA_d 10000000 110 ..... ... ... ..... . 0 ...= @op_64 =20 BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 FMOPA_h 10000001 101 ..... ... ... ..... . 00 .. @op_32 + +SMOPA_s 1010000 0 10 0 ..... ... ... ..... . 00 .. @op_32 +SUMOPA_s 1010000 0 10 1 ..... ... ... ..... . 00 .. @op_32 +USMOPA_s 1010000 1 10 0 ..... ... ... ..... . 00 .. @op_32 +UMOPA_s 1010000 1 10 1 ..... ... ... ..... . 00 .. @op_32 + +SMOPA_d 1010000 0 11 0 ..... ... ... ..... . 0 ... @op_64 +SUMOPA_d 1010000 0 11 1 ..... ... ... ..... . 0 ... @op_64 +USMOPA_d 1010000 1 11 0 ..... ... ... ..... . 0 ... @op_64 +UMOPA_d 1010000 1 11 1 ..... ... ... ..... . 0 ... @op_64 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 302f89c30b..f891306bb9 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -1117,3 +1117,85 @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *= vzm, void *vpn, } while (row & 15); } } + +typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool); + +static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm, + uint8_t *pn, uint8_t *pm, + uint32_t desc, IMOPFn *fn) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8; + bool neg =3D simd_data(desc); + + for (row =3D 0; row < oprsz; ++row) { + uint8_t pa =3D pn[H1(row)]; + uint64_t *za_row =3D &za[tile_vslice_index(row)]; + uint64_t n =3D zn[row]; + + for (col =3D 0; col < oprsz; ++col) { + uint8_t pb =3D pm[H1(col)]; + uint64_t *a =3D &za_row[col]; + + *a =3D fn(n, zm[col], *a, pa & pb, neg); + } + } +} + +#define DEF_IMOP_32(NAME, NTYPE, MTYPE) \ +static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool n= eg) \ +{ = \ + uint32_t sum0 =3D 0, sum1 =3D 0; = \ + /* Apply P to N as a mask, making the inactive elements 0. */ = \ + n &=3D expand_pred_b(p); = \ + sum0 +=3D (NTYPE)(n >> 0) * (MTYPE)(m >> 0); = \ + sum0 +=3D (NTYPE)(n >> 8) * (MTYPE)(m >> 8); = \ + sum0 +=3D (NTYPE)(n >> 16) * (MTYPE)(m >> 16); = \ + sum0 +=3D (NTYPE)(n >> 24) * (MTYPE)(m >> 24); = \ + sum1 +=3D (NTYPE)(n >> 32) * (MTYPE)(m >> 32); = \ + sum1 +=3D (NTYPE)(n >> 40) * (MTYPE)(m >> 40); = \ + sum1 +=3D (NTYPE)(n >> 48) * (MTYPE)(m >> 48); = \ + sum1 +=3D (NTYPE)(n >> 56) * (MTYPE)(m >> 56); = \ + if (neg) { = \ + sum0 =3D (uint32_t)a - sum0, sum1 =3D (uint32_t)(a >> 32) - sum1; = \ + } else { = \ + sum0 =3D (uint32_t)a + sum0, sum1 =3D (uint32_t)(a >> 32) + sum1; = \ + } = \ + return ((uint64_t)sum1 << 32) | sum0; = \ +} + +#define DEF_IMOP_64(NAME, NTYPE, MTYPE) \ +static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool n= eg) \ +{ = \ + uint64_t sum =3D 0; = \ + /* Apply P to N as a mask, making the inactive elements 0. */ = \ + n &=3D expand_pred_h(p); = \ + sum +=3D (NTYPE)(n >> 0) * (MTYPE)(m >> 0); = \ + sum +=3D (NTYPE)(n >> 16) * (MTYPE)(m >> 16); = \ + sum +=3D (NTYPE)(n >> 32) * (MTYPE)(m >> 32); = \ + sum +=3D (NTYPE)(n >> 48) * (MTYPE)(m >> 48); = \ + return neg ? a - sum : a + sum; = \ +} + +DEF_IMOP_32(smopa_s, int8_t, int8_t) +DEF_IMOP_32(umopa_s, uint8_t, uint8_t) +DEF_IMOP_32(sumopa_s, int8_t, uint8_t) +DEF_IMOP_32(usmopa_s, uint8_t, int8_t) + +DEF_IMOP_64(smopa_d, int16_t, int16_t) +DEF_IMOP_64(umopa_d, uint16_t, uint16_t) +DEF_IMOP_64(sumopa_d, int16_t, uint16_t) +DEF_IMOP_64(usmopa_d, uint16_t, int16_t) + +#define DEF_IMOPH(NAME) \ + void HELPER(sme_##NAME)(void *vza, void *vzn, void *vzm, void *vpn, = \ + void *vpm, uint32_t desc) = \ + { do_imopa(vza, vzn, vzm, vpn, vpm, desc, NAME); } + +DEF_IMOPH(smopa_s) +DEF_IMOPH(umopa_s) +DEF_IMOPH(sumopa_s) +DEF_IMOPH(usmopa_s) +DEF_IMOPH(smopa_d) +DEF_IMOPH(umopa_d) +DEF_IMOPH(sumopa_d) +DEF_IMOPH(usmopa_d) diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index c2953b22ce..7b87a9df63 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -361,3 +361,13 @@ TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, = a, MO_64, gen_helper_sme_f =20 /* TODO: FEAT_EBF16 */ TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa) + +TRANS_FEAT(SMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_smopa_s) +TRANS_FEAT(UMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_umopa_s) +TRANS_FEAT(SUMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_sumopa= _s) +TRANS_FEAT(USMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_usmopa= _s) + +TRANS_FEAT(SMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_= smopa_d) +TRANS_FEAT(UMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_= umopa_d) +TRANS_FEAT(SUMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme= _sumopa_d) +TRANS_FEAT(USMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme= _usmopa_d) --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657294747; cv=none; d=zohomail.com; s=zohoarc; b=i0N7X3AP6b08fK7ZE0wj/QcC2paYQnHTzpdvkzTcyXPx2w1AoKF4fjAU4ALtwmgEQCmMHxs0vBYh6UU2VE3SBb6llhYQC+uh6YEfwr0TJbGzJnCZa3QHMkr3ztCvgRauvvCedOl1pEIi3iOje98JmxijCYuNzwiqa3l6+hCausk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657294747; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=z4hqPmoRZ7cVUM8Y9hb593g0CFOYpdMYGSA5G3fCVmQ=; b=NpEAwphqoPajQiCyqcFFCY7inQIxcfhh0AKNt+hCZjAfobLo0SQwiljClqCF90oS9F8wykmqYIYZh+MV0LAakqaksaymCHe0+1Y3rCeglhtgCNtEuAKisAUQsLDayit1nc2NdKPrgu0boTQ0TFKfxvhuJ0Hzq2V0diy8z7rDWNA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657294747823826.6534775474615; Fri, 8 Jul 2022 08:39:07 -0700 (PDT) Received: from localhost ([::1]:50380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9q4P-0003OC-Qb for importer@patchew.org; Fri, 08 Jul 2022 11:39:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37660) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pjG-00047A-8i for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:14 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:33680) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pjE-0002PV-HP for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:13 -0400 Received: by mail-pl1-x632.google.com with SMTP id p16so1876497plo.0 for ; Fri, 08 Jul 2022 08:17:12 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z4hqPmoRZ7cVUM8Y9hb593g0CFOYpdMYGSA5G3fCVmQ=; b=TW36E2ZK6c6exLnYdxw9aKW14NSYb0f2AI10Ldr3/CGISt0fY0S91+p76qgATLxcD+ uABJfHIgOAzI5B3eTlX+eKY8TlASbeG53QFanniCX4ZDf+xwWz9uQjZg/wScYCngfqgT 9WZ1aSq1dsAww3W8XN6kGdrIq4VdHnnw5TRYVI4rP3DMLgdVR3BdBniyRLdjD18nhAqA cm4evZW5C77Fzg+0EABpSQP1R+y3ZheiXQATQSBmaq76mRIMTwmevI5EXQQiK3pxn6li TFyo0Lh/hIBc8Vl1n368LG3CD2BXiRqOV7+ix8Tx2c5p9TzuB5x0icMAbvC0izXqFtcn 1nzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z4hqPmoRZ7cVUM8Y9hb593g0CFOYpdMYGSA5G3fCVmQ=; b=HZ3w6C0+tt9HXP9EV4F7VRaIFVJzhsCyOsmbVWVPjSSW9Bso0yXX57kA1NIq+OKYbs 8Ge42pmisCAzIDe1fmPsfUGAd4xEqXu7DZpb+Hcox2g2QiIqSYWBQVHx4qZvuBZBMGEX NDtXF2Vp+2WgjvhiPjI5pHmAPkXMTDaUf9BSzEYtSmWFV1D91XRabhm+w4j7Loof0UWH xeh8MEG7MS2wbXhWQApQvKaVcA/mbzMr+wiowdI81GMSk8eqoTNEUgFp3eafS0e/DTdB VEPEDlhr+s58hSsgdgs7wAncGpCRPUVLO/ApEW1KC77c5iwyXjLq2fNmZVtbrXJ9TiUd GvJQ== X-Gm-Message-State: AJIora8mSEcTh3V5nxtWou3grSXfmzGfIjejhK8iLLOY2+EGaRwpvi02 Ct4XtVSQ0tihRrSZsLN1ACHzai+DWIvVx96F X-Google-Smtp-Source: AGRyM1tedZLM7QZ0hQiqILugkM8fcjsJhNOdf8dlAm8g0tHstmx/j9b/M6j2UQEQhpaClD1Hl/zLkQ== X-Received: by 2002:a17:902:9a46:b0:16b:f25b:d50 with SMTP id x6-20020a1709029a4600b0016bf25b0d50mr4117137plv.154.1657293431258; Fri, 08 Jul 2022 08:17:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 28/45] target/arm: Implement PSEL Date: Fri, 8 Jul 2022 20:45:23 +0530 Message-Id: <20220708151540.18136-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657294749650100001 Content-Type: text/plain; charset="utf-8" This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve.decode | 20 +++++++++++++ target/arm/translate-sve.c | 57 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 95af08c139..966803cbb7 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1674,3 +1674,23 @@ BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ...= .. @rrxr_3a esz=3D2 =20 ### SVE2 floating-point bfloat16 dot-product (indexed) BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=3D2 + +### SVE broadcast predicate element + +&psel esz pd pn pm rv imm +%psel_rv 16:2 !function=3Dplus_12 +%psel_imm_b 22:2 19:2 +%psel_imm_h 22:2 20:1 +%psel_imm_s 22:2 +%psel_imm_d 23:1 +@psel ........ .. . ... .. .. pn:4 . pm:4 . pd:4 \ + &psel rv=3D%psel_rv + +PSEL 00100101 .. 1 ..1 .. 01 .... 0 .... 0 .... \ + @psel esz=3D0 imm=3D%psel_imm_b +PSEL 00100101 .. 1 .10 .. 01 .... 0 .... 0 .... \ + @psel esz=3D1 imm=3D%psel_imm_h +PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \ + @psel esz=3D2 imm=3D%psel_imm_s +PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ + @psel esz=3D3 imm=3D%psel_imm_d diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index fd1a173637..24ffb69a2a 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7419,3 +7419,60 @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr= _esz *a, bool sel) =20 TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false) TRANS_FEAT(BFMLALT_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, true) + +static bool trans_PSEL(DisasContext *s, arg_psel *a) +{ + int vl =3D vec_full_reg_size(s); + int pl =3D pred_gvec_reg_size(s); + int elements =3D vl >> a->esz; + TCGv_i64 tmp, didx, dbit; + TCGv_ptr ptr; + + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (!sve_access_check(s)) { + return true; + } + + tmp =3D tcg_temp_new_i64(); + dbit =3D tcg_temp_new_i64(); + didx =3D tcg_temp_new_i64(); + ptr =3D tcg_temp_new_ptr(); + + /* Compute the predicate element. */ + tcg_gen_addi_i64(tmp, cpu_reg(s, a->rv), a->imm); + if (is_power_of_2(elements)) { + tcg_gen_andi_i64(tmp, tmp, elements - 1); + } else { + tcg_gen_remu_i64(tmp, tmp, tcg_constant_i64(elements)); + } + + /* Extract the predicate byte and bit indices. */ + tcg_gen_shli_i64(tmp, tmp, a->esz); + tcg_gen_andi_i64(dbit, tmp, 7); + tcg_gen_shri_i64(didx, tmp, 3); + if (HOST_BIG_ENDIAN) { + tcg_gen_xori_i64(didx, didx, 7); + } + + /* Load the predicate word. */ + tcg_gen_trunc_i64_ptr(ptr, didx); + tcg_gen_add_ptr(ptr, ptr, cpu_env); + tcg_gen_ld8u_i64(tmp, ptr, pred_full_reg_offset(s, a->pm)); + + /* Extract the predicate bit and replicate to MO_64. */ + tcg_gen_shr_i64(tmp, tmp, dbit); + tcg_gen_andi_i64(tmp, tmp, 1); + tcg_gen_neg_i64(tmp, tmp); + + /* Apply to either copy the source, or write zeros. */ + tcg_gen_gvec_ands(MO_64, pred_full_reg_offset(s, a->pd), + pred_full_reg_offset(s, a->pn), tmp, pl, pl); + + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(dbit); + tcg_temp_free_i64(didx); + tcg_temp_free_ptr(ptr); + return true; +} --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657295501; cv=none; d=zohomail.com; s=zohoarc; b=i5voEX24pGyb3MPWTriPfX7radK5CBZkBFDMJsqpDgXSL8ZAGsf+qQCTJrfGnDHeIkpB8I/7ve0S7pjlzhsKncvgJJLTV5b+Ps2Y/SXp/CoBHl0SpiopZkKlC1Vcf+Hw3U5arJWcPAfcd9cu5MEbZa8CFg0/mIabNOMhLTNtM0I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yhKgrJaomw461n0G8r0qwjF4jfQCq4qrekPPxrMl0oY=; b=K50VoL0XGnWjHINp1/GMgweMk7v3hcTWzlYN9ePN/rOZYoZDHkLL+iMI0QMVl7BzFx dK+YlgZk8Vqcb3oE2WdGh5CiT6Ep809TFJJlXIoGXIA8g3jpXFAFQk9vWL57r2Zw+Fp4 6X9BJA9rKpdO2446fu6E43C1nPRb9OZV2SMnDLe0FO7qnxfmZ72LszJEVRojO4b4bZVM uVGDJScATeE9sfHkxahRBXtIqs/vxfJ5X4YfGEUjc6v+biHvKXAzTAH3uamkxtomdu/n FENOKy+BN/eY58pVgkLmQottUMme4hl3I4hWov7QIYToxuiuuz/+fgsEVQeMV4SZzQLc TrFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yhKgrJaomw461n0G8r0qwjF4jfQCq4qrekPPxrMl0oY=; b=k34xAKkilUpJWfp68W4aC4uIjiAL4gGonibraiqJAHuaKzwmbg46WPZhQlJM8JWeB6 jcUUQhVy4ThZYHq52WXwnIJSEa6SdWph0EroxMCvlxcFgQEypC8Ceku3E7r7vwL+IiDB Xc8WUrS6dc1qYLfr8eSQ8uUjbeoJCIyR10zTervOXXfHollESaYPiBW6AhulkvQem+T1 dZsQjbET2pR9PgM72Sy+tkcEIuiVZ7ae5avJN1hB8BVux+MXGEeS6iVyyjjqxKaLXfmr hcwCkMCPOeUpl0u3FqC8phOturBBazO+pmoxqUDFRgrONbXcxbuPSt7F6OAOFgvSsvI4 w/Og== X-Gm-Message-State: AJIora/7xG6P+bdf7KpTSdbu+qpyOY0IF1y+xMY8G6Roov0nusqkhgO4 wNxw/BI89VS1c6Z5utEy5K0QDYV/V/b9xZQV X-Google-Smtp-Source: AGRyM1sTstBC8t6RD0eWC0dsg6TJAn4UJ0c9MnoszyxbQWxWkh1y+ngalqaOymxFAbzRzNzyAwpIVQ== X-Received: by 2002:a63:f415:0:b0:408:808b:238f with SMTP id g21-20020a63f415000000b00408808b238fmr3660350pgi.469.1657293434384; Fri, 08 Jul 2022 08:17:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 29/45] target/arm: Implement REVD Date: Fri, 8 Jul 2022 20:45:24 +0530 Message-Id: <20220708151540.18136-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657295502036100003 Content-Type: text/plain; charset="utf-8" This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 2 ++ target/arm/sve.decode | 1 + target/arm/sve_helper.c | 16 ++++++++++++++++ target/arm/translate-sve.c | 2 ++ 4 files changed, 21 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index ab0333400f..cc4e1d8948 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -719,6 +719,8 @@ DEF_HELPER_FLAGS_4(sve_revh_d, TCG_CALL_NO_RWG, void, p= tr, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_4(sve_revw_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(sme_revd_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(sve_rbit_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_rbit_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_rbit_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 966803cbb7..a9e48f07b4 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -652,6 +652,7 @@ REVB 00000101 .. 1001 00 100 ... ..... .....= @rd_pg_rn REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn +REVD 00000101 00 1011 10 100 ... ..... ..... @rd_pg_rn_= e0 =20 # SVE vector splice (predicated, destructive) SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index df16170469..d6f7ef94fe 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -931,6 +931,22 @@ DO_ZPZ_D(sve_revh_d, uint64_t, hswap64) =20 DO_ZPZ_D(sve_revw_d, uint64_t, wswap64) =20 +void HELPER(sme_revd_q)(void *vd, void *vn, void *vg, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd, *n =3D vn; + uint8_t *pg =3D vg; + + for (i =3D 0; i < opr_sz; i +=3D 2) { + if (pg[H1(i)] & 1) { + uint64_t n0 =3D n[i + 0]; + uint64_t n1 =3D n[i + 1]; + d[i + 0] =3D n1; + d[i + 1] =3D n0; + } + } +} + DO_ZPZ(sve_rbit_b, uint8_t, H1, revbit8) DO_ZPZ(sve_rbit_h, uint16_t, H1_2, revbit16) DO_ZPZ(sve_rbit_s, uint32_t, H1_4, revbit32) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 24ffb69a2a..9ed3b267fd 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -2901,6 +2901,8 @@ TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh= _fns[a->esz], a, 0) TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz, a->esz =3D=3D 3 ? gen_helper_sve_revw_d : NULL, a, 0) =20 +TRANS_FEAT(REVD, aa64_sme, gen_gvec_ool_arg_zpz, gen_helper_sme_revd_q, a,= 0) + TRANS_FEAT(SPLICE, aa64_sve, gen_gvec_ool_arg_zpzz, gen_helper_sve_splice, a, a->esz) =20 --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657295323; cv=none; d=zohomail.com; s=zohoarc; b=I3D7CRofusJP2hfUvUNvJpoBBBG34Atmqfvq0/ZHoBzgn+HiSFxMmvibXHt0atcAIII65l7x39cslUW0evTpuiAYCy8jjY0G24SWza8gYAnfn1pSPZEE2+vR2eioMQyshsr5W6gMLPEtKV6WXwmhGGSGoNSn0xPONcZD6tNwtIk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657295323; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xDxZQB7t7jC7e11iBt04ewldeYznmzQBar7IyZiGr2c=; b=iiQQMo9KKViVCkuqHaSMxg1d2tYfHx8ByQ9cvVRtBQ4QRUoztZbUt5H3dCteObFEmzST1O3nYG0NhnxNRpLXPfyiOAkGoEOYdOMzhbcoIjGO5Xv2w4/zL+QYBXYmZ2OcMG6Nqxxlx2X/6LNDZ/8g8OE/Ewg8xM20Vk7+ajmPieI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657295323775267.2880546013637; Fri, 8 Jul 2022 08:48:43 -0700 (PDT) Received: from localhost ([::1]:48468 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9qDi-0005xz-JO for importer@patchew.org; Fri, 08 Jul 2022 11:48:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37758) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pjM-0004Lz-Mc for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:20 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:42957) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pjK-0002S4-NX for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:20 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d10so9996391pfd.9 for ; Fri, 08 Jul 2022 08:17:18 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xDxZQB7t7jC7e11iBt04ewldeYznmzQBar7IyZiGr2c=; b=CC/uRJhVs/t+i96t2DEXFbjTKMmlUFMgw5Y1LmAMWxratlU/g+3wvUlL+16E1l93/F Y2XVriwbMRgMsP8Veo6xuVjSGD0Jv1FQJwSQllR37vINjIYJ3CJkF3jBIfEuViXwAiCm zP6/sA72NIFgDNzVV80yFxP1ofPOTMhUcfNTdqP8MAAjG3keaqXTYulmuFCqDKDy5drL L12ISOu+VlXmqyjTjar1kKC40plclRv44Fsc2Zi9L/lZr2cVP6a97Sxp2Rv5J0xxHonX CUfYW1r2f8HDcTYfymFKzpF9ITSJVd7UdzU4b1lIEpITAv4Z1Qgz23kZg+1/LSx2BW1W zWKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xDxZQB7t7jC7e11iBt04ewldeYznmzQBar7IyZiGr2c=; b=bNvJACTuUKLf7WBWsVeO1nzHnAafKmm/a0FPv1MQjqjjKJmMUejarfj1EsL8MnUoLX maQL8Z7H7Wce4rkmzrmFuAAhfkoXDw3hmU1fgT4r/AJ2iUZJlhEw4C73/cA6LsquntUW CpeGMsTzkzCHqQQS56zQQw15rOc3kY8x1mXKfEm8zQjvDW/KRVQQx12is+vHwWOV7iIy gmC7GmUcZyg1MGzIPvpjtv1wOkLqV1+Dta0tKp18ln7fQ0a5LMSW2Sm6L/alwD2+RaHP pTECWfjmA3qu11xhdPFJE6JjhQ8kBIUXMCaGkDKR4mI+WDRAzAgQfX/YRVrjnnAjm0ew iQHw== X-Gm-Message-State: AJIora9zNQhIBPNeYWHuB+v/0buTlfZdAYlq4u45Piixp2X/LjC4rkKp c7mwQEL1xvpI3i7sMbkaB1WW2jKQOr4Gq/b0 X-Google-Smtp-Source: AGRyM1vf5CR9al66ZMRezM3TQxdiBcSsfnqfpemDpWLM3+Xrx4fFWC4x3ot0nPMBolEYT1/hL+bHDw== X-Received: by 2002:a63:e202:0:b0:412:7a7a:53e9 with SMTP id q2-20020a63e202000000b004127a7a53e9mr3753129pgh.624.1657293437321; Fri, 08 Jul 2022 08:17:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 30/45] target/arm: Implement SCLAMP, UCLAMP Date: Fri, 8 Jul 2022 20:45:25 +0530 Message-Id: <20220708151540.18136-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657295325259100001 Content-Type: text/plain; charset="utf-8" This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h | 18 +++++++ target/arm/sve.decode | 5 ++ target/arm/translate-sve.c | 102 +++++++++++++++++++++++++++++++++++++ target/arm/vec_helper.c | 24 +++++++++ 4 files changed, 149 insertions(+) diff --git a/target/arm/helper.h b/target/arm/helper.h index 3a8ce42ab0..92f36d9dbb 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1019,6 +1019,24 @@ DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_uclamp_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a9e48f07b4..14b3a69c36 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1695,3 +1695,8 @@ PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0= .... \ @psel esz=3D2 imm=3D%psel_imm_s PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ @psel esz=3D3 imm=3D%psel_imm_d + +### SVE clamp + +SCLAMP 01000100 .. 0 ..... 110000 ..... ..... @rda_rn_rm +UCLAMP 01000100 .. 0 ..... 110001 ..... ..... @rda_rn_rm diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 9ed3b267fd..41f8b12259 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7478,3 +7478,105 @@ static bool trans_PSEL(DisasContext *s, arg_psel *a) tcg_temp_free_ptr(ptr); return true; } + +static void gen_sclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a) +{ + tcg_gen_smax_i32(d, a, n); + tcg_gen_smin_i32(d, d, m); +} + +static void gen_sclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a) +{ + tcg_gen_smax_i64(d, a, n); + tcg_gen_smin_i64(d, d, m); +} + +static void gen_sclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n, + TCGv_vec m, TCGv_vec a) +{ + tcg_gen_smax_vec(vece, d, a, n); + tcg_gen_smin_vec(vece, d, d, m); +} + +static void gen_sclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m, + uint32_t a, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop[] =3D { + INDEX_op_smin_vec, INDEX_op_smax_vec, 0 + }; + static const GVecGen4 ops[4] =3D { + { .fniv =3D gen_sclamp_vec, + .fno =3D gen_helper_gvec_sclamp_b, + .opt_opc =3D vecop, + .vece =3D MO_8 }, + { .fniv =3D gen_sclamp_vec, + .fno =3D gen_helper_gvec_sclamp_h, + .opt_opc =3D vecop, + .vece =3D MO_16 }, + { .fni4 =3D gen_sclamp_i32, + .fniv =3D gen_sclamp_vec, + .fno =3D gen_helper_gvec_sclamp_s, + .opt_opc =3D vecop, + .vece =3D MO_32 }, + { .fni8 =3D gen_sclamp_i64, + .fniv =3D gen_sclamp_vec, + .fno =3D gen_helper_gvec_sclamp_d, + .opt_opc =3D vecop, + .vece =3D MO_64, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64 } + }; + tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]); +} + +TRANS_FEAT(SCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_sclamp, a) + +static void gen_uclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a) +{ + tcg_gen_umax_i32(d, a, n); + tcg_gen_umin_i32(d, d, m); +} + +static void gen_uclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a) +{ + tcg_gen_umax_i64(d, a, n); + tcg_gen_umin_i64(d, d, m); +} + +static void gen_uclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n, + TCGv_vec m, TCGv_vec a) +{ + tcg_gen_umax_vec(vece, d, a, n); + tcg_gen_umin_vec(vece, d, d, m); +} + +static void gen_uclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m, + uint32_t a, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop[] =3D { + INDEX_op_umin_vec, INDEX_op_umax_vec, 0 + }; + static const GVecGen4 ops[4] =3D { + { .fniv =3D gen_uclamp_vec, + .fno =3D gen_helper_gvec_uclamp_b, + .opt_opc =3D vecop, + .vece =3D MO_8 }, + { .fniv =3D gen_uclamp_vec, + .fno =3D gen_helper_gvec_uclamp_h, + .opt_opc =3D vecop, + .vece =3D MO_16 }, + { .fni4 =3D gen_uclamp_i32, + .fniv =3D gen_uclamp_vec, + .fno =3D gen_helper_gvec_uclamp_s, + .opt_opc =3D vecop, + .vece =3D MO_32 }, + { .fni8 =3D gen_uclamp_i64, + .fniv =3D gen_uclamp_vec, + .fno =3D gen_helper_gvec_uclamp_d, + .opt_opc =3D vecop, + .vece =3D MO_64, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64 } + }; + tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]); +} + +TRANS_FEAT(UCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_uclamp, a) diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 9a9c034e36..f59d3b26ea 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -2690,3 +2690,27 @@ void HELPER(gvec_bfmlal_idx)(void *vd, void *vn, voi= d *vm, } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +#define DO_CLAMP(NAME, TYPE) \ +void HELPER(NAME)(void *d, void *n, void *m, void *a, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc); \ + for (i =3D 0; i < opr_sz; i +=3D sizeof(TYPE)) { = \ + TYPE aa =3D *(TYPE *)(a + i); \ + TYPE nn =3D *(TYPE *)(n + i); \ + TYPE mm =3D *(TYPE *)(m + i); \ + TYPE dd =3D MIN(MAX(aa, nn), mm); \ + *(TYPE *)(d + i) =3D dd; \ + } \ + clear_tail(d, opr_sz, simd_maxsz(desc)); \ +} + +DO_CLAMP(gvec_sclamp_b, int8_t) +DO_CLAMP(gvec_sclamp_h, int16_t) +DO_CLAMP(gvec_sclamp_s, int32_t) +DO_CLAMP(gvec_sclamp_d, int64_t) + +DO_CLAMP(gvec_uclamp_b, uint8_t) +DO_CLAMP(gvec_uclamp_h, uint16_t) +DO_CLAMP(gvec_uclamp_s, uint32_t) +DO_CLAMP(gvec_uclamp_d, uint64_t) --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=84H03quhV23tsQtptgYsSVgdXeP+LjLwInxbgDJtprk=; b=Oz/TiA8MmV3xIdM+MaurNIuOibDIJq9clPQeaz9a71rTsJbLiHTTesr937A8KG/OKV Nc7AD2D/1xFcWsqS3xG/4Xff7gGPFSxtzOsvxXQWaU4GwQjxYnAxnzW48UYddBAQM/+W A+Oxp9TXoxgZS2aNrT7Oq/LDEScveVl22bU2174Du6deXIad4QQI55IAGUxL62IQHMRc 4AIsoY6wWK9LRVjBicR4q+s1z/lhFLqdnybdJPIQ6lhBF+m/7hNF7s/RlSutIKAK9R8n jZoN6ZsWsY4xCelmiehmovy/zEbCubZLVT1Trw7PiDkzjlnlNNzrO9BNR/+luj7PDdBv dapg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=84H03quhV23tsQtptgYsSVgdXeP+LjLwInxbgDJtprk=; b=gty8Bb0jeCkJqDqrRoYWRUtn1bAOm4w+U7hdtt74K9n2dO2K0n2gTbw0vww4QF8133 m1YrzMcieD7FyKM2PSaBH8SSr9eRYGbYMEqSNwWLK5TVIHlcDc8A8oPIXSNCWGeJyptL zwdn0fLMCVQRGQXh+Poyy2w1hQosAvaxHCu3cxMKOjpLMO1wsJUsgT9KYY8fSjfhZOdU OL3wD4/8jKf9XEcAIGq7PlWHlvtyesF3lqOfBQS/Z+I4KbAIopQHoC9lKVD41gcpd3xS vLAubBiRzAOA63IaGt7jdGWxumUBGc3KbONMkBIonnrZ/zKMLfJZ7ErrOK66O9IaQFT2 roCw== X-Gm-Message-State: AJIora9yMoj/Zmvvg8EhTaRTPG77oZcztiZ6a8kqQV1PrliEqyqPgvq2 tPdqcgYK8GJ39l+bBsnE11lkMbPRi/exRvc/ X-Google-Smtp-Source: AGRyM1tW+JCQeVmxtMR+g5U/ubjn/ttP1VlpYNxx3C/mKrRpd5FIO9FYnPrhFt7h0vko/zXYfv1v6A== X-Received: by 2002:a62:a113:0:b0:51c:1b4c:38d1 with SMTP id b19-20020a62a113000000b0051c1b4c38d1mr4453742pff.13.1657293439963; Fri, 08 Jul 2022 08:17:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 31/45] target/arm: Reset streaming sve state on exception boundaries Date: Fri, 8 Jul 2022 20:45:26 +0530 Message-Id: <20220708151540.18136-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657295683736100001 Content-Type: text/plain; charset="utf-8" We can handle both exception entry and exception return by hooking into aarch64_sve_change_el. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 73a5b2b86d..cfcad97ce0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11242,6 +11242,19 @@ void aarch64_sve_change_el(CPUARMState *env, int o= ld_el, return; } =20 + old_a64 =3D old_el ? arm_el_is_aa64(env, old_el) : el0_a64; + new_a64 =3D new_el ? arm_el_is_aa64(env, new_el) : el0_a64; + + /* + * Both AArch64.TakeException and AArch64.ExceptionReturn + * invoke ResetSVEState when taking an exception from, or + * returning to, AArch32 state when PSTATE.SM is enabled. + */ + if (old_a64 !=3D new_a64 && FIELD_EX64(env->svcr, SVCR, SM)) { + arm_reset_sve_state(env); + return; + } + /* * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped * at ELx, or not available because the EL is in AArch32 state, then @@ -11254,10 +11267,8 @@ void aarch64_sve_change_el(CPUARMState *env, int o= ld_el, * we already have the correct register contents when encountering the * vq0->vq0 transition between EL0->EL1. */ - old_a64 =3D old_el ? arm_el_is_aa64(env, old_el) : el0_a64; old_len =3D (old_a64 && !sve_exception_el(env, old_el) ? sve_vqm1_for_el(env, old_el) : 0); - new_a64 =3D new_el ? arm_el_is_aa64(env, new_el) : el0_a64; new_len =3D (new_a64 && !sve_exception_el(env, new_el) ? sve_vqm1_for_el(env, new_el) : 0); =20 --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657295499; cv=none; d=zohomail.com; s=zohoarc; b=bgm6zQpk7ntjbF5LFkgUWmI2GdyTRaJNv5YApab56+RGcJX5hEiXnmROlmMVcuVhVLDzr4clQY1Gf/xtUSv0LQQbT//6Bno5XBJ8soScQItVKfa7kaP30pPSzy2jB7ODpFg35zE5bKzdWoyzgZBbogzUXLbj5+20QSaL7I/4H3A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657295499; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vrb9+6VIoq7Bg5bHZHKrK2kLLIpATDy32zLGrACiZHA=; b=Z8fe2NVUxV+6ShCoUGR43TyvMT+cIITbrfiBT30Bd8kQjpIirMkZ1hFSvPf+ocIRYp0C7N/3W0BgFh+kOFssyE1QOWPg26dt4HrM95t3G+LzuRahUwZbjJJS7qs13k5qRqGY5ieMszqkQ5VIk5ImbB1K3oPKs8iAspVsWXCp8T8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657295499629480.01167558594534; Fri, 8 Jul 2022 08:51:39 -0700 (PDT) Received: from localhost ([::1]:57226 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9qGY-0003Za-47 for importer@patchew.org; Fri, 08 Jul 2022 11:51:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pjS-0004Oc-9H for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:26 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:42957) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pjP-0002S4-Ot for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:25 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d10so9996589pfd.9 for ; Fri, 08 Jul 2022 08:17:23 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vrb9+6VIoq7Bg5bHZHKrK2kLLIpATDy32zLGrACiZHA=; b=JsNuTco92PWee4YPTOxZ0ukqtXHhyzxdktd4+4b/Kd1wSsVzI2bo3/L2cz4Y1l8D5k JG1tRPfWDPYsh7IKTRnXKVADszStX9kZxLyRAfIxT13YmKT3RIwbyDoQ21UXw+VoYDd1 MTLHstHmZrolixbWN1FI114M3lSzZLbYFIKStnfWeFzpQzcSfnXupGHUWn48oTfHvkDV KvUuue/nBQHHXXspVe6hNyy1ty044KC+wCF3iPe4sj56KdUTOOZhe6VCbu7iC+5pYSBC JIDwsRh7RsSgdqph+qudtiN1TgQW7ZQ5AgQiDzyQWVOffDQ+imRE6eAV8uxA9vbRt9b8 23ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vrb9+6VIoq7Bg5bHZHKrK2kLLIpATDy32zLGrACiZHA=; b=EetKJyUP0yYCP4XPMK4IhkgtL9XMFzsAkU/lHtyr5wN0YK3TH/KtsD+rO+Gvc+/dN6 PipyOeagCrrRhN0ndFz3/r/qpD/bDRJyBHgDk5uFkPmRpsuEJLD8Or9vNWTx0lERcMB+ iq2m3HwkwflwVBNXICxiIcBwWIPnwlbYyKzHP5fT3iClwwr6ftNrmnhsHWgZkAXAyFNW khjiqpG6xvDMkuhAeHbanU1uVyy5kKaRgTA0MDrLULr/tH0JEk55d4+nx/z7B8nwvbHQ Pe6IkMolxFPJ4+tfMG8FRaXziHCxOety8wJbuHTmLuOWR6FjL2ZsuTBRyZq7/Ec4YJ0x 9uKg== X-Gm-Message-State: AJIora97xMxGDJbZ/HMr0loBjRpsUE9b+bWk0f+bD+FoNqTiHpkboypr bbKZgmxTSAdzgC7aji/UYYoyTTKGxhF1JbyU X-Google-Smtp-Source: AGRyM1vA0vxevD+ZLRkTxqkGxnBMkDbcLmde48n8iOxBauRr3XWPuhRji4UjYf/i37XTvcLMDOn9DA== X-Received: by 2002:a05:6a00:1688:b0:517:cf7b:9293 with SMTP id k8-20020a056a00168800b00517cf7b9293mr4523126pfc.7.1657293442649; Fri, 08 Jul 2022 08:17:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 32/45] target/arm: Enable SME for -cpu max Date: Fri, 8 Jul 2022 20:45:27 +0530 Message-Id: <20220708151540.18136-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657295500120100001 Content-Type: text/plain; charset="utf-8" Note that SME remains effectively disabled for user-only, because we do not yet set CPACR_EL1.SMEN. This needs to wait until the kernel ABI is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 4 ++++ target/arm/cpu64.c | 11 +++++++++++ 2 files changed, 15 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 83b4410065..8e494c8bea 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -65,6 +65,10 @@ the following architecture extensions: - FEAT_SHA512 (Advanced SIMD SHA512 instructions) - FEAT_SM3 (Advanced SIMD SM3 instructions) - FEAT_SM4 (Advanced SIMD SM4 instructions) +- FEAT_SME (Scalable Matrix Extension) +- FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode) +- FEAT_SME_F64F64 (Double-precision floating-point outer product instructi= ons) +- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instruc= tions) - FEAT_SPECRES (Speculation restriction instructions) - FEAT_SSBS (Speculative Store Bypass Safe) - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index b4fd4b7ec8..78e27f778a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1024,6 +1024,7 @@ static void aarch64_max_initfn(Object *obj) */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ t =3D FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT= _DoubleFault */ + t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr1 =3D t; =20 @@ -1074,6 +1075,16 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 + t =3D cpu->isar.id_aa64smfr0; + t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ + cpu->isar.id_aa64smfr0 =3D t; + /* Replicate the same data to the 32-bit id registers. */ aa32_max_features(cpu); =20 --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657296326; cv=none; d=zohomail.com; s=zohoarc; b=Wthv4wA+NymVe1DZWPz6/ZrjKeCZw3O+FgZzHimitqT5yojbO262liPXgnGGOQajy+glW4pUgGkZ9ph62ga+XyIDU1eR0erpJheZ7xyMXEz7XB1AlAjtLyBLaYHSTkG1Gkmxw2Rf8nvftoegm3bgEBzTnwESCNbBITbikP2SmDo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657296326; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5PME71S11cSPKZ4C3ISqAJ4KA5QkjnbMhk+jE1tP2f8=; b=j0myT/n7yIMLY6mjHWg319mWZIXrWpFn0k51glLZrCCDO7gnOuB72nSLNiSpwxVGddy0L1Rb34p4Pintut4bJkSFzAu//p6j9osbHgnUGKEF9K27uwQqgjkjVkhVkm+Kd4vG/IoJNVIUbiXzWoUcFnbFSvpjIn6Rg95fFfIO1as= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657296326142744.3499812772548; Fri, 8 Jul 2022 09:05:26 -0700 (PDT) Received: from localhost ([::1]:34938 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9qTr-0001VZ-SM for importer@patchew.org; Fri, 08 Jul 2022 12:05:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37900) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pjX-0004Ps-NI for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:40 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:40672) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pjU-0002WJ-0V for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:30 -0400 Received: by mail-pg1-x533.google.com with SMTP id i190so10006052pge.7 for ; Fri, 08 Jul 2022 08:17:26 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657296326711100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/target_cpu.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cp= u.h index 97a477bd3e..f90359faf2 100644 --- a/linux-user/aarch64/target_cpu.h +++ b/linux-user/aarch64/target_cpu.h @@ -34,10 +34,13 @@ static inline void cpu_clone_regs_parent(CPUARMState *e= nv, unsigned flags) =20 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) { - /* Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is + /* + * Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is * different from AArch32 Linux, which uses TPIDRRO. */ env->cp15.tpidr_el[0] =3D newtls; + /* TPIDR2_EL0 is cleared with CLONE_SETTLS. */ + env->cp15.tpidr2_el0 =3D 0; } =20 static inline abi_ulong get_sp_from_cpustate(CPUARMState *state) --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657295998; cv=none; d=zohomail.com; s=zohoarc; b=OZvF6O1QIG7lUA/be5fZDf3EGgfmZS7K1Ud6dgesmDOOwow2XRuwNFam617/sA8Kkw8y4vgTsFD1hEMgFQf8oBeys0YMlcgTX5RVR0Iutz9spbADMD/wnbsJEugeIAgNA09XvXICQaev8R1e5TQ9gAspAOSH7AjQgSAdiF24OCE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QXu/KgUnFX9XdonKOb4RpodqXgfNtkqVhXPaRa0Wz+g=; b=iPqiAvNnaPHiE+AFIGN3QAnhp87OHXfDLk7LAnf0PL92ygxf9A/1QsN8BOPsAA89lw 4tkayynTtTHbSXgy5HFOAqxP+pvV20i6XZ3jd8pMmu/VP1DrdIUsmAbp+9lL4GD8GDyN 9PQcUZzU27o/FB5ctTGsLVVXVRhV5mfb1bMBwXHYsCov9RQnMk4iKojYCq6xAhelh30N H6LF3VNsSokP9E+fxT5jj8O44Ajzp45v1gxk2X1iTqDjwF9PWHqGAkba4s/mH/KY9rak UF2R2/uOAekTQM9WyEYuSIPqcmYpyXNmQP2b3scGTLtW7WMpVvCOoSGW04V+QsCu8lqD w+EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657295999995100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index f7ef36cd9f..9875d609a9 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -89,6 +89,15 @@ void cpu_loop(CPUARMState *env) =20 switch (trapnr) { case EXCP_SWI: + /* + * On syscall, PSTATE.ZA is preserved, along with the ZA matri= x. + * PSTATE.SM is cleared, per SMSTOP, which does ResetSVEState. + */ + if (FIELD_EX64(env->svcr, SVCR, SM)) { + env->svcr =3D FIELD_DP64(env->svcr, SVCR, SM, 0); + arm_rebuild_hflags(env); + arm_reset_sve_state(env); + } ret =3D do_syscall(env, env->xregs[8], env->xregs[0], --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657295829; cv=none; d=zohomail.com; s=zohoarc; b=epaeaj42PBFyy4mTKeyo8Ei0Iw4YtJp3W4JMrSzkTi7wSDZDw492lUlQf9GwNv0QNH5WXcT9uybUlutucEu8GnOYQgw4ABbUG/j//9zePKi7iLNKiKKXgi44Dyh9B0vMDaWRqZFr0RfBZ/gwYmgWFURwD0qnKaf3dYZixPEnOkI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657295829; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ObBO5dq04E0/5WroJlYaFhrT48czebw/dLTC4ZwRUvk=; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ObBO5dq04E0/5WroJlYaFhrT48czebw/dLTC4ZwRUvk=; b=a0gTKm+YDEunXFRMEWfBfGCbrdFz7mYChFjdQiQhBUUeCzicP/Kh9Fr8kP6vrKsmBZ 0SReZTNRmWQFUH8HqteykSr3JcKjJpWo1bCWbrwgdP9K0PgNG3PM3vWr/FJ3jjeNBEW2 nNvdIT1LSVqqKt09HNxAJsAUCmlZK8u6wRVB4spQEzq+Osd0jz/lZZC6OlMATC8h16Oo D0Pb3372TsJCLg14dbAUAwl3grSCJdeG2GN2D0SGg2/deQziiukZt9H4JkjLe6MVcGVx f8M/6BEemEYbqDlqtvj5QM1q0GCkZhmym1wmyXQ2jp5pQ46ufUmDN2jVrvgurzhnA33o MRNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ObBO5dq04E0/5WroJlYaFhrT48czebw/dLTC4ZwRUvk=; b=AXRC3oteSOO7adZBvOhtTrWTvZJflzt/UhMOuEJtEX6T89gUjTp8gweEvVcxyuu2CV P9BLDGKNurujY4dHzDyIrzm30UuxSbjav3I+sjEb0EG6YQXzVfy4r+syC3/2zgxr+WM1 +59kc4eDPz8T7P4LufIxzU1Gp/r+lKHXhkM4m1G+G480eOwHPyPcD57b/Jb78nbIB+6l sF9B342BewfNr4Tl9JYDjibbUilajMKIa33lZ2vjgWaK9YdNFjTFiab8El+w7YRCsx7g XWut5J7u6xOjKTPdz1v9aqwmt2mdIMBS8EwIUxs+Vq25MqnCjsElHvgFMx36qFN0ORvQ nOuw== X-Gm-Message-State: AJIora8JUIy99lUvXqnTMcBJy2qtWticeMtgCglZedLMYoVsXljcEHFG LKJrDfafE9j2hMTYrzwz3HfKNVrvrGPQPtNO X-Google-Smtp-Source: AGRyM1tsXKyhPNB0sAnw7Mv4Gf7owVpUvnxp/IMl4F9BGe4sxsbxRgfTE3hdI1k74fbTTmZnI5IF6g== X-Received: by 2002:a63:1a21:0:b0:412:b103:97a2 with SMTP id a33-20020a631a21000000b00412b10397a2mr3787164pga.12.1657293451081; Fri, 08 Jul 2022 08:17:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 35/45] linux-user/aarch64: Add SM bit to SVE signal context Date: Fri, 8 Jul 2022 20:45:30 +0530 Message-Id: <20220708151540.18136-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657295830823100001 Content-Type: text/plain; charset="utf-8" Make sure to zero the currently reserved fields. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 7da0e36c6d..3cef2f44cf 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -78,7 +78,8 @@ struct target_extra_context { struct target_sve_context { struct target_aarch64_ctx head; uint16_t vl; - uint16_t reserved[3]; + uint16_t flags; + uint16_t reserved[2]; /* The actual SVE data immediately follows. It is laid out * according to TARGET_SVE_SIG_{Z,P}REG_OFFSET, based off of * the original struct pointer. @@ -101,6 +102,8 @@ struct target_sve_context { #define TARGET_SVE_SIG_CONTEXT_SIZE(VQ) \ (TARGET_SVE_SIG_PREG_OFFSET(VQ, 17)) =20 +#define TARGET_SVE_SIG_FLAG_SM 1 + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -177,9 +180,13 @@ static void target_setup_sve_record(struct target_sve_= context *sve, { int i, j; =20 + memset(sve, 0, sizeof(*sve)); __put_user(TARGET_SVE_MAGIC, &sve->head.magic); __put_user(size, &sve->head.size); __put_user(vq * TARGET_SVE_VQ_BYTES, &sve->vl); + if (FIELD_EX64(env->svcr, SVCR, SM)) { + __put_user(TARGET_SVE_SIG_FLAG_SM, &sve->flags); + } =20 /* Note that SVE regs are stored as a byte stream, with each byte elem= ent * at a subsequent address. This corresponds to a little-endian store --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657294278; cv=none; d=zohomail.com; s=zohoarc; b=SwPLArC5H0AFCPettQSdbpHhz8qIewzcyZHOANFODTXdNjSV7KPTXd+lTOGhSVS+nsCxFxaQYKMRjnr0dDDODzlr4lxgxlPzU1K+szl6oRMHPxqugn1oXRrrUqR65pxdQHpLoJCNGl+WvvxTxrwg5d06FXU4lVGfiNSxPV7R0N0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657294278; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=u6i1Exm7OWbV1UGGZQ+hkV1UWXfqGJYzldSUkhdBqXw=; b=jUE+DBIjZWZYLXGeUb6rPVE6bPtm/IzqYe0e3BMHVId/jJD5rGGxrJSomMVjfuCjFcZUx5eVQKBZbWTb7U0jNAfRJv2qCD88tCrbYZ/C/cfZBh9q0+D3a+TM9CTNm97TEkM1TeVskFKUiqMqB6Zr/8SrYpQJY7QNrztbwv1vZSI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657294278697470.5876975508103; Fri, 8 Jul 2022 08:31:18 -0700 (PDT) Received: from localhost ([::1]:33380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9pwr-0007yZ-FK for importer@patchew.org; Fri, 08 Jul 2022 11:31:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37982) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pjd-0004Q8-0k for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:40 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:38908) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pjb-0002ZA-Bb for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:36 -0400 Received: by mail-pg1-x52b.google.com with SMTP id e132so22609902pgc.5 for ; Fri, 08 Jul 2022 08:17:34 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u6i1Exm7OWbV1UGGZQ+hkV1UWXfqGJYzldSUkhdBqXw=; b=rt0nNnyNQ1uHsjGVm3/byx2d9Hw3ePkexkIcAo3cBtU6byzZF2DOOtydSjwAB2W+jo l5BsfDYtCUu9RDBvKYIAonxnwma7OdDnGYbquOCpRCjINpc1qxOGqXT4tWIG5FE+FdTY tH/fPcPisz+BemVMeSpB/DzM1Qec8IsoR+k1b8OHeUiCN6z3BOuAkFwyBei0N4Ul+rHU xG8PzPKfrtK/Bx/17F+kvbZ90YF83DRvPMB6SrNmphuo0R9vCMSeDVw2nbMOqrodPkc/ q9+31FQh7ZGrvCb+/QnqTpH5EpwAWtBvVWfN1j9WGDNZnZoieXzxGDHlrHL6RNT4VWE6 R2tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u6i1Exm7OWbV1UGGZQ+hkV1UWXfqGJYzldSUkhdBqXw=; b=tV9AT4u9QEXJPmhyTP3kKpTmUg1vOJbE4nhFI2dErMPbvhmisTByDdBqZ3W1GGmE/D y/3COrWgamxRlvc3tVpHUIhNK7sfyVJtkY6QT087PNA8PFy53FYqQ+d6/desqbyYOEHL QDDTyeT4ZGOGUe+y5FYzWR7k12C4vXQQ1G6UgAZ7uiJmu6rLUxPsJFOTM06h5t2xo6iU fz7xOfjo3cFANl+7lwLdaFJ/P0N6ulY84n0uqmbUR4XD+3EjHfhAKY8ER18g9VJUrlPt cpt3cvFhup1a+nIuWrXvCpeO6276d1DJH/DVvwRfiQGtHgD+qjuyzZDL9L0X5hPh8p+I nMdQ== X-Gm-Message-State: AJIora8iSh9nKik2TIsDv0SgJlmPMv3XKPjj3WKSrJdxDMESorKGAnGe LfMY1qBkrLUPaVcD3YqX5aNE3qRFD3QZhvni X-Google-Smtp-Source: AGRyM1u08X3BvMl3U3H65HyI0dQHKjq2L+zJCKdhSA40M1que92g7c/CUmsoL4ogodQt3ncdPT3dZQ== X-Received: by 2002:a05:6a00:9a9:b0:505:974f:9fd6 with SMTP id u41-20020a056a0009a900b00505974f9fd6mr4587839pfg.12.1657293454069; Fri, 08 Jul 2022 08:17:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 36/45] linux-user/aarch64: Tidy target_restore_sigframe error return Date: Fri, 8 Jul 2022 20:45:31 +0530 Message-Id: <20220708151540.18136-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657294279038100003 Content-Type: text/plain; charset="utf-8" Fold the return value setting into the goto, so each point of failure need not do both. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 3cef2f44cf..8b352abb97 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -287,7 +287,6 @@ static int target_restore_sigframe(CPUARMState *env, struct target_sve_context *sve =3D NULL; uint64_t extra_datap =3D 0; bool used_extra =3D false; - bool err =3D false; int vq =3D 0, sve_size =3D 0; =20 target_restore_general_frame(env, sf); @@ -301,8 +300,7 @@ static int target_restore_sigframe(CPUARMState *env, switch (magic) { case 0: if (size !=3D 0) { - err =3D true; - goto exit; + goto err; } if (used_extra) { ctx =3D NULL; @@ -314,8 +312,7 @@ static int target_restore_sigframe(CPUARMState *env, =20 case TARGET_FPSIMD_MAGIC: if (fpsimd || size !=3D sizeof(struct target_fpsimd_context)) { - err =3D true; - goto exit; + goto err; } fpsimd =3D (struct target_fpsimd_context *)ctx; break; @@ -329,13 +326,11 @@ static int target_restore_sigframe(CPUARMState *env, break; } } - err =3D true; - goto exit; + goto err; =20 case TARGET_EXTRA_MAGIC: if (extra || size !=3D sizeof(struct target_extra_context)) { - err =3D true; - goto exit; + goto err; } __get_user(extra_datap, &((struct target_extra_context *)ctx)->datap); @@ -348,8 +343,7 @@ static int target_restore_sigframe(CPUARMState *env, /* Unknown record -- we certainly didn't generate it. * Did we in fact get out of sync? */ - err =3D true; - goto exit; + goto err; } ctx =3D (void *)ctx + size; } @@ -358,17 +352,19 @@ static int target_restore_sigframe(CPUARMState *env, if (fpsimd) { target_restore_fpsimd_record(env, fpsimd); } else { - err =3D true; + goto err; } =20 /* SVE data, if present, overwrites FPSIMD data. */ if (sve) { target_restore_sve_record(env, sve, vq); } - - exit: unlock_user(extra, extra_datap, 0); - return err; + return 0; + + err: + unlock_user(extra, extra_datap, 0); + return 1; } =20 static abi_ulong get_sigframe(struct target_sigaction *ka, --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657295656; cv=none; d=zohomail.com; s=zohoarc; b=URUHiTH+T/OBLcFYFUfiiahNcgII06Bp69k/xW6X8q4UBOWo9DTulHU3aQoZmlu9eHNxvt/shhs6uR03owD3Z0W0W/My3qNnTOZwy9ITAUoGHytvaMlSxzl612xKJ1Et91HHCOkHASFbQPogsTNRRfTavmN793r5bmJ+t8rXD6U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657295656; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=f5ee/kpTJRv70/KN+irqbHOKZ1TmVta3xQPxo1FwOpU=; b=LSa5iU+ENGqE3xOyvoEnec0jr9rRrl+fhmnR4xhEEYzl+dSc09yQfc40cTZfFsd6rr6WRG2mBUxhjp7mg3OQN2xvr+bL1UCslCrwbOP1zU3TkfPMc92QoTkGJ6XlaASqFR5S2yyyd2bHfBoUNQ0gUyAoqZwLJoDLFg/4R46WFiM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657295656418506.6292889252145; Fri, 8 Jul 2022 08:54:16 -0700 (PDT) Received: from localhost ([::1]:37554 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9qJ5-0000rW-5H for importer@patchew.org; Fri, 08 Jul 2022 11:54:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38016) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pjf-0004QE-JT for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:40 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:40672) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pje-0002WJ-73 for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:39 -0400 Received: by mail-pg1-x533.google.com with SMTP id i190so10006478pge.7 for ; Fri, 08 Jul 2022 08:17:37 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f5ee/kpTJRv70/KN+irqbHOKZ1TmVta3xQPxo1FwOpU=; b=m8lc/pwbr7mOPs+Mt8Ipy+vH/nDdM+Nqn1gbwlAUSUBI6tZAAXjkjlgKDBB6vq0lTg /JprRslQkO5G4EufQ5oGWEPQqZT2u/09UPtj4AG+/RJyYHLAhXgVO/YGiFy+EHYgpy34 7fWedvVT0sBScEMW+LttyKyRtKi3a6xRx7nbJkDDO1ufBoIk9w8lsKsRNAzbRqz+Rsz4 JdPIQUhJcQEo/goTJukhEldVy+iBVYc0TWXHr/818dqiSvs9OIiYWmpE0n7ATNoyONRD Nupm6pM8EzbH/4hqNqpa0IsnP+6IU3jifpFXfcZxppcae8PtoCMcKP5JD1lO/SKfl8Ku o1kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f5ee/kpTJRv70/KN+irqbHOKZ1TmVta3xQPxo1FwOpU=; b=VjHtBe+yc6Gdj3D4auEx1aZxGsvmELY87xCiK8pMtl3eNBPKcUqN+mXI03ahtdPPIV IqVcUqlcFGin9/Mh8uhbLTysQDNyzBv3nw4RR34gucMHShWn10sr2SGxZ76bt9Vmt0AY G1EX5mDXeSoaH4DalhP9/vor8SsYHPuvw9xQNu1BtjzQY3K85lsZC9lei6JP75mbV6WS RPT7f5LmGYMIAlqUcNnB92cyjJ1miRmuzBJhiEuffKbpl2iVnHpesIkOc7oe5v0+/VwG +BvPP1pT4Gu7pUy4nJw1uRBL/16wibtqEqJyhGmYs7oOKF8TwSYEUrtrqmcHOYInQQzh LTXA== X-Gm-Message-State: AJIora9mT5mpqhNqcrFaRDjX+H4G7cZtOrvJDXlFTAQrlZLYJvq+uRxV qxMDV7CRUNVA2tENtmJOC+y/wvyp8DBoGpsi X-Google-Smtp-Source: AGRyM1vCplbx/74qdRssZw4kFtrShEoJnmayLsaSs4RHUtx5VAxdrLo06nmgc8dtYuBtfJwhAcH/vQ== X-Received: by 2002:a05:6a00:2188:b0:50c:ef4d:ef3b with SMTP id h8-20020a056a00218800b0050cef4def3bmr4224400pfi.83.1657293456949; Fri, 08 Jul 2022 08:17:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 37/45] linux-user/aarch64: Do not allow duplicate or short sve records Date: Fri, 8 Jul 2022 20:45:32 +0530 Message-Id: <20220708151540.18136-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657295657130100001 Content-Type: text/plain; charset="utf-8" In parse_user_sigframe, the kernel rejects duplicate sve records, or records that are smaller than the header. We were silently allowing these cases to pass, dropping the record. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 8b352abb97..8fbe98d72f 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -318,10 +318,13 @@ static int target_restore_sigframe(CPUARMState *env, break; =20 case TARGET_SVE_MAGIC: + if (sve || size < sizeof(struct target_sve_context)) { + goto err; + } if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { vq =3D sve_vq(env); sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq)= , 16); - if (!sve && size =3D=3D sve_size) { + if (size =3D=3D sve_size) { sve =3D (struct target_sve_context *)ctx; break; } --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657294952; cv=none; d=zohomail.com; s=zohoarc; b=mL0wg489f+hJweKZrCwjN8ViZ2fPu1zXIvqutHa7SmgX7m1ZB0bt2qGv18fUHnbybm5rwp3V29vyJUPsLUAfHUcWOlxlfSkCthLkrzFzcc5EfrXCfn9v8aS2kSLiuQ2DXYxEZTjQSm/2KNlkMg9kfPlZV7YXXpJcedCsjHRAAkI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657294952; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7xmxavNGvmm3BzQ45g11tA0Bzd0iytuo9+dpLfOmZxs=; b=G09IIS7TYDIa5Bn7LrLO8jkFgnGKmLx42PevLxgQUIM34Uswp5dEIjY9R7Lj8wycxRkr2gYfmv7nQhrqippecIk/PqORtZQRIimWaZcJryjQZkeNPdgG4REBKSs3vYavusLyZP+Yz4q8R3FpkTzaPj49DjmGM6Igfe2FrDoTd3c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657294952598971.8396746360075; Fri, 8 Jul 2022 08:42:32 -0700 (PDT) Received: from localhost ([::1]:59848 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9q7j-0001sL-Fb for importer@patchew.org; Fri, 08 Jul 2022 11:42:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38048) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pji-0004Qp-6c for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:43 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:44605) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pjg-0002TY-O5 for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:41 -0400 Received: by mail-pg1-x52f.google.com with SMTP id bf13so9557417pgb.11 for ; Fri, 08 Jul 2022 08:17:40 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657294953586100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 8fbe98d72f..9ff79da4be 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -340,6 +340,9 @@ static int target_restore_sigframe(CPUARMState *env, __get_user(extra_size, &((struct target_extra_context *)ctx)->size); extra =3D lock_user(VERIFY_READ, extra_datap, extra_size, 0); + if (!extra) { + return 1; + } break; =20 default: --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657295190; cv=none; d=zohomail.com; s=zohoarc; b=Z51S+2/9bXjWpXlDUVbkwGtyWDxGlulffT6BvW8mLrzbUjwjBqX/dkCd0AM/7fcIWtG6eIGE8kFP1kyZlHLqWN5FLz/MM1ZpdcaQFQt2FT4rREqgFCrj22tgDIu1/1KNec66s1CLi22IYhuTtyqvDwbY/E+tr3Zd7GbjbzxX6po= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657295190; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=suiCkAICShG42hE+LmFGlXABJkWbjcp+Qv1m7n85pMU=; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=suiCkAICShG42hE+LmFGlXABJkWbjcp+Qv1m7n85pMU=; b=n4Mt5u75pC0Eo/kXJNeBm3RulDjKnIAA4EAeCt4a+vPQqhIT5B2PUUIyyJYTIQMDil FycSTq79D+fxohvetFvF5CZrheSC2A7sxk7ggWQ2aCe79CbOZjo4u2CvUVnmmXhF+2J1 v+N2qCFTLKR/uqkJ+85HWxvsCPkWFCl9Hs9frajvG56lEInA8iC+RpNqXhpM/t2R0BIn doG9oVCr5QIeR5fdzlUSwsY4sgBv2DuhpZG+MFNkpAA9sXUuYwaLvipC+7qNd/bNMJ7m Hbu8RWCmXRqLy0c8BYE1ciLWHymZvnhL2Te1buH/PSjGGdazOPspEDkTmpjYeWs/ykM9 4Ipg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=suiCkAICShG42hE+LmFGlXABJkWbjcp+Qv1m7n85pMU=; b=s0Jt0A4vb7we/r0KSjFDpIhqukLiyMbcN8gxKVRF+6jUouFvHShaK3eAqlORO3ikk2 Sar1SWK0vNH5ThvhfHpzjNcxQLnSqFPTRDjv2NE8h6GDHtCE+XMFY1loyznqRKLPYpYK ndX5DzQ2DLkRXZ+9EAfhW2iVpoo7hHNHmtIbXQmhU7inSAX/kVfgcKCZaz+/A8OLcaJt lL24Qvdbg8ZYMwJlaPfJ+WKhWtWcSARD65A5iWQVD6XCiKH4TCbh9COUqSGYiPJx4AJy BltOA2ffdFhXygq36ji8nXtMuZ+iIjnC0syuKuoAhtcdlrZdbYsHE9XbZtOvYQAqA+3+ ypkw== X-Gm-Message-State: AJIora+sXZKN8EvjVwsRYyhHGxTrlrG/gChIO+2qDndw/8H6oEGbhnmW 2UX2MRoa08LdenMU1Ug2xLDgHmv+9akLoNsZ X-Google-Smtp-Source: AGRyM1vW7xcR1vKzOGDQEvXj9CLqJjf2Lcaa9+pIQpRZHosHBCJEB7v1NKYU/xgxqgymj7RBKoGpsw== X-Received: by 2002:aa7:8e45:0:b0:528:9e96:744b with SMTP id d5-20020aa78e45000000b005289e96744bmr4296473pfr.19.1657293462788; Fri, 08 Jul 2022 08:17:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 39/45] linux-user/aarch64: Move sve record checks into restore Date: Fri, 8 Jul 2022 20:45:34 +0530 Message-Id: <20220708151540.18136-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657295192566100001 Content-Type: text/plain; charset="utf-8" Move the checks out of the parsing loop and into the restore function. This more closely mirrors the code structure in the kernel, and is slightly clearer. Reject rather than silently skip incorrect VL and SVE record sizes, bringing our checks in to line with those the kernel does. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 51 +++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 16 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 9ff79da4be..22d0b8b4ec 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -250,12 +250,36 @@ static void target_restore_fpsimd_record(CPUARMState = *env, } } =20 -static void target_restore_sve_record(CPUARMState *env, - struct target_sve_context *sve, int = vq) +static bool target_restore_sve_record(CPUARMState *env, + struct target_sve_context *sve, + int size) { - int i, j; + int i, j, vl, vq; =20 - /* Note that SVE regs are stored as a byte stream, with each byte elem= ent + if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) { + return false; + } + + __get_user(vl, &sve->vl); + vq =3D sve_vq(env); + + /* Reject mismatched VL. */ + if (vl !=3D vq * TARGET_SVE_VQ_BYTES) { + return false; + } + + /* Accept empty record -- used to clear PSTATE.SM. */ + if (size <=3D sizeof(*sve)) { + return true; + } + + /* Reject non-empty but incomplete record. */ + if (size < TARGET_SVE_SIG_CONTEXT_SIZE(vq)) { + return false; + } + + /* + * Note that SVE regs are stored as a byte stream, with each byte elem= ent * at a subsequent address. This corresponds to a little-endian load * of our 64-bit hunks. */ @@ -277,6 +301,7 @@ static void target_restore_sve_record(CPUARMState *env, } } } + return true; } =20 static int target_restore_sigframe(CPUARMState *env, @@ -287,7 +312,7 @@ static int target_restore_sigframe(CPUARMState *env, struct target_sve_context *sve =3D NULL; uint64_t extra_datap =3D 0; bool used_extra =3D false; - int vq =3D 0, sve_size =3D 0; + int sve_size =3D 0; =20 target_restore_general_frame(env, sf); =20 @@ -321,15 +346,9 @@ static int target_restore_sigframe(CPUARMState *env, if (sve || size < sizeof(struct target_sve_context)) { goto err; } - if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { - vq =3D sve_vq(env); - sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq)= , 16); - if (size =3D=3D sve_size) { - sve =3D (struct target_sve_context *)ctx; - break; - } - } - goto err; + sve =3D (struct target_sve_context *)ctx; + sve_size =3D size; + break; =20 case TARGET_EXTRA_MAGIC: if (extra || size !=3D sizeof(struct target_extra_context)) { @@ -362,8 +381,8 @@ static int target_restore_sigframe(CPUARMState *env, } =20 /* SVE data, if present, overwrites FPSIMD data. */ - if (sve) { - target_restore_sve_record(env, sve, vq); + if (sve && !target_restore_sve_record(env, sve, sve_size)) { + goto err; } unlock_user(extra, extra_datap, 0); return 0; --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657295573; cv=none; d=zohomail.com; s=zohoarc; b=GZXvAqpmw+qCVvNd0sEaIcagnt4hLK7VM1NYQqr1csYMqP6eGmc2NsvyZESyBkt+VnkcAWnfvJF4iGwp4a/5Gn9wY/MBVJlDjsal8pYgI+kwk+jzbx/V2JAfU/1bKqCPWdUmyLQYPUMVh4CFlP6bazRM53keqKgmzPwsAgZ8FI4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657295573; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eZwyJS+DI6VXP8TVU6OuO37fm60h5FhLdjsLlNVqKXk=; b=erdyV2vsRLEC8fDDNxq3f9jXTBYFsZDpfbFd5nJ3M538bo1wC0QRZMYF2XMj2tgmGlvhFJ0aBMJLjwRqQ6hjAGFcyUIQ/oysjyeJJd/anOlXri3H+IKxrB5FrnyC/QCAJeFaKRx3Q45tBmqBu3mxG2GVojvx0YvJsjW2JeIDSbI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657295573206750.7703305200063; Fri, 8 Jul 2022 08:52:53 -0700 (PDT) Received: from localhost ([::1]:60704 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9qHj-0005s1-93 for importer@patchew.org; Fri, 08 Jul 2022 11:52:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38870) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pmo-0003Eq-Hz for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:20:54 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:35557) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pmm-0003EB-JK for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:20:54 -0400 Received: by mail-pf1-x431.google.com with SMTP id x184so10404291pfx.2 for ; Fri, 08 Jul 2022 08:20:52 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id cp2-20020a170902e78200b0015e8d4eb1d7sm30067741plb.33.2022.07.08.08.20.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:20:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eZwyJS+DI6VXP8TVU6OuO37fm60h5FhLdjsLlNVqKXk=; b=l0eUZFbwuXNFm8Z28qebRMsopGHJpOh4hwAKUJa9xlE4rhkqlSo146+GlWLg326yCB mMb1a5MV5kfzNGHAPiVdRP0MCGiOGkFU06+rLSlONe5uySBVUDvrzbfMTTTcGCffrDbi PFo05DkdAEeinAsA2yQ3rdu67oQGnyhQvUoTlRxYB1mfBCzH8fzknvIq7JN4RMXCQpxJ 5vfayod/aZ625R7EGbquTsh25Zh6V0YClCPFOQ8gJIM+5jaHzUg6vrZ5SjgV5R1tnqMl rSh3swG6mnMh+tf/PPmyU7PUx2pHe/7Jtnuzq+xyvN8GT42+WXU+QjpfVWT+KjrEOxHn eB2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eZwyJS+DI6VXP8TVU6OuO37fm60h5FhLdjsLlNVqKXk=; b=tWm2e/+ZfRO83RW8DhVU+C+UutAs4mnHFgFwJynwpI52BPsYgtEtpspxbPJwXAF1HX RI5YckV+TmFP9OZPZggqIJV09cj4mzMUkO+VLb1Xi1FHedVaoZW9SGfIAyMDGoJmejVr hCX5lIeqcBCDYIgrQKtYOlY/1UjIpagzwoLl2U8P/zfJMdNsvcEjE1pWwUpmwabUX8Ik vZL8rAuXV9J97YcvsAOSL2DzW91AKujDPM1ETOQxVdh32lAKA5pLRNxPpkLjtZ382ffk 8rhDyPd4RU0t9LknY0jTC+1bxVgQ8zWaNd4nvPZSJTXjjqjJDGtuQzSjKpJGP4TSZ39P FKoA== X-Gm-Message-State: AJIora97IJX9nwO25iVyh1N4Xqmx5zb4BJbvGeUYHM8I8SF+VXoTfkZg 3YeKP6Y/aMl7N6Oha5tBunWUY587l+19uoe5 X-Google-Smtp-Source: AGRyM1truwjbjKwbcSGpjEJMFqe5Zd/Cgn6/pv9D0mmsbUhpRkIeJJNOBJxcrHLdtpyodEqsAmbIuA== X-Received: by 2002:a63:8649:0:b0:415:c328:4dff with SMTP id x70-20020a638649000000b00415c3284dffmr1053576pgd.430.1657293650994; Fri, 08 Jul 2022 08:20:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 40/45] linux-user/aarch64: Implement SME signal handling Date: Fri, 8 Jul 2022 20:45:35 +0530 Message-Id: <20220708151540.18136-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657295574423100001 Content-Type: text/plain; charset="utf-8" Set the SM bit in the SVE record on signal delivery, create the ZA record. Restore SM and ZA state according to the records present on return. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 167 +++++++++++++++++++++++++++++++++--- 1 file changed, 154 insertions(+), 13 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 22d0b8b4ec..6a2c6e06d2 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -104,6 +104,22 @@ struct target_sve_context { =20 #define TARGET_SVE_SIG_FLAG_SM 1 =20 +#define TARGET_ZA_MAGIC 0x54366345 + +struct target_za_context { + struct target_aarch64_ctx head; + uint16_t vl; + uint16_t reserved[3]; + /* The actual ZA data immediately follows. */ +}; + +#define TARGET_ZA_SIG_REGS_OFFSET \ + QEMU_ALIGN_UP(sizeof(struct target_za_context), TARGET_SVE_VQ_BYTES) +#define TARGET_ZA_SIG_ZAV_OFFSET(VQ, N) \ + (TARGET_ZA_SIG_REGS_OFFSET + (VQ) * TARGET_SVE_VQ_BYTES * (N)) +#define TARGET_ZA_SIG_CONTEXT_SIZE(VQ) \ + TARGET_ZA_SIG_ZAV_OFFSET(VQ, VQ * TARGET_SVE_VQ_BYTES) + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -176,9 +192,9 @@ static void target_setup_end_record(struct target_aarch= 64_ctx *end) } =20 static void target_setup_sve_record(struct target_sve_context *sve, - CPUARMState *env, int vq, int size) + CPUARMState *env, int size) { - int i, j; + int i, j, vq =3D sve_vq(env); =20 memset(sve, 0, sizeof(*sve)); __put_user(TARGET_SVE_MAGIC, &sve->head.magic); @@ -207,6 +223,35 @@ static void target_setup_sve_record(struct target_sve_= context *sve, } } =20 +static void target_setup_za_record(struct target_za_context *za, + CPUARMState *env, int size) +{ + int vq =3D sme_vq(env); + int vl =3D vq * TARGET_SVE_VQ_BYTES; + int i, j; + + memset(za, 0, sizeof(*za)); + __put_user(TARGET_ZA_MAGIC, &za->head.magic); + __put_user(size, &za->head.size); + __put_user(vl, &za->vl); + + if (size =3D=3D TARGET_ZA_SIG_CONTEXT_SIZE(0)) { + return; + } + assert(size =3D=3D TARGET_ZA_SIG_CONTEXT_SIZE(vq)); + + /* + * Note that ZA vectors are stored as a byte stream, + * with each byte element at a subsequent address. + */ + for (i =3D 0; i < vl; ++i) { + uint64_t *z =3D (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i); + for (j =3D 0; j < vq * 2; ++j) { + __put_user_e(env->zarray[i].d[j], z + j, le); + } + } +} + static void target_restore_general_frame(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -252,16 +297,28 @@ static void target_restore_fpsimd_record(CPUARMState = *env, =20 static bool target_restore_sve_record(CPUARMState *env, struct target_sve_context *sve, - int size) + int size, int *svcr) { - int i, j, vl, vq; + int i, j, vl, vq, flags; + bool sm; =20 - if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) { + __get_user(vl, &sve->vl); + __get_user(flags, &sve->flags); + + sm =3D flags & TARGET_SVE_SIG_FLAG_SM; + + /* The cpu must support Streaming or Non-streaming SVE. */ + if (sm + ? !cpu_isar_feature(aa64_sme, env_archcpu(env)) + : !cpu_isar_feature(aa64_sve, env_archcpu(env))) { return false; } =20 - __get_user(vl, &sve->vl); - vq =3D sve_vq(env); + /* + * Note that we cannot use sve_vq() because that depends on the + * current setting of PSTATE.SM, not the state to be restored. + */ + vq =3D sve_vqm1_for_el_sm(env, 0, sm) + 1; =20 /* Reject mismatched VL. */ if (vl !=3D vq * TARGET_SVE_VQ_BYTES) { @@ -278,6 +335,8 @@ static bool target_restore_sve_record(CPUARMState *env, return false; } =20 + *svcr =3D FIELD_DP64(*svcr, SVCR, SM, sm); + /* * Note that SVE regs are stored as a byte stream, with each byte elem= ent * at a subsequent address. This corresponds to a little-endian load @@ -304,15 +363,57 @@ static bool target_restore_sve_record(CPUARMState *en= v, return true; } =20 +static bool target_restore_za_record(CPUARMState *env, + struct target_za_context *za, + int size, int *svcr) +{ + int i, j, vl, vq; + + if (!cpu_isar_feature(aa64_sme, env_archcpu(env))) { + return false; + } + + __get_user(vl, &za->vl); + vq =3D sme_vq(env); + + /* Reject mismatched VL. */ + if (vl !=3D vq * TARGET_SVE_VQ_BYTES) { + return false; + } + + /* Accept empty record -- used to clear PSTATE.ZA. */ + if (size <=3D TARGET_ZA_SIG_CONTEXT_SIZE(0)) { + return true; + } + + /* Reject non-empty but incomplete record. */ + if (size < TARGET_ZA_SIG_CONTEXT_SIZE(vq)) { + return false; + } + + *svcr =3D FIELD_DP64(*svcr, SVCR, ZA, 1); + + for (i =3D 0; i < vl; ++i) { + uint64_t *z =3D (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i); + for (j =3D 0; j < vq * 2; ++j) { + __get_user_e(env->zarray[i].d[j], z + j, le); + } + } + return true; +} + static int target_restore_sigframe(CPUARMState *env, struct target_rt_sigframe *sf) { struct target_aarch64_ctx *ctx, *extra =3D NULL; struct target_fpsimd_context *fpsimd =3D NULL; struct target_sve_context *sve =3D NULL; + struct target_za_context *za =3D NULL; uint64_t extra_datap =3D 0; bool used_extra =3D false; int sve_size =3D 0; + int za_size =3D 0; + int svcr =3D 0; =20 target_restore_general_frame(env, sf); =20 @@ -350,6 +451,14 @@ static int target_restore_sigframe(CPUARMState *env, sve_size =3D size; break; =20 + case TARGET_ZA_MAGIC: + if (za || size < sizeof(struct target_za_context)) { + goto err; + } + za =3D (struct target_za_context *)ctx; + za_size =3D size; + break; + case TARGET_EXTRA_MAGIC: if (extra || size !=3D sizeof(struct target_extra_context)) { goto err; @@ -381,9 +490,16 @@ static int target_restore_sigframe(CPUARMState *env, } =20 /* SVE data, if present, overwrites FPSIMD data. */ - if (sve && !target_restore_sve_record(env, sve, sve_size)) { + if (sve && !target_restore_sve_record(env, sve, sve_size, &svcr)) { goto err; } + if (za && !target_restore_za_record(env, za, za_size, &svcr)) { + goto err; + } + if (env->svcr !=3D svcr) { + env->svcr =3D svcr; + arm_rebuild_hflags(env); + } unlock_user(extra, extra_datap, 0); return 0; =20 @@ -451,7 +567,8 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, .total_size =3D offsetof(struct target_rt_sigframe, uc.tuc_mcontext.__reserved), }; - int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, vq =3D 0, sve_size =3D 0; + int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, za_ofs =3D 0; + int sve_size =3D 0, za_size =3D 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; abi_ulong frame_addr, return_addr; @@ -461,11 +578,20 @@ static void target_setup_frame(int usig, struct targe= t_sigaction *ka, &layout); =20 /* SVE state needs saving only if it exists. */ - if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { - vq =3D sve_vq(env); - sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); + if (cpu_isar_feature(aa64_sve, env_archcpu(env)) || + cpu_isar_feature(aa64_sme, env_archcpu(env))) { + sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(sve_vq(env)= ), 16); sve_ofs =3D alloc_sigframe_space(sve_size, &layout); } + if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { + /* ZA state needs saving only if it is enabled. */ + if (FIELD_EX64(env->svcr, SVCR, ZA)) { + za_size =3D TARGET_ZA_SIG_CONTEXT_SIZE(sme_vq(env)); + } else { + za_size =3D TARGET_ZA_SIG_CONTEXT_SIZE(0); + } + za_ofs =3D alloc_sigframe_space(za_size, &layout); + } =20 if (layout.extra_ofs) { /* Reserve space for the extra end marker. The standard end marker @@ -512,7 +638,10 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, target_setup_end_record((void *)frame + layout.extra_end_ofs); } if (sve_ofs) { - target_setup_sve_record((void *)frame + sve_ofs, env, vq, sve_size= ); + target_setup_sve_record((void *)frame + sve_ofs, env, sve_size); + } + if (za_ofs) { + target_setup_za_record((void *)frame + za_ofs, env, za_size); } =20 /* Set up the stack frame for unwinding. */ @@ -536,6 +665,18 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, env->btype =3D 2; } =20 + /* + * Invoke the signal handler with both SM and ZA disabled. + * When clearing SM, ResetSVEState, per SMSTOP. + */ + if (FIELD_EX64(env->svcr, SVCR, SM)) { + arm_reset_sve_state(env); + } + if (env->svcr) { + env->svcr =3D 0; + arm_rebuild_hflags(env); + } + if (info) { tswap_siginfo(&frame->info, info); env->xregs[1] =3D frame_addr + offsetof(struct target_rt_sigframe,= info); --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657296577; cv=none; d=zohomail.com; s=zohoarc; b=ViKv1WbZIPdCdFXfgXqP9f22nRGqjvj3hf1QdLC5+4T9Q82tXNkgOV5YfbOoTWPRnIj8/R6X3ash1Q5paptI17XX4ZYKts7gRmNJfJzlZHZzZf5Kk9uTHm8MGpDn0R2A5CbswQlIVE4Prh0RVEdc2ZHbUJXyKWlCbKwbacY4Sxs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657296577; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=V2fLCOd7w5RVaZMEE/2yClzk5I5RfuvEjcRKKU0Ql6A=; b=V9I1b+vNy+p7hoIgbYHipcTZbLU3oaZDX4PP9KWP3YCq3uAaj8/9mY3rqvx+0wTwV0wLvyo6zhfDpSk6dgIkaQ+mYbKrEu0wKU+RXKeEIUZ4okZN1g3xxc7JiDqNUaPFQ2wi/qrLWdVGaUFKptoI+MSnOoxDesmaWeSOPehURgc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657296577908927.443568772282; Fri, 8 Jul 2022 09:09:37 -0700 (PDT) Received: from localhost ([::1]:43418 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9qXw-0007QX-RV for importer@patchew.org; Fri, 08 Jul 2022 12:09:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38904) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pmq-0003Mv-Ns for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:20:56 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:46025) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pmp-0003F5-1p for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:20:56 -0400 Received: by mail-pg1-x52d.google.com with SMTP id 145so22594005pga.12 for ; Fri, 08 Jul 2022 08:20:54 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id cp2-20020a170902e78200b0015e8d4eb1d7sm30067741plb.33.2022.07.08.08.20.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:20:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V2fLCOd7w5RVaZMEE/2yClzk5I5RfuvEjcRKKU0Ql6A=; b=dytHw4yHn9aQZiiETbPqvNBq7y0fHoTgmVXEA9wNgNhw7/wa5b4S8S/vO4hv11wdi3 8TxSlDY2MXKDKNSxyaYf7jMszGmUVtU3zmM9NXy4Sz+s2ym9yfJli7Kdt5ciRFkeC1Bi Tx8dA+9YaZTTxVaS3riauBtUxI4mSVh1oZaniW4renTeJn0vcFTCy/d9ceezLUIoCVIz WYzAq9v7U0upxK5f2an5o3P+PiLg1Ll/S72XwcyB+ZWcbQUEUd557+GuWen1zCVHqt/W RAhNMNk0TpAqdQGEE3uVxh1tzVuUXiLzkeSnDqrcMyePuIJTWcy4DtacOxQJeIyqjw// 3ISg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V2fLCOd7w5RVaZMEE/2yClzk5I5RfuvEjcRKKU0Ql6A=; b=a2h7PZ2paT+30inD305BbI/QH1NS59tx8MCkSVWrH+aesDsF9viOU8YaObn2+Phccd fzRX0IpwokFr3p+o32FegtTH86Pei5RZym0ytGWU1CeSOuLNeZSHRXa8HuBKnEJQymJf 8GaSYs8WZTfTDCcw8XETE43z30U6nyai/RCsAqRnnAvSmuoPZk27m6tM1cl4LKIEBjP8 KfL3Fkr7MXgduy/i4TtKDtc/cPCFPPMld413uKpdIb6uEtEEGebq6o9BpS5v6mkHf4yI 52rqGT0LHc2W4OgCynyIxkgEbTgd4YaVdI4VKgHj2epHcOE5bYDvUQ2RNnk/aNYjhpjy 69nQ== X-Gm-Message-State: AJIora8E1Nu9/HAQQao1my568xL1VwP3Oly9Onri4VqMRtBEnrePcqhH Uj39/vfGpa994ne3sEF8pBgLfbExcOyRlEq0 X-Google-Smtp-Source: AGRyM1vhWvWAoq3Pn2YIBCjUc6kze1JMVknL/i6c8RjTWxQvqey4vNkvdMYxXSCicTo8tfV4we4UXA== X-Received: by 2002:a63:460f:0:b0:412:7a8b:128c with SMTP id t15-20020a63460f000000b004127a8b128cmr3968354pga.270.1657293653809; Fri, 08 Jul 2022 08:20:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 41/45] linux-user: Rename sve prctls Date: Fri, 8 Jul 2022 20:45:36 +0530 Message-Id: <20220708151540.18136-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657296578745100001 Content-Type: text/plain; charset="utf-8" Add "sve" to the sve prctl functions, to distinguish them from the coming "sme" prctls with similar names. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 8 ++++---- linux-user/syscall.c | 12 ++++++------ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_= prctl.h index 1d440ffbea..40481e6663 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -6,7 +6,7 @@ #ifndef AARCH64_TARGET_PRCTL_H #define AARCH64_TARGET_PRCTL_H =20 -static abi_long do_prctl_get_vl(CPUArchState *env) +static abi_long do_prctl_sve_get_vl(CPUArchState *env) { ARMCPU *cpu =3D env_archcpu(env); if (cpu_isar_feature(aa64_sve, cpu)) { @@ -14,9 +14,9 @@ static abi_long do_prctl_get_vl(CPUArchState *env) } return -TARGET_EINVAL; } -#define do_prctl_get_vl do_prctl_get_vl +#define do_prctl_sve_get_vl do_prctl_sve_get_vl =20 -static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2) +static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2) { /* * We cannot support either PR_SVE_SET_VL_ONEXEC or PR_SVE_VL_INHERIT. @@ -47,7 +47,7 @@ static abi_long do_prctl_set_vl(CPUArchState *env, abi_lo= ng arg2) } return -TARGET_EINVAL; } -#define do_prctl_set_vl do_prctl_set_vl +#define do_prctl_sve_set_vl do_prctl_sve_set_vl =20 static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) { diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 669add74c1..cbde82c907 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6362,11 +6362,11 @@ static abi_long do_prctl_inval1(CPUArchState *env, = abi_long arg2) #ifndef do_prctl_set_fp_mode #define do_prctl_set_fp_mode do_prctl_inval1 #endif -#ifndef do_prctl_get_vl -#define do_prctl_get_vl do_prctl_inval0 +#ifndef do_prctl_sve_get_vl +#define do_prctl_sve_get_vl do_prctl_inval0 #endif -#ifndef do_prctl_set_vl -#define do_prctl_set_vl do_prctl_inval1 +#ifndef do_prctl_sve_set_vl +#define do_prctl_sve_set_vl do_prctl_inval1 #endif #ifndef do_prctl_reset_keys #define do_prctl_reset_keys do_prctl_inval1 @@ -6431,9 +6431,9 @@ static abi_long do_prctl(CPUArchState *env, abi_long = option, abi_long arg2, case PR_SET_FP_MODE: return do_prctl_set_fp_mode(env, arg2); case PR_SVE_GET_VL: - return do_prctl_get_vl(env); + return do_prctl_sve_get_vl(env); case PR_SVE_SET_VL: - return do_prctl_set_vl(env, arg2); + return do_prctl_sve_set_vl(env, arg2); case PR_PAC_RESET_KEYS: if (arg3 || arg4 || arg5) { return -TARGET_EINVAL; --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657294565; cv=none; d=zohomail.com; s=zohoarc; b=OnT5uVNC2KG/BiJXoQbHewGHWoKHFpEdZ3Iq+RQmSYQ3cnHigDFLTASVtiZFFwfOB5Ku06MxmB1ndjitGThXkr7E2gxSMgnxT5E+H3IXpeNXAHBUd4ld5G88QkvtqvDWHtWP4qlf+KNIY4edlO7kYTU1UmJdTxKu6zMx9dPHJqQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657294565; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QT+j4xhm70EdfcVhkO7HkP89Z4Z0asvpHZ6p48VqoaU=; b=J8doDTKr26eQ/zlOG7Go8dlSsJMrdNyg8OK0W/XMw0zrhZEH8U4Yikz/bzujCO3VPhV71c6ttBBOZMsmvGZS+EUGI8aNKmvYM9pVv1mR0sOefFVCtflz9gEO0bE/jvTmSX3pEYMcAscll2En/OcRx4DwBQdP6p4BqqTNct/l6ZM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657294565302677.9716592852413; Fri, 8 Jul 2022 08:36:05 -0700 (PDT) Received: from localhost ([::1]:42936 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9q1U-0006Hn-44 for importer@patchew.org; Fri, 08 Jul 2022 11:36:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38962) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pmu-0003Ta-0i for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:21:01 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:33662) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pmr-0003GB-V3 for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:20:59 -0400 Received: by mail-pf1-x42b.google.com with SMTP id n12so23847334pfq.0 for ; Fri, 08 Jul 2022 08:20:57 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id cp2-20020a170902e78200b0015e8d4eb1d7sm30067741plb.33.2022.07.08.08.20.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:20:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QT+j4xhm70EdfcVhkO7HkP89Z4Z0asvpHZ6p48VqoaU=; b=ECNVhHBnuFyy5aiwg2TX0p1hNXUE5EYxY3DbXyf6GdMLR6hp6QTgGBtuVgnqG2lhik BxuYZzVOKZTlVqJesjt3yvu11wee2iA6BtFduqcYkXon8iLlxhzFQUT8PKCw5xUq5BNE dMgsVayrkX0cAUv5VYK2IUdzn2CCOKBx19aHunQxHg9y2sp4Dfkzl6brkPd6Sm/LSYPK x9hhuDPURI+6KTZUcjO/WKgu1zgEAZDG5Z6Zly2Z3/p4Tn4VIEjcIYDWkwV+HpzENOtq Ab2WGoG6VN+JAsnElg4KzSxOCNL/IVYMFHl2xQRJOZLIhiVr546jF0Ezpf0sE+r3HqJd E6CQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QT+j4xhm70EdfcVhkO7HkP89Z4Z0asvpHZ6p48VqoaU=; b=mpqVX4sWIdOf3UjcMydLTBUPA+LrnmS6voIRmNIxyfFfkMKRDdWfkFR/4Cos9tzck1 esgggwL2ZR8l6WCCQ3zmdh/AmusBK8/nJSxpAlWlmqh5Nzl0S7MjVUXg1ljlS2JaclHb xyYQ1nCLlVi3fh/rf91iI8+w1iXf5T9B9eIWR9k5pVObJCjnQqPXS4z2APcNmcY26Er8 IEOgscn5VvdEJIM8aW+wI7o0vk/GdVnW1/FJjB3qZUV2+K6UmeMCNpuFLecXKTtVZCSy QDOupZLExLy4w+0KL03g5wcVDEAFXLbp9/Be+AHjrwDBQc3FQEKwaILbcoeX9PyTJdzQ K63Q== X-Gm-Message-State: AJIora8lMKqkpeCRNtoA1iyJkHjGdlBemSphvnEzqIa79wWkFNeXCYcj GGdxak335/0q8cm6p66DMQs0nGBHe+/IyA2R X-Google-Smtp-Source: AGRyM1t0ynntIkCgcUySwSFCZc+nOSpuAT6SlMrPRqY+hMm7FhxL/GJ+AmAPZwlmsWWEfw4Axs+55A== X-Received: by 2002:aa7:88d2:0:b0:525:92bb:cb3c with SMTP id k18-20020aa788d2000000b0052592bbcb3cmr4580572pff.2.1657293656425; Fri, 08 Jul 2022 08:20:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 42/45] linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL Date: Fri, 8 Jul 2022 20:45:37 +0530 Message-Id: <20220708151540.18136-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657294566790100002 Content-Type: text/plain; charset="utf-8" These prctl set the Streaming SVE vector length, which may be completely different from the Normal SVE vector length. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 54 +++++++++++++++++++++++++++++++ linux-user/syscall.c | 16 +++++++++ 2 files changed, 70 insertions(+) diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_= prctl.h index 40481e6663..907c314146 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -10,6 +10,7 @@ static abi_long do_prctl_sve_get_vl(CPUArchState *env) { ARMCPU *cpu =3D env_archcpu(env); if (cpu_isar_feature(aa64_sve, cpu)) { + /* PSTATE.SM is always unset on syscall entry. */ return sve_vq(env) * 16; } return -TARGET_EINVAL; @@ -27,6 +28,7 @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, ab= i_long arg2) && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { uint32_t vq, old_vq; =20 + /* PSTATE.SM is always unset on syscall entry. */ old_vq =3D sve_vq(env); =20 /* @@ -49,6 +51,58 @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, a= bi_long arg2) } #define do_prctl_sve_set_vl do_prctl_sve_set_vl =20 +static abi_long do_prctl_sme_get_vl(CPUArchState *env) +{ + ARMCPU *cpu =3D env_archcpu(env); + if (cpu_isar_feature(aa64_sme, cpu)) { + return sme_vq(env) * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_sme_get_vl do_prctl_sme_get_vl + +static abi_long do_prctl_sme_set_vl(CPUArchState *env, abi_long arg2) +{ + /* + * We cannot support either PR_SME_SET_VL_ONEXEC or PR_SME_VL_INHERIT. + * Note the kernel definition of sve_vl_valid allows for VQ=3D512, + * i.e. VL=3D8192, even though the architectural maximum is VQ=3D16. + */ + if (cpu_isar_feature(aa64_sme, env_archcpu(env)) + && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { + int vq, old_vq; + + old_vq =3D sme_vq(env); + + /* + * Bound the value of vq, so that we know that it fits into + * the 4-bit field in SMCR_EL1. Because PSTATE.SM is cleared + * on syscall entry, we are not modifying the current SVE + * vector length. + */ + vq =3D MAX(arg2 / 16, 1); + vq =3D MIN(vq, 16); + env->vfp.smcr_el[1] =3D + FIELD_DP64(env->vfp.smcr_el[1], SMCR, LEN, vq - 1); + + /* Delay rebuilding hflags until we know if ZA must change. */ + vq =3D sve_vqm1_for_el_sm(env, 0, true) + 1; + + if (vq !=3D old_vq) { + /* + * PSTATE.ZA state is cleared on any change to SVL. + * We need not call arm_rebuild_hflags because PSTATE.SM was + * cleared on syscall entry, so this hasn't changed VL. + */ + env->svcr =3D FIELD_DP64(env->svcr, SVCR, ZA, 0); + arm_rebuild_hflags(env); + } + return vq * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_sme_set_vl do_prctl_sme_set_vl + static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) { ARMCPU *cpu =3D env_archcpu(env); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index cbde82c907..991b85e6b4 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6343,6 +6343,12 @@ abi_long do_arch_prctl(CPUX86State *env, int code, a= bi_ulong addr) #ifndef PR_SET_SYSCALL_USER_DISPATCH # define PR_SET_SYSCALL_USER_DISPATCH 59 #endif +#ifndef PR_SME_SET_VL +# define PR_SME_SET_VL 63 +# define PR_SME_GET_VL 64 +# define PR_SME_VL_LEN_MASK 0xffff +# define PR_SME_VL_INHERIT (1 << 17) +#endif =20 #include "target_prctl.h" =20 @@ -6383,6 +6389,12 @@ static abi_long do_prctl_inval1(CPUArchState *env, a= bi_long arg2) #ifndef do_prctl_set_unalign #define do_prctl_set_unalign do_prctl_inval1 #endif +#ifndef do_prctl_sme_get_vl +#define do_prctl_sme_get_vl do_prctl_inval0 +#endif +#ifndef do_prctl_sme_set_vl +#define do_prctl_sme_set_vl do_prctl_inval1 +#endif =20 static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5) @@ -6434,6 +6446,10 @@ static abi_long do_prctl(CPUArchState *env, abi_long= option, abi_long arg2, return do_prctl_sve_get_vl(env); case PR_SVE_SET_VL: return do_prctl_sve_set_vl(env, arg2); + case PR_SME_GET_VL: + return do_prctl_sme_get_vl(env); + case PR_SME_SET_VL: + return do_prctl_sme_set_vl(env, arg2); case PR_PAC_RESET_KEYS: if (arg3 || arg4 || arg5) { return -TARGET_EINVAL; --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657296181; cv=none; d=zohomail.com; s=zohoarc; b=D3XEY5JxPmmPmjkbvH6JI86KwE/f28OlpqJX+y060e+hh/0UNpJP3cUgbO87Bq6T+WdYcYpGTuxLJMjFsPwl7ha5IK0VfhGeY3x9ET2T+h3VkS7kdK1+hOlivOFywzCwPoOcyqN+RPFAYVNMBHVAK+h/+vPxlbNqEjpYP/yNHqg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657296181; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=H9uf8O4CUiqyVcmvjic8DcvLpWT2fCMJa8CUUeRGTi0=; b=VQdxQQQ20Wp0MG9sbXIBvhf3D+B0JWs7K752VVCugY3soEU5jQ3NNMfyfUzMdJybuiBvw+6V6RbGk4LSlCU8jYbY15W+r3YqTXSdxnO+4s7lAgY9F+V2tqSfBxYg+B/mW/14l5wVP2wrbzw4YrMIEsUHTwvemIzzUeZElC4e9KI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165729618134034.81988307450797; Fri, 8 Jul 2022 09:03:01 -0700 (PDT) Received: from localhost ([::1]:57220 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9qRW-0005zS-SA for importer@patchew.org; Fri, 08 Jul 2022 12:02:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39010) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pmw-0003XA-O6 for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:21:02 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:44623) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pmv-0003Gv-Bs for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:21:02 -0400 Received: by mail-pf1-x431.google.com with SMTP id e16so11018081pfm.11 for ; Fri, 08 Jul 2022 08:21:00 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id cp2-20020a170902e78200b0015e8d4eb1d7sm30067741plb.33.2022.07.08.08.20.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:20:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H9uf8O4CUiqyVcmvjic8DcvLpWT2fCMJa8CUUeRGTi0=; b=GB4PC84GnlTLbLfDNQpejeBxBDIV/D4gw5BDGWnulLVKnzZcoEN5D0EVV9gkkitUHY 6aDhlEy2X15c4lIzekAYmvNvMRP4zCgnL5ZVYUlexDYs/L47roGhfKragbHc0flB4CGh pk9rpZpOtYNyI/2gSGHkwIAGTAkHLOD34DQ8XkvIW2YVBTe/Wq5mokrhKWZKHYc3aIbY eXwI5avX04ClhSHyrTUchojkMTKgw+H3BjBpiPVvrkbeoGD9wHFJsgHmRNEQUsRU6T/c Jwq2WyXIooX4WErFOmukNn1NPDlasQC9TG5snI9TqgFiQLwc/q740uHVgsv2kcTf9uXU dsCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H9uf8O4CUiqyVcmvjic8DcvLpWT2fCMJa8CUUeRGTi0=; b=a6Haxo55X9EHfmbg1z4MUVD7C0XtQjBzhtuz3+aC/ovYDFrlst4AAlbRxqm40qdhtC s1CmGok+qE8hjNJYPn2dV7P4JCAmFCBmL3KIj6rIaQVQqe6FcX5RwR1GOgSOtClqvFl/ UpbjRzCTaPJH6gz8jnt7wKs89HW/LI31/IwNVSWE7aoBaDCT76g8JIbNhX+q2hDwZj08 5XMsVjwznjt1rmiUIMm044LWLmY8CvrxaS/owDqVIZmXMMVwQS0XUx6nf0Xab3NWeRmi zutvcYWw0P6BBnvyxxUrqFqx0wDr5+Bgv35c/7PnERF2fq9HA56Ul/Eqo+Sorgkwd5FE KzQQ== X-Gm-Message-State: AJIora8786Hj8b1e5lJQUqL2pwzvL/u+7so0ttVvRYb1x/dSUVYcqFuj c5R+PiTYCX7cRIa/3nUR/NpiRSuPFEwgc9c4 X-Google-Smtp-Source: AGRyM1tDqNKpHD2wB2AgL64yFLWAruwwSOlVRxll7Q1mIg8ewIpsUrHtlKVswZK/V7sINEfEpGqieg== X-Received: by 2002:a05:6a00:218c:b0:525:5236:74c with SMTP id h12-20020a056a00218c00b005255236074cmr4396978pfi.44.1657293659628; Fri, 08 Jul 2022 08:20:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 43/45] target/arm: Only set ZEN in reset if SVE present Date: Fri, 8 Jul 2022 20:45:38 +0530 Message-Id: <20220708151540.18136-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657296183464100001 Content-Type: text/plain; charset="utf-8" There's no reason to set CPACR_EL1.ZEN if SVE disabled. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9c58be8b14..9b54443843 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -204,11 +204,10 @@ static void arm_cpu_reset(DeviceState *dev) /* and to the FP/Neon instructions */ env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, CPACR_EL1, FPEN, 3); - /* and to the SVE instructions */ - env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, - CPACR_EL1, ZEN, 3); - /* with reasonable vector length */ + /* and to the SVE instructions, with default vector length */ if (cpu_isar_feature(aa64_sve, cpu)) { + env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, + CPACR_EL1, ZEN, 3); env->vfp.zcr_el[1] =3D cpu->sve_default_vq - 1; } /* --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657296439; cv=none; d=zohomail.com; s=zohoarc; b=LVAiNDLC8U4bQazWc/7/9jreJ0AS1o7NoLCgbFtHTEtl9fvky9TWTdBB0Ik8bXIP5ctO8nodIC4yjaVshMxx7TlOaP5nKEBhlbHlk+VVZYGCO/AhwE6u0PeBKuE4thnH63pDI8y40NQV2/D7fpZqg4W0H00MnPneaGwBzrIxe1c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657296439; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ojyZOIf2uqXDhLYPW4II9jqD/RYb57Q1CkTjNakDECE=; b=aUwD6maiErrBGu/jQIIoNvvmPoMtZVXw1yUz1PViDaHFS7GFoOzAHUFwth5elcMd6aH9vUDGeGu9o4Ef9n1vmjKGVu7oP9bq5D4KiVrikewJjynDUTSz13+1bbYNRxlg2JMzyzr7T1fIaOtEmpkTCgDk9VEQetDFR1w06JizwTU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657296439440939.4252253792472; Fri, 8 Jul 2022 09:07:19 -0700 (PDT) Received: from localhost ([::1]:37622 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9qVh-0003RI-AS for importer@patchew.org; Fri, 08 Jul 2022 12:07:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pmz-0003gk-DX for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:21:05 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:43715) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pmx-0003IP-O9 for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:21:05 -0400 Received: by mail-pl1-x62f.google.com with SMTP id r1so16590508plo.10 for ; Fri, 08 Jul 2022 08:21:03 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id cp2-20020a170902e78200b0015e8d4eb1d7sm30067741plb.33.2022.07.08.08.21.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:21:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ojyZOIf2uqXDhLYPW4II9jqD/RYb57Q1CkTjNakDECE=; b=Ugm1HCxkCao/v3DlPh90pZ+19YwR0BAOX8TjVko46238qJmZWwWqS/+93D7imAmP80 KccZBJDy5gFrkcYzu3N5271KDlcbo05kz8XexqLEIDVSxXZi2ddCQmI3z6rsjKWSApr/ KGVFZhRc8ayjwihQjgzA2sywVqdOBnL8hkAe+vSyhpN190MAHOoe2sdBZP8ymBpSeBrf pXejthiWHlksyMUVCe6w/WwWnkSTSBsp8yJXImSmh6FsbOq15ATsFAExl0VkD8CwIZCW Djj4zbaeirmx9xFlnjQD+uUDQkihpeh5wDnSfJwhLWuzdBeFXBQAJl7VJJNdWRt7Ylt1 HFOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ojyZOIf2uqXDhLYPW4II9jqD/RYb57Q1CkTjNakDECE=; b=WiYjH1BxBkfX920RRX2yWMj/sRoTJPpE+sKsvjCwlLnJURQMJdKJ5RXo81DxgSz43v Dt+XX4OdTYnVH4HLI2PvXvO0JxpjDpT1xliTyhaOA28Pn88OALHWIw+fEQmjRcxtZ5Ys vl2YtTt/EV1xlwSeZm2mfUotgIBNsQ6Z5T0XYK+tmEaFo2JMEbrY9v71fPYRC0pnK9a9 jtzhkeY0ks+5dijVAFTB5Yj/fbGybVndNcHPH08KynzGAsysc4OAHKhX6mToKzKwN0Bx L5pgImd8QaaCiDZVZ2QrcrB59S4hIPjOLiuUWoyu6Mlyw3eAm3rTngtB86Ta9/sdC7u+ aORg== X-Gm-Message-State: AJIora/3KbErsuuLdLJJ2emtW5womkHuZgOAgMa2L6tamvcfQvnvDrQ+ +oG0krhEF32xRt2nbQTKjQhIRnnqCL/7nc5d X-Google-Smtp-Source: AGRyM1vstiEKDzjpvHFHgrNCQ01dzvERlldhTdyZXCjkLHAeGvha8+s4PiVVWQPigqk+x+IJYUj6HA== X-Received: by 2002:a17:902:8345:b0:167:879c:abe8 with SMTP id z5-20020a170902834500b00167879cabe8mr4250447pln.7.1657293662404; Fri, 08 Jul 2022 08:21:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 44/45] target/arm: Enable SME for user-only Date: Fri, 8 Jul 2022 20:45:39 +0530 Message-Id: <20220708151540.18136-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657296440715100001 Content-Type: text/plain; charset="utf-8" Enable SME, TPIDR2_EL0, and FA64 if supported by the cpu. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9b54443843..5de7e097e9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -210,6 +210,17 @@ static void arm_cpu_reset(DeviceState *dev) CPACR_EL1, ZEN, 3); env->vfp.zcr_el[1] =3D cpu->sve_default_vq - 1; } + /* and for SME instructions, with default vector length, and TPIDR= 2 */ + if (cpu_isar_feature(aa64_sme, cpu)) { + env->cp15.sctlr_el[1] |=3D SCTLR_EnTP2; + env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, + CPACR_EL1, SMEN, 3); + env->vfp.smcr_el[1] =3D cpu->sme_default_vq - 1; + if (cpu_isar_feature(aa64_sme_fa64, cpu)) { + env->vfp.smcr_el[1] =3D FIELD_DP64(env->vfp.smcr_el[1], + SMCR, FA64, 1); + } + } /* * Enable 48-bit address space (TODO: take reserved_va into accoun= t). * Enable TBI0 but not TBI1. --=20 2.34.1 From nobody Sun May 19 06:23:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657296948; cv=none; d=zohomail.com; s=zohoarc; b=hMdmFT4RCrq43yq+J3149A/9x4MlDCLOW9IaObe7qvF+rOiCcQUQeHQSgq+F8z117NrMLgdAqfbzWeg8qvHR9Z085JZpqCf9VxcmvecfPtIH6/yWAWTPpUneSSWH0Loozzw3jywMZQlekoC4Y2RXsYIUJaf317828UB+D6nVNOk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657296948; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IH0GiEUf1cl31EpypJHGc9N38GuuWqV/keLjTWnDRUI=; b=ENkZNHv6QcIRAsh2APgC4+5hdpUrYgb6J8yOuUTpM6dIYnqNJ4oboUyzveOijYKjtTfJcuCrMsuD65sYHwb5jl3Y8PlLmPGiQrVgHbj7nrGe8pbPa8F/GPmktqZaSqzoUGECdeCJG9Rv45WGTUCFQagP00nN9gXJab2S5xz1Qm0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657296948048239.53021000580566; Fri, 8 Jul 2022 09:15:48 -0700 (PDT) Received: from localhost ([::1]:54322 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9qdu-0006dt-St for importer@patchew.org; Fri, 08 Jul 2022 12:15:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39074) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pn1-0003qm-U1 for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:21:07 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:37518) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pn0-0003JW-Av for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:21:07 -0400 Received: by mail-pl1-x634.google.com with SMTP id f11so4055476plr.4 for ; Fri, 08 Jul 2022 08:21:05 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id cp2-20020a170902e78200b0015e8d4eb1d7sm30067741plb.33.2022.07.08.08.21.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:21:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IH0GiEUf1cl31EpypJHGc9N38GuuWqV/keLjTWnDRUI=; b=xgquYLXYJXsW1UdcvjlI689LtEmJcoi3Hr7/dyoIlSxt75FzcYeh8n6q5oqoVq7jiM bnn+CpvLDm4RRA7cKilyTkHndqjIruzjPAJZDzZVZa+ktu79asB5pjTzdT3QyWnJPrPY vkUm6ZrfFg8/jiwajXZyBaJvPUV7UN3IpzVDqJQ8IpU4Zbod5h6t1oUSuqpiV54rVOXe M9a5Wtnnrwrx+habCsi3qxjLPspeXVtqjm/NKWyHi6IHyqkysnvLuxeXnCbnlGb0xt+5 0drSnI7tYK9i1QyQKlKfbzqmBCsHFKnI/JML9Aul+4PoeLS23o2+qoSJFG7YMdtodHvc 0geA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IH0GiEUf1cl31EpypJHGc9N38GuuWqV/keLjTWnDRUI=; b=cWxefQuHCzFU6Ycf5AqW3cEz599lRFX9VyisxU2mICZvncDt0QcOvOyt8Aw92/xdQu 8anApUVI2kvlWaHewL2my5Uo0UxxOHGQdo1eEUXLLt10foT4s9Ac7/N53uw7vXEkfNlG dd5g3LCBF1R1ce/RpGk8LZwn9jTd1H4mQnL8y8II5ch4rGAd+wGoxbqV35J1dvSa+YW4 HJ0qIJe4KvSPDEY+P8E87Wi2FqNpOfa863WG3REaDSove0/z1g2KuzVT6fNAeyS58kFw 6d8zYj01Dsrg+I6puBYxhkL3nkRwLwGk/KZoXLoHKw1JE/2Y1ROjohS0bXyLXAPjWNV4 XCCg== X-Gm-Message-State: AJIora9zvK7QnNj9BK7lYXqeh3NjoH5opoaOoJawBHS9Hl99RRf+kLVy GBYWlPTy2bniJjdZ6NvrWyxJRTHrRGDAdYNH X-Google-Smtp-Source: AGRyM1s2TQsHBNDcTnokgrOaaCK8nMfva+py7DwicVtwuGa3tJYEnD/kZKrmOPolEx9e81mAJWgFQg== X-Received: by 2002:a17:902:e84f:b0:16c:76c:561d with SMTP id t15-20020a170902e84f00b0016c076c561dmr4301208plg.119.1657293665113; Fri, 08 Jul 2022 08:21:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 45/45] linux-user/aarch64: Add SME related hwcap entries Date: Fri, 8 Jul 2022 20:45:40 +0530 Message-Id: <20220708151540.18136-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657296949790100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/elfload.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 1de77c7959..ce902dbd56 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -605,6 +605,18 @@ enum { ARM_HWCAP2_A64_RNG =3D 1 << 16, ARM_HWCAP2_A64_BTI =3D 1 << 17, ARM_HWCAP2_A64_MTE =3D 1 << 18, + ARM_HWCAP2_A64_ECV =3D 1 << 19, + ARM_HWCAP2_A64_AFP =3D 1 << 20, + ARM_HWCAP2_A64_RPRES =3D 1 << 21, + ARM_HWCAP2_A64_MTE3 =3D 1 << 22, + ARM_HWCAP2_A64_SME =3D 1 << 23, + ARM_HWCAP2_A64_SME_I16I64 =3D 1 << 24, + ARM_HWCAP2_A64_SME_F64F64 =3D 1 << 25, + ARM_HWCAP2_A64_SME_I8I32 =3D 1 << 26, + ARM_HWCAP2_A64_SME_F16F32 =3D 1 << 27, + ARM_HWCAP2_A64_SME_B16F32 =3D 1 << 28, + ARM_HWCAP2_A64_SME_F32F32 =3D 1 << 29, + ARM_HWCAP2_A64_SME_FA64 =3D 1 << 30, }; =20 #define ELF_HWCAP get_elf_hwcap() @@ -674,6 +686,14 @@ static uint32_t get_elf_hwcap2(void) GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG); GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI); GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE); + GET_FEATURE_ID(aa64_sme, (ARM_HWCAP2_A64_SME | + ARM_HWCAP2_A64_SME_F32F32 | + ARM_HWCAP2_A64_SME_B16F32 | + ARM_HWCAP2_A64_SME_F16F32 | + ARM_HWCAP2_A64_SME_I8I32)); + GET_FEATURE_ID(aa64_sme_f64f64, ARM_HWCAP2_A64_SME_F64F64); + GET_FEATURE_ID(aa64_sme_i16i64, ARM_HWCAP2_A64_SME_I16I64); + GET_FEATURE_ID(aa64_sme_fa64, ARM_HWCAP2_A64_SME_FA64); =20 return hwcaps; } --=20 2.34.1