From nobody Fri May 10 15:50:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532960030041291.04274781520917; Mon, 30 Jul 2018 07:13:50 -0700 (PDT) Received: from localhost ([::1]:52849 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fk8vk-0005tE-Sb for importer@patchew.org; Mon, 30 Jul 2018 10:13:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56637) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fk8tw-0004ou-GL for qemu-devel@nongnu.org; Mon, 30 Jul 2018 10:11:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fk8tr-0005W9-OH for qemu-devel@nongnu.org; Mon, 30 Jul 2018 10:11:56 -0400 Received: from 5.mo7.mail-out.ovh.net ([178.32.120.239]:56948) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fk8tr-0005VW-H4 for qemu-devel@nongnu.org; Mon, 30 Jul 2018 10:11:51 -0400 Received: from player787.ha.ovh.net (unknown [10.109.159.69]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id AF9D8C1D46 for ; Mon, 30 Jul 2018 16:11:49 +0200 (CEST) Received: from zorba.kaod.org.com (bad36-1-78-202-132-1.fbx.proxad.net [78.202.132.1]) (Authenticated sender: clg@kaod.org) by player787.ha.ovh.net (Postfix) with ESMTPSA id 2F8F16000C7; Mon, 30 Jul 2018 16:11:44 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Mon, 30 Jul 2018 16:11:31 +0200 Message-Id: <20180730141134.31153-2-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180730141134.31153-1-clg@kaod.org> References: <20180730141134.31153-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2064056008270646246 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtiedrkeejgdejudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.32.120.239 Subject: [Qemu-devel] [PATCH v6 1/4] spapr: Add a pseries-3.1 machine type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- include/hw/compat.h | 3 +++ hw/ppc/spapr.c | 23 +++++++++++++++++++++-- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/include/hw/compat.h b/include/hw/compat.h index c08f4040bb80..6f4d5fc64704 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -1,6 +1,9 @@ #ifndef HW_COMPAT_H #define HW_COMPAT_H =20 +#define HW_COMPAT_3_0 \ + /* empty */ + #define HW_COMPAT_2_12 \ {\ .driver =3D "migration",\ diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 421b2dd09b51..3c72173c7e0f 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4058,19 +4058,38 @@ static const TypeInfo spapr_machine_info =3D { } \ type_init(spapr_machine_register_##suffix) =20 + /* + * pseries-3.1 + */ +static void spapr_machine_3_1_instance_options(MachineState *machine) +{ +} + +static void spapr_machine_3_1_class_options(MachineClass *mc) +{ + /* Defaults for the latest behaviour inherited from the base class */ +} + +DEFINE_SPAPR_MACHINE(3_1, "3.1", true); + /* * pseries-3.0 */ +#define SPAPR_COMPAT_3_0 \ + HW_COMPAT_3_0 + static void spapr_machine_3_0_instance_options(MachineState *machine) { + spapr_machine_3_1_instance_options(machine); } =20 static void spapr_machine_3_0_class_options(MachineClass *mc) { - /* Defaults for the latest behaviour inherited from the base class */ + spapr_machine_3_1_class_options(mc); + SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_3_0); } =20 -DEFINE_SPAPR_MACHINE(3_0, "3.0", true); +DEFINE_SPAPR_MACHINE(3_0, "3.0", false); =20 /* * pseries-2.12 --=20 2.17.1 From nobody Fri May 10 15:50:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15329600618711001.500690092114; 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Mon, 30 Jul 2018 16:11:49 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Mon, 30 Jul 2018 16:11:32 +0200 Message-Id: <20180730141134.31153-3-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180730141134.31153-1-clg@kaod.org> References: <20180730141134.31153-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2065463380506807270 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtiedrkeejgdeilecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.61.98 Subject: [Qemu-devel] [PATCH v6 2/4] spapr: introduce a fixed IRQ number space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This proposal introduces a new IRQ number space layout using static numbers for all devices, depending on a device index, and a bitmap allocator for the MSI IRQ numbers which are negotiated by the guest at runtime. As the VIO device model does not have a device index but a "reg" property, we introduce a formula to compute an IRQ number from a "reg" value. It should minimize most of the collisions. The previous layout is kept in pre-3.1 machines raising the 'legacy_irq_allocation' machine class flag. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- include/hw/ppc/spapr.h | 5 +++ include/hw/ppc/spapr_irq.h | 32 ++++++++++++++++++ hw/ppc/spapr.c | 32 ++++++++++++++++++ hw/ppc/spapr_events.c | 12 ++++--- hw/ppc/spapr_irq.c | 56 ++++++++++++++++++++++++++++++++ hw/ppc/spapr_pci.c | 29 +++++++++++++---- hw/ppc/spapr_vio.c | 66 ++++++++++++++++++++++++++++++++++---- hw/ppc/Makefile.objs | 2 +- 8 files changed, 216 insertions(+), 18 deletions(-) create mode 100644 include/hw/ppc/spapr_irq.h create mode 100644 hw/ppc/spapr_irq.c diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 7e5de1a6fd42..73067f5ee8aa 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -8,6 +8,7 @@ #include "hw/ppc/spapr_drc.h" #include "hw/mem/pc-dimm.h" #include "hw/ppc/spapr_ovec.h" +#include "hw/ppc/spapr_irq.h" =20 struct VIOsPAPRBus; struct sPAPRPHBState; @@ -101,6 +102,8 @@ struct sPAPRMachineClass { bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs = */ bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ bool pre_2_10_has_unused_icps; + bool legacy_irq_allocation; + void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, uint64_t *buid, hwaddr *pio,=20 hwaddr *mmio32, hwaddr *mmio64, @@ -167,6 +170,8 @@ struct sPAPRMachineState { char *kvm_type; =20 const char *icp_type; + int32_t irq_map_nr; + unsigned long *irq_map; =20 bool cmd_line_caps[SPAPR_CAP_NUM]; sPAPRCapabilities def, eff, mig; diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h new file mode 100644 index 000000000000..6f7f50548809 --- /dev/null +++ b/include/hw/ppc/spapr_irq.h @@ -0,0 +1,32 @@ +/* + * QEMU PowerPC sPAPR IRQ backend definitions + * + * Copyright (c) 2018, IBM Corporation. + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ + +#ifndef HW_SPAPR_IRQ_H +#define HW_SPAPR_IRQ_H + +/* + * IRQ range offsets per device type + */ +#define SPAPR_IRQ_EPOW 0x1000 /* XICS_IRQ_BASE offset */ +#define SPAPR_IRQ_HOTPLUG 0x1001 +#define SPAPR_IRQ_VIO 0x1100 /* 256 VIO devices */ +#define SPAPR_IRQ_PCI_LSI 0x1200 /* 32+ PHBs devices */ + +#define SPAPR_IRQ_MSI 0x1300 /* Offset of the dynamic range covered + * by the bitmap allocator */ + +typedef struct sPAPRMachineState sPAPRMachineState; + +void spapr_irq_msi_init(sPAPRMachineState *spapr, uint32_t nr_msis); +int spapr_irq_msi_alloc(sPAPRMachineState *spapr, uint32_t num, bool align, + Error **errp); +void spapr_irq_msi_free(sPAPRMachineState *spapr, int irq, uint32_t num); +void spapr_irq_msi_reset(sPAPRMachineState *spapr); + +#endif diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 3c72173c7e0f..792e24453d8b 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -189,6 +189,11 @@ static void xics_system_init(MachineState *machine, in= t nr_irqs, Error **errp) sPAPRMachineState *spapr =3D SPAPR_MACHINE(machine); Error *local_err =3D NULL; =20 + /* Initialize the MSI IRQ allocator. */ + if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { + spapr_irq_msi_init(spapr, XICS_IRQ_BASE + nr_irqs - SPAPR_IRQ_MSI); + } + if (kvm_enabled()) { if (machine_kernel_irqchip_allowed(machine) && !xics_kvm_init(spapr, &local_err)) { @@ -1636,6 +1641,10 @@ static void spapr_machine_reset(void) ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); } =20 + if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { + spapr_irq_msi_reset(spapr); + } + qemu_devices_reset(); =20 /* DRC reset may cause a device to be unplugged. This will cause troub= les @@ -1910,6 +1919,24 @@ static const VMStateDescription vmstate_spapr_patb_e= ntry =3D { }, }; =20 +static bool spapr_irq_map_needed(void *opaque) +{ + sPAPRMachineState *spapr =3D opaque; + + return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_= nr); +} + +static const VMStateDescription vmstate_spapr_irq_map =3D { + .name =3D "spapr_irq_map", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D spapr_irq_map_needed, + .fields =3D (VMStateField[]) { + VMSTATE_BITMAP(irq_map, sPAPRMachineState, 0, irq_map_nr), + VMSTATE_END_OF_LIST() + }, +}; + static const VMStateDescription vmstate_spapr =3D { .name =3D "spapr", .version_id =3D 3, @@ -1937,6 +1964,7 @@ static const VMStateDescription vmstate_spapr =3D { &vmstate_spapr_cap_cfpc, &vmstate_spapr_cap_sbbc, &vmstate_spapr_cap_ibs, + &vmstate_spapr_irq_map, NULL } }; @@ -4085,8 +4113,12 @@ static void spapr_machine_3_0_instance_options(Machi= neState *machine) =20 static void spapr_machine_3_0_class_options(MachineClass *mc) { + sPAPRMachineClass *smc =3D SPAPR_MACHINE_CLASS(mc); + spapr_machine_3_1_class_options(mc); SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_3_0); + + smc->legacy_irq_allocation =3D true; } =20 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index e4f5946a2188..32719a1b72d0 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -707,9 +707,11 @@ void spapr_clear_pending_events(sPAPRMachineState *spa= pr) =20 void spapr_events_init(sPAPRMachineState *spapr) { - int epow_irq; + int epow_irq =3D SPAPR_IRQ_EPOW; =20 - epow_irq =3D spapr_irq_findone(spapr, &error_fatal); + if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { + epow_irq =3D spapr_irq_findone(spapr, &error_fatal); + } =20 spapr_irq_claim(spapr, epow_irq, false, &error_fatal); =20 @@ -729,9 +731,11 @@ void spapr_events_init(sPAPRMachineState *spapr) * checking that it's enabled. */ if (spapr->use_hotplug_event_source) { - int hp_irq; + int hp_irq =3D SPAPR_IRQ_HOTPLUG; =20 - hp_irq =3D spapr_irq_findone(spapr, &error_fatal); + if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { + hp_irq =3D spapr_irq_findone(spapr, &error_fatal); + } =20 spapr_irq_claim(spapr, hp_irq, false, &error_fatal); =20 diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c new file mode 100644 index 000000000000..24e9c1d4433c --- /dev/null +++ b/hw/ppc/spapr_irq.c @@ -0,0 +1,56 @@ +/* + * QEMU PowerPC sPAPR IRQ interface + * + * Copyright (c) 2018, IBM Corporation. + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "hw/ppc/spapr.h" +#include "hw/ppc/xics.h" + +void spapr_irq_msi_init(sPAPRMachineState *spapr, uint32_t nr_msis) +{ + spapr->irq_map_nr =3D nr_msis; + spapr->irq_map =3D bitmap_new(spapr->irq_map_nr); +} + +int spapr_irq_msi_alloc(sPAPRMachineState *spapr, uint32_t num, bool align, + Error **errp) +{ + int irq; + + /* + * The 'align_mask' parameter of bitmap_find_next_zero_area() + * should be one less than a power of 2; 0 means no + * alignment. Adapt the 'align' value of the former allocator + * to fit the requirements of bitmap_find_next_zero_area() + */ + align -=3D 1; + + irq =3D bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, = 0, num, + align); + if (irq =3D=3D spapr->irq_map_nr) { + error_setg(errp, "can't find a free %d-IRQ block", num); + return -1; + } + + bitmap_set(spapr->irq_map, irq, num); + + return irq + SPAPR_IRQ_MSI; +} + +void spapr_irq_msi_free(sPAPRMachineState *spapr, int irq, uint32_t num) +{ + bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num); +} + +void spapr_irq_msi_reset(sPAPRMachineState *spapr) +{ + bitmap_clear(spapr->irq_map, 0, spapr->irq_map_nr); +} diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 497b896c7d24..3791ced6c536 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -334,6 +334,9 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRM= achineState *spapr, return; } =20 + if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { + spapr_irq_msi_free(spapr, msi->first_irq, msi->num); + } spapr_irq_free(spapr, msi->first_irq, msi->num); if (msi_present(pdev)) { spapr_msi_setmsg(pdev, 0, false, 0, 0); @@ -372,7 +375,13 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPR= MachineState *spapr, } =20 /* Allocate MSIs */ - irq =3D spapr_irq_find(spapr, req_num, ret_intr_type =3D=3D RTAS_TYPE_= MSI, &err); + if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { + irq =3D spapr_irq_find(spapr, req_num, ret_intr_type =3D=3D RTAS_T= YPE_MSI, + &err); + } else { + irq =3D spapr_irq_msi_alloc(spapr, req_num, + ret_intr_type =3D=3D RTAS_TYPE_MSI, &err= ); + } if (err) { error_reportf_err(err, "Can't allocate MSIs for device %x: ", config_addr); @@ -392,6 +401,9 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRM= achineState *spapr, =20 /* Release previous MSIs */ if (msi) { + if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { + spapr_irq_msi_free(spapr, msi->first_irq, msi->num); + } spapr_irq_free(spapr, msi->first_irq, msi->num); g_hash_table_remove(phb->msi, &config_addr); } @@ -1705,14 +1717,16 @@ static void spapr_phb_realize(DeviceState *dev, Err= or **errp) =20 /* Initialize the LSI table */ for (i =3D 0; i < PCI_NUM_PINS; i++) { - uint32_t irq; + uint32_t irq =3D SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + = i; Error *local_err =3D NULL; =20 - irq =3D spapr_irq_findone(spapr, &local_err); - if (local_err) { - error_propagate(errp, local_err); - error_prepend(errp, "can't allocate LSIs: "); - return; + if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { + irq =3D spapr_irq_findone(spapr, &local_err); + if (local_err) { + error_propagate(errp, local_err); + error_prepend(errp, "can't allocate LSIs: "); + return; + } } =20 spapr_irq_claim(spapr, irq, true, &local_err); @@ -2123,6 +2137,7 @@ int spapr_populate_pci_dt(sPAPRPHBState *phb, _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); + /* TODO: fine tune the total count of allocatable MSIs per PHB */ _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS_SPA= PR)); =20 /* Dynamic DMA window */ diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c index be9af71437cc..840d4a3c451c 100644 --- a/hw/ppc/spapr_vio.c +++ b/hw/ppc/spapr_vio.c @@ -37,12 +37,13 @@ =20 #include "hw/ppc/spapr.h" #include "hw/ppc/spapr_vio.h" -#include "hw/ppc/xics.h" #include "hw/ppc/fdt.h" #include "trace.h" =20 #include =20 +#define SPAPR_VIO_REG_BASE 0x71000000 + static void spapr_vio_get_irq(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -445,6 +446,55 @@ static void spapr_vio_busdev_reset(DeviceState *qdev) } } =20 +/* + * The register property of a VIO device is defined in livirt using + * 0x1000 as a base register number plus a 0x1000 increment. For the + * VIO tty device, the base number is changed to 0x30000000. QEMU uses + * a base register number of 0x71000000 and then a simple increment. + * + * The formula below tries to compute a unique index number from the + * register value that will be used to define the IRQ number of the + * VIO device. + * + * A maximum of 256 VIO devices is covered. Collisions are possible + * but they will be detected when the IRQ is claimed. + */ +static inline uint32_t spapr_vio_reg_to_irq(uint32_t reg) +{ + uint32_t irq; + + if (reg >=3D SPAPR_VIO_REG_BASE) { + /* + * VIO device register values when allocated by QEMU. For + * these, we simply mask the high bits to fit the overall + * range: [0x00 - 0xff]. + * + * The nvram VIO device (reg=3D0x71000000) is a static device of + * the pseries machine and so is always allocated by QEMU. Its + * IRQ number is 0x0. + */ + irq =3D reg & 0xff; + + } else if (reg >=3D 0x30000000) { + /* + * VIO tty devices register values, when allocated by livirt, + * are mapped in range [0xf0 - 0xff], gives us a maximum of 16 + * vtys. + */ + irq =3D 0xf0 | ((reg >> 12) & 0xf); + + } else { + /* + * Other VIO devices register values, when allocated by + * livirt, should be mapped in range [0x00 - 0xef]. Conflicts + * will be detected when IRQ is claimed. + */ + irq =3D (reg >> 12) & 0xff; + } + + return SPAPR_IRQ_VIO | irq; +} + static void spapr_vio_busdev_realize(DeviceState *qdev, Error **errp) { sPAPRMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); @@ -485,10 +535,14 @@ static void spapr_vio_busdev_realize(DeviceState *qde= v, Error **errp) } =20 if (!dev->irq) { - dev->irq =3D spapr_irq_findone(spapr, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; + dev->irq =3D spapr_vio_reg_to_irq(dev->reg); + + if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { + dev->irq =3D spapr_irq_findone(spapr, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } } } =20 @@ -557,7 +611,7 @@ VIOsPAPRBus *spapr_vio_bus_init(void) /* Create bus on bridge device */ qbus =3D qbus_create(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio"); bus =3D SPAPR_VIO_BUS(qbus); - bus->next_reg =3D 0x71000000; + bus->next_reg =3D SPAPR_VIO_REG_BASE; =20 /* hcall-vio */ spapr_register_hypercall(H_VIO_SIGNAL, h_vio_signal); diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs index bcab6323b7ed..4ab556467289 100644 --- a/hw/ppc/Makefile.objs +++ b/hw/ppc/Makefile.objs @@ -4,7 +4,7 @@ obj-y +=3D ppc.o ppc_booke.o fdt.o obj-$(CONFIG_PSERIES) +=3D spapr.o spapr_caps.o spapr_vio.o spapr_events.o obj-$(CONFIG_PSERIES) +=3D spapr_hcall.o spapr_iommu.o spapr_rtas.o obj-$(CONFIG_PSERIES) +=3D spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng.o -obj-$(CONFIG_PSERIES) +=3D spapr_cpu_core.o spapr_ovec.o +obj-$(CONFIG_PSERIES) +=3D spapr_cpu_core.o spapr_ovec.o spapr_irq.o # IBM PowerNV obj-$(CONFIG_POWERNV) +=3D pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.= o pnv_occ.o pnv_bmc.o ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy) --=20 2.17.1 From nobody Fri May 10 15:50:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153296017969189.80001591149005; Mon, 30 Jul 2018 07:16:19 -0700 (PDT) Received: from localhost ([::1]:52868 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fk8yA-0008Fg-De for importer@patchew.org; Mon, 30 Jul 2018 10:16:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56683) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fk8u6-0004w4-UJ for qemu-devel@nongnu.org; Mon, 30 Jul 2018 10:12:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fk8u2-0005bs-1d for qemu-devel@nongnu.org; Mon, 30 Jul 2018 10:12:06 -0400 Received: from 6.mo178.mail-out.ovh.net ([46.105.53.132]:48940) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fk8u1-0005bE-MT for qemu-devel@nongnu.org; Mon, 30 Jul 2018 10:12:01 -0400 Received: from player787.ha.ovh.net (unknown [10.109.159.139]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id 307241DEC4 for ; Mon, 30 Jul 2018 16:11:59 +0200 (CEST) Received: from zorba.kaod.org.com (bad36-1-78-202-132-1.fbx.proxad.net [78.202.132.1]) (Authenticated sender: clg@kaod.org) by player787.ha.ovh.net (Postfix) with ESMTPSA id 951F66000A4; Mon, 30 Jul 2018 16:11:54 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Mon, 30 Jul 2018 16:11:33 +0200 Message-Id: <20180730141134.31153-4-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180730141134.31153-1-clg@kaod.org> References: <20180730141134.31153-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2066870757030136806 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtiedrkeejgdeilecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.53.132 Subject: [Qemu-devel] [PATCH v6 3/4] spapr: introduce a IRQ controller backend to the machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This proposal moves all the related IRQ routines of the sPAPR machine behind a sPAPR IRQ backend interface 'spapr_irq' to prepare for future changes. First of which will be to increase the size of the IRQ number space, then, will follow a new backend for the POWER9 XIVE IRQ controller. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- include/hw/ppc/spapr.h | 11 +- include/hw/ppc/spapr_irq.h | 22 ++++ hw/ppc/spapr.c | 180 +---------------------------- hw/ppc/spapr_cpu_core.c | 1 + hw/ppc/spapr_irq.c | 230 +++++++++++++++++++++++++++++++++++++ 5 files changed, 259 insertions(+), 185 deletions(-) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 73067f5ee8aa..ad4d7cfd97b0 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -4,7 +4,6 @@ #include "qemu/units.h" #include "sysemu/dma.h" #include "hw/boards.h" -#include "hw/ppc/xics.h" #include "hw/ppc/spapr_drc.h" #include "hw/mem/pc-dimm.h" #include "hw/ppc/spapr_ovec.h" @@ -16,6 +15,7 @@ struct sPAPRNVRAM; typedef struct sPAPREventLogEntry sPAPREventLogEntry; typedef struct sPAPREventSource sPAPREventSource; typedef struct sPAPRPendingHPT sPAPRPendingHPT; +typedef struct ICSState ICSState; =20 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL #define SPAPR_ENTRY_POINT 0x100 @@ -110,6 +110,7 @@ struct sPAPRMachineClass { unsigned n_dma, uint32_t *liobns, Error **errp); sPAPRResizeHPT resize_hpt_default; sPAPRCapabilities default_caps; + sPAPRIrq *irq; }; =20 /** @@ -780,14 +781,6 @@ int spapr_get_vcpu_id(PowerPCCPU *cpu); void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); PowerPCCPU *spapr_find_cpu(int vcpu_id); =20 -int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, - Error **errp); -#define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, err= p) -int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **e= rrp); -void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num); -qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq); - - int spapr_caps_pre_load(void *opaque); int spapr_caps_pre_save(void *opaque); =20 diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 6f7f50548809..0e98c4474bb2 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -29,4 +29,26 @@ int spapr_irq_msi_alloc(sPAPRMachineState *spapr, uint32= _t num, bool align, void spapr_irq_msi_free(sPAPRMachineState *spapr, int irq, uint32_t num); void spapr_irq_msi_reset(sPAPRMachineState *spapr); =20 +typedef struct sPAPRIrq { + uint32_t nr_irqs; + + void (*init)(sPAPRMachineState *spapr, Error **errp); + int (*claim)(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp= ); + void (*free)(sPAPRMachineState *spapr, int irq, int num); + qemu_irq (*qirq)(sPAPRMachineState *spapr, int irq); + void (*print_info)(sPAPRMachineState *spapr, Monitor *mon); +} sPAPRIrq; + +extern sPAPRIrq spapr_irq_xics; + +int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **e= rrp); +void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num); +qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq); + +/* + * XICS legacy routines + */ +int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **= errp); +#define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, err= p) + #endif diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 792e24453d8b..d9f8cca49208 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -54,7 +54,6 @@ #include "hw/ppc/spapr.h" #include "hw/ppc/spapr_vio.h" #include "hw/pci-host/spapr.h" -#include "hw/ppc/xics.h" #include "hw/pci/msi.h" =20 #include "hw/pci/pci.h" @@ -117,33 +116,6 @@ static bool spapr_is_thread0_in_vcore(sPAPRMachineStat= e *spapr, return spapr_get_vcpu_id(cpu) % spapr->vsmt =3D=3D 0; } =20 -static ICSState *spapr_ics_create(sPAPRMachineState *spapr, - const char *type_ics, - int nr_irqs, Error **errp) -{ - Error *local_err =3D NULL; - Object *obj; - - obj =3D object_new(type_ics); - object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); - object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), - &error_abort); - object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); - if (local_err) { - goto error; - } - object_property_set_bool(obj, true, "realized", &local_err); - if (local_err) { - goto error; - } - - return ICS_BASE(obj); - -error: - error_propagate(errp, local_err); - return NULL; -} - static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) { /* Dummy entries correspond to unused ICPState objects in older QEMUs, @@ -184,43 +156,6 @@ static int xics_max_server_number(sPAPRMachineState *s= papr) return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); } =20 -static void xics_system_init(MachineState *machine, int nr_irqs, Error **e= rrp) -{ - sPAPRMachineState *spapr =3D SPAPR_MACHINE(machine); - Error *local_err =3D NULL; - - /* Initialize the MSI IRQ allocator. */ - if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { - spapr_irq_msi_init(spapr, XICS_IRQ_BASE + nr_irqs - SPAPR_IRQ_MSI); - } - - if (kvm_enabled()) { - if (machine_kernel_irqchip_allowed(machine) && - !xics_kvm_init(spapr, &local_err)) { - spapr->icp_type =3D TYPE_KVM_ICP; - spapr->ics =3D spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, - &local_err); - } - if (machine_kernel_irqchip_required(machine) && !spapr->ics) { - error_prepend(&local_err, - "kernel_irqchip requested but unavailable: "); - goto error; - } - error_free(local_err); - local_err =3D NULL; - } - - if (!spapr->ics) { - xics_spapr_init(spapr); - spapr->icp_type =3D TYPE_ICP; - spapr->ics =3D spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, - &local_err); - } - -error: - error_propagate(errp, local_err); -} - static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, int smt_threads) { @@ -2618,7 +2553,7 @@ static void spapr_machine_init(MachineState *machine) load_limit =3D MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; =20 /* Set up Interrupt Controller before we create the VCPUs */ - xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); + smc->irq->init(spapr, &error_fatal); =20 /* Set up containers for ibm,client-architecture-support negotiated op= tions */ @@ -3810,121 +3745,13 @@ static ICPState *spapr_icp_get(XICSFabric *xi, int= vcpu_id) return cpu ? ICP(cpu->intc) : NULL; } =20 -#define ICS_IRQ_FREE(ics, srcno) \ - (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) - -static int ics_find_free_block(ICSState *ics, int num, int alignnum) -{ - int first, i; - - for (first =3D 0; first < ics->nr_irqs; first +=3D alignnum) { - if (num > (ics->nr_irqs - first)) { - return -1; - } - for (i =3D first; i < first + num; ++i) { - if (!ICS_IRQ_FREE(ics, i)) { - break; - } - } - if (i =3D=3D (first + num)) { - return first; - } - } - - return -1; -} - -int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **= errp) -{ - ICSState *ics =3D spapr->ics; - int first =3D -1; - - assert(ics); - - /* - * MSIMesage::data is used for storing VIRQ so - * it has to be aligned to num to support multiple - * MSI vectors. MSI-X is not affected by this. - * The hint is used for the first IRQ, the rest should - * be allocated continuously. - */ - if (align) { - assert((num =3D=3D 1) || (num =3D=3D 2) || (num =3D=3D 4) || - (num =3D=3D 8) || (num =3D=3D 16) || (num =3D=3D 32)); - first =3D ics_find_free_block(ics, num, num); - } else { - first =3D ics_find_free_block(ics, num, 1); - } - - if (first < 0) { - error_setg(errp, "can't find a free %d-IRQ block", num); - return -1; - } - - return first + ics->offset; -} - -int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **e= rrp) -{ - ICSState *ics =3D spapr->ics; - - assert(ics); - - if (!ics_valid_irq(ics, irq)) { - error_setg(errp, "IRQ %d is invalid", irq); - return -1; - } - - if (!ICS_IRQ_FREE(ics, irq - ics->offset)) { - error_setg(errp, "IRQ %d is not free", irq); - return -1; - } - - ics_set_irq_type(ics, irq - ics->offset, lsi); - return 0; -} - -void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num) -{ - ICSState *ics =3D spapr->ics; - int srcno =3D irq - ics->offset; - int i; - - if (ics_valid_irq(ics, irq)) { - trace_spapr_irq_free(0, irq, num); - for (i =3D srcno; i < srcno + num; ++i) { - if (ICS_IRQ_FREE(ics, i)) { - trace_spapr_irq_free_warn(0, i + ics->offset); - } - memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); - } - } -} - -qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq) -{ - ICSState *ics =3D spapr->ics; - - if (ics_valid_irq(ics, irq)) { - return ics->qirqs[irq - ics->offset]; - } - - return NULL; -} - static void spapr_pic_print_info(InterruptStatsProvider *obj, Monitor *mon) { sPAPRMachineState *spapr =3D SPAPR_MACHINE(obj); - CPUState *cs; - - CPU_FOREACH(cs) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - - icp_pic_print_info(ICP(cpu->intc), mon); - } + sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); =20 - ics_pic_print_info(spapr->ics, mon); + smc->irq->print_info(spapr, mon); } =20 int spapr_get_vcpu_id(PowerPCCPU *cpu) @@ -4036,6 +3863,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) smc->default_caps.caps[SPAPR_CAP_IBS] =3D SPAPR_CAP_BROKEN; smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] =3D 16; /* 64kiB */ spapr_caps_add_properties(smc, &error_abort); + smc->irq =3D &spapr_irq_xics; } =20 static const TypeInfo spapr_machine_info =3D { diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 993759db47fa..fb091995a11f 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -11,6 +11,7 @@ #include "hw/ppc/spapr_cpu_core.h" #include "target/ppc/cpu.h" #include "hw/ppc/spapr.h" +#include "hw/ppc/xics.h" /* for icp_create() - to be removed */ #include "hw/boards.h" #include "qapi/error.h" #include "sysemu/cpus.h" diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 24e9c1d4433c..0cbb5dd39368 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -13,6 +13,9 @@ #include "qapi/error.h" #include "hw/ppc/spapr.h" #include "hw/ppc/xics.h" +#include "sysemu/kvm.h" + +#include "trace.h" =20 void spapr_irq_msi_init(sPAPRMachineState *spapr, uint32_t nr_msis) { @@ -54,3 +57,230 @@ void spapr_irq_msi_reset(sPAPRMachineState *spapr) { bitmap_clear(spapr->irq_map, 0, spapr->irq_map_nr); } + + +/* + * XICS IRQ backend. + */ + +static ICSState *spapr_ics_create(sPAPRMachineState *spapr, + const char *type_ics, + int nr_irqs, Error **errp) +{ + Error *local_err =3D NULL; + Object *obj; + + obj =3D object_new(type_ics); + object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); + object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), + &error_abort); + object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); + if (local_err) { + goto error; + } + object_property_set_bool(obj, true, "realized", &local_err); + if (local_err) { + goto error; + } + + return ICS_BASE(obj); + +error: + error_propagate(errp, local_err); + return NULL; +} + +static void spapr_irq_init_xics(sPAPRMachineState *spapr, Error **errp) +{ + MachineState *machine =3D MACHINE(spapr); + sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); + int nr_irqs =3D smc->irq->nr_irqs; + Error *local_err =3D NULL; + + /* Initialize the MSI IRQ allocator. */ + if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { + spapr_irq_msi_init(spapr, XICS_IRQ_BASE + nr_irqs - SPAPR_IRQ_MSI); + } + + if (kvm_enabled()) { + if (machine_kernel_irqchip_allowed(machine) && + !xics_kvm_init(spapr, &local_err)) { + spapr->icp_type =3D TYPE_KVM_ICP; + spapr->ics =3D spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, + &local_err); + } + if (machine_kernel_irqchip_required(machine) && !spapr->ics) { + error_prepend(&local_err, + "kernel_irqchip requested but unavailable: "); + goto error; + } + error_free(local_err); + local_err =3D NULL; + } + + if (!spapr->ics) { + xics_spapr_init(spapr); + spapr->icp_type =3D TYPE_ICP; + spapr->ics =3D spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, + &local_err); + } + +error: + error_propagate(errp, local_err); +} + +#define ICS_IRQ_FREE(ics, srcno) \ + (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) + +static int spapr_irq_claim_xics(sPAPRMachineState *spapr, int irq, bool ls= i, + Error **errp) +{ + ICSState *ics =3D spapr->ics; + + assert(ics); + + if (!ics_valid_irq(ics, irq)) { + error_setg(errp, "IRQ %d is invalid", irq); + return -1; + } + + if (!ICS_IRQ_FREE(ics, irq - ics->offset)) { + error_setg(errp, "IRQ %d is not free", irq); + return -1; + } + + ics_set_irq_type(ics, irq - ics->offset, lsi); + return 0; +} + +static void spapr_irq_free_xics(sPAPRMachineState *spapr, int irq, int num) +{ + ICSState *ics =3D spapr->ics; + uint32_t srcno =3D irq - ics->offset; + int i; + + if (ics_valid_irq(ics, irq)) { + trace_spapr_irq_free(0, irq, num); + for (i =3D srcno; i < srcno + num; ++i) { + if (ICS_IRQ_FREE(ics, i)) { + trace_spapr_irq_free_warn(0, i); + } + memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); + } + } +} + +static qemu_irq spapr_qirq_xics(sPAPRMachineState *spapr, int irq) +{ + ICSState *ics =3D spapr->ics; + uint32_t srcno =3D irq - ics->offset; + + if (ics_valid_irq(ics, irq)) { + return ics->qirqs[srcno]; + } + + return NULL; +} + +static void spapr_irq_print_info_xics(sPAPRMachineState *spapr, Monitor *m= on) +{ + CPUState *cs; + + CPU_FOREACH(cs) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + + icp_pic_print_info(ICP(cpu->intc), mon); + } + + ics_pic_print_info(spapr->ics, mon); +} + +sPAPRIrq spapr_irq_xics =3D { + .nr_irqs =3D XICS_IRQS_SPAPR, + + .init =3D spapr_irq_init_xics, + .claim =3D spapr_irq_claim_xics, + .free =3D spapr_irq_free_xics, + .qirq =3D spapr_qirq_xics, + .print_info =3D spapr_irq_print_info_xics, +}; + +/* + * sPAPR IRQ frontend routines for devices + */ + +int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **e= rrp) +{ + sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); + + return smc->irq->claim(spapr, irq, lsi, errp); +} + +void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num) +{ + sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); + + smc->irq->free(spapr, irq, num); +} + +qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq) +{ + sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); + + return smc->irq->qirq(spapr, irq); +} + +/* + * XICS legacy routines - to deprecate one day + */ + +static int ics_find_free_block(ICSState *ics, int num, int alignnum) +{ + int first, i; + + for (first =3D 0; first < ics->nr_irqs; first +=3D alignnum) { + if (num > (ics->nr_irqs - first)) { + return -1; + } + for (i =3D first; i < first + num; ++i) { + if (!ICS_IRQ_FREE(ics, i)) { + break; + } + } + if (i =3D=3D (first + num)) { + return first; + } + } + + return -1; +} + +int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **= errp) +{ + ICSState *ics =3D spapr->ics; + int first =3D -1; + + assert(ics); + + /* + * MSIMesage::data is used for storing VIRQ so + * it has to be aligned to num to support multiple + * MSI vectors. MSI-X is not affected by this. + * The hint is used for the first IRQ, the rest should + * be allocated continuously. + */ + if (align) { + assert((num =3D=3D 1) || (num =3D=3D 2) || (num =3D=3D 4) || + (num =3D=3D 8) || (num =3D=3D 16) || (num =3D=3D 32)); + first =3D ics_find_free_block(ics, num, num); + } else { + first =3D ics_find_free_block(ics, num, 1); + } + + if (first < 0) { + error_setg(errp, "can't find a free %d-IRQ block", num); + return -1; + } + + return first + ics->offset; +} --=20 2.17.1 From nobody Fri May 10 15:50:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532960313815813.7969720300051; Mon, 30 Jul 2018 07:18:33 -0700 (PDT) Received: from localhost ([::1]:52875 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fk90K-0000yq-OB for importer@patchew.org; Mon, 30 Jul 2018 10:18:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56740) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fk8uC-0004zl-JR for qemu-devel@nongnu.org; Mon, 30 Jul 2018 10:12:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fk8u7-0005fE-Py for qemu-devel@nongnu.org; Mon, 30 Jul 2018 10:12:12 -0400 Received: from 7.mo7.mail-out.ovh.net ([46.105.43.131]:57326) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fk8u7-0005e3-HY for qemu-devel@nongnu.org; Mon, 30 Jul 2018 10:12:07 -0400 Received: from player787.ha.ovh.net (unknown [10.109.146.5]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 1C028B97F3 for ; Mon, 30 Jul 2018 16:12:05 +0200 (CEST) Received: from zorba.kaod.org.com (bad36-1-78-202-132-1.fbx.proxad.net [78.202.132.1]) (Authenticated sender: clg@kaod.org) by player787.ha.ovh.net (Postfix) with ESMTPSA id C73F76000A4; Mon, 30 Jul 2018 16:11:59 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Mon, 30 Jul 2018 16:11:34 +0200 Message-Id: <20180730141134.31153-5-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180730141134.31153-1-clg@kaod.org> References: <20180730141134.31153-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2068278129260923878 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtiedrkeejgdejudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.43.131 Subject: [Qemu-devel] [PATCH v6 4/4] spapr: increase the size of the IRQ number space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The new layout using static IRQ number does not leave much space to the dynamic MSI range, only 0x100 IRQ numbers. Increase the total number of IRQS for newer machines and introduce a legacy XICS backend for pre-3.1 machines to maintain compatibility. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/spapr_irq.h | 1 + hw/ppc/spapr.c | 1 + hw/ppc/spapr_irq.c | 12 +++++++++++- 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 0e98c4474bb2..626160ba475e 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -40,6 +40,7 @@ typedef struct sPAPRIrq { } sPAPRIrq; =20 extern sPAPRIrq spapr_irq_xics; +extern sPAPRIrq spapr_irq_xics_legacy; =20 int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **e= rrp); void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num); diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index d9f8cca49208..5ae62b0682d2 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3947,6 +3947,7 @@ static void spapr_machine_3_0_class_options(MachineCl= ass *mc) SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_3_0); =20 smc->legacy_irq_allocation =3D true; + smc->irq =3D &spapr_irq_xics_legacy; } =20 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 0cbb5dd39368..620c49b38455 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -196,7 +196,7 @@ static void spapr_irq_print_info_xics(sPAPRMachineState= *spapr, Monitor *mon) } =20 sPAPRIrq spapr_irq_xics =3D { - .nr_irqs =3D XICS_IRQS_SPAPR, + .nr_irqs =3D 0x1000, =20 .init =3D spapr_irq_init_xics, .claim =3D spapr_irq_claim_xics, @@ -284,3 +284,13 @@ int spapr_irq_find(sPAPRMachineState *spapr, int num, = bool align, Error **errp) =20 return first + ics->offset; } + +sPAPRIrq spapr_irq_xics_legacy =3D { + .nr_irqs =3D XICS_IRQS_SPAPR, + + .init =3D spapr_irq_init_xics, + .claim =3D spapr_irq_claim_xics, + .free =3D spapr_irq_free_xics, + .qirq =3D spapr_qirq_xics, + .print_info =3D spapr_irq_print_info_xics, +}; --=20 2.17.1