From nobody Sat May 4 16:01:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530829406337398.3117815380365; Thu, 5 Jul 2018 15:23:26 -0700 (PDT) Received: from localhost ([::1]:55021 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fbCel-00007z-DH for importer@patchew.org; Thu, 05 Jul 2018 18:23:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40240) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fbCdB-0007jC-5s for qemu-devel@nongnu.org; Thu, 05 Jul 2018 18:21:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fbCd9-0003ag-Uw for qemu-devel@nongnu.org; Thu, 05 Jul 2018 18:21:41 -0400 Received: from smtp32.i.mail.ru ([94.100.177.92]:44746) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fbCd9-0003ZX-Mm for qemu-devel@nongnu.org; Thu, 05 Jul 2018 18:21:39 -0400 Received: by smtp32.i.mail.ru with esmtpa (envelope-from ) id 1fbCd7-0006AF-W5; Fri, 06 Jul 2018 01:21:38 +0300 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=s+fiXGnalHenHQl4j9Q422jPCmwUb9Alw5NtoImnrTA=; b=bXfQx6ydxJQ0dGkDG0MPPxTNRwVwWZpg7PTLEOj3+nqDhrurDCRFkTAXnGiqkwkHjf/2jgG8/Nzp8uyJYdAS9zJSF511Ut/6R0FKjQdsAjyporrfU5Bn7yUJxm2bvvRhaXRe+NUf+NsluaIOpVSq4b+rE/FXhvo9aY7O2ccZkqE=; To: qemu-devel@nongnu.org Date: Fri, 6 Jul 2018 01:21:14 +0300 Message-Id: <20180705222115.17013-2-jusual@mail.ru> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180705222115.17013-1-jusual@mail.ru> References: <20180705222115.17013-1-jusual@mail.ru> Authentication-Results: smtp32.i.mail.ru; auth=pass smtp.auth=jusual@mail.ru smtp.mailfrom=jusual@mail.ru X-7FA49CB5: 0D63561A33F958A5BDAC135BB289C00681F87543B3A29360F8932D5BCF88BCDB0A6AB1C7CE11FEE35EF3C447179F0106BA3038C0950A5D36B5C8C57E37DE458B4C7702A67D5C33162DBA43225CD8A89F9FFED5BD9FB417554D4E1E404F4A93BEF5AD0C9FECD3D6B843847C11F186F3C5E7DDDDC251EA7DABCC89B49CDF41148FFC2B27DE93B9EBF03B503F486389A921A5CC5B56E945C8DA X-Mailru-Sender: 7766D515518070DE138AAC7428EA760D63B09624B1CDFBFBA767218002104F5E0E686DC7B565B70A7C4160E8B47E48163DDE9B364B0DF2898CB68AF7A628805D594FB4C9F0DBF412AE208404248635DF X-Mras: OK X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 94.100.177.92 Subject: [Qemu-devel] [PATCH v3 1/2] nvic: Handle ARMv6-M SCS reserved registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Julia Suvorova via Qemu-devel Reply-To: Julia Suvorova Cc: Peter Maydell , Jim Mussared , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Joel Stanley , Stefan Hajnoczi , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1. All reserved registers are RAZ/WI. ARM_FEATURE_M_MAIN is used for the checks, because these registers are reserved in ARMv8-M Baseline too. Signed-off-by: Julia Suvorova Reviewed-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 51 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index aba4510c70..7f71b336bd 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -865,6 +865,9 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offse= t, MemTxAttrs attrs) } return val; case 0xd10: /* System Control. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { + goto bad_offset; + } return cpu->env.v7m.scr[attrs.secure]; case 0xd14: /* Configuration Control. */ /* The BFHFNMIGN bit is the only non-banked bit; we @@ -986,12 +989,21 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) } return val; case 0xd2c: /* Hard Fault Status. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->env.v7m.hfsr; case 0xd30: /* Debug Fault Status. */ return cpu->env.v7m.dfsr; case 0xd34: /* MMFAR MemManage Fault Address */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->env.v7m.mmfar[attrs.secure]; case 0xd38: /* Bus Fault Address. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->env.v7m.bfar; case 0xd3c: /* Aux Fault Status. */ /* TODO: Implement fault status registers. */ @@ -1287,6 +1299,9 @@ static void nvic_writel(NVICState *s, uint32_t offset= , uint32_t value, } break; case 0xd10: /* System Control. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { + goto bad_offset; + } /* We don't implement deep-sleep so these bits are RAZ/WI. * The other bits in the register are banked. * QEMU's implementation ignores SEVONPEND and SLEEPONEXIT, which @@ -1388,15 +1403,24 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, nvic_irq_update(s); break; case 0xd2c: /* Hard Fault Status. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } cpu->env.v7m.hfsr &=3D ~value; /* W1C */ break; case 0xd30: /* Debug Fault Status. */ cpu->env.v7m.dfsr &=3D ~value; /* W1C */ break; case 0xd34: /* Mem Manage Address. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } cpu->env.v7m.mmfar[attrs.secure] =3D value; return; case 0xd38: /* Bus Fault Address. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } cpu->env.v7m.bfar =3D value; return; case 0xd3c: /* Aux Fault Status. */ @@ -1626,6 +1650,11 @@ static void nvic_writel(NVICState *s, uint32_t offse= t, uint32_t value, case 0xf00: /* Software Triggered Interrupt Register */ { int excnum =3D (value & 0x1ff) + NVIC_FIRST_IRQ; + + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } + if (excnum < s->num_irq) { armv7m_nvic_set_pending(s, excnum, false); } @@ -1775,7 +1804,13 @@ static MemTxResult nvic_sysreg_read(void *opaque, hw= addr addr, } } break; - case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3)= */ + case 0xd18: /* System Handler Priority (SHPR1) */ + if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { + val =3D 0; + break; + } + /* fall through */ + case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */ val =3D 0; for (i =3D 0; i < size; i++) { unsigned hdlidx =3D (offset - 0xd14) + i; @@ -1788,6 +1823,10 @@ static MemTxResult nvic_sysreg_read(void *opaque, hw= addr addr, } break; case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */ + if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { + val =3D 0; + break; + }; /* The BFSR bits [15:8] are shared between security states * and we store them in the NS copy */ @@ -1882,7 +1921,12 @@ static MemTxResult nvic_sysreg_write(void *opaque, h= waddr addr, } nvic_irq_update(s); return MEMTX_OK; - case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3)= */ + case 0xd18: /* System Handler Priority (SHPR1) */ + if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { + return MEMTX_OK; + } + /* fall through */ + case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */ for (i =3D 0; i < size; i++) { unsigned hdlidx =3D (offset - 0xd14) + i; int newprio =3D extract32(value, i * 8, 8); @@ -1896,6 +1940,9 @@ static MemTxResult nvic_sysreg_write(void *opaque, hw= addr addr, nvic_irq_update(s); return MEMTX_OK; case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */ + if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { + return MEMTX_OK; + } /* All bits are W1C, so construct 32 bit value with 0s in * the parts not written by the access size */ --=20 2.17.1 From nobody Sat May 4 16:01:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530829406172331.3823661550414; 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s=mail2; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=Iqwgw1AmpCeOMK+FtjGhwZzlNEyu93a52V80bEbwa9Q=; b=ulPD6Hu1c8TVNEGe+DhOZy5Pp+n51afIBzGsDl7c0Ve5PP0wAm+6m3CnPyXagoNyORdvMhmwlEMfe74bxk4YnhQik9G4X4VNDS3HtMH3HjrR64VYGLr9tPpwB2SyIhgwhwWmNF9Zsr/dULBpzMxVlbnWkKZmxuCdECpcoX34O7E=; To: qemu-devel@nongnu.org Date: Fri, 6 Jul 2018 01:21:15 +0300 Message-Id: <20180705222115.17013-3-jusual@mail.ru> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180705222115.17013-1-jusual@mail.ru> References: <20180705222115.17013-1-jusual@mail.ru> Authentication-Results: smtp32.i.mail.ru; auth=pass smtp.auth=jusual@mail.ru smtp.mailfrom=jusual@mail.ru X-7FA49CB5: 0D63561A33F958A5B72FE8CCDEBB47FA81F87543B3A29360BDC0DCA081F5CECE0A6AB1C7CE11FEE35EF3C447179F0106BA3038C0950A5D36B5C8C57E37DE458B4C7702A67D5C33162DBA43225CD8A89F9FFED5BD9FB417556A3B6BD506CCC113C2EEAE1A4D735BFE43847C11F186F3C5E7DDDDC251EA7DABCC89B49CDF41148FFC2B27DE93B9EBF03B503F486389A921A5CC5B56E945C8DA X-Mailru-Sender: 7766D515518070DE138AAC7428EA760D19C4AEEC1B7D013EEB62ACA2B0A389F67B57453E6972826A7C4160E8B47E48163DDE9B364B0DF2898CB68AF7A628805D594FB4C9F0DBF412AE208404248635DF X-Mras: OK X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 94.100.177.92 Subject: [Qemu-devel] [RFC v3 2/2] tests: Add ARMv6-M reserved register test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Julia Suvorova via Qemu-devel Reply-To: Julia Suvorova Cc: Peter Maydell , Jim Mussared , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Joel Stanley , Stefan Hajnoczi , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Check that reserved SCS registers return 0 at read, and writes are ignored. Based-on: <20180627143815.1829-1-joel@jms.id.au> Based-on: <20180630091343.14391-1-stefanha@redhat.com> Signed-off-by: Julia Suvorova --- Test will work if Joel's patches will use ARMv6-M. tests/Makefile.include | 2 ++ tests/tcg/arm/test-reserved-reg.c | 60 +++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) create mode 100644 tests/tcg/arm/test-reserved-reg.c diff --git a/tests/Makefile.include b/tests/Makefile.include index d323c42682..8ab0b0d15f 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -387,6 +387,7 @@ gcov-files-arm-y +=3D hw/timer/arm_mptimer.c check-qtest-arm-y +=3D tests/boot-serial-test$(EXESUF) check-qtest-arm-y +=3D tests/sdhci-test$(EXESUF) check-qtest-arm-y +=3D tests/hexloader-test$(EXESUF) +check-qtest-arm-y +=3D tests/tcg/arm/test-reserved-reg$(EXESUF) =20 check-qtest-aarch64-y =3D tests/numa-test$(EXESUF) check-qtest-aarch64-y +=3D tests/sdhci-test$(EXESUF) @@ -771,6 +772,7 @@ tests/device-introspect-test$(EXESUF): tests/device-int= rospect-test.o tests/rtc-test$(EXESUF): tests/rtc-test.o tests/m48t59-test$(EXESUF): tests/m48t59-test.o tests/hexloader-test$(EXESUF): tests/hexloader-test.o +tests/test-reserved-reg$(EXESUF): tests/tcg/arm/test-reserved-reg.o tests/endianness-test$(EXESUF): tests/endianness-test.o tests/spapr-phb-test$(EXESUF): tests/spapr-phb-test.o $(libqos-obj-y) tests/prom-env-test$(EXESUF): tests/prom-env-test.o $(libqos-obj-y) diff --git a/tests/tcg/arm/test-reserved-reg.c b/tests/tcg/arm/test-reserve= d-reg.c new file mode 100644 index 0000000000..97273ff24d --- /dev/null +++ b/tests/tcg/arm/test-reserved-reg.c @@ -0,0 +1,60 @@ +/* + * Test ARMv6-M SCS reserved registers + * + * Copyright (c) 2018 Julia Suvorova + * + * This work is licensed under the terms of the GNU GPL, version 2 + * or later. See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "libqtest.h" + +static void test_reserved_reg(void) +{ + QTestState *s; + int i; + static const uint64_t reserved_reg[] =3D { 0xe000ed10, /* SCR */ + 0xe000ed18, /* SHPR1 */ + 0xe000ed28, /* CFSR */ + 0xe000ed2c, /* HFSR */ + 0xe000ed34, /* MMFAR */ + 0xe000ed38, /* BFAR */ + 0xe000ed3c, /* AFSR */ + 0xe000ed40, /* CPUID */ + 0xe000ed88, /* CPACR */ + 0xe000ef00 /* STIR */ }; + static const uint8_t mini_kernel[] =3D { 0x00, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00 }; + ssize_t wlen, kernel_size =3D sizeof(mini_kernel); + int code_fd; + char codetmp[] =3D "/tmp/reserved-reg-test-XXXXXX"; + + code_fd =3D mkstemp(codetmp); + wlen =3D write(code_fd, mini_kernel, sizeof(mini_kernel)); + g_assert(wlen =3D=3D kernel_size); + close(code_fd); + + s =3D qtest_startf("-kernel %s -M microbit -nographic", codetmp); + + for (i =3D 0; i < ARRAY_SIZE(reserved_reg); i++) { + int res; + qtest_writel(s, reserved_reg[i], 1); + res =3D qtest_readl(s, reserved_reg[i]); + g_assert(!res); + } + + qtest_quit(s); +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + + qtest_add_func("tcg/arm/test-reserved-reg", test_reserved_reg); + ret =3D g_test_run(); + + return ret; +} --=20 2.17.1