From nobody Sat May 18 15:49:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=oracle.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530310863678739.5249287398156; Fri, 29 Jun 2018 15:21:03 -0700 (PDT) Received: from localhost ([::1]:44710 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fZ1lG-0002W7-Rr for importer@patchew.org; Fri, 29 Jun 2018 18:21:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42612) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fZ1jo-0001JB-LA for qemu-devel@nongnu.org; Fri, 29 Jun 2018 18:19:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fZ1jk-0007EJ-LN for qemu-devel@nongnu.org; Fri, 29 Jun 2018 18:19:32 -0400 Received: from aserp2120.oracle.com ([141.146.126.78]:40466) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fZ1jk-0007DT-DS for qemu-devel@nongnu.org; Fri, 29 Jun 2018 18:19:28 -0400 Received: from pps.filterd (aserp2120.oracle.com [127.0.0.1]) by aserp2120.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w5TMJPWd089521; Fri, 29 Jun 2018 22:19:26 GMT Received: from aserv0021.oracle.com (aserv0021.oracle.com [141.146.126.233]) by aserp2120.oracle.com with ESMTP id 2jukhsr6x1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 29 Jun 2018 22:19:26 +0000 Received: from aserv0122.oracle.com (aserv0122.oracle.com [141.146.126.236]) by aserv0021.oracle.com (8.14.4/8.14.4) with ESMTP id w5TMJQs3009873 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 29 Jun 2018 22:19:26 GMT Received: from abhmp0004.oracle.com (abhmp0004.oracle.com [141.146.116.10]) by aserv0122.oracle.com (8.14.4/8.14.4) with ESMTP id w5TMJPcx015800; Fri, 29 Jun 2018 22:19:25 GMT Received: from troi.attlocal.net (/10.154.170.104) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Fri, 29 Jun 2018 15:19:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2017-10-26; bh=bRcSCrR0eMb0pEtzuGydein6jsC4IZY5rQn6f1vJMK0=; b=LqXCgzkFjzmIg//7imV5IjP6h0rzXSiXLkFlkOQSzSOnClkdbQBS4wa+xOsCw8upvn0Q M49RlzzyGXl7ADlTGNx6ZP0WJy4JQzHoZP+eG+GPcBYX0coC9p3+zqq87xi/bvNzGnes 09JNRCC+behptpmKIfHntXLQbJ9EYUmRpNrlsgMQCH6jMj4I50eTDFwdVKnhOo9GEVo7 KTEohez5mnUPJvkkGo1PI0UD1TEZF6vowT/MTdmQo1uF7yOL8S3d8TLrJcaaq9Mwq2FT LUv9C0jNu7uLWprmbRyDicmwXVdsT6MlzIEC7C4Lw4bESs8NYWoJ84PH5Mcv55A8Usca rg== From: Venu Busireddy To: venu.busireddy@oracle.com, "Michael S . Tsirkin" , Marcel Apfelbaum Date: Fri, 29 Jun 2018 17:19:04 -0500 Message-Id: <20180629221907.3662-2-venu.busireddy@oracle.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180629221907.3662-1-venu.busireddy@oracle.com> References: <20180629221907.3662-1-venu.busireddy@oracle.com> X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=8939 signatures=668703 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1806210000 definitions=main-1806290237 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 141.146.126.78 Subject: [Qemu-devel] [PATCH v3 1/3] Add "Group Identifier" support to virtio devices. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: virtio-dev@lists.oasis-open.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use the virtio PCI capability "VIRTIO_PCI_CAP_GROUP_ID_CFG" to store the "Group Identifier" specified via the command line option "failover-group-id" for the virtio device. The capability will be present in the virtio device's configuration space iff the "failover-group-id" option is specified. Group Identifier is used to pair a virtio device with a passthrough device. Signed-off-by: Venu Busireddy --- hw/virtio/virtio-pci.c | 15 +++++++++++++++ hw/virtio/virtio-pci.h | 3 ++- include/hw/pci/pci.h | 1 + include/hw/pci/pcie.h | 1 + include/standard-headers/linux/virtio_pci.h | 8 ++++++++ 5 files changed, 27 insertions(+), 1 deletion(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 3a01fe90f0..cdf907e9c5 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1638,6 +1638,10 @@ static void virtio_pci_device_plugged(DeviceState *d= , Error **errp) .cap.cap_len =3D sizeof cfg, .cap.cfg_type =3D VIRTIO_PCI_CAP_PCI_CFG, }; + struct virtio_pci_group_id_cap group =3D { + .cap.cap_len =3D sizeof group, + .cap.cfg_type =3D VIRTIO_PCI_CAP_GROUP_ID_CFG, + }; struct virtio_pci_notify_cap notify_pio =3D { .cap.cap_len =3D sizeof notify, .notify_off_multiplier =3D cpu_to_le32(0x0), @@ -1647,6 +1651,11 @@ static void virtio_pci_device_plugged(DeviceState *d= , Error **errp) =20 virtio_pci_modern_regions_init(proxy); =20 + if (proxy->pci_dev.failover_group_id !=3D ULLONG_MAX) { + group.failover_group_id =3D proxy->pci_dev.failover_group_id; + virtio_pci_modern_mem_region_map(proxy, &proxy->group, &group.= cap); + } + virtio_pci_modern_mem_region_map(proxy, &proxy->common, &cap); virtio_pci_modern_mem_region_map(proxy, &proxy->isr, &cap); virtio_pci_modern_mem_region_map(proxy, &proxy->device, &cap); @@ -1763,6 +1772,10 @@ static void virtio_pci_realize(PCIDevice *pci_dev, E= rror **errp) proxy->device.size =3D 0x1000; proxy->device.type =3D VIRTIO_PCI_CAP_DEVICE_CFG; =20 + proxy->group.offset =3D 0; + proxy->group.size =3D 0; + proxy->group.type =3D VIRTIO_PCI_CAP_GROUP_ID_CFG; + proxy->notify.offset =3D 0x3000; proxy->notify.size =3D virtio_pci_queue_mem_mult(proxy) * VIRTIO_QUEUE= _MAX; proxy->notify.type =3D VIRTIO_PCI_CAP_NOTIFY_CFG; @@ -1898,6 +1911,8 @@ static Property virtio_pci_properties[] =3D { VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true), DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_INIT_PM_BIT, true), + DEFINE_PROP_UINT64(COMPAT_PROP_FAILOVER_GROUP_ID, + PCIDevice, failover_group_id, ULLONG_MAX), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/virtio/virtio-pci.h b/hw/virtio/virtio-pci.h index 813082b0d7..e4592e90bf 100644 --- a/hw/virtio/virtio-pci.h +++ b/hw/virtio/virtio-pci.h @@ -164,10 +164,11 @@ struct VirtIOPCIProxy { VirtIOPCIRegion common; VirtIOPCIRegion isr; VirtIOPCIRegion device; + VirtIOPCIRegion group; VirtIOPCIRegion notify; VirtIOPCIRegion notify_pio; }; - VirtIOPCIRegion regs[5]; + VirtIOPCIRegion regs[6]; }; MemoryRegion modern_bar; MemoryRegion io_bar; diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 990d6fcbde..b59c3e7e38 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -343,6 +343,7 @@ struct PCIDevice { bool has_rom; MemoryRegion rom; uint32_t rom_bar; + uint64_t failover_group_id; =20 /* INTx routing notifier */ PCIINTxRoutingNotifier intx_routing_notifier; diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index b71e369703..71cd143ee4 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -82,6 +82,7 @@ struct PCIExpressDevice { }; =20 #define COMPAT_PROP_PCP "power_controller_present" +#define COMPAT_PROP_FAILOVER_GROUP_ID "failover-group-id" =20 /* PCI express capability helper functions */ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, diff --git a/include/standard-headers/linux/virtio_pci.h b/include/standard= -headers/linux/virtio_pci.h index 9262acd130..e46df63e52 100644 --- a/include/standard-headers/linux/virtio_pci.h +++ b/include/standard-headers/linux/virtio_pci.h @@ -113,6 +113,8 @@ #define VIRTIO_PCI_CAP_DEVICE_CFG 4 /* PCI configuration access */ #define VIRTIO_PCI_CAP_PCI_CFG 5 +/* Group Identifier */ +#define VIRTIO_PCI_CAP_GROUP_ID_CFG 6 =20 /* This is the PCI capability header: */ struct virtio_pci_cap { @@ -163,6 +165,12 @@ struct virtio_pci_cfg_cap { uint8_t pci_cfg_data[4]; /* Data for BAR access. */ }; =20 +/* Fields in VIRTIO_PCI_CAP_GROUP_ID_CFG: */ +struct virtio_pci_group_id_cap { + struct virtio_pci_cap cap; + uint64_t failover_group_id; +}; + /* Macro versions of offsets for the Old Timers! */ #define VIRTIO_PCI_CAP_VNDR 0 #define VIRTIO_PCI_CAP_NEXT 1 From nobody Sat May 18 15:49:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=oracle.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530310967690725.4190796650043; Fri, 29 Jun 2018 15:22:47 -0700 (PDT) Received: from localhost ([::1]:44717 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fZ1mx-0004Hm-1e for importer@patchew.org; Fri, 29 Jun 2018 18:22:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42660) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fZ1k7-0001u5-9G for qemu-devel@nongnu.org; Fri, 29 Jun 2018 18:19:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fZ1k3-00089f-7D for qemu-devel@nongnu.org; Fri, 29 Jun 2018 18:19:51 -0400 Received: from aserp2130.oracle.com ([141.146.126.79]:50264) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fZ1k2-00088n-UW for qemu-devel@nongnu.org; Fri, 29 Jun 2018 18:19:47 -0400 Received: from pps.filterd (aserp2130.oracle.com [127.0.0.1]) by aserp2130.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w5TMJjFB083036; Fri, 29 Jun 2018 22:19:45 GMT Received: from userv0022.oracle.com (userv0022.oracle.com [156.151.31.74]) by aserp2130.oracle.com with ESMTP id 2jukmu85ws-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 29 Jun 2018 22:19:45 +0000 Received: from aserv0122.oracle.com (aserv0122.oracle.com [141.146.126.236]) by userv0022.oracle.com (8.14.4/8.14.4) with ESMTP id w5TMJhkk025469 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 29 Jun 2018 22:19:44 GMT Received: from abhmp0004.oracle.com (abhmp0004.oracle.com [141.146.116.10]) by aserv0122.oracle.com (8.14.4/8.14.4) with ESMTP id w5TMJh3a015919; Fri, 29 Jun 2018 22:19:43 GMT Received: from troi.attlocal.net (/10.154.170.104) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Fri, 29 Jun 2018 15:19:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2017-10-26; bh=8mPiuKvl/AmjGRepILqoA9VAiGyo1zgUFVnZmWIHZIM=; b=bSJteljqinXwPRLZAblk+NDRvV0y11YjDleEqg53Xbt1mV6tRLmZ/cOer3AhYZrwYvRP O+0O9tWkXU+OC0Mh8MQCYXebwMcOgjkar+MVyRa+6VcH1p/3UEGwW7IsgIGa7VQx82Mn J51zqolWP/UvPoakz47abtgAvW7+Z9QGxtVx3bIB+lqtzceTFkJEuJiSKBUaLkQZ84c7 g669deAjAXH9ewP6lh8Fa2KoXuPhqP2K4EfwLldRsmHENCj34ANMTRlyrPUqtj20LmcP dP0XGeXkDvaHgRhGb6p8BsG2Ca8fpTsYkciTQNCABes+ptbqdhiYTQgRWgPi+44JEhy2 9g== From: Venu Busireddy To: venu.busireddy@oracle.com, "Michael S . Tsirkin" , Marcel Apfelbaum Date: Fri, 29 Jun 2018 17:19:07 -0500 Message-Id: <20180629221907.3662-5-venu.busireddy@oracle.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180629221907.3662-1-venu.busireddy@oracle.com> References: <20180629221907.3662-1-venu.busireddy@oracle.com> X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=8939 signatures=668703 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=968 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1806210000 definitions=main-1806290237 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 141.146.126.79 Subject: [Qemu-devel] [PATCH v3 virtio 1/1] Add "Group Identifier" to virtio PCI capabilities. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: virtio-dev@lists.oasis-open.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add VIRTIO_PCI_CAP_GROUP_ID_CFG (Group Identifier) capability to the virtio PCI capabilities to allow for the grouping of devices. Signed-off-by: Venu Busireddy --- content.tex | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/content.tex b/content.tex index be18234..34627e5 100644 --- a/content.tex +++ b/content.tex @@ -599,6 +599,8 @@ The fields are interpreted as follows: #define VIRTIO_PCI_CAP_DEVICE_CFG 4 /* PCI configuration access */ #define VIRTIO_PCI_CAP_PCI_CFG 5 +/* Group Identifier */ +#define VIRTIO_PCI_CAP_GROUP_ID_CFG 6 \end{lstlisting} =20 Any other value is reserved for future use. @@ -997,6 +999,34 @@ address \field{cap.length} bytes within a BAR range specified by some other Virtio Structure PCI Capability of type other than \field{VIRTIO_PCI_CAP_PCI_CFG}. =20 +\subsubsection{Group Identifier capability}\label{sec:Virtio Transport Opt= ions / Virtio Over PCI Bus / PCI Device Layout / Group Identifier capabilit= y} + +The VIRTIO_PCI_CAP_GROUP_ID_CFG capability provides means for grouping +devices together. + +The capability is immediately followed by an identifier of type u64 +as below: + +\begin{lstlisting} +struct virtio_pci_group_id_cap { + struct virtio_pci_cap cap; + u64 group_id; /* Group Identifier */ +}; +\end{lstlisting} + +\devicenormative{\paragraph}{Group Identifier capability}{Virtio Transport= Options / Virtio Over PCI Bus / PCI Device Layout / Group Identifier capab= ility} + +The device MAY present the VIRTIO_PCI_CAP_GROUP_ID_CFG capability. + +When this capability is present, the device must set the fields +\field{cap.bar}, \field{cap.offset} and \field{cap.length} to 0, and +set the group_id to a unique identifier. + +\drivernormative{\paragraph}{Group Identifier capability}{Virtio Transport= Options / Virtio Over PCI Bus / PCI Device Layout / Group Identifier capab= ility} + +The fields \field{cap.bar}, \field{cap.offset}, \field{cap.length} +and \field{group_id} are read-only for the driver. + \subsubsection{Legacy Interfaces: A Note on PCI Device Layout}\label{sec:V= irtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / Legacy = Interfaces: A Note on PCI Device Layout} =20 Transitional devices MUST present part of configuration From nobody Sat May 18 15:49:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=oracle.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15303109769881012.289477749019; Fri, 29 Jun 2018 15:22:56 -0700 (PDT) Received: from localhost ([::1]:44718 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fZ1n5-0004NI-6y for importer@patchew.org; Fri, 29 Jun 2018 18:22:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42627) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fZ1jw-0001VE-UU for qemu-devel@nongnu.org; Fri, 29 Jun 2018 18:19:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fZ1js-0007Vb-RT for qemu-devel@nongnu.org; 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Fri, 29 Jun 2018 22:19:32 GMT Received: from troi.attlocal.net (/10.154.170.104) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Fri, 29 Jun 2018 15:19:32 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2017-10-26; bh=t1OsBmfBVQyuoTea/wK6gCLYid/zua7JAczGhSF3SJA=; b=WYZswAzgFv6gHL57/2pc/LoPWAhTkkeGmjPB2iUK+nt5KcORV+Aw6p7lt68UWjdrDCUU zVm994Fad6XWZAmeO7a47Hu7f2ZyeCixcQY3TR0agus5XUmw49JVnOXat1rW53Sf7Yc/ cliclwlzlnWja0tqpt5+6CTeKjjHh+q4igJMyaTw4x4KBqJ0XB0oAQ1L09Ivn0zX+IMw v6rgOyjCUbXeEhngbL/ft/3HrtW45Kt2OFC80cYqFaQsOfLuHSpbIzhIrnOZOq9hgbC4 1QXjso12k/XhQJOW7zbXpzntVRXAgkJ5hcHgqfbWXds7OyS/QXxU4IYOmMEq9X1Q9nVv wQ== From: Venu Busireddy To: venu.busireddy@oracle.com, "Michael S . Tsirkin" , Marcel Apfelbaum Date: Fri, 29 Jun 2018 17:19:05 -0500 Message-Id: <20180629221907.3662-3-venu.busireddy@oracle.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180629221907.3662-1-venu.busireddy@oracle.com> References: <20180629221907.3662-1-venu.busireddy@oracle.com> X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=8939 signatures=668703 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1806210000 definitions=main-1806290237 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 141.146.126.79 Subject: [Qemu-devel] [PATCH v3 2/3] Add "Group Identifier" support to Red Hat PCI bridge. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: virtio-dev@lists.oasis-open.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add the "Vendor-Specific" capability to the Red Hat PCI bridge device "pci-bridge", to contain the "Group Identifier" that will be used to pair a virtio device with the passthrough device attached to that bridge. Also, change the Device ID of the bridge to PCI_DEVICE_ID_REDHAT_BRIDGE_FAILOVER to avoid confusion with bridges that don't have this capability. This capability is added to the bridge iff the "failover-group-id" option is specified for the bridge. Signed-off-by: Venu Busireddy --- hw/pci-bridge/pci_bridge_dev.c | 10 ++++++++++ hw/pci/pci_bridge.c | 34 +++++++++++++++++++++++++++++++++ include/hw/pci/pci.h | 35 +++++++++++++++++----------------- include/hw/pci/pci_bridge.h | 2 ++ 4 files changed, 64 insertions(+), 17 deletions(-) diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c index b2d861d216..d3879071a8 100644 --- a/hw/pci-bridge/pci_bridge_dev.c +++ b/hw/pci-bridge/pci_bridge_dev.c @@ -71,6 +71,13 @@ static void pci_bridge_dev_realize(PCIDevice *dev, Error= **errp) bridge_dev->msi =3D ON_OFF_AUTO_OFF; } =20 + err =3D pci_bridge_vendor_init(dev, 0, PCI_DEVICE_ID_REDHAT_BRIDGE_FAI= LOVER, + errp); + if (err < 0) { + error_append_hint(errp, "Can't init group ID, error %d\n", err); + goto vendor_cap_err; + } + err =3D slotid_cap_init(dev, 0, bridge_dev->chassis_nr, 0, errp); if (err) { goto slotid_error; @@ -109,6 +116,7 @@ slotid_error: if (shpc_present(dev)) { shpc_cleanup(dev, &bridge_dev->bar); } +vendor_cap_err: shpc_error: pci_bridge_exitfn(dev); } @@ -162,6 +170,8 @@ static Property pci_bridge_dev_properties[] =3D { ON_OFF_AUTO_AUTO), DEFINE_PROP_BIT(PCI_BRIDGE_DEV_PROP_SHPC, PCIBridgeDev, flags, PCI_BRIDGE_DEV_F_SHPC_REQ, true), + DEFINE_PROP_UINT64(COMPAT_PROP_FAILOVER_GROUP_ID, + PCIDevice, failover_group_id, ULLONG_MAX), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index 40a39f57cb..68cc619c20 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -40,6 +40,10 @@ #define PCI_SSVID_SVID 4 #define PCI_SSVID_SSID 6 =20 +#define PCI_VENDOR_SIZEOF 12 +#define PCI_VENDOR_CAP_LEN_OFFSET 2 +#define PCI_VENDOR_GROUP_ID_OFFSET 4 + int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, uint16_t svid, uint16_t ssid, Error **errp) @@ -57,6 +61,36 @@ int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, return pos; } =20 +int pci_bridge_vendor_init(PCIDevice *d, uint8_t offset, + uint16_t device_id, Error **errp) +{ + int pos; + PCIDeviceClass *dc =3D PCI_DEVICE_GET_CLASS(d); + + if (d->failover_group_id =3D=3D ULLONG_MAX) { + return 0; + } + + pos =3D pci_add_capability(d, PCI_CAP_ID_VNDR, offset, PCI_VENDOR_SIZE= OF, + errp); + if (pos < 0) { + return pos; + } + + /* + * Tweak the Device ID to avoid confusion + * with bridges that don't have the group id capability. + */ + dc->device_id =3D device_id; + pci_set_word(d->config + PCI_DEVICE_ID, device_id); + + pci_set_word(d->config + pos + PCI_VENDOR_CAP_LEN_OFFSET, + PCI_VENDOR_SIZEOF); + memcpy(d->config + pos + PCI_VENDOR_GROUP_ID_OFFSET, + &d->failover_group_id, sizeof(uint64_t)); + return pos; +} + /* Accessor function to get parent bridge device from pci bus. */ PCIDevice *pci_bridge_get_device(PCIBus *bus) { diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index b59c3e7e38..bc38032761 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -86,23 +86,24 @@ extern bool pci_available; #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 =20 -#define PCI_VENDOR_ID_REDHAT 0x1b36 -#define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 -#define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 -#define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 -#define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 -#define PCI_DEVICE_ID_REDHAT_TEST 0x0005 -#define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 -#define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 -#define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 -#define PCI_DEVICE_ID_REDHAT_PXB 0x0009 -#define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a -#define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b -#define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c -#define PCI_DEVICE_ID_REDHAT_XHCI 0x000d -#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e -#define PCI_DEVICE_ID_REDHAT_MDPY 0x000f -#define PCI_DEVICE_ID_REDHAT_QXL 0x0100 +#define PCI_VENDOR_ID_REDHAT 0x1b36 +#define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 +#define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 +#define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 +#define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 +#define PCI_DEVICE_ID_REDHAT_TEST 0x0005 +#define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 +#define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 +#define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 +#define PCI_DEVICE_ID_REDHAT_PXB 0x0009 +#define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a +#define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b +#define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c +#define PCI_DEVICE_ID_REDHAT_XHCI 0x000d +#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e +#define PCI_DEVICE_ID_REDHAT_MDPY 0x000f +#define PCI_DEVICE_ID_REDHAT_BRIDGE_FAILOVER 0x0010 +#define PCI_DEVICE_ID_REDHAT_QXL 0x0100 =20 #define FMT_PCIBUS PRIx64 =20 diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index 0347da52d2..aa471ec5a4 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -83,6 +83,8 @@ struct PCIBridge { int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, uint16_t svid, uint16_t ssid, Error **errp); +int pci_bridge_vendor_init(PCIDevice *dev, uint8_t offset, + uint16_t device_id, Error **errp); =20 PCIDevice *pci_bridge_get_device(PCIBus *bus); PCIBus *pci_bridge_get_sec_bus(PCIBridge *br); From nobody Sat May 18 15:49:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=oracle.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530311056160905.6387644197048; Fri, 29 Jun 2018 15:24:16 -0700 (PDT) Received: from localhost ([::1]:44724 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fZ1oN-0005BO-EF for importer@patchew.org; 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Fri, 29 Jun 2018 22:19:38 GMT Received: from abhmp0004.oracle.com (abhmp0004.oracle.com [141.146.116.10]) by aserv0122.oracle.com (8.14.4/8.14.4) with ESMTP id w5TMJbiI015909; Fri, 29 Jun 2018 22:19:37 GMT Received: from troi.attlocal.net (/10.154.170.104) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Fri, 29 Jun 2018 15:19:37 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2017-10-26; bh=MoniBj3NOVqdGy2EFa10W9p7zbQFxXQIY0NcZAXLdW8=; b=Sx7ToDNSNL8xsxhyQQral3wZeDDLoRQhEOi/a9T45PyFjwKRGZJEkqvk4cPdWKLZQlN5 6irSqeK+D6zE9ibChvvmmCdLzJ0nV99spaFIWzoXkY9Hs1wP0ywpULpkCEtkQmRsQwGa MLOS24mST6cqoUjAGK9rkFg7jnJDmdQvJUBtZzuT8ian9mtcmTnZpeVb2ij6TIU097Cn zv6l7/GpPoFISyc0zdsg2bubmKzVvHWnm5k53LNX7ebPKmghht/md11Zx7j/qYtIk3/4 oBZh6F3IRMUycXthwMx7BdLj2JPtJyh6pODOYvOQxcFcwQl9IF+ZRG7O9s+13hFN2jZM kw== From: Venu Busireddy To: venu.busireddy@oracle.com, "Michael S . Tsirkin" , Marcel Apfelbaum Date: Fri, 29 Jun 2018 17:19:06 -0500 Message-Id: <20180629221907.3662-4-venu.busireddy@oracle.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180629221907.3662-1-venu.busireddy@oracle.com> References: <20180629221907.3662-1-venu.busireddy@oracle.com> X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=8939 signatures=668703 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1806210000 definitions=main-1806290237 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 156.151.31.86 Subject: [Qemu-devel] [PATCH v3 3/3] Add "Group Identifier" support to Red Hat PCI Express bridge. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: virtio-dev@lists.oasis-open.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add a new bridge device "pcie-downstream" with a Vendor ID of PCI_VENDOR_ID_REDHAT and a Device ID of PCI_DEVICE_ID_REDHAT_DOWNPORT_FAILOVER. Also, add the "Vendor-Specific" capability to the bridge to contain the "Group Identifier" that will be used to pair a virtio device with the passthrough device attached to that bridge. This capability is added to the bridge iff the "failover-group-id" option is specified for the bridge. Signed-off-by: Venu Busireddy --- default-configs/arm-softmmu.mak | 1 + default-configs/i386-softmmu.mak | 1 + default-configs/x86_64-softmmu.mak | 1 + hw/pci-bridge/Makefile.objs | 1 + hw/pci-bridge/pcie_downstream.c | 220 +++++++++++++++++++++++++++++ hw/pci-bridge/pcie_downstream.h | 10 ++ include/hw/pci/pci.h | 1 + 7 files changed, 235 insertions(+) create mode 100644 hw/pci-bridge/pcie_downstream.c create mode 100644 hw/pci-bridge/pcie_downstream.h diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index 834d45cfaf..b86c6fb122 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -139,6 +139,7 @@ CONFIG_IMX_I2C=3Dy CONFIG_PCIE_PORT=3Dy CONFIG_XIO3130=3Dy CONFIG_IOH3420=3Dy +CONFIG_PCIE_DOWNSTREAM=3Dy CONFIG_I82801B11=3Dy CONFIG_ACPI=3Dy CONFIG_SMBIOS=3Dy diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmm= u.mak index 8c7d4a0fa0..a900c8f052 100644 --- a/default-configs/i386-softmmu.mak +++ b/default-configs/i386-softmmu.mak @@ -56,6 +56,7 @@ CONFIG_ACPI_NVDIMM=3Dy CONFIG_PCIE_PORT=3Dy CONFIG_XIO3130=3Dy CONFIG_IOH3420=3Dy +CONFIG_PCIE_DOWNSTREAM=3Dy CONFIG_I82801B11=3Dy CONFIG_SMBIOS=3Dy CONFIG_HYPERV_TESTDEV=3D$(CONFIG_KVM) diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-so= ftmmu.mak index 0390b4303c..481e4764be 100644 --- a/default-configs/x86_64-softmmu.mak +++ b/default-configs/x86_64-softmmu.mak @@ -56,6 +56,7 @@ CONFIG_ACPI_NVDIMM=3Dy CONFIG_PCIE_PORT=3Dy CONFIG_XIO3130=3Dy CONFIG_IOH3420=3Dy +CONFIG_PCIE_DOWNSTREAM=3Dy CONFIG_I82801B11=3Dy CONFIG_SMBIOS=3Dy CONFIG_HYPERV_TESTDEV=3D$(CONFIG_KVM) diff --git a/hw/pci-bridge/Makefile.objs b/hw/pci-bridge/Makefile.objs index 47065f87d9..5b42212edc 100644 --- a/hw/pci-bridge/Makefile.objs +++ b/hw/pci-bridge/Makefile.objs @@ -3,6 +3,7 @@ common-obj-$(CONFIG_PCIE_PORT) +=3D pcie_root_port.o gen_pc= ie_root_port.o pcie_pci common-obj-$(CONFIG_PXB) +=3D pci_expander_bridge.o common-obj-$(CONFIG_XIO3130) +=3D xio3130_upstream.o xio3130_downstream.o common-obj-$(CONFIG_IOH3420) +=3D ioh3420.o +common-obj-$(CONFIG_PCIE_DOWNSTREAM) +=3D pcie_downstream.o common-obj-$(CONFIG_I82801B11) +=3D i82801b11.o # NewWorld PowerMac common-obj-$(CONFIG_DEC_PCI) +=3D dec.o diff --git a/hw/pci-bridge/pcie_downstream.c b/hw/pci-bridge/pcie_downstrea= m.c new file mode 100644 index 0000000000..49b0d1e933 --- /dev/null +++ b/hw/pci-bridge/pcie_downstream.c @@ -0,0 +1,220 @@ +/* + * Red Hat PCI Express downstream port. + * + * pcie_downstream.c + * Most of this code is copied from xio3130_downstream.c + * + * Copyright (c) 2018 Oracle and/or its affiliates. + * Author: Venu Busireddy + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "hw/pci/pci_ids.h" +#include "hw/pci/msi.h" +#include "hw/pci/pcie.h" +#include "pcie_downstream.h" +#include "qapi/error.h" + +#define REDHAT_PCIE_DOWNSTREAM_REVISION 0x1 +#define REDHAT_PCIE_DOWNSTREAM_MSI_OFFSET 0x70 +#define REDHAT_PCIE_DOWNSTREAM_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT +#define REDHAT_PCIE_DOWNSTREAM_MSI_NR_VECTOR 1 +#define REDHAT_PCIE_DOWNSTREAM_SSVID_OFFSET 0x80 +#define REDHAT_PCIE_DOWNSTREAM_SSVID_SVID 0 +#define REDHAT_PCIE_DOWNSTREAM_SSVID_SSID 0 +#define REDHAT_PCIE_DOWNSTREAM_EXP_OFFSET 0x90 +#define REDHAT_PCIE_DOWNSTREAM_VENDOR_OFFSET 0xCC +#define REDHAT_PCIE_DOWNSTREAM_AER_OFFSET 0x100 + +static void pcie_downstream_write_config(PCIDevice *d, uint32_t address, + uint32_t val, int len) +{ + pci_bridge_write_config(d, address, val, len); + pcie_cap_flr_write_config(d, address, val, len); + pcie_cap_slot_write_config(d, address, val, len); + pcie_aer_write_config(d, address, val, len); +} + +static void pcie_downstream_reset(DeviceState *qdev) +{ + PCIDevice *d =3D PCI_DEVICE(qdev); + + pcie_cap_deverr_reset(d); + pcie_cap_slot_reset(d); + pcie_cap_arifwd_reset(d); + pci_bridge_reset(qdev); +} + +static void pcie_downstream_realize(PCIDevice *d, Error **errp) +{ + PCIEPort *p =3D PCIE_PORT(d); + PCIESlot *s =3D PCIE_SLOT(d); + int rc; + + pci_bridge_initfn(d, TYPE_PCIE_BUS); + pcie_port_init_reg(d); + + rc =3D pci_bridge_vendor_init(d, REDHAT_PCIE_DOWNSTREAM_VENDOR_OFFSET, + PCI_DEVICE_ID_REDHAT_DOWNPORT_FAILOVER, errp); + if (rc < 0) { + error_append_hint(errp, "Can't init group ID, error %d\n", rc); + goto err_bridge; + } + + rc =3D msi_init(d, REDHAT_PCIE_DOWNSTREAM_MSI_OFFSET, + REDHAT_PCIE_DOWNSTREAM_MSI_NR_VECTOR, + REDHAT_PCIE_DOWNSTREAM_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64B= IT, + REDHAT_PCIE_DOWNSTREAM_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MAS= KBIT, + errp); + if (rc < 0) { + assert(rc =3D=3D -ENOTSUP); + goto err_bridge; + } + + rc =3D pci_bridge_ssvid_init(d, REDHAT_PCIE_DOWNSTREAM_SSVID_OFFSET, + REDHAT_PCIE_DOWNSTREAM_SSVID_SVID, + REDHAT_PCIE_DOWNSTREAM_SSVID_SSID, errp); + if (rc < 0) { + goto err_bridge; + } + + rc =3D pcie_cap_init(d, REDHAT_PCIE_DOWNSTREAM_EXP_OFFSET, + PCI_EXP_TYPE_DOWNSTREAM, p->port, errp); + if (rc < 0) { + goto err_msi; + } + pcie_cap_flr_init(d); + pcie_cap_deverr_init(d); + pcie_cap_slot_init(d, s->slot); + pcie_cap_arifwd_init(d); + + pcie_chassis_create(s->chassis); + rc =3D pcie_chassis_add_slot(s); + if (rc < 0) { + error_setg(errp, "Can't add chassis slot, error %d", rc); + goto err_pcie_cap; + } + + rc =3D pcie_aer_init(d, PCI_ERR_VER, REDHAT_PCIE_DOWNSTREAM_AER_OFFSET, + PCI_ERR_SIZEOF, errp); + if (rc < 0) { + goto err; + } + + return; + +err: + pcie_chassis_del_slot(s); +err_pcie_cap: + pcie_cap_exit(d); +err_msi: + msi_uninit(d); +err_bridge: + pci_bridge_exitfn(d); +} + +static void pcie_downstream_exitfn(PCIDevice *d) +{ + PCIESlot *s =3D PCIE_SLOT(d); + + pcie_aer_exit(d); + pcie_chassis_del_slot(s); + pcie_cap_exit(d); + msi_uninit(d); + pci_bridge_exitfn(d); +} + +PCIESlot *pcie_downstream_init(PCIBus *bus, int devfn, bool multifunction, + const char *bus_name, pci_map_irq_fn map_ir= q, + uint8_t port, uint8_t chassis, uint16_t slo= t) +{ + PCIDevice *d; + PCIBridge *br; + DeviceState *qdev; + + d =3D pci_create_multifunction(bus, devfn, multifunction, "pcie-downst= ream"); + if (!d) { + return NULL; + } + br =3D PCI_BRIDGE(d); + + qdev =3D DEVICE(d); + pci_bridge_map_irq(br, bus_name, map_irq); + qdev_prop_set_uint8(qdev, "port", port); + qdev_prop_set_uint8(qdev, "chassis", chassis); + qdev_prop_set_uint16(qdev, "slot", slot); + qdev_init_nofail(qdev); + + return PCIE_SLOT(d); +} + +static Property pcie_downstream_props[] =3D { + DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, + QEMU_PCIE_SLTCAP_PCP_BITNR, true), + DEFINE_PROP_UINT64(COMPAT_PROP_FAILOVER_GROUP_ID, + PCIDevice, failover_group_id, ULLONG_MAX), + DEFINE_PROP_END_OF_LIST() +}; + +static const VMStateDescription vmstate_pcie_ds =3D { + .name =3D "pcie-downstream-port", + .priority =3D MIG_PRI_PCI_BUS, + .version_id =3D 1, + .minimum_version_id =3D 1, + .post_load =3D pcie_cap_slot_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot), + VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log, + PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog), + VMSTATE_END_OF_LIST() + } +}; + +static void pcie_downstream_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->is_bridge =3D 1; + k->config_write =3D pcie_downstream_write_config; + k->realize =3D pcie_downstream_realize; + k->exit =3D pcie_downstream_exitfn; + k->vendor_id =3D PCI_VENDOR_ID_REDHAT; + k->device_id =3D PCI_DEVICE_ID_REDHAT_DOWNPORT_FAILOVER; + k->revision =3D REDHAT_PCIE_DOWNSTREAM_REVISION; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + dc->desc =3D "Red Hat PCIe Downstream Port"; + dc->reset =3D pcie_downstream_reset; + dc->vmsd =3D &vmstate_pcie_ds; + dc->props =3D pcie_downstream_props; +} + +static const TypeInfo pcie_downstream_info =3D { + .name =3D "pcie-downstream", + .parent =3D TYPE_PCIE_SLOT, + .class_init =3D pcie_downstream_class_init, + .interfaces =3D (InterfaceInfo[]) { + { INTERFACE_PCIE_DEVICE }, + { } + }, +}; + +static void pcie_downstream_register_types(void) +{ + type_register_static(&pcie_downstream_info); +} + +type_init(pcie_downstream_register_types) diff --git a/hw/pci-bridge/pcie_downstream.h b/hw/pci-bridge/pcie_downstrea= m.h new file mode 100644 index 0000000000..a7f1aae4bb --- /dev/null +++ b/hw/pci-bridge/pcie_downstream.h @@ -0,0 +1,10 @@ +#ifndef QEMU_PCIE_DOWNSTREAM_H +#define QEMU_PCIE_DOWNSTREAM_H + +#include "hw/pci/pcie_port.h" + +PCIESlot *pcie_downstream_init(PCIBus *bus, int devfn, bool multifunction, + const char *bus_name, pci_map_irq_fn map_irq, uint8_t port, + uint8_t chassis, uint16_t slot); + +#endif /* QEMU_PCIE_DOWNSTREAM_H */ diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index bc38032761..bf04ef59f3 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -103,6 +103,7 @@ extern bool pci_available; #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f #define PCI_DEVICE_ID_REDHAT_BRIDGE_FAILOVER 0x0010 +#define PCI_DEVICE_ID_REDHAT_DOWNPORT_FAILOVER 0x0011 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 =20 #define FMT_PCIBUS PRIx64