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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ann9GPHiOSMoq3Qqao3S2P8vkeiOe/5qFZmIeDX/9/I=; b=eacP1ujx9XpKZ3pYDciBa9otjwft4PkU1N8tqp0nQ4F4if1kLZNif0y0yQ/S/Te02S i2Lal0Kf7wXbF1mqyqlirTFVL5C9VpNs2d1b92IQmoG+K+KiGwNipXGUjjcECMJosr5G k3gOIyWAYBuEeulJClm1ds4z/saRFzr0Ogjb4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ann9GPHiOSMoq3Qqao3S2P8vkeiOe/5qFZmIeDX/9/I=; b=dZWtQ2dtiOXN9PxCtW8X4Htgr6lXTRudz5t+96V30G1qpMDjPbE+GeX1Ao8ZvypcT+ bBy12omJe4/M0cbPMn3w2swjQMP2G7LOvDX+WaVti4F0JA9GYIHj7GiT9TSEo3xMHEeH ZRXNwhZjTNP+J9/bG74Y389SkI4rHk2qfGFxXAW5Kj83Tptnmndq2FjfGuWdlbVSG26x ZlQIHjzR8gl7wp9yreW+3Jj1YRC8WkHGdn0gHhYJ7BYDEsrW4j8Y7pHxyQD6E5mqQiTC EbTqq7Le5rTe8t5iwoULuTeSDHviDQvSHnFETNK7V+l4ufyIxZGVhpQ7stB0ueNzg1jR JYew== X-Gm-Message-State: APt69E2MLp/ppHq1jhi5727jVvve2hADMy2ueVAK2ZVjKv6zJfkHPUXD OqCqcFPDiwBocPSZc0P7oQxFU+hw8Yk= X-Google-Smtp-Source: AAOMgpeqC394zB7ZwYxKkjPCPfR3kanFcE0kMAWDZ0JK0sTrhWQy8Bo+ps8xY88CDESXpMxSYut3Tg== X-Received: by 2002:a62:fe19:: with SMTP id z25-v6mr8176136pfh.167.1530155014002; Wed, 27 Jun 2018 20:03:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:08 -0700 Message-Id: <20180628030330.15615-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::231 Subject: [Qemu-devel] [PATCH v3 01/23] target/openrisc: Fix mtspr shadow gprs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Missing break. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/openrisc/sys_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index b284064381..2f337363ec 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -98,6 +98,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ idx =3D (spr - 1024); env->shadow_gpr[idx / 32][idx % 32] =3D rb; + break; =20 case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ idx =3D spr - TO_SPR(1, 512); --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530155339330333.6928500646279; Wed, 27 Jun 2018 20:08:59 -0700 (PDT) Received: from localhost ([::1]:34261 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNIo-0000Dp-EK for importer@patchew.org; Wed, 27 Jun 2018 23:08:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39874) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNDi-0004v4-8q for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNDd-0007dK-Nq for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:42 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:46921) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNDd-0007cz-CZ for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:37 -0400 Received: by mail-pf0-x242.google.com with SMTP id q1-v6so1882738pff.13 for ; Wed, 27 Jun 2018 20:03:37 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rjP0WcEQVKvrrKZaE1rx2rVvCp4c9dTWMv6CuqD2ckg=; b=HML2g3UaMiY6ACiB1jTppPhhzOhmmaDsAIasdOA+ejmUrBItAkPiRMqQpSCjtdfb5a Q5/EeAH2bamxwam4MVcGQ0lr6H+BC/2fTYhICA5JcbMi6HZe0cVQ8IfeybRlUMh4NNYt EH6LvLnMQXcw+I2W62UlQ7zu92gEpHh51PecQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rjP0WcEQVKvrrKZaE1rx2rVvCp4c9dTWMv6CuqD2ckg=; b=QBBQv3MWi0Pj82hrRpgVLvi2WTGIoR2VA9P1vnJIOKQXUoUKF1BeqVkskOpnDG+5O2 oiq8k/UadRjniucbBZuthvm04rV8B+P1LsKDsGrlPDfAIHNEQcE1iU4CgSwtIK8/hUZ1 0nhHJCglhQGpUgp5d+B95Bb7e3pjGMSNoHr1ssQNneDniPyDap6GbNpUr1399qXB81C0 9r0opGrAOG1FYk1/8vmrW9pwuYXvtTaCSsU6/zh7sKmru2Uk61tqrXCS7KJxOLV9qKu4 MngRtEuAYKb0bvjN7WH8DBEv68nv/dJkP9AUZxrgWO2oepK7ieJV8+/WQ7YpKBGHtd/s 1jeA== X-Gm-Message-State: APt69E3UNxpHz4dX25pLPwm6X8Uyh6fJK8zbAzR24Q+hRx0HBjK0taWQ seVShn778iJKWvUNBpuVEZttG5LvYP4= X-Google-Smtp-Source: AAOMgpfoH3OaGHHomQSm0m4VLkoumTq6PPOJQnleXEdE7YH2OaKXytJzFNffF+siQ43MXYBohcDF0A== X-Received: by 2002:aa7:80cf:: with SMTP id a15-v6mr8331712pfn.19.1530155015429; Wed, 27 Jun 2018 20:03:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:09 -0700 Message-Id: <20180628030330.15615-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v3 02/23] target/openrisc: Add print_insn_or1k X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Rather than emit disassembly while translating, reuse the generated decoder to build a separate disassembler. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 1 + target/openrisc/cpu.c | 6 ++ target/openrisc/disas.c | 170 ++++++++++++++++++++++++++++++++++ target/openrisc/translate.c | 114 ----------------------- target/openrisc/Makefile.objs | 3 +- 5 files changed, 179 insertions(+), 115 deletions(-) create mode 100644 target/openrisc/disas.c diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 35cab65f11..c871d6bfe1 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -358,6 +358,7 @@ void openrisc_translate_init(void); int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, int mmu_idx); int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); +int print_insn_or1k(bfd_vma addr, disassemble_info *info); =20 #define cpu_list cpu_openrisc_list #define cpu_signal_handler cpu_openrisc_signal_handler diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index a692a98ec0..fa8e342ff7 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -35,6 +35,11 @@ static bool openrisc_cpu_has_work(CPUState *cs) CPU_INTERRUPT_TIMER); } =20 +static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) +{ + info->print_insn =3D print_insn_or1k; +} + /* CPUClass::reset() */ static void openrisc_cpu_reset(CPUState *s) { @@ -152,6 +157,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) #endif cc->gdb_num_core_regs =3D 32 + 3; cc->tcg_initialize =3D openrisc_translate_init; + cc->disas_set_info =3D openrisc_disas_set_info; } =20 /* Sort alphabetically by type name, except for "any". */ diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c new file mode 100644 index 0000000000..5acf4f4744 --- /dev/null +++ b/target/openrisc/disas.c @@ -0,0 +1,170 @@ +/* + * OpenRISC disassembler + * + * Copyright (c) 2018 Richard Henderson + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "disas/bfd.h" +#include "qemu/bitops.h" +#include "cpu.h" + +typedef disassemble_info DisasContext; + +/* Include the auto-generated decoder. */ +#include "decode.inc.c" + +#define output(mnemonic, format, ...) \ + info->fprintf_func(info->stream, "%-9s " format, \ + mnemonic, ##__VA_ARGS__) + +int print_insn_or1k(bfd_vma addr, disassemble_info *info) +{ + bfd_byte buffer[4]; + uint32_t insn; + int status; + + status =3D info->read_memory_func(addr, buffer, 4, info); + if (status !=3D 0) { + info->memory_error_func(status, addr, info); + return -1; + } + insn =3D bfd_getb32(buffer); + + if (!decode(info, insn)) { + output(".long", "%#08x", insn); + } + return 4; +} + +#define INSN(opcode, format, ...) \ +static bool trans_l_##opcode(disassemble_info *info, \ + arg_l_##opcode *a, uint32_t insn) \ +{ \ + output("l." #opcode, format, ##__VA_ARGS__); \ + return true; \ +} + +INSN(add, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(addc, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(sub, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(and, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(or, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(xor, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(sll, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(srl, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(sra, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(ror, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(exths, "r%d, r%d", a->d, a->a) +INSN(extbs, "r%d, r%d", a->d, a->a) +INSN(exthz, "r%d, r%d", a->d, a->a) +INSN(extbz, "r%d, r%d", a->d, a->a) +INSN(cmov, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(ff1, "r%d, r%d", a->d, a->a) +INSN(fl1, "r%d, r%d", a->d, a->a) +INSN(mul, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(mulu, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(div, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(divu, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(muld, "r%d, r%d", a->a, a->b) +INSN(muldu, "r%d, r%d", a->a, a->b) +INSN(j, "%d", a->n) +INSN(jal, "%d", a->n) +INSN(bf, "%d", a->n) +INSN(bnf, "%d", a->n) +INSN(jr, "r%d", a->b) +INSN(jalr, "r%d", a->b) +INSN(lwa, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(lwz, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(lws, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(lbz, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(lbs, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(lhz, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(lhs, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(swa, "%d(r%d), r%d", a->i, a->a, a->b) +INSN(sw, "%d(r%d), r%d", a->i, a->a, a->b) +INSN(sb, "%d(r%d), r%d", a->i, a->a, a->b) +INSN(sh, "%d(r%d), r%d", a->i, a->a, a->b) +INSN(nop, "") +INSN(addi, "r%d, r%d, %d", a->d, a->a, a->i) +INSN(addic, "r%d, r%d, %d", a->d, a->a, a->i) +INSN(muli, "r%d, r%d, %d", a->d, a->a, a->i) +INSN(maci, "r%d, %d", a->a, a->i) +INSN(andi, "r%d, r%d, %d", a->d, a->a, a->k) +INSN(ori, "r%d, r%d, %d", a->d, a->a, a->k) +INSN(xori, "r%d, r%d, %d", a->d, a->a, a->i) +INSN(mfspr, "r%d, r%d, %d", a->d, a->a, a->k) +INSN(mtspr, "r%d, r%d, %d", a->a, a->b, a->k) +INSN(mac, "r%d, r%d", a->a, a->b) +INSN(msb, "r%d, r%d", a->a, a->b) +INSN(macu, "r%d, r%d", a->a, a->b) +INSN(msbu, "r%d, r%d", a->a, a->b) +INSN(slli, "r%d, r%d, %d", a->d, a->a, a->l) +INSN(srli, "r%d, r%d, %d", a->d, a->a, a->l) +INSN(srai, "r%d, r%d, %d", a->d, a->a, a->l) +INSN(rori, "r%d, r%d, %d", a->d, a->a, a->l) +INSN(movhi, "r%d, %d", a->d, a->k) +INSN(macrc, "r%d", a->d) +INSN(sfeq, "r%d, r%d", a->a, a->b) +INSN(sfne, "r%d, r%d", a->a, a->b) +INSN(sfgtu, "r%d, r%d", a->a, a->b) +INSN(sfgeu, "r%d, r%d", a->a, a->b) +INSN(sfltu, "r%d, r%d", a->a, a->b) +INSN(sfleu, "r%d, r%d", a->a, a->b) +INSN(sfgts, "r%d, r%d", a->a, a->b) +INSN(sfges, "r%d, r%d", a->a, a->b) +INSN(sflts, "r%d, r%d", a->a, a->b) +INSN(sfles, "r%d, r%d", a->a, a->b) +INSN(sfeqi, "r%d, %d", a->a, a->i) +INSN(sfnei, "r%d, %d", a->a, a->i) +INSN(sfgtui, "r%d, %d", a->a, a->i) +INSN(sfgeui, "r%d, %d", a->a, a->i) +INSN(sfltui, "r%d, %d", a->a, a->i) +INSN(sfleui, "r%d, %d", a->a, a->i) +INSN(sfgtsi, "r%d, %d", a->a, a->i) +INSN(sfgesi, "r%d, %d", a->a, a->i) +INSN(sfltsi, "r%d, %d", a->a, a->i) +INSN(sflesi, "r%d, %d", a->a, a->i) +INSN(sys, "%d", a->k) +INSN(trap, "%d", a->k) +INSN(msync, "") +INSN(psync, "") +INSN(csync, "") +INSN(rfe, "") + +#define FP_INSN(opcode, suffix, format, ...) \ +static bool trans_lf_##opcode##_##suffix(disassemble_info *info, \ + arg_lf_##opcode##_##suffix *a, uint32_t insn) \ +{ \ + output("lf." #opcode "." #suffix, format, ##__VA_ARGS__); \ + return true; \ +} + +FP_INSN(add, s, "r%d, r%d, r%d", a->d, a->a, a->b) +FP_INSN(sub, s, "r%d, r%d, r%d", a->d, a->a, a->b) +FP_INSN(mul, s, "r%d, r%d, r%d", a->d, a->a, a->b) +FP_INSN(div, s, "r%d, r%d, r%d", a->d, a->a, a->b) +FP_INSN(rem, s, "r%d, r%d, r%d", a->d, a->a, a->b) +FP_INSN(itof, s, "r%d, r%d", a->d, a->a) +FP_INSN(ftoi, s, "r%d, r%d", a->d, a->a) +FP_INSN(madd, s, "r%d, r%d, r%d", a->d, a->a, a->b) +FP_INSN(sfeq, s, "r%d, r%d", a->a, a->b) +FP_INSN(sfne, s, "r%d, r%d", a->a, a->b) +FP_INSN(sfgt, s, "r%d, r%d", a->a, a->b) +FP_INSN(sfge, s, "r%d, r%d", a->a, a->b) +FP_INSN(sflt, s, "r%d, r%d", a->a, a->b) +FP_INSN(sfle, s, "r%d, r%d", a->a, a->b) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index d69f8d0422..fbdc2058dc 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -36,10 +36,6 @@ #include "trace-tcg.h" #include "exec/log.h" =20 -#define LOG_DIS(str, ...) \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->base.pc_next, \ - ## __VA_ARGS__) - /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ @@ -457,7 +453,6 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv = srcb) =20 static bool trans_l_add(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.add r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); gen_add(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -465,7 +460,6 @@ static bool trans_l_add(DisasContext *dc, arg_dab *a, u= int32_t insn) =20 static bool trans_l_addc(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.addc r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); gen_addc(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -473,7 +467,6 @@ static bool trans_l_addc(DisasContext *dc, arg_dab *a, = uint32_t insn) =20 static bool trans_l_sub(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.sub r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); gen_sub(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -481,7 +474,6 @@ static bool trans_l_sub(DisasContext *dc, arg_dab *a, u= int32_t insn) =20 static bool trans_l_and(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.and r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_and_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -489,7 +481,6 @@ static bool trans_l_and(DisasContext *dc, arg_dab *a, u= int32_t insn) =20 static bool trans_l_or(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.or r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_or_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -497,7 +488,6 @@ static bool trans_l_or(DisasContext *dc, arg_dab *a, ui= nt32_t insn) =20 static bool trans_l_xor(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.xor r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_xor_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -505,7 +495,6 @@ static bool trans_l_xor(DisasContext *dc, arg_dab *a, u= int32_t insn) =20 static bool trans_l_sll(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.sll r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_shl_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -513,7 +502,6 @@ static bool trans_l_sll(DisasContext *dc, arg_dab *a, u= int32_t insn) =20 static bool trans_l_srl(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.srl r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_shr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -521,7 +509,6 @@ static bool trans_l_srl(DisasContext *dc, arg_dab *a, u= int32_t insn) =20 static bool trans_l_sra(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.sra r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_sar_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -529,7 +516,6 @@ static bool trans_l_sra(DisasContext *dc, arg_dab *a, u= int32_t insn) =20 static bool trans_l_ror(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.ror r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_rotr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -537,7 +523,6 @@ static bool trans_l_ror(DisasContext *dc, arg_dab *a, u= int32_t insn) =20 static bool trans_l_exths(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("l.exths r%d, r%d\n", a->d, a->a); check_r0_write(a->d); tcg_gen_ext16s_tl(cpu_R[a->d], cpu_R[a->a]); return true; @@ -545,7 +530,6 @@ static bool trans_l_exths(DisasContext *dc, arg_da *a, = uint32_t insn) =20 static bool trans_l_extbs(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("l.extbs r%d, r%d\n", a->d, a->a); check_r0_write(a->d); tcg_gen_ext8s_tl(cpu_R[a->d], cpu_R[a->a]); return true; @@ -553,7 +537,6 @@ static bool trans_l_extbs(DisasContext *dc, arg_da *a, = uint32_t insn) =20 static bool trans_l_exthz(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("l.exthz r%d, r%d\n", a->d, a->a); check_r0_write(a->d); tcg_gen_ext16u_tl(cpu_R[a->d], cpu_R[a->a]); return true; @@ -561,7 +544,6 @@ static bool trans_l_exthz(DisasContext *dc, arg_da *a, = uint32_t insn) =20 static bool trans_l_extbz(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("l.extbz r%d, r%d\n", a->d, a->a); check_r0_write(a->d); tcg_gen_ext8u_tl(cpu_R[a->d], cpu_R[a->a]); return true; @@ -570,7 +552,6 @@ static bool trans_l_extbz(DisasContext *dc, arg_da *a, = uint32_t insn) static bool trans_l_cmov(DisasContext *dc, arg_dab *a, uint32_t insn) { TCGv zero; - LOG_DIS("l.cmov r%d, r%d, r%d\n", a->d, a->a, a->b); =20 check_r0_write(a->d); zero =3D tcg_const_tl(0); @@ -582,8 +563,6 @@ static bool trans_l_cmov(DisasContext *dc, arg_dab *a, = uint32_t insn) =20 static bool trans_l_ff1(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("l.ff1 r%d, r%d\n", a->d, a->a); - check_r0_write(a->d); tcg_gen_ctzi_tl(cpu_R[a->d], cpu_R[a->a], -1); tcg_gen_addi_tl(cpu_R[a->d], cpu_R[a->d], 1); @@ -592,8 +571,6 @@ static bool trans_l_ff1(DisasContext *dc, arg_da *a, ui= nt32_t insn) =20 static bool trans_l_fl1(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("l.fl1 r%d, r%d\n", a->d, a->a); - check_r0_write(a->d); tcg_gen_clzi_tl(cpu_R[a->d], cpu_R[a->a], TARGET_LONG_BITS); tcg_gen_subfi_tl(cpu_R[a->d], TARGET_LONG_BITS, cpu_R[a->d]); @@ -602,8 +579,6 @@ static bool trans_l_fl1(DisasContext *dc, arg_da *a, ui= nt32_t insn) =20 static bool trans_l_mul(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.mul r%d, r%d, r%d\n", a->d, a->a, a->b); - check_r0_write(a->d); gen_mul(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -611,8 +586,6 @@ static bool trans_l_mul(DisasContext *dc, arg_dab *a, u= int32_t insn) =20 static bool trans_l_mulu(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.mulu r%d, r%d, r%d\n", a->d, a->a, a->b); - check_r0_write(a->d); gen_mulu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -620,8 +593,6 @@ static bool trans_l_mulu(DisasContext *dc, arg_dab *a, = uint32_t insn) =20 static bool trans_l_div(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.div r%d, r%d, r%d\n", a->d, a->a, a->b); - check_r0_write(a->d); gen_div(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -629,8 +600,6 @@ static bool trans_l_div(DisasContext *dc, arg_dab *a, u= int32_t insn) =20 static bool trans_l_divu(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.divu r%d, r%d, r%d\n", a->d, a->a, a->b); - check_r0_write(a->d); gen_divu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -638,14 +607,12 @@ static bool trans_l_divu(DisasContext *dc, arg_dab *a= , uint32_t insn) =20 static bool trans_l_muld(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("l.muld r%d, r%d\n", a->a, a->b); gen_muld(dc, cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_muldu(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("l.muldu r%d, r%d\n", a->a, a->b); gen_muldu(dc, cpu_R[a->a], cpu_R[a->b]); return true; } @@ -654,7 +621,6 @@ static bool trans_l_j(DisasContext *dc, arg_l_j *a, uin= t32_t insn) { target_ulong tmp_pc =3D dc->base.pc_next + a->n * 4; =20 - LOG_DIS("l.j %d\n", a->n); tcg_gen_movi_tl(jmp_pc, tmp_pc); dc->delayed_branch =3D 2; return true; @@ -665,7 +631,6 @@ static bool trans_l_jal(DisasContext *dc, arg_l_jal *a,= uint32_t insn) target_ulong tmp_pc =3D dc->base.pc_next + a->n * 4; target_ulong ret_pc =3D dc->base.pc_next + 8; =20 - LOG_DIS("l.jal %d\n", a->n); tcg_gen_movi_tl(cpu_R[9], ret_pc); /* Optimize jal being used to load the PC for PIC. */ if (tmp_pc !=3D ret_pc) { @@ -692,21 +657,18 @@ static void do_bf(DisasContext *dc, arg_l_bf *a, TCGC= ond cond) =20 static bool trans_l_bf(DisasContext *dc, arg_l_bf *a, uint32_t insn) { - LOG_DIS("l.bf %d\n", a->n); do_bf(dc, a, TCG_COND_NE); return true; } =20 static bool trans_l_bnf(DisasContext *dc, arg_l_bf *a, uint32_t insn) { - LOG_DIS("l.bnf %d\n", a->n); do_bf(dc, a, TCG_COND_EQ); return true; } =20 static bool trans_l_jr(DisasContext *dc, arg_l_jr *a, uint32_t insn) { - LOG_DIS("l.jr r%d\n", a->b); tcg_gen_mov_tl(jmp_pc, cpu_R[a->b]); dc->delayed_branch =3D 2; return true; @@ -714,7 +676,6 @@ static bool trans_l_jr(DisasContext *dc, arg_l_jr *a, u= int32_t insn) =20 static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a, uint32_t insn) { - LOG_DIS("l.jalr r%d\n", a->b); tcg_gen_mov_tl(jmp_pc, cpu_R[a->b]); tcg_gen_movi_tl(cpu_R[9], dc->base.pc_next + 8); dc->delayed_branch =3D 2; @@ -725,8 +686,6 @@ static bool trans_l_lwa(DisasContext *dc, arg_load *a, = uint32_t insn) { TCGv ea; =20 - LOG_DIS("l.lwa r%d, r%d, %d\n", a->d, a->a, a->i); - check_r0_write(a->d); ea =3D tcg_temp_new(); tcg_gen_addi_tl(ea, cpu_R[a->a], a->i); @@ -750,42 +709,36 @@ static void do_load(DisasContext *dc, arg_load *a, TC= GMemOp mop) =20 static bool trans_l_lwz(DisasContext *dc, arg_load *a, uint32_t insn) { - LOG_DIS("l.lwz r%d, r%d, %d\n", a->d, a->a, a->i); do_load(dc, a, MO_TEUL); return true; } =20 static bool trans_l_lws(DisasContext *dc, arg_load *a, uint32_t insn) { - LOG_DIS("l.lws r%d, r%d, %d\n", a->d, a->a, a->i); do_load(dc, a, MO_TESL); return true; } =20 static bool trans_l_lbz(DisasContext *dc, arg_load *a, uint32_t insn) { - LOG_DIS("l.lbz r%d, r%d, %d\n", a->d, a->a, a->i); do_load(dc, a, MO_UB); return true; } =20 static bool trans_l_lbs(DisasContext *dc, arg_load *a, uint32_t insn) { - LOG_DIS("l.lbs r%d, r%d, %d\n", a->d, a->a, a->i); do_load(dc, a, MO_SB); return true; } =20 static bool trans_l_lhz(DisasContext *dc, arg_load *a, uint32_t insn) { - LOG_DIS("l.lhz r%d, r%d, %d\n", a->d, a->a, a->i); do_load(dc, a, MO_TEUW); return true; } =20 static bool trans_l_lhs(DisasContext *dc, arg_load *a, uint32_t insn) { - LOG_DIS("l.lhs r%d, r%d, %d\n", a->d, a->a, a->i); do_load(dc, a, MO_TESW); return true; } @@ -795,8 +748,6 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a,= uint32_t insn) TCGv ea, val; TCGLabel *lab_fail, *lab_done; =20 - LOG_DIS("l.swa r%d, r%d, %d\n", a->a, a->b, a->i); - ea =3D tcg_temp_new(); tcg_gen_addi_tl(ea, cpu_R[a->a], a->i); =20 @@ -837,28 +788,24 @@ static void do_store(DisasContext *dc, arg_store *a, = TCGMemOp mop) =20 static bool trans_l_sw(DisasContext *dc, arg_store *a, uint32_t insn) { - LOG_DIS("l.sw r%d, r%d, %d\n", a->a, a->b, a->i); do_store(dc, a, MO_TEUL); return true; } =20 static bool trans_l_sb(DisasContext *dc, arg_store *a, uint32_t insn) { - LOG_DIS("l.sb r%d, r%d, %d\n", a->a, a->b, a->i); do_store(dc, a, MO_UB); return true; } =20 static bool trans_l_sh(DisasContext *dc, arg_store *a, uint32_t insn) { - LOG_DIS("l.sh r%d, r%d, %d\n", a->a, a->b, a->i); do_store(dc, a, MO_TEUW); return true; } =20 static bool trans_l_nop(DisasContext *dc, arg_l_nop *a, uint32_t insn) { - LOG_DIS("l.nop %d\n", a->k); return true; } =20 @@ -866,7 +813,6 @@ static bool trans_l_addi(DisasContext *dc, arg_rri *a, = uint32_t insn) { TCGv t0; =20 - LOG_DIS("l.addi r%d, r%d, %d\n", a->d, a->a, a->i); check_r0_write(a->d); t0 =3D tcg_const_tl(a->i); gen_add(dc, cpu_R[a->d], cpu_R[a->a], t0); @@ -878,7 +824,6 @@ static bool trans_l_addic(DisasContext *dc, arg_rri *a,= uint32_t insn) { TCGv t0; =20 - LOG_DIS("l.addic r%d, r%d, %d\n", a->d, a->a, a->i); check_r0_write(a->d); t0 =3D tcg_const_tl(a->i); gen_addc(dc, cpu_R[a->d], cpu_R[a->a], t0); @@ -890,7 +835,6 @@ static bool trans_l_muli(DisasContext *dc, arg_rri *a, = uint32_t insn) { TCGv t0; =20 - LOG_DIS("l.muli r%d, r%d, %d\n", a->d, a->a, a->i); check_r0_write(a->d); t0 =3D tcg_const_tl(a->i); gen_mul(dc, cpu_R[a->d], cpu_R[a->a], t0); @@ -902,7 +846,6 @@ static bool trans_l_maci(DisasContext *dc, arg_l_maci *= a, uint32_t insn) { TCGv t0; =20 - LOG_DIS("l.maci r%d, %d\n", a->a, a->i); t0 =3D tcg_const_tl(a->i); gen_mac(dc, cpu_R[a->a], t0); tcg_temp_free(t0); @@ -911,7 +854,6 @@ static bool trans_l_maci(DisasContext *dc, arg_l_maci *= a, uint32_t insn) =20 static bool trans_l_andi(DisasContext *dc, arg_rrk *a, uint32_t insn) { - LOG_DIS("l.andi r%d, r%d, %d\n", a->d, a->a, a->k); check_r0_write(a->d); tcg_gen_andi_tl(cpu_R[a->d], cpu_R[a->a], a->k); return true; @@ -919,7 +861,6 @@ static bool trans_l_andi(DisasContext *dc, arg_rrk *a, = uint32_t insn) =20 static bool trans_l_ori(DisasContext *dc, arg_rrk *a, uint32_t insn) { - LOG_DIS("l.ori r%d, r%d, %d\n", a->d, a->a, a->k); check_r0_write(a->d); tcg_gen_ori_tl(cpu_R[a->d], cpu_R[a->a], a->k); return true; @@ -927,7 +868,6 @@ static bool trans_l_ori(DisasContext *dc, arg_rrk *a, u= int32_t insn) =20 static bool trans_l_xori(DisasContext *dc, arg_rri *a, uint32_t insn) { - LOG_DIS("l.xori r%d, r%d, %d\n", a->d, a->a, a->i); check_r0_write(a->d); tcg_gen_xori_tl(cpu_R[a->d], cpu_R[a->a], a->i); return true; @@ -935,7 +875,6 @@ static bool trans_l_xori(DisasContext *dc, arg_rri *a, = uint32_t insn) =20 static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn) { - LOG_DIS("l.mfspr r%d, r%d, %d\n", a->d, a->a, a->k); check_r0_write(a->d); =20 #ifdef CONFIG_USER_ONLY @@ -954,8 +893,6 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr= *a, uint32_t insn) =20 static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) { - LOG_DIS("l.mtspr r%d, r%d, %d\n", a->a, a->b, a->k); - #ifdef CONFIG_USER_ONLY gen_illegal_exception(dc); #else @@ -972,35 +909,30 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mts= pr *a, uint32_t insn) =20 static bool trans_l_mac(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("l.mac r%d, r%d\n", a->a, a->b); gen_mac(dc, cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_msb(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("l.msb r%d, r%d\n", a->a, a->b); gen_msb(dc, cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_macu(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("l.mac r%d, r%d\n", a->a, a->b); gen_macu(dc, cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_msbu(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("l.msb r%d, r%d\n", a->a, a->b); gen_msbu(dc, cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_slli(DisasContext *dc, arg_dal *a, uint32_t insn) { - LOG_DIS("l.slli r%d, r%d, %d\n", a->d, a->a, a->l); check_r0_write(a->d); tcg_gen_shli_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1= )); return true; @@ -1008,7 +940,6 @@ static bool trans_l_slli(DisasContext *dc, arg_dal *a,= uint32_t insn) =20 static bool trans_l_srli(DisasContext *dc, arg_dal *a, uint32_t insn) { - LOG_DIS("l.srli r%d, r%d, %d\n", a->d, a->a, a->l); check_r0_write(a->d); tcg_gen_shri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1= )); return true; @@ -1016,7 +947,6 @@ static bool trans_l_srli(DisasContext *dc, arg_dal *a,= uint32_t insn) =20 static bool trans_l_srai(DisasContext *dc, arg_dal *a, uint32_t insn) { - LOG_DIS("l.srai r%d, r%d, %d\n", a->d, a->a, a->l); check_r0_write(a->d); tcg_gen_sari_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1= )); return true; @@ -1024,7 +954,6 @@ static bool trans_l_srai(DisasContext *dc, arg_dal *a,= uint32_t insn) =20 static bool trans_l_rori(DisasContext *dc, arg_dal *a, uint32_t insn) { - LOG_DIS("l.rori r%d, r%d, %d\n", a->d, a->a, a->l); check_r0_write(a->d); tcg_gen_rotri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - = 1)); return true; @@ -1032,7 +961,6 @@ static bool trans_l_rori(DisasContext *dc, arg_dal *a,= uint32_t insn) =20 static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a, uint32_t insn) { - LOG_DIS("l.movhi r%d, %d\n", a->d, a->k); check_r0_write(a->d); tcg_gen_movi_tl(cpu_R[a->d], a->k << 16); return true; @@ -1040,7 +968,6 @@ static bool trans_l_movhi(DisasContext *dc, arg_l_movh= i *a, uint32_t insn) =20 static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a, uint32_t insn) { - LOG_DIS("l.macrc r%d\n", a->d); check_r0_write(a->d); tcg_gen_trunc_i64_tl(cpu_R[a->d], cpu_mac); tcg_gen_movi_i64(cpu_mac, 0); @@ -1049,147 +976,126 @@ static bool trans_l_macrc(DisasContext *dc, arg_l_= macrc *a, uint32_t insn) =20 static bool trans_l_sfeq(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfeq r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_sfne(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfne r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_sfgtu(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfgtu r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_sfgeu(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfgeu r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_sfltu(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfltu r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_sfleu(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfleu r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_sfgts(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfgts r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_sfges(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfges r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_sflts(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sflts r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_sfles(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfles r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfeqi r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 static bool trans_l_sfnei(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfnei r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfgtui r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfgeui r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 static bool trans_l_sfltui(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfltui r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 static bool trans_l_sfleui(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfleui r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfgtsi r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfgesi r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfltsi r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 static bool trans_l_sflesi(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sflesi r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 static bool trans_l_sys(DisasContext *dc, arg_l_sys *a, uint32_t insn) { - LOG_DIS("l.sys %d\n", a->k); tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); gen_exception(dc, EXCP_SYSCALL); dc->base.is_jmp =3D DISAS_NORETURN; @@ -1198,7 +1104,6 @@ static bool trans_l_sys(DisasContext *dc, arg_l_sys *= a, uint32_t insn) =20 static bool trans_l_trap(DisasContext *dc, arg_l_trap *a, uint32_t insn) { - LOG_DIS("l.trap %d\n", a->k); tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); gen_exception(dc, EXCP_TRAP); dc->base.is_jmp =3D DISAS_NORETURN; @@ -1207,27 +1112,22 @@ static bool trans_l_trap(DisasContext *dc, arg_l_tr= ap *a, uint32_t insn) =20 static bool trans_l_msync(DisasContext *dc, arg_l_msync *a, uint32_t insn) { - LOG_DIS("l.msync\n"); tcg_gen_mb(TCG_MO_ALL); return true; } =20 static bool trans_l_psync(DisasContext *dc, arg_l_psync *a, uint32_t insn) { - LOG_DIS("l.psync\n"); return true; } =20 static bool trans_l_csync(DisasContext *dc, arg_l_csync *a, uint32_t insn) { - LOG_DIS("l.csync\n"); return true; } =20 static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn) { - LOG_DIS("l.rfe\n"); - #ifdef CONFIG_USER_ONLY gen_illegal_exception(dc); #else @@ -1274,56 +1174,48 @@ static void do_fpcmp(DisasContext *dc, arg_ab *a, =20 static bool trans_lf_add_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("lf.add.s r%d, r%d, r%d\n", a->d, a->a, a->b); do_fp3(dc, a, gen_helper_float_add_s); return true; } =20 static bool trans_lf_sub_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("lf.sub.s r%d, r%d, r%d\n", a->d, a->a, a->b); do_fp3(dc, a, gen_helper_float_sub_s); return true; } =20 static bool trans_lf_mul_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("lf.mul.s r%d, r%d, r%d\n", a->d, a->a, a->b); do_fp3(dc, a, gen_helper_float_mul_s); return true; } =20 static bool trans_lf_div_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("lf.div.s r%d, r%d, r%d\n", a->d, a->a, a->b); do_fp3(dc, a, gen_helper_float_div_s); return true; } =20 static bool trans_lf_rem_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("lf.rem.s r%d, r%d, r%d\n", a->d, a->a, a->b); do_fp3(dc, a, gen_helper_float_rem_s); return true; } =20 static bool trans_lf_itof_s(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("lf.itof.s r%d, r%d\n", a->d, a->a); do_fp2(dc, a, gen_helper_itofs); return true; } =20 static bool trans_lf_ftoi_s(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("lf.ftoi.s r%d, r%d\n", a->d, a->a); do_fp2(dc, a, gen_helper_ftois); return true; } =20 static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("lf.madd.s r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); gen_helper_float_madd_s(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); @@ -1333,42 +1225,36 @@ static bool trans_lf_madd_s(DisasContext *dc, arg_d= ab *a, uint32_t insn) =20 static bool trans_lf_sfeq_s(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("lf.sfeq.s r%d, r%d\n", a->a, a->b); do_fpcmp(dc, a, gen_helper_float_eq_s, false, false); return true; } =20 static bool trans_lf_sfne_s(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("lf.sfne.s r%d, r%d\n", a->a, a->b); do_fpcmp(dc, a, gen_helper_float_eq_s, true, false); return true; } =20 static bool trans_lf_sfgt_s(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("lf.sfgt.s r%d, r%d\n", a->a, a->b); do_fpcmp(dc, a, gen_helper_float_lt_s, false, true); return true; } =20 static bool trans_lf_sfge_s(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("lf.sfge.s r%d, r%d\n", a->a, a->b); do_fpcmp(dc, a, gen_helper_float_le_s, false, true); return true; } =20 static bool trans_lf_sflt_s(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("lf.sflt.s r%d, r%d\n", a->a, a->b); do_fpcmp(dc, a, gen_helper_float_lt_s, false, false); return true; } =20 static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("lf.sfle.s r%d, r%d\n", a->a, a->b); do_fpcmp(dc, a, gen_helper_float_le_s, false, false); return true; } diff --git a/target/openrisc/Makefile.objs b/target/openrisc/Makefile.objs index 1b98a911ea..8b8a890c59 100644 --- a/target/openrisc/Makefile.objs +++ b/target/openrisc/Makefile.objs @@ -1,5 +1,5 @@ obj-$(CONFIG_SOFTMMU) +=3D machine.o -obj-y +=3D cpu.o exception.o interrupt.o mmu.o translate.o +obj-y +=3D cpu.o exception.o interrupt.o mmu.o translate.o disas.o obj-y +=3D exception_helper.o fpu_helper.o \ interrupt_helper.o mmu_helper.o sys_helper.o obj-y +=3D gdbstub.o @@ -12,3 +12,4 @@ target/openrisc/decode.inc.c: \ $(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@) =20 target/openrisc/translate.o: target/openrisc/decode.inc.c +target/openrisc/disas.o: target/openrisc/decode.inc.c --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gdll25WvOZuztr1hmk/CT+S5g3LKYtpRoC2GPEK/peQ=; b=UkrJvCWhxGV/2o6iO17EzCzdaOdV6NsSk54F6o6NJ28hbU9V5RCmYki8k8ZK9+O2QB 7c0eeMVGqES+8cvLoS9WL6i/IL4rAmY8tlUSQN90Rl96rue2K0vwIQnhf2kxNCEH1kAM nv3cdX9pH6e+lkw5/yBWUMlAk49i/Qnec3ytQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gdll25WvOZuztr1hmk/CT+S5g3LKYtpRoC2GPEK/peQ=; b=OugAOuHzNz76ePowBZf13RYGGHEl8KkDqsx6W3YKBlCa/pKlu8TFRVVsmW1a3FA6eX JckblQwNk/1pjLXTjH3wKHBkcC36cRztvSe5Z1Yn8dNdh11zVgRrV4sZxDbT/1D+mpWE jocT886Ew4CaA9RTUqCccWs+XslC42zedQKv5GAL6QEnWvn7oYYdkvNFAV14SjCBho1P yB29g1cTG8Pium8Lkf8EedAlCWyVVAxi9OhR8HmOr5NG8SysAK1r3RfjNEUHH85hbaU0 QQHwAaUZg2qnDgZQ0pp/qkbwt8NDqKc9EGYe+p1s4L2WmvlrxgBzMNR/OvwzWWZBkL3D nWtA== X-Gm-Message-State: APt69E3iw48cJ1XhJUmUM1NoJ3/NVyioeurpYvSHODWXW46McQuXSeX5 l0uWfHyFhtRNcCa3eIsQEBsDwWPZ+Dk= X-Google-Smtp-Source: AAOMgpfNI8aUhEyrjYXRT59m7vOX+P8bCdOuG0oyIs5Weo9LnatnQLFoh3nOznKvyhtaqLWbaayvLQ== X-Received: by 2002:a62:4395:: with SMTP id l21-v6mr8454307pfi.196.1530155016706; Wed, 27 Jun 2018 20:03:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:10 -0700 Message-Id: <20180628030330.15615-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::235 Subject: [Qemu-devel] [PATCH v3 03/23] target/openrisc: Log interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/openrisc/interrupt.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 3959671c59..25351d5de3 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -32,6 +32,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) #ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); CPUOpenRISCState *env =3D &cpu->env; + int exception =3D cs->exception_index; =20 env->epcr =3D env->pc; if (env->dflag) { @@ -41,12 +42,12 @@ void openrisc_cpu_do_interrupt(CPUState *cs) } else { env->sr &=3D ~SR_DSX; } - if (cs->exception_index =3D=3D EXCP_SYSCALL) { + if (exception =3D=3D EXCP_SYSCALL) { env->epcr +=3D 4; } /* When we have an illegal instruction the error effective address shall be set to the illegal instruction address. */ - if (cs->exception_index =3D=3D EXCP_ILLEGAL) { + if (exception =3D=3D EXCP_ILLEGAL) { env->eear =3D env->pc; } =20 @@ -66,8 +67,27 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->tlb->cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys_nom= mu; env->lock_addr =3D -1; =20 - if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { - hwaddr vect_pc =3D cs->exception_index << 8; + if (exception > 0 && exception < EXCP_NR) { + static const char * const int_name[EXCP_NR] =3D { + [EXCP_RESET] =3D "RESET", + [EXCP_BUSERR] =3D "BUSERR (bus error)", + [EXCP_DPF] =3D "DFP (data protection fault)", + [EXCP_IPF] =3D "IPF (code protection fault)", + [EXCP_TICK] =3D "TICK (timer interrupt)", + [EXCP_ALIGN] =3D "ALIGN", + [EXCP_ILLEGAL] =3D "ILLEGAL", + [EXCP_INT] =3D "INT (device interrupt)", + [EXCP_DTLBMISS] =3D "DTLBMISS (data tlb miss)", + [EXCP_ITLBMISS] =3D "ITLBMISS (code tlb miss)", + [EXCP_RANGE] =3D "RANGE", + [EXCP_SYSCALL] =3D "SYSCALL", + [EXCP_FPE] =3D "FPE", + [EXCP_TRAP] =3D "TRAP", + }; + + qemu_log_mask(CPU_LOG_INT, "INT: %s\n", int_name[exception]); + + hwaddr vect_pc =3D exception << 8; if (env->cpucfgr & CPUCFGR_EVBARP) { vect_pc |=3D env->evbar; } @@ -76,7 +96,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) } env->pc =3D vect_pc; } else { - cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); + cpu_abort(cs, "Unhandled exception 0x%x\n", exception); } #endif =20 --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530155327744363.67012711914094; Wed, 27 Jun 2018 20:08:47 -0700 (PDT) Received: from localhost ([::1]:34258 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNIc-000052-Uw for importer@patchew.org; Wed, 27 Jun 2018 23:08:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39856) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNDg-0004tp-GB for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNDf-0007e1-KO for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:40 -0400 Received: from mail-pf0-x230.google.com ([2607:f8b0:400e:c00::230]:40667) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNDf-0007dp-E6 for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:39 -0400 Received: by mail-pf0-x230.google.com with SMTP id z24-v6so1887375pfe.7 for ; Wed, 27 Jun 2018 20:03:39 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RMq3UagQQRq1eCWiLtYcyhJ383CIfBeY/Y6nCwoDUMU=; b=TMkSBt5Xmqn6EAbJ9CRWOgPFjImVOfGS/OGqz3z0u6Xc7FA4olgQ9uNjEjWHV4B66H lcY//uT1ZjHDWl8x9eS2L6qJrUHy6vZCQu6ZPmYawAOe6vYr1sRLrvqRKu9lt3WG1Xm9 w/n2Xg1a54Bbzay6kbrWv5f8ylnquNJCF1d4w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RMq3UagQQRq1eCWiLtYcyhJ383CIfBeY/Y6nCwoDUMU=; b=FWJvpfFBTDeHDUIHc9oMOXAqjgGfblGPSDu/QgIAOz9aHj72rY3LaPBHigz88gpE8Y ahThzJRfYxBeaENNiC4ZLuwfNz3jhFcZ2RY7X59zC6y1s1rMevgV9EZDVciYy6OnA7Rz xosd0nI/ItlP9tw4r5r4/HuWmhBJ3Co2ZvE5QK8xQKNyf1qW30BORsIkmbh1vG9AO3DG oQatT+jAFHsNIVPPe5yfVIv/NaU7kLCkWYUQVnAGz/OMr/8cy8VcJNx6+5QrVHWT2JSV c7a3pOgEeSbsrL/I1Jrtpv+tMomQEonZjLjoUWmOgpgRWTjyfL0HkkDSrvq3ykwl3sXQ tVRA== X-Gm-Message-State: APt69E3zT3AI7AIX51vY0w5AdToWCd8y7Rbxnm6zvT6LsiUKgxuGqbuT ngconou8r+KYLUV3FV0sgn9lDSue260= X-Google-Smtp-Source: AAOMgpdU6nA5k2buePgzDbkAnOHn+Ct8L7rXZK7+6IxhbVG+O8D3CpOrYJiVygl+Y8Bfx6Lj+ACwlw== X-Received: by 2002:a62:e310:: with SMTP id g16-v6mr8360528pfh.25.1530155018065; Wed, 27 Jun 2018 20:03:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:11 -0700 Message-Id: <20180628030330.15615-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::230 Subject: [Qemu-devel] [PATCH v3 04/23] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 These values are unused. Reviewed-by: Stafford Horne Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index fbdc2058dc..f5af515979 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -37,9 +37,7 @@ #include "exec/log.h" =20 /* is_jmp field values */ -#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ -#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ =20 typedef struct DisasContext { DisasContextBase base; @@ -1353,8 +1351,6 @@ static void openrisc_tr_tb_stop(DisasContextBase *dcb= ase, CPUState *cs) gen_goto_tb(dc, 0, dc->base.pc_next); break; case DISAS_NORETURN: - case DISAS_JUMP: - case DISAS_TB_JUMP: break; case DISAS_UPDATE: /* indicate that the hash table must be used --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530155160960786.6483968024821; Wed, 27 Jun 2018 20:06:00 -0700 (PDT) Received: from localhost ([::1]:34247 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNFs-0006Jz-S2 for importer@patchew.org; Wed, 27 Jun 2018 23:05:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39872) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNDh-0004uh-UT for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNDg-0007eQ-Tl for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:41 -0400 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:40768) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNDg-0007eC-O1 for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:40 -0400 Received: by mail-pl0-x242.google.com with SMTP id t6-v6so2010179plo.7 for ; Wed, 27 Jun 2018 20:03:40 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aJQOgLhmdjBLyZG1/Zx4n3oTLHrsOdzZdDsXgKO1Fbs=; b=Qc1QHJBtiIAfPJ1ApE6hveDp9rhMdhl1MedtecbTxilS1nfyRlJr/k6f8WSpV/2OeN U+4zHrxE+BDZa6HD4qpSj7hG+lUcQuAEnH6Xp339i/789BNZRCfojwuslBWkiyeRalu7 i3SKq0uVDJAsqpdh/IrbnSA/Xid6o/ZumSZz0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aJQOgLhmdjBLyZG1/Zx4n3oTLHrsOdzZdDsXgKO1Fbs=; b=G3ZbDhMpxyyedY/2RMXxD0KhEF9GfoHtKLOgDWGLBvInjXcMf9dKJ+lDCQ1+nsPRNk eFx6ouRqWJAn/xdOQ0pd7AzKHBtBTBIxzq83NCyoL8G/3dhDpPuoympSTebq5ZJPFn/c zaobl0axvosixOuM4olSTRlSYONs662lPlXYTlnmyRylp1q+6xmxqe1Nvcv2ZFD+RAHd HxVSfyWJe8d1f7UZUdQn3R4TfWBzElDPC6SW2Y3Xzd9GYC+u1xdkbypLRuH3Di+OUiyz FCk3ueGr+QX2EWcKjD8cgRvxXsx0o5e8iWlsDOuJWYmiUl0yo17n9bO+c8L/RXCdy/JN zDwQ== X-Gm-Message-State: APt69E0BxqCpcHD5Vws5GgYcquBkHzZGZwwwsThL5GZuHLowIZkXYvqI Zp3XfL/4YQJRkNhigygtYcm1uEMGOig= X-Google-Smtp-Source: ADUXVKJSVA808vf2iTXyPK13yW4YGP4GaPIcOduXAEiTgrpSIPrjoS89Kf7Z7fpr+TtsdRAQfVQJzg== X-Received: by 2002:a17:902:7b95:: with SMTP id w21-v6mr8703843pll.150.1530155019461; Wed, 27 Jun 2018 20:03:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:12 -0700 Message-Id: <20180628030330.15615-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v3 05/23] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No need to use the interrupt mechanisms when we can simply exit the tb directly. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/interrupt_helper.c | 3 +-- target/openrisc/translate.c | 6 +++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt= _helper.c index 56620e0571..b865738f8b 100644 --- a/target/openrisc/interrupt_helper.c +++ b/target/openrisc/interrupt_helper.c @@ -26,7 +26,6 @@ void HELPER(rfe)(CPUOpenRISCState *env) { OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); #ifndef CONFIG_USER_ONLY int need_flush_tlb =3D (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^ (cpu->env.esr & (SR_SM | SR_IME | SR_DME)); @@ -53,8 +52,8 @@ void HELPER(rfe)(CPUOpenRISCState *env) } =20 if (need_flush_tlb) { + CPUState *cs =3D CPU(cpu); tlb_flush(cs); } #endif - cs->interrupt_request |=3D CPU_INTERRUPT_EXITTB; } diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index f5af515979..43bdf378eb 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -37,6 +37,7 @@ #include "exec/log.h" =20 /* is_jmp field values */ +#define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ =20 typedef struct DisasContext { @@ -1133,7 +1134,7 @@ static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *= a, uint32_t insn) gen_illegal_exception(dc); } else { gen_helper_rfe(cpu_env); - dc->base.is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_EXIT; } #endif return true; @@ -1353,8 +1354,7 @@ static void openrisc_tr_tb_stop(DisasContextBase *dcb= ase, CPUState *cs) case DISAS_NORETURN: break; case DISAS_UPDATE: - /* indicate that the hash table must be used - to find the next TB */ + case DISAS_EXIT: tcg_gen_exit_tb(NULL, 0); break; default: --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530155327600303.1359307214841; Wed, 27 Jun 2018 20:08:47 -0700 (PDT) Received: from localhost ([::1]:34259 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNIc-000062-PW for importer@patchew.org; Wed, 27 Jun 2018 23:08:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39889) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNDj-0004w4-7d for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNDi-0007g3-CW for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:43 -0400 Received: from mail-pl0-x230.google.com ([2607:f8b0:400e:c01::230]:44071) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNDi-0007fQ-7L for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:42 -0400 Received: by mail-pl0-x230.google.com with SMTP id m16-v6so2005323pls.11 for ; Wed, 27 Jun 2018 20:03:42 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c01::230 Subject: [Qemu-devel] [PATCH v3 06/23] target/openrisc: Fix singlestep_enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We failed to store to cpu_pc before raising the exception, which caused us to re-execute the same insn that we stepped. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 43bdf378eb..22848b17ad 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1335,31 +1335,30 @@ static void openrisc_tr_tb_stop(DisasContextBase *d= cbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 + /* If we have already exited the TB, nothing following has effect. */ + if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { + return; + } + if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) !=3D (dc->delayed_branch != =3D 0)) { tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch !=3D 0); } =20 tcg_gen_movi_tl(cpu_ppc, dc->base.pc_next - 4); - if (dc->base.is_jmp =3D=3D DISAS_NEXT) { - dc->base.is_jmp =3D DISAS_UPDATE; - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); - } - if (unlikely(dc->base.singlestep_enabled)) { - gen_exception(dc, EXCP_DEBUG); - } else { - switch (dc->base.is_jmp) { - case DISAS_TOO_MANY: - gen_goto_tb(dc, 0, dc->base.pc_next); - break; - case DISAS_NORETURN: - break; - case DISAS_UPDATE: - case DISAS_EXIT: + switch (dc->base.is_jmp) { + case DISAS_TOO_MANY: + gen_goto_tb(dc, 0, dc->base.pc_next); + break; + case DISAS_UPDATE: + case DISAS_EXIT: + if (unlikely(dc->base.singlestep_enabled)) { + gen_exception(dc, EXCP_DEBUG); + } else { tcg_gen_exit_tb(NULL, 0); - break; - default: - g_assert_not_reached(); } + break; + default: + g_assert_not_reached(); } } =20 --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530155550383444.2751745788021; Wed, 27 Jun 2018 20:12:30 -0700 (PDT) Received: from localhost ([::1]:34281 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNMD-0003W3-Ie for importer@patchew.org; Wed, 27 Jun 2018 23:12:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39902) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNDk-0004xu-UA for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNDj-0007iL-JU for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:44 -0400 Received: from mail-pl0-x230.google.com ([2607:f8b0:400e:c01::230]:43239) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNDj-0007h6-Bx for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:43 -0400 Received: by mail-pl0-x230.google.com with SMTP id c41-v6so2003026plj.10 for ; Wed, 27 Jun 2018 20:03:43 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+cJgkwx/ep9kNHhp/NZWR+Qsl0Zh1HJMnithEE7rNEI=; b=XdghUrcA3PUsKTeIIO/xXyJjYMeUpMiU5gx5HCuxt5D+VtENUNoGXuWFbs83Z8KZvb WmGnm5pCA90Xm84cIlIGeL+ojzFySJyCAZXATTUE/E4+gR3c6GC+O2n2ABt6KYHbZoi2 LuGOjHx5aQvmeeILYJsreFzqpzDfZR2zOI1cA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+cJgkwx/ep9kNHhp/NZWR+Qsl0Zh1HJMnithEE7rNEI=; b=mRIRd3yN3Roh0qDVr5wS7VvshiKa2H0UC0oqIkkxSBB44zwV18fngLgHbM9y2rrr69 f9S651JF+cQVz+UOoDr9+XwGy55ZvHb6h7+8dTBA9zK4K+glu4yUo6P/UBi/pKBtn/Ex +5NgwNag1guMfXt6mj5omDZLUDnvJg3xmPvIkyO9GHG9fNTQJ19zgemytrMyvze7pPHx sBvZASqBUWMdoCAGVC5O8/SAUnS7y9GIaBXkXNGhaANvKngvNyaZf08hjzop3om7iz4W se1I9gJJ0waBCYMn4Luf6FF9glV4XG+uatkOkpE1W39UlX4o3gYtY24RHMMut19v5WEN Ydrg== X-Gm-Message-State: APt69E2AD+cA/oh/em0o7ILPZApDUMnW/1VArtJokgabMtx3/zjGKCGE XOxyoT5Lq9fTFkhcD6Gaxy/wTa+Abu8= X-Google-Smtp-Source: ADUXVKInZebU6zQpOdsEf6mGoooBdNdw0EDxIDqP7qWhzhuSQrQk98ZpQzq4OuUW4Fksf2STZzMUnA== X-Received: by 2002:a17:902:8d91:: with SMTP id v17-v6mr8773071plo.9.1530155022151; Wed, 27 Jun 2018 20:03:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:14 -0700 Message-Id: <20180628030330.15615-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::230 Subject: [Qemu-devel] [PATCH v3 07/23] target/openrisc: Link more translation blocks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Track direct jumps via dc->jmp_pc_imm. Use that in preference to jmp_pc when possible. Emit goto_tb in that case, and lookup_and_goto_tb otherwise. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 96 +++++++++++++++++++++---------------- 1 file changed, 55 insertions(+), 41 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 22848b17ad..a618d39242 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -38,13 +38,16 @@ =20 /* is_jmp field values */ #define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */ -#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_JUMP DISAS_TARGET_1 /* exit via jmp_pc/jmp_pc_imm */ =20 typedef struct DisasContext { DisasContextBase base; uint32_t mem_idx; uint32_t tb_flags; uint32_t delayed_branch; + + /* If not -1, jmp_pc contains this value and so is a direct jump. */ + target_ulong jmp_pc_imm; } DisasContext; =20 /* Include the auto-generated decoder. */ @@ -160,34 +163,6 @@ static void check_ov64s(DisasContext *dc) } \ } while (0) =20 -static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) -{ - if (unlikely(dc->base.singlestep_enabled)) { - return false; - } - -#ifndef CONFIG_USER_ONLY - return (dc->base.tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE= _MASK); -#else - return true; -#endif -} - -static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) -{ - if (use_goto_tb(dc, dest)) { - tcg_gen_movi_tl(cpu_pc, dest); - tcg_gen_goto_tb(n); - tcg_gen_exit_tb(dc->base.tb, n); - } else { - tcg_gen_movi_tl(cpu_pc, dest); - if (dc->base.singlestep_enabled) { - gen_exception(dc, EXCP_DEBUG); - } - tcg_gen_exit_tb(NULL, 0); - } -} - static void gen_ove_cy(DisasContext *dc) { if (dc->tb_flags & SR_OVE) { @@ -621,6 +596,7 @@ static bool trans_l_j(DisasContext *dc, arg_l_j *a, uin= t32_t insn) target_ulong tmp_pc =3D dc->base.pc_next + a->n * 4; =20 tcg_gen_movi_tl(jmp_pc, tmp_pc); + dc->jmp_pc_imm =3D tmp_pc; dc->delayed_branch =3D 2; return true; } @@ -634,6 +610,7 @@ static bool trans_l_jal(DisasContext *dc, arg_l_jal *a,= uint32_t insn) /* Optimize jal being used to load the PC for PIC. */ if (tmp_pc !=3D ret_pc) { tcg_gen_movi_tl(jmp_pc, tmp_pc); + dc->jmp_pc_imm =3D tmp_pc; dc->delayed_branch =3D 2; } return true; @@ -1267,6 +1244,8 @@ static void openrisc_tr_init_disas_context(DisasConte= xtBase *dcb, CPUState *cs) dc->mem_idx =3D cpu_mmu_index(env, false); dc->tb_flags =3D dc->base.tb->flags; dc->delayed_branch =3D (dc->tb_flags & TB_FLAGS_DFLAG) !=3D 0; + dc->jmp_pc_imm =3D -1; + bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns =3D MIN(dc->base.max_insns, bound); } @@ -1319,37 +1298,72 @@ static void openrisc_tr_translate_insn(DisasContext= Base *dcbase, CPUState *cs) } dc->base.pc_next +=3D 4; =20 - /* delay slot */ - if (dc->delayed_branch) { - dc->delayed_branch--; - if (!dc->delayed_branch) { - tcg_gen_mov_tl(cpu_pc, jmp_pc); - tcg_gen_discard_tl(jmp_pc); - dc->base.is_jmp =3D DISAS_UPDATE; - return; - } + /* When exiting the delay slot normally, exit via jmp_pc. + * For DISAS_NORETURN, we have raised an exception and already exited. + * For DISAS_EXIT, we found l.rfe in a delay slot. There's nothing + * in the manual saying this is illegal, but it surely it should. + * At least or1ksim overrides pcnext and ignores the branch. + */ + if (dc->delayed_branch + && --dc->delayed_branch =3D=3D 0 + && dc->base.is_jmp =3D=3D DISAS_NEXT) { + dc->base.is_jmp =3D DISAS_JUMP; } } =20 static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); + target_ulong jmp_dest; =20 /* If we have already exited the TB, nothing following has effect. */ if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { return; } =20 + /* Adjust the delayed branch state for the next TB. */ if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) !=3D (dc->delayed_branch != =3D 0)) { tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch !=3D 0); } =20 - tcg_gen_movi_tl(cpu_ppc, dc->base.pc_next - 4); + /* For DISAS_TOO_MANY, jump to the next insn. */ + jmp_dest =3D dc->base.pc_next; + tcg_gen_movi_tl(cpu_ppc, jmp_dest - 4); + switch (dc->base.is_jmp) { + case DISAS_JUMP: + jmp_dest =3D dc->jmp_pc_imm; + if (jmp_dest =3D=3D -1) { + /* The jump destination is indirect/computed; use jmp_pc. */ + tcg_gen_mov_tl(cpu_pc, jmp_pc); + tcg_gen_discard_tl(jmp_pc); + if (unlikely(dc->base.singlestep_enabled)) { + gen_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_lookup_and_goto_ptr(); + } + break; + } + /* The jump destination is direct; use jmp_pc_imm. + However, we will have stored into jmp_pc as well; + we know now that it wasn't needed. */ + tcg_gen_discard_tl(jmp_pc); + /* fallthru */ + case DISAS_TOO_MANY: - gen_goto_tb(dc, 0, dc->base.pc_next); + if (unlikely(dc->base.singlestep_enabled)) { + tcg_gen_movi_tl(cpu_pc, jmp_dest); + gen_exception(dc, EXCP_DEBUG); + } else if ((dc->base.pc_first ^ jmp_dest) & TARGET_PAGE_MASK) { + tcg_gen_movi_tl(cpu_pc, jmp_dest); + tcg_gen_lookup_and_goto_ptr(); + } else { + tcg_gen_goto_tb(0); + tcg_gen_movi_tl(cpu_pc, jmp_dest); + tcg_gen_exit_tb(dc->base.tb, 0); + } break; - case DISAS_UPDATE: + case DISAS_EXIT: if (unlikely(dc->base.singlestep_enabled)) { gen_exception(dc, EXCP_DEBUG); --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530155500169366.9090132666844; Wed, 27 Jun 2018 20:11:40 -0700 (PDT) Received: from localhost ([::1]:34277 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNLG-0002hH-ON for importer@patchew.org; Wed, 27 Jun 2018 23:11:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39942) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNDo-00050Y-S6 for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNDk-0007l6-TF for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:48 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:45138) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNDk-0007jM-Mf for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:44 -0400 Received: by mail-pf0-x242.google.com with SMTP id a22-v6so1883172pfo.12 for ; Wed, 27 Jun 2018 20:03:44 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v3 08/23] target/openrisc: Split out is_user X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This allows us to limit the amount of ifdefs and isolate the test for usermode. Reviewed-by: Stafford Horne Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index a618d39242..db149986af 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -50,6 +50,15 @@ typedef struct DisasContext { target_ulong jmp_pc_imm; } DisasContext; =20 +static inline bool is_user(DisasContext *dc) +{ +#ifdef CONFIG_USER_ONLY + return true; +#else + return dc->mem_idx =3D=3D MMU_USER_IDX; +#endif +} + /* Include the auto-generated decoder. */ #include "decode.inc.c" =20 @@ -853,33 +862,25 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfs= pr *a, uint32_t insn) { check_r0_write(a->d); =20 -#ifdef CONFIG_USER_ONLY - gen_illegal_exception(dc); -#else - if (dc->mem_idx =3D=3D MMU_USER_IDX) { + if (is_user(dc)) { gen_illegal_exception(dc); } else { TCGv_i32 ti =3D tcg_const_i32(a->k); gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], t= i); tcg_temp_free_i32(ti); } -#endif return true; } =20 static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) { -#ifdef CONFIG_USER_ONLY - gen_illegal_exception(dc); -#else - if (dc->mem_idx =3D=3D MMU_USER_IDX) { + if (is_user(dc)) { gen_illegal_exception(dc); } else { TCGv_i32 ti =3D tcg_const_i32(a->k); gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti); tcg_temp_free_i32(ti); } -#endif return true; } =20 @@ -1104,16 +1105,12 @@ static bool trans_l_csync(DisasContext *dc, arg_l_c= sync *a, uint32_t insn) =20 static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn) { -#ifdef CONFIG_USER_ONLY - gen_illegal_exception(dc); -#else - if (dc->mem_idx =3D=3D MMU_USER_IDX) { + if (is_user(dc)) { gen_illegal_exception(dc); } else { gen_helper_rfe(cpu_env); dc->base.is_jmp =3D DISAS_EXIT; } -#endif return true; } =20 --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530155330710264.8234741446131; Wed, 27 Jun 2018 20:08:50 -0700 (PDT) Received: from localhost ([::1]:34260 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNIf-00008V-Un for importer@patchew.org; Wed, 27 Jun 2018 23:08:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39940) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNDo-00050X-RP for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNDm-0007nW-BM for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:48 -0400 Received: from mail-pg0-x22a.google.com ([2607:f8b0:400e:c05::22a]:45810) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNDm-0007mt-3x for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:46 -0400 Received: by mail-pg0-x22a.google.com with SMTP id z1-v6so1790113pgv.12 for ; Wed, 27 Jun 2018 20:03:45 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dSZQhtzn1k0rEud0t3gj0aR0y80zWn5TQzJYzMcrdao=; b=Tmcbgj3rb01wwZH+qw6tYVfSkLzoKdv/0sYvpJPQkX1HxjZLPt9D7tv/voXslUf9AB 13mt7r6KoBGWFQqRyDDe0p4yImApAKGu01CKCNSAxegBmiduI3k/a8XoNXoMl5X/EGlc /9UaUoAoUhB46PVyM8tZNWPRXwBheUhGJq/B8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dSZQhtzn1k0rEud0t3gj0aR0y80zWn5TQzJYzMcrdao=; b=Gs5tegtCUnOy9mJdsjPOxJjGExhB3MKNnYIYdzXHVcBBVWDLafTq4VRpf10MHHscBy 4n9vcrFjzAuwgsZwBSlRycg22hwGA9EAqnJ64YrNhXL00A8UYT0KK37btUSD0nmBmCmn szMA45clLlD3zJqjAHmuAe8UrXyUjiOIMts4ijkhOM0VbvIlYKlpN3XfjKSi6I6zvlVE BSvrQH2nVylH8qpuudfZrWnHrSxm2dsVIepGtYhA314larNqzmNQxFzVsL6iR2XzGFPp FThKTBG4oI6jg1fZwNCArma/gLTbr2ULL0/j3adewdZYFB0eQrAAA2JgcnS5o1/rSZnA Ljyw== X-Gm-Message-State: APt69E2FRHN5LJxCeh57zmEQyvQIUzq3vGGdLquTScq2BuNqbhOFWnkL FH87htwqeGh/x4c4LHARGO+yOKn9sZw= X-Google-Smtp-Source: AAOMgpfCf3mrqtgv5iPV0OjvlGUVScv7U8cdyZo7WEi8ubcJEPbRedUNsYa49WWTuRIxu9wwX8GTGQ== X-Received: by 2002:a62:642:: with SMTP id 63-v6mr8439845pfg.222.1530155024820; Wed, 27 Jun 2018 20:03:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:16 -0700 Message-Id: <20180628030330.15615-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PATCH v3 09/23] target/openrisc: Exit the TB after l.mtspr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" A store to SR changes interrupt state, which should return to the main loop to recognize that state. Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index db149986af..59605aacca 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -877,7 +877,22 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtsp= r *a, uint32_t insn) if (is_user(dc)) { gen_illegal_exception(dc); } else { - TCGv_i32 ti =3D tcg_const_i32(a->k); + TCGv_i32 ti; + + /* For SR, we will need to exit the TB to recognize the new + * exception state. For NPC, in theory this counts as a branch + * (although the SPR only exists for use by an ICE). Save all + * of the cpu state first, allowing it to be overwritten. + */ + if (dc->delayed_branch) { + tcg_gen_mov_tl(cpu_pc, jmp_pc); + tcg_gen_discard_tl(jmp_pc); + } else { + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); + } + dc->base.is_jmp =3D DISAS_EXIT; + + ti =3D tcg_const_i32(a->k); gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti); tcg_temp_free_i32(ti); } --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153015551087596.51486408165931; Wed, 27 Jun 2018 20:11:50 -0700 (PDT) Received: from localhost ([::1]:34280 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNLW-0002vh-70 for importer@patchew.org; Wed, 27 Jun 2018 23:11:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39939) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNDo-00050W-RD for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNDn-0007qW-Q3 for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:48 -0400 Received: from mail-pg0-x234.google.com ([2607:f8b0:400e:c05::234]:43008) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNDn-0007oe-KA for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:47 -0400 Received: by mail-pg0-x234.google.com with SMTP id a14-v6so1794411pgw.10 for ; Wed, 27 Jun 2018 20:03:47 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S4gTFeZHYbzKEYFy+mCAPw0hiMK8NeY0BQXvoQHvQSQ=; b=LahRxlltZXO2f3fjpHYmJb+xFN4by79AHRaGwNPFruaBWFlsnFCQWKibJSuvqMr5yn C8IG2PEtvsj87Azda2AdCR6N/PXI2weruD3Wdn7xt5T6zKSRZzQM8w2SZLPLfGwaTN1T LaOF0973N1HwJ/qTKCAGLVv6y7aIzehWvGojs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S4gTFeZHYbzKEYFy+mCAPw0hiMK8NeY0BQXvoQHvQSQ=; b=G01n2ab6B92RSVBUQUWRnsR00zLNXiur3AYsrUsVLCvbMr/WK5nmy3Obo6Dz7zmBj9 NqbsQ0FYASPTQbiGiOsV+PIR/+8FYHzREpZMkarpLAJElbSv9qgLBHSWLlzC6qE4qBB5 5438l4KKeoAoW/fiesuRFXGC2W4KmKqzamw+Osb9sjudQpCI5mCx143P9mayK80ENQVn gphGjozbbTkPqAMqpXcnFaFdN20SUlVy7zKEOmfp58dtj9kWoi/QaTTaMUH0bW+yfsx7 ULOAJ7TyU+wnB3PPIYihtYeuUGBVzW0c8XoBJ3VPIQKxVSFqaErRjD/aw9S0y4Kn4vLm jOLQ== X-Gm-Message-State: APt69E0YFdPF08WDYzzMZSPc8EWYsyMhKHoQc5YvjsZD4HLe1Gf9qfkv URKQZST5RFmSeFnGMdGU6VVTzj2NtII= X-Google-Smtp-Source: AAOMgpeD/3Gdo9EjBku1ZJq5YwHMprJakIkSA6J4bzLCAjPOYrAD2SJY26ZFPEDcOIJL3Tixga+yyA== X-Received: by 2002:a62:678f:: with SMTP id t15-v6mr4999349pfj.85.1530155026211; Wed, 27 Jun 2018 20:03:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:17 -0700 Message-Id: <20180628030330.15615-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::234 Subject: [Qemu-devel] [PATCH v3 10/23] target/openrisc: Form the spr index from tcg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Rather than pass base+offset to the helper, pass the full index. In most cases the base is r0 and optimization yields a constant. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/openrisc/helper.h | 4 ++-- target/openrisc/sys_helper.c | 9 +++------ target/openrisc/translate.c | 16 +++++++++------- 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h index e37dabc77a..9db9bf3963 100644 --- a/target/openrisc/helper.h +++ b/target/openrisc/helper.h @@ -56,5 +56,5 @@ FOP_CMP(le) DEF_HELPER_FLAGS_1(rfe, 0, void, env) =20 /* sys */ -DEF_HELPER_FLAGS_4(mtspr, 0, void, env, tl, tl, tl) -DEF_HELPER_FLAGS_4(mfspr, TCG_CALL_NO_WG, tl, env, tl, tl, tl) +DEF_HELPER_FLAGS_3(mtspr, 0, void, env, tl, tl) +DEF_HELPER_FLAGS_3(mfspr, TCG_CALL_NO_WG, tl, env, tl, tl) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 2f337363ec..2c959f63f4 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -27,13 +27,11 @@ =20 #define TO_SPR(group, number) (((group) << 11) + (number)) =20 -void HELPER(mtspr)(CPUOpenRISCState *env, - target_ulong ra, target_ulong rb, target_ulong offset) +void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong r= b) { #ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); CPUState *cs =3D CPU(cpu); - int spr =3D (ra | offset); int idx; =20 switch (spr) { @@ -202,13 +200,12 @@ void HELPER(mtspr)(CPUOpenRISCState *env, #endif } =20 -target_ulong HELPER(mfspr)(CPUOpenRISCState *env, - target_ulong rd, target_ulong ra, uint32_t offs= et) +target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, + target_ulong spr) { #ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); CPUState *cs =3D CPU(cpu); - int spr =3D (ra | offset); int idx; =20 switch (spr) { diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 59605aacca..64b5e84630 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -865,9 +865,10 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfsp= r *a, uint32_t insn) if (is_user(dc)) { gen_illegal_exception(dc); } else { - TCGv_i32 ti =3D tcg_const_i32(a->k); - gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], t= i); - tcg_temp_free_i32(ti); + TCGv spr =3D tcg_temp_new(); + tcg_gen_ori_tl(spr, cpu_R[a->a], a->k); + gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], spr); + tcg_temp_free(spr); } return true; } @@ -877,7 +878,7 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr= *a, uint32_t insn) if (is_user(dc)) { gen_illegal_exception(dc); } else { - TCGv_i32 ti; + TCGv spr; =20 /* For SR, we will need to exit the TB to recognize the new * exception state. For NPC, in theory this counts as a branch @@ -892,9 +893,10 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtsp= r *a, uint32_t insn) } dc->base.is_jmp =3D DISAS_EXIT; =20 - ti =3D tcg_const_i32(a->k); - gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti); - tcg_temp_free_i32(ti); + spr =3D tcg_temp_new(); + tcg_gen_ori_tl(spr, cpu_R[a->a], a->k); + gen_helper_mtspr(cpu_env, spr, cpu_R[a->b]); + tcg_temp_free(spr); } return true; } --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530155716071684.7356097248163; Wed, 27 Jun 2018 20:15:16 -0700 (PDT) Received: from localhost ([::1]:34295 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNOt-0005oW-50 for importer@patchew.org; Wed, 27 Jun 2018 23:15:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39965) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNDr-00051A-5D for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNDp-0007sY-A9 for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:51 -0400 Received: from mail-pf0-x233.google.com ([2607:f8b0:400e:c00::233]:39078) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNDp-0007rI-2O for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:49 -0400 Received: by mail-pf0-x233.google.com with SMTP id s21-v6so1888565pfm.6 for ; Wed, 27 Jun 2018 20:03:48 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CrBclbME8h7vRl7FDGtoB5X2GKw8cuhuB68oMAULcgI=; b=VnxZk0J+HhOR6j+CrzH37W6aZObQPCB3OMZZHtEY/krTLacNEq04MdDg4fW2psxAzx vknXzj1CUwIMmeqsxv9qI2jOgzXe57gDWywVLMTef1bYT4x2SI62eUhB3uv9lxmHsDba oqPct3en07Py6fg0C/lnZrGL9RKwMIw756ED8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CrBclbME8h7vRl7FDGtoB5X2GKw8cuhuB68oMAULcgI=; b=oS4zToruJScpOh0YBkT2GA2SKtkEV+oFzxk0bE3rZx8KpSLW5jBBXpH8mgFmBUFX2F 9otHLYNopQ3EDHBvLU72YwqBTK3Flp/o2Eop7Zlj8MeBa81sTIxxMZvPRCcSSObVehmb +AiYLN2lXrkC2+hLomJ8utDZkmNfbmOaYYsXT8zdSyHelzw0yG/gYrIiC+xXgu5OHeTh Qj4zAfvare/aj/0FRmvKV/n4idDShE7TQbVIefJQKf0kZ8cGZO9CW7vPRrZeugPDhyeL rYqcdq9RJH5JhRypbwCD8c2xbmPYY3rLBJSrPJyQP9Uqle+OI0Nw8C8UoMxncqpcFJTn t1Yw== X-Gm-Message-State: APt69E23vUWooTywOp1Gh7lGovG9p9O4On3Ohk12Z/P3+v+GJdKBMZaY JUZ4UE9oI6WQ62PXr7EY6comnzVDH6w= X-Google-Smtp-Source: AAOMgpdBMbt3xlHuPaglB7oVMoxercJ+erG0ZlvwqZL18bWfi8F9y+6ov5Yu27ssi6kbiGqhaeKrrw== X-Received: by 2002:a62:234a:: with SMTP id j71-v6mr8144618pfj.221.1530155027655; Wed, 27 Jun 2018 20:03:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:18 -0700 Message-Id: <20180628030330.15615-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::233 Subject: [Qemu-devel] [PATCH v3 11/23] target/openrisc: Merge tlb allocation into CPUOpenRISCState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There is no reason to allocate this separately. This was probably copied from target/mips which makes the same mistake. While doing so, move tlb into the clear-on-reset range. While not all of the TLB bits are guaranteed zero on reset, all of the valid bits are cleared, and the rest of the bits are unspecified. Therefore clearing the whole of the TLB is correct. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 6 ++++-- target/openrisc/interrupt.c | 4 ++-- target/openrisc/interrupt_helper.c | 8 +++---- target/openrisc/machine.c | 15 ++++++------- target/openrisc/mmu.c | 34 ++++++++++++++---------------- target/openrisc/sys_helper.c | 28 ++++++++++++------------ 6 files changed, 46 insertions(+), 49 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index c871d6bfe1..96b7f58659 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -301,6 +301,10 @@ typedef struct CPUOpenRISCState { =20 uint32_t dflag; /* In delay slot (boolean) */ =20 +#ifndef CONFIG_USER_ONLY + CPUOpenRISCTLBContext tlb; +#endif + /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 @@ -310,8 +314,6 @@ typedef struct CPUOpenRISCState { uint32_t cpucfgr; /* CPU configure register */ =20 #ifndef CONFIG_USER_ONLY - CPUOpenRISCTLBContext * tlb; - QEMUTimer *timer; uint32_t ttmr; /* Timer tick mode register */ int is_counting; diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 25351d5de3..2d0b55afa9 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -63,8 +63,8 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr &=3D ~SR_TEE; env->pmr &=3D ~PMR_DME; env->pmr &=3D ~PMR_SME; - env->tlb->cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys_nom= mu; - env->tlb->cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys_nom= mu; + env->tlb.cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys_nomm= u; + env->tlb.cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys_nomm= u; env->lock_addr =3D -1; =20 if (exception > 0 && exception < EXCP_NR) { diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt= _helper.c index b865738f8b..dc97b38704 100644 --- a/target/openrisc/interrupt_helper.c +++ b/target/openrisc/interrupt_helper.c @@ -36,18 +36,18 @@ void HELPER(rfe)(CPUOpenRISCState *env) =20 #ifndef CONFIG_USER_ONLY if (cpu->env.sr & SR_DME) { - cpu->env.tlb->cpu_openrisc_map_address_data =3D + cpu->env.tlb.cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys_data; } else { - cpu->env.tlb->cpu_openrisc_map_address_data =3D + cpu->env.tlb.cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys_nommu; } =20 if (cpu->env.sr & SR_IME) { - cpu->env.tlb->cpu_openrisc_map_address_code =3D + cpu->env.tlb.cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys_code; } else { - cpu->env.tlb->cpu_openrisc_map_address_code =3D + cpu->env.tlb.cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys_nommu; } =20 diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 0a793eb14d..c10d28b055 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -30,18 +30,18 @@ static int env_post_load(void *opaque, int version_id) =20 /* Restore MMU handlers */ if (env->sr & SR_DME) { - env->tlb->cpu_openrisc_map_address_data =3D + env->tlb.cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys_data; } else { - env->tlb->cpu_openrisc_map_address_data =3D + env->tlb.cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys_nommu; } =20 if (env->sr & SR_IME) { - env->tlb->cpu_openrisc_map_address_code =3D + env->tlb.cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys_code; } else { - env->tlb->cpu_openrisc_map_address_code =3D + env->tlb.cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys_nommu; } =20 @@ -77,10 +77,6 @@ static const VMStateDescription vmstate_cpu_tlb =3D { } }; =20 -#define VMSTATE_CPU_TLB(_f, _s) \ - VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_tlb, CPUOpenRISCTLBContext) - - static int get_sr(QEMUFile *f, void *opaque, size_t size, VMStateField *fi= eld) { CPUOpenRISCState *env =3D opaque; @@ -143,7 +139,8 @@ static const VMStateDescription vmstate_env =3D { VMSTATE_UINT32(fpcsr, CPUOpenRISCState), VMSTATE_UINT64(mac, CPUOpenRISCState), =20 - VMSTATE_CPU_TLB(tlb, CPUOpenRISCState), + VMSTATE_STRUCT(tlb, CPUOpenRISCState, 1, + vmstate_cpu_tlb, CPUOpenRISCTLBContext), =20 VMSTATE_TIMER_PTR(timer, CPUOpenRISCState), VMSTATE_UINT32(ttmr, CPUOpenRISCState), diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 2bd782f89b..5665bb7cc9 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -46,19 +46,19 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, int idx =3D vpn & ITLB_MASK; int right =3D 0; =20 - if ((cpu->env.tlb->itlb[0][idx].mr >> TARGET_PAGE_BITS) !=3D vpn) { + if ((cpu->env.tlb.itlb[0][idx].mr >> TARGET_PAGE_BITS) !=3D vpn) { return TLBRET_NOMATCH; } - if (!(cpu->env.tlb->itlb[0][idx].mr & 1)) { + if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) { return TLBRET_INVALID; } =20 if (cpu->env.sr & SR_SM) { /* supervisor mode */ - if (cpu->env.tlb->itlb[0][idx].tr & SXE) { + if (cpu->env.tlb.itlb[0][idx].tr & SXE) { right |=3D PAGE_EXEC; } } else { - if (cpu->env.tlb->itlb[0][idx].tr & UXE) { + if (cpu->env.tlb.itlb[0][idx].tr & UXE) { right |=3D PAGE_EXEC; } } @@ -67,7 +67,7 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, return TLBRET_BADADDR; } =20 - *physical =3D (cpu->env.tlb->itlb[0][idx].tr & TARGET_PAGE_MASK) | + *physical =3D (cpu->env.tlb.itlb[0][idx].tr & TARGET_PAGE_MASK) | (address & (TARGET_PAGE_SIZE-1)); *prot =3D right; return TLBRET_MATCH; @@ -81,25 +81,25 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, int idx =3D vpn & DTLB_MASK; int right =3D 0; =20 - if ((cpu->env.tlb->dtlb[0][idx].mr >> TARGET_PAGE_BITS) !=3D vpn) { + if ((cpu->env.tlb.dtlb[0][idx].mr >> TARGET_PAGE_BITS) !=3D vpn) { return TLBRET_NOMATCH; } - if (!(cpu->env.tlb->dtlb[0][idx].mr & 1)) { + if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) { return TLBRET_INVALID; } =20 if (cpu->env.sr & SR_SM) { /* supervisor mode */ - if (cpu->env.tlb->dtlb[0][idx].tr & SRE) { + if (cpu->env.tlb.dtlb[0][idx].tr & SRE) { right |=3D PAGE_READ; } - if (cpu->env.tlb->dtlb[0][idx].tr & SWE) { + if (cpu->env.tlb.dtlb[0][idx].tr & SWE) { right |=3D PAGE_WRITE; } } else { - if (cpu->env.tlb->dtlb[0][idx].tr & URE) { + if (cpu->env.tlb.dtlb[0][idx].tr & URE) { right |=3D PAGE_READ; } - if (cpu->env.tlb->dtlb[0][idx].tr & UWE) { + if (cpu->env.tlb.dtlb[0][idx].tr & UWE) { right |=3D PAGE_WRITE; } } @@ -111,7 +111,7 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, return TLBRET_BADADDR; } =20 - *physical =3D (cpu->env.tlb->dtlb[0][idx].tr & TARGET_PAGE_MASK) | + *physical =3D (cpu->env.tlb.dtlb[0][idx].tr & TARGET_PAGE_MASK) | (address & (TARGET_PAGE_SIZE-1)); *prot =3D right; return TLBRET_MATCH; @@ -126,10 +126,10 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cp= u, =20 if (rw =3D=3D MMU_INST_FETCH) { /* ITLB */ *physical =3D 0; - ret =3D cpu->env.tlb->cpu_openrisc_map_address_code(cpu, physical, + ret =3D cpu->env.tlb.cpu_openrisc_map_address_code(cpu, physical, prot, address, r= w); } else { /* DTLB */ - ret =3D cpu->env.tlb->cpu_openrisc_map_address_data(cpu, physical, + ret =3D cpu->env.tlb.cpu_openrisc_map_address_data(cpu, physical, prot, address, r= w); } =20 @@ -247,9 +247,7 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, v= addr addr) =20 void cpu_openrisc_mmu_init(OpenRISCCPU *cpu) { - cpu->env.tlb =3D g_malloc0(sizeof(CPUOpenRISCTLBContext)); - - cpu->env.tlb->cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys= _nommu; - cpu->env.tlb->cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys= _nommu; + cpu->env.tlb.cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys_= nommu; + cpu->env.tlb.cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys_= nommu; } #endif diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 2c959f63f4..ff315f6f1a 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -61,18 +61,18 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong = spr, target_ulong rb) } cpu_set_sr(env, rb); if (env->sr & SR_DME) { - env->tlb->cpu_openrisc_map_address_data =3D + env->tlb.cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys_data; } else { - env->tlb->cpu_openrisc_map_address_data =3D + env->tlb.cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys_nommu; } =20 if (env->sr & SR_IME) { - env->tlb->cpu_openrisc_map_address_code =3D + env->tlb.cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys_code; } else { - env->tlb->cpu_openrisc_map_address_code =3D + env->tlb.cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys_nommu; } break; @@ -101,14 +101,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulon= g spr, target_ulong rb) case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ idx =3D spr - TO_SPR(1, 512); if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MAS= K); + tlb_flush_page(cs, env->tlb.dtlb[0][idx].mr & TARGET_PAGE_MASK= ); } - env->tlb->dtlb[0][idx].mr =3D rb; + env->tlb.dtlb[0][idx].mr =3D rb; break; =20 case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 = */ idx =3D spr - TO_SPR(1, 640); - env->tlb->dtlb[0][idx].tr =3D rb; + env->tlb.dtlb[0][idx].tr =3D rb; break; case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ @@ -120,14 +120,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulon= g spr, target_ulong rb) case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-12= 7 */ idx =3D spr - TO_SPR(2, 512); if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MAS= K); + tlb_flush_page(cs, env->tlb.itlb[0][idx].mr & TARGET_PAGE_MASK= ); } - env->tlb->itlb[0][idx].mr =3D rb; + env->tlb.itlb[0][idx].mr =3D rb; break; =20 case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 = */ idx =3D spr - TO_SPR(2, 640); - env->tlb->itlb[0][idx].tr =3D rb; + env->tlb.itlb[0][idx].tr =3D rb; break; case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ @@ -259,11 +259,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, tar= get_ulong rd, =20 case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ idx =3D spr - TO_SPR(1, 512); - return env->tlb->dtlb[0][idx].mr; + return env->tlb.dtlb[0][idx].mr; =20 case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 = */ idx =3D spr - TO_SPR(1, 640); - return env->tlb->dtlb[0][idx].tr; + return env->tlb.dtlb[0][idx].tr; =20 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ @@ -275,11 +275,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, tar= get_ulong rd, =20 case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 = */ idx =3D spr - TO_SPR(2, 512); - return env->tlb->itlb[0][idx].mr; + return env->tlb.itlb[0][idx].mr; =20 case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 = */ idx =3D spr - TO_SPR(2, 640); - return env->tlb->itlb[0][idx].tr; + return env->tlb.itlb[0][idx].tr; =20 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530155654898734.7597382301271; Wed, 27 Jun 2018 20:14:14 -0700 (PDT) Received: from localhost ([::1]:34291 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNNu-0004x4-4R for importer@patchew.org; Wed, 27 Jun 2018 23:14:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39973) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNDt-00051C-Ad for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNDq-0007v4-Il for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:52 -0400 Received: from mail-pg0-x229.google.com ([2607:f8b0:400e:c05::229]:34555) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNDq-0007th-BF for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:50 -0400 Received: by mail-pg0-x229.google.com with SMTP id y1-v6so1801139pgv.1 for ; Wed, 27 Jun 2018 20:03:50 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=n8zIBshyKm5ShnwDFhZMEvedoWaqKvRMo6Si4yG69yo=; b=OaHaCWIK1Ntt3pU7acEuy2jFA9qQ9kIasKRknZTITxuglO7zRf0f40+gJ3h2inh324 oTFsTGtpvqRMaJMsqkWNlY6Oy3MDw0IO6oxx2dVqz4QdZShHAApVTYoUr95VGyenTUZi KOvy82nNZ3o4nZa2/u3M3MKPVBImxRWMfWEYY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=n8zIBshyKm5ShnwDFhZMEvedoWaqKvRMo6Si4yG69yo=; b=iTxXqtdUBTFPeQYYL7RYROQUwQp7ZvWakkZ5vywtGyYdXTvz6MYG5V0iBSRmgsmNNj V5HTTFivmlSY889Y0D62i3hK+QZ7qyvrw8G+jMhS5nAh1RL8GDL1GrELxDOuAoVtqmEV 9Q7NwQJ+5otb8rJTeIAJZXa8q5R82rdMJGQwoiIf05ZDVh26MeSvjYvREvoOm2FlTyX7 FmQ1GcEjZdvv3jzbMWe2C5FSNdZJt/3qbPex1pd6/h81QsRL4vM4eVzpqPfuNI+mIYiz aeJ37vjCGZ8VdFp0hOmlwv7a1mgzfiAEFr1Mi1hbEKb+cZk0OAg2YNTXn4ZGQ3ylZjtA J59w== X-Gm-Message-State: APt69E1nX2IYfbbIkRztyqPqkcT+aobBoGKqWa+izBc83WLNlRPSujmY yL3/j0JYBX8wm+WFIyImnsDKjliRb4g= X-Google-Smtp-Source: ADUXVKI+MEN8Cza+cV2G3Ql5a6QGFC3j3Qg3nNOEiRibTbuDTKqug0huEwDFFC471Cp7uZamgG95DQ== X-Received: by 2002:a65:444f:: with SMTP id e15-v6mr7438149pgq.348.1530155028984; Wed, 27 Jun 2018 20:03:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:19 -0700 Message-Id: <20180628030330.15615-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::229 Subject: [Qemu-devel] [PATCH v3 12/23] target/openrisc: Remove indirect function calls for mmu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There is no reason to use an indirect branch instead of simply testing the SR bits that control mmu state. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 11 ----- target/openrisc/cpu.c | 4 -- target/openrisc/interrupt.c | 2 - target/openrisc/interrupt_helper.c | 25 ++--------- target/openrisc/machine.c | 26 ------------ target/openrisc/mmu.c | 66 +++++++++++++----------------- target/openrisc/sys_helper.c | 15 ------- 7 files changed, 31 insertions(+), 118 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 96b7f58659..a27adad085 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -379,17 +379,6 @@ void cpu_openrisc_count_update(OpenRISCCPU *cpu); void cpu_openrisc_timer_update(OpenRISCCPU *cpu); void cpu_openrisc_count_start(OpenRISCCPU *cpu); void cpu_openrisc_count_stop(OpenRISCCPU *cpu); - -void cpu_openrisc_mmu_init(OpenRISCCPU *cpu); -int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw); -int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw); -int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw); #endif =20 #define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index fa8e342ff7..b92de51ecf 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -92,10 +92,6 @@ static void openrisc_cpu_initfn(Object *obj) OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 cs->env_ptr =3D &cpu->env; - -#ifndef CONFIG_USER_ONLY - cpu_openrisc_mmu_init(cpu); -#endif } =20 /* CPU models */ diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 2d0b55afa9..23abcf29ed 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -63,8 +63,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr &=3D ~SR_TEE; env->pmr &=3D ~PMR_DME; env->pmr &=3D ~PMR_SME; - env->tlb.cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys_nomm= u; - env->tlb.cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys_nomm= u; env->lock_addr =3D -1; =20 if (exception > 0 && exception < EXCP_NR) { diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt= _helper.c index dc97b38704..a2e9003969 100644 --- a/target/openrisc/interrupt_helper.c +++ b/target/openrisc/interrupt_helper.c @@ -29,31 +29,12 @@ void HELPER(rfe)(CPUOpenRISCState *env) #ifndef CONFIG_USER_ONLY int need_flush_tlb =3D (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^ (cpu->env.esr & (SR_SM | SR_IME | SR_DME)); -#endif - cpu->env.pc =3D cpu->env.epcr; - cpu_set_sr(&cpu->env, cpu->env.esr); - cpu->env.lock_addr =3D -1; - -#ifndef CONFIG_USER_ONLY - if (cpu->env.sr & SR_DME) { - cpu->env.tlb.cpu_openrisc_map_address_data =3D - &cpu_openrisc_get_phys_data; - } else { - cpu->env.tlb.cpu_openrisc_map_address_data =3D - &cpu_openrisc_get_phys_nommu; - } - - if (cpu->env.sr & SR_IME) { - cpu->env.tlb.cpu_openrisc_map_address_code =3D - &cpu_openrisc_get_phys_code; - } else { - cpu->env.tlb.cpu_openrisc_map_address_code =3D - &cpu_openrisc_get_phys_nommu; - } - if (need_flush_tlb) { CPUState *cs =3D CPU(cpu); tlb_flush(cs); } #endif + cpu->env.pc =3D cpu->env.epcr; + cpu->env.lock_addr =3D -1; + cpu_set_sr(&cpu->env, cpu->env.esr); } diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index c10d28b055..73e0abcfd7 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -24,31 +24,6 @@ #include "hw/boards.h" #include "migration/cpu.h" =20 -static int env_post_load(void *opaque, int version_id) -{ - CPUOpenRISCState *env =3D opaque; - - /* Restore MMU handlers */ - if (env->sr & SR_DME) { - env->tlb.cpu_openrisc_map_address_data =3D - &cpu_openrisc_get_phys_data; - } else { - env->tlb.cpu_openrisc_map_address_data =3D - &cpu_openrisc_get_phys_nommu; - } - - if (env->sr & SR_IME) { - env->tlb.cpu_openrisc_map_address_code =3D - &cpu_openrisc_get_phys_code; - } else { - env->tlb.cpu_openrisc_map_address_code =3D - &cpu_openrisc_get_phys_nommu; - } - - - return 0; -} - static const VMStateDescription vmstate_tlb_entry =3D { .name =3D "tlb_entry", .version_id =3D 1, @@ -102,7 +77,6 @@ static const VMStateDescription vmstate_env =3D { .name =3D "env", .version_id =3D 6, .minimum_version_id =3D 6, - .post_load =3D env_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32), VMSTATE_UINTTL(pc, CPUOpenRISCState), diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 5665bb7cc9..b2effaa6d7 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -29,18 +29,16 @@ #endif =20 #ifndef CONFIG_USER_ONLY -int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw) +static inline int get_phys_nommu(hwaddr *physical, int *prot, + target_ulong address) { *physical =3D address; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TLBRET_MATCH; } =20 -int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw) +static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot, + target_ulong address, int rw, bool supervisor) { int vpn =3D address >> TARGET_PAGE_BITS; int idx =3D vpn & ITLB_MASK; @@ -52,8 +50,7 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) { return TLBRET_INVALID; } - - if (cpu->env.sr & SR_SM) { /* supervisor mode */ + if (supervisor) { if (cpu->env.tlb.itlb[0][idx].tr & SXE) { right |=3D PAGE_EXEC; } @@ -62,7 +59,6 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, right |=3D PAGE_EXEC; } } - if ((rw & 2) && ((right & PAGE_EXEC) =3D=3D 0)) { return TLBRET_BADADDR; } @@ -73,9 +69,8 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, return TLBRET_MATCH; } =20 -int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw) +static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot, + target_ulong address, int rw, bool supervisor) { int vpn =3D address >> TARGET_PAGE_BITS; int idx =3D vpn & DTLB_MASK; @@ -87,8 +82,7 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) { return TLBRET_INVALID; } - - if (cpu->env.sr & SR_SM) { /* supervisor mode */ + if (supervisor) { if (cpu->env.tlb.dtlb[0][idx].tr & SRE) { right |=3D PAGE_READ; } @@ -117,20 +111,24 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, return TLBRET_MATCH; } =20 -static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, - int rw) +static int get_phys_addr(OpenRISCCPU *cpu, hwaddr *physical, + int *prot, target_ulong address, int rw) { - int ret =3D TLBRET_MATCH; + bool supervisor =3D (cpu->env.sr & SR_SM) !=3D 0; + int ret; =20 - if (rw =3D=3D MMU_INST_FETCH) { /* ITLB */ - *physical =3D 0; - ret =3D cpu->env.tlb.cpu_openrisc_map_address_code(cpu, physical, - prot, address, r= w); - } else { /* DTLB */ - ret =3D cpu->env.tlb.cpu_openrisc_map_address_data(cpu, physical, - prot, address, r= w); + /* Assume nommu results for a moment. */ + ret =3D get_phys_nommu(physical, prot, address); + + /* Overwrite with TLB lookup if enabled. */ + if (rw =3D=3D MMU_INST_FETCH) { + if (cpu->env.sr & SR_IME) { + ret =3D get_phys_code(cpu, physical, prot, address, rw, superv= isor); + } + } else { + if (cpu->env.sr & SR_DME) { + ret =3D get_phys_data(cpu, physical, prot, address, rw, superv= isor); + } } =20 return ret; @@ -186,8 +184,7 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr a= ddress, int size, hwaddr physical =3D 0; int prot =3D 0; =20 - ret =3D cpu_openrisc_get_phys_addr(cpu, &physical, &prot, - address, rw); + ret =3D get_phys_addr(cpu, &physical, &prot, address, rw); =20 if (ret =3D=3D TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, @@ -225,17 +222,16 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs,= vaddr addr) =20 /* Check memory for any kind of address, since during debug the gdb can ask for anything, check data tlb for address */ - miss =3D cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0); + miss =3D get_phys_addr(cpu, &phys_addr, &prot, addr, 0); =20 /* Check instruction tlb */ if (miss) { - miss =3D cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, - MMU_INST_FETCH); + miss =3D get_phys_addr(cpu, &phys_addr, &prot, addr, MMU_INST_FETC= H); } =20 /* Last, fall back to a plain address */ if (miss) { - miss =3D cpu_openrisc_get_phys_nommu(cpu, &phys_addr, &prot, addr,= 0); + miss =3D get_phys_nommu(&phys_addr, &prot, addr); } =20 if (miss) { @@ -244,10 +240,4 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, = vaddr addr) return phys_addr; } } - -void cpu_openrisc_mmu_init(OpenRISCCPU *cpu) -{ - cpu->env.tlb.cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys_= nommu; - cpu->env.tlb.cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys_= nommu; -} #endif diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index ff315f6f1a..9b4339b34e 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -60,21 +60,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong s= pr, target_ulong rb) tlb_flush(cs); } cpu_set_sr(env, rb); - if (env->sr & SR_DME) { - env->tlb.cpu_openrisc_map_address_data =3D - &cpu_openrisc_get_phys_data; - } else { - env->tlb.cpu_openrisc_map_address_data =3D - &cpu_openrisc_get_phys_nommu; - } - - if (env->sr & SR_IME) { - env->tlb.cpu_openrisc_map_address_code =3D - &cpu_openrisc_get_phys_code; - } else { - env->tlb.cpu_openrisc_map_address_code =3D - &cpu_openrisc_get_phys_nommu; - } break; =20 case TO_SPR(0, 18): /* PPC */ --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530155503572407.250909388334; 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Oiaw84aOleXkI3aNsvyBwT2UQxV+BKJ1RrZpjWmHXRA=; b=STy332Y+LBrX50W4fjuGzcXWDeyNKCErtHWHo/1N7bPJK+/PH2exMhWy+0iDpoKWGm Xz7iLYGedv6A2hT4Whs7soJ1xnG3HdmLFoDqIN5Ca++ULi8acZdMkXCwG7erNRwo9cFA oZOg8fBow7QFG0KLfdSVQ/6zlwQMwi74w3R78= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Oiaw84aOleXkI3aNsvyBwT2UQxV+BKJ1RrZpjWmHXRA=; b=lYd313MhcUiGF2PI/4q0FW5QqR9jZMi09311IrDMh32x1Ckvl8506wUgShl8+EubuC ps7n4K1kkhmK62mKwyw4TFiW8HplBSO2Tu8dFXpZZrK3lRnX5fulp95EQmAieQcDNCQm d70+XbLT3ThuBKwUSjlb1+DITa/75Sgq7p7kHRjtsfu6Xqu7h5DnkUJ6/AnGntM98/N+ 4WgQIGL4LLjflEcJxuGAXSPvskopM7rV4W80qGnKgV+qBtIhk6i5nokl1p4SeLpzsKlj 4e3J0vfc3vprs6Pz/QE8ph2UG3L2p342wUyhnbSwJeFynuX/vdfOCGOZt8xIYv+UZAVD jy8A== X-Gm-Message-State: APt69E0pyBfyvlBJRoCjA6PWC+aPVQUk4wCxg5pf0Q9ZPmMXn9jBsh5U CD0APn6M/FBax/YG783fbPYZ5pWW0fo= X-Google-Smtp-Source: ADUXVKIiQz+9e4+lss+paVFZ4pt6uClMAKrJbJRa+ua9fTn1js5nrcFPzssiLwlGNCkgcclTbydD3g== X-Received: by 2002:a63:4002:: with SMTP id n2-v6mr7153477pga.285.1530155030276; Wed, 27 Jun 2018 20:03:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:20 -0700 Message-Id: <20180628030330.15615-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v3 13/23] target/openrisc: Merge mmu_helper.c into mmu.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 With tlb_fill in mmu.c, we can simplify things further. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/openrisc/mmu.c | 11 ++++++++++ target/openrisc/mmu_helper.c | 40 ----------------------------------- target/openrisc/Makefile.objs | 2 +- 3 files changed, 12 insertions(+), 41 deletions(-) delete mode 100644 target/openrisc/mmu_helper.c diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index b2effaa6d7..9b4b5cf04f 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -240,4 +240,15 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, = vaddr addr) return phys_addr; } } + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + int ret =3D openrisc_cpu_handle_mmu_fault(cs, addr, size, + access_type, mmu_idx); + if (ret) { + /* Raise Exception. */ + cpu_loop_exit_restore(cs, retaddr); + } +} #endif diff --git a/target/openrisc/mmu_helper.c b/target/openrisc/mmu_helper.c deleted file mode 100644 index 97e1d17b5a..0000000000 --- a/target/openrisc/mmu_helper.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * OpenRISC MMU helper routines - * - * Copyright (c) 2011-2012 Jia Liu - * Zhizhou Zhang - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "exec/exec-all.h" -#include "exec/cpu_ldst.h" - -#ifndef CONFIG_USER_ONLY - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret =3D openrisc_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu= _idx); - - if (ret) { - /* Raise Exception. */ - cpu_loop_exit_restore(cs, retaddr); - } -} -#endif diff --git a/target/openrisc/Makefile.objs b/target/openrisc/Makefile.objs index 8b8a890c59..b5432f4684 100644 --- a/target/openrisc/Makefile.objs +++ b/target/openrisc/Makefile.objs @@ -1,7 +1,7 @@ obj-$(CONFIG_SOFTMMU) +=3D machine.o obj-y +=3D cpu.o exception.o interrupt.o mmu.o translate.o disas.o obj-y +=3D exception_helper.o fpu_helper.o \ - interrupt_helper.o mmu_helper.o sys_helper.o + interrupt_helper.o sys_helper.o obj-y +=3D gdbstub.o =20 DECODETREE =3D $(SRC_PATH)/scripts/decodetree.py --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530155670129101.43196114948478; Wed, 27 Jun 2018 20:14:30 -0700 (PDT) Received: from localhost ([::1]:34293 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNO9-00059G-85 for importer@patchew.org; Wed, 27 Jun 2018 23:14:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39998) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNDu-00052i-LQ for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNDt-0007yw-6k for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:54 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:42593) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNDs-0007yM-Up for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:53 -0400 Received: by mail-pg0-x243.google.com with SMTP id c10-v6so1794416pgu.9 for ; Wed, 27 Jun 2018 20:03:52 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 14/23] target/openrisc: Reduce tlb to a single dimension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 While we had defines for *_WAYS, we didn't define more than 1. Reduce the complexity by eliminating this unused dimension. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 6 ++---- target/openrisc/machine.c | 6 ++---- target/openrisc/mmu.c | 30 ++++++++++++++++-------------- target/openrisc/sys_helper.c | 20 ++++++++++---------- 4 files changed, 30 insertions(+), 32 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index a27adad085..eaf6cdd40e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -222,10 +222,8 @@ enum { =20 /* TLB size */ enum { - DTLB_WAYS =3D 1, DTLB_SIZE =3D 64, DTLB_MASK =3D (DTLB_SIZE-1), - ITLB_WAYS =3D 1, ITLB_SIZE =3D 64, ITLB_MASK =3D (ITLB_SIZE-1), }; @@ -256,8 +254,8 @@ typedef struct OpenRISCTLBEntry { =20 #ifndef CONFIG_USER_ONLY typedef struct CPUOpenRISCTLBContext { - OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE]; - OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE]; + OpenRISCTLBEntry itlb[ITLB_SIZE]; + OpenRISCTLBEntry dtlb[DTLB_SIZE]; =20 int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu, hwaddr *physical, diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 73e0abcfd7..b795b56dc6 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -42,11 +42,9 @@ static const VMStateDescription vmstate_cpu_tlb =3D { .minimum_version_id =3D 1, .minimum_version_id_old =3D 1, .fields =3D (VMStateField[]) { - VMSTATE_STRUCT_2DARRAY(itlb, CPUOpenRISCTLBContext, - ITLB_WAYS, ITLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, ITLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), - VMSTATE_STRUCT_2DARRAY(dtlb, CPUOpenRISCTLBContext, - DTLB_WAYS, DTLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, DTLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), VMSTATE_END_OF_LIST() } diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 9b4b5cf04f..856969a7f2 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -43,19 +43,21 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *phys= ical, int *prot, int vpn =3D address >> TARGET_PAGE_BITS; int idx =3D vpn & ITLB_MASK; int right =3D 0; + uint32_t mr =3D cpu->env.tlb.itlb[idx].mr; + uint32_t tr =3D cpu->env.tlb.itlb[idx].tr; =20 - if ((cpu->env.tlb.itlb[0][idx].mr >> TARGET_PAGE_BITS) !=3D vpn) { + if ((mr >> TARGET_PAGE_BITS) !=3D vpn) { return TLBRET_NOMATCH; } - if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) { + if (!(mr & 1)) { return TLBRET_INVALID; } if (supervisor) { - if (cpu->env.tlb.itlb[0][idx].tr & SXE) { + if (tr & SXE) { right |=3D PAGE_EXEC; } } else { - if (cpu->env.tlb.itlb[0][idx].tr & UXE) { + if (tr & UXE) { right |=3D PAGE_EXEC; } } @@ -63,8 +65,7 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physic= al, int *prot, return TLBRET_BADADDR; } =20 - *physical =3D (cpu->env.tlb.itlb[0][idx].tr & TARGET_PAGE_MASK) | - (address & (TARGET_PAGE_SIZE-1)); + *physical =3D (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK); *prot =3D right; return TLBRET_MATCH; } @@ -75,25 +76,27 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *phys= ical, int *prot, int vpn =3D address >> TARGET_PAGE_BITS; int idx =3D vpn & DTLB_MASK; int right =3D 0; + uint32_t mr =3D cpu->env.tlb.dtlb[idx].mr; + uint32_t tr =3D cpu->env.tlb.dtlb[idx].tr; =20 - if ((cpu->env.tlb.dtlb[0][idx].mr >> TARGET_PAGE_BITS) !=3D vpn) { + if ((mr >> TARGET_PAGE_BITS) !=3D vpn) { return TLBRET_NOMATCH; } - if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) { + if (!(mr & 1)) { return TLBRET_INVALID; } if (supervisor) { - if (cpu->env.tlb.dtlb[0][idx].tr & SRE) { + if (tr & SRE) { right |=3D PAGE_READ; } - if (cpu->env.tlb.dtlb[0][idx].tr & SWE) { + if (tr & SWE) { right |=3D PAGE_WRITE; } } else { - if (cpu->env.tlb.dtlb[0][idx].tr & URE) { + if (tr & URE) { right |=3D PAGE_READ; } - if (cpu->env.tlb.dtlb[0][idx].tr & UWE) { + if (tr & UWE) { right |=3D PAGE_WRITE; } } @@ -105,8 +108,7 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *phys= ical, int *prot, return TLBRET_BADADDR; } =20 - *physical =3D (cpu->env.tlb.dtlb[0][idx].tr & TARGET_PAGE_MASK) | - (address & (TARGET_PAGE_SIZE-1)); + *physical =3D (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK); *prot =3D right; return TLBRET_MATCH; } diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 9b4339b34e..7f458b0d17 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -86,14 +86,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong = spr, target_ulong rb) case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ idx =3D spr - TO_SPR(1, 512); if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.dtlb[0][idx].mr & TARGET_PAGE_MASK= ); + tlb_flush_page(cs, env->tlb.dtlb[idx].mr & TARGET_PAGE_MASK); } - env->tlb.dtlb[0][idx].mr =3D rb; + env->tlb.dtlb[idx].mr =3D rb; break; =20 case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 = */ idx =3D spr - TO_SPR(1, 640); - env->tlb.dtlb[0][idx].tr =3D rb; + env->tlb.dtlb[idx].tr =3D rb; break; case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ @@ -105,14 +105,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulon= g spr, target_ulong rb) case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-12= 7 */ idx =3D spr - TO_SPR(2, 512); if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.itlb[0][idx].mr & TARGET_PAGE_MASK= ); + tlb_flush_page(cs, env->tlb.itlb[idx].mr & TARGET_PAGE_MASK); } - env->tlb.itlb[0][idx].mr =3D rb; + env->tlb.itlb[idx].mr =3D rb; break; =20 case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 = */ idx =3D spr - TO_SPR(2, 640); - env->tlb.itlb[0][idx].tr =3D rb; + env->tlb.itlb[idx].tr =3D rb; break; case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ @@ -244,11 +244,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, tar= get_ulong rd, =20 case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ idx =3D spr - TO_SPR(1, 512); - return env->tlb.dtlb[0][idx].mr; + return env->tlb.dtlb[idx].mr; =20 case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 = */ idx =3D spr - TO_SPR(1, 640); - return env->tlb.dtlb[0][idx].tr; + return env->tlb.dtlb[idx].tr; =20 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ @@ -260,11 +260,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, tar= get_ulong rd, =20 case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 = */ idx =3D spr - TO_SPR(2, 512); - return env->tlb.itlb[0][idx].mr; + return env->tlb.itlb[idx].mr; =20 case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 = */ idx =3D spr - TO_SPR(2, 640); - return env->tlb.itlb[0][idx].tr; + return env->tlb.itlb[idx].tr; =20 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530155658409263.4819853188426; Wed, 27 Jun 2018 20:14:18 -0700 (PDT) Received: from localhost ([::1]:34292 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNNx-000507-Lg for importer@patchew.org; Wed, 27 Jun 2018 23:14:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40022) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNDy-000573-Ez for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNDu-00080z-Hk for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:58 -0400 Received: from mail-pg0-x236.google.com ([2607:f8b0:400e:c05::236]:42720) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNDu-000800-Ck for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:54 -0400 Received: by mail-pg0-x236.google.com with SMTP id c10-v6so1794446pgu.9 for ; Wed, 27 Jun 2018 20:03:54 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aHlqpS7RETtmpB2uggIW2fraBTAjhAqUaCXBJAbuBE8=; b=CxdgLthmO345k1/TbiJlil7fhHHhsK6E0ja/c5RmXXyE0cPBrdB6YP+OE8KRzOprDW CakHsDl7oiPNgUD6sMI7KtIiH/qoqNb4+V/iAy+A0HY1XeezKU45hOlUBseICqvuI0E9 LWMSFs1eGu7m5dR5SpXmcInnkWzlPbscl/8A0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aHlqpS7RETtmpB2uggIW2fraBTAjhAqUaCXBJAbuBE8=; b=k1nAxTzmXFIE9OuMsVVt22vGnL+IsnYYOmPPSG7KijcOWUT+JBr3GS6Ek1TkKTAWRU qDNKG/LvawxMvuxzM18ETnHjVGqeWYobVwybtAevXY0X1E4MGhvt5mkFx0WgCCBDcQay pEv1971dGb4p6VzQFTy8hc+VwT9WLJGfYoUQhhOOknLmQSlKgUQPsfyXuRAmZ4wEHDzQ Crrz/7gZwjO/ZTfRXSDBI0aA3Tn+LVHqI7xLmqHEWdsK2nyjzlACpA7VOc/UatP7NTYl 5Sg1HB67HzAma2yNCz9PTxZJr5cciX8mdbXXgPr3iRCMxtsK6zYSdK+vZMnWGsYrtjR7 SBNA== X-Gm-Message-State: APt69E21P1cWHtfqDqo6XDiV+2vxxvoacDNYmnGLZlBjIx5ovrTUPdzN xT74t6daTslt3p+13Yjem5dZ2VhOCoA= X-Google-Smtp-Source: ADUXVKIUbdAvZNC3S/p3wCccKUnrHX3nf3AFrg3KNC5RV5K+elqLB6zxM21Mg7+zGrCNbg4C+ioijg== X-Received: by 2002:a63:6d8b:: with SMTP id i133-v6mr7473053pgc.215.1530155033026; Wed, 27 Jun 2018 20:03:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:22 -0700 Message-Id: <20180628030330.15615-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::236 Subject: [Qemu-devel] [PATCH v3 15/23] target/openrisc: Fix tlb flushing in mtspr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The previous code was confused, avoiding the flush of the old entry if the new entry is invalid. We need to flush the old page if the old entry is valid and the new page if the new entry is valid. This bug was masked by over-flushing elsewhere. Signed-off-by: Richard Henderson --- target/openrisc/sys_helper.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 7f458b0d17..c9702cd26c 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -32,6 +32,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong sp= r, target_ulong rb) #ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); CPUState *cs =3D CPU(cpu); + target_ulong mr; int idx; =20 switch (spr) { @@ -85,12 +86,15 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong = spr, target_ulong rb) =20 case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ idx =3D spr - TO_SPR(1, 512); - if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.dtlb[idx].mr & TARGET_PAGE_MASK); + mr =3D env->tlb.dtlb[idx].mr; + if (mr & 1) { + tlb_flush_page(cs, mr & TARGET_PAGE_MASK); + } + if (rb & 1) { + tlb_flush_page(cs, rb & TARGET_PAGE_MASK); } env->tlb.dtlb[idx].mr =3D rb; break; - case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 = */ idx =3D spr - TO_SPR(1, 640); env->tlb.dtlb[idx].tr =3D rb; @@ -102,14 +106,18 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulon= g spr, target_ulong rb) case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ break; + case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-12= 7 */ idx =3D spr - TO_SPR(2, 512); - if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.itlb[idx].mr & TARGET_PAGE_MASK); + mr =3D env->tlb.itlb[idx].mr; + if (mr & 1) { + tlb_flush_page(cs, mr & TARGET_PAGE_MASK); + } + if (rb & 1) { + tlb_flush_page(cs, rb & TARGET_PAGE_MASK); } env->tlb.itlb[idx].mr =3D rb; break; - case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 = */ idx =3D spr - TO_SPR(2, 640); env->tlb.itlb[idx].tr =3D rb; @@ -121,6 +129,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong = spr, target_ulong rb) case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ break; + case TO_SPR(5, 1): /* MACLO */ env->mac =3D deposit64(env->mac, 0, 32, rb); break; --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530155846339401.67817338425243; Wed, 27 Jun 2018 20:17:26 -0700 (PDT) Received: from localhost ([::1]:34311 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNQx-0007gF-Cn for importer@patchew.org; Wed, 27 Jun 2018 23:17:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40023) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNDy-000576-FV for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNDw-00084X-MV for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:58 -0400 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:45774) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNDw-00083O-E0 for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:56 -0400 Received: by mail-pl0-x244.google.com with SMTP id bi1-v6so2004306plb.12 for ; Wed, 27 Jun 2018 20:03:56 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gqpkBrnMXmCHUNA04bgHmVGCH8EZrj3KsqVze2SkZ1g=; b=UTkgQwfJ+MjjxZ7AYSxpmb9xWGArMuqM5TYJDgHz2BB4uq3OY20h44dOMYweQQ8xA9 1oReLVMG/96naohA4sWHGp8wiA8ofHE6fcMxe3kNCXeNR4ApD/tPPoPwd6jRUiYbCf6d TfDGFMJt93emRLtIh0kgSBpSbqDencyDsd5Co= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gqpkBrnMXmCHUNA04bgHmVGCH8EZrj3KsqVze2SkZ1g=; b=UH1r+kDD6Jy8zHeD3ICazk6veIN4YG3dF5aVktE9/t1ApCnLzBEleNIwU7oGkHB+uR zDzSMSEO1Nm5tcwJOtKAG85hsCnITqZf7ydR6WIqs6zjHDVO2R0FjeXy22vm+Jq5EBCH jBcZzekBX/ZKLbPwW3OXkeQ3jcIAtxaw5Hg44AMQg7fA9uDiDtxlH5HQx1LY9FRcF6ow yhcOZiVzDibyMdVhDiUz1o/swYrNjOwTO2GTbOQ70lPTHoKVscVw6TnnwGJ3yCFJx49w zFrjGLrg46UWjHpqOZjEXNtz8VdpvN8KUO5aFw5FiVPGFh5xIlCIPhCnYAmsjPHE+wf+ wGyg== X-Gm-Message-State: APt69E2th7yV4wp+pWgpvnQEdfTfy4b4izeJ5FtLYwbZAc/WRvWbhBYu rQHBXw2dB7NbO9blpZF98FkhiNfvlLo= X-Google-Smtp-Source: ADUXVKKBPLWUuPnupH1HNti5kW+s1FzgiZTuh+7dPQUQNeKjyCI2E+8X78EnCz9P/0LyqKxtDh4uhA== X-Received: by 2002:a17:902:7891:: with SMTP id q17-v6mr8781468pll.186.1530155035094; Wed, 27 Jun 2018 20:03:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:23 -0700 Message-Id: <20180628030330.15615-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v3 16/23] target/openrisc: Fix cpu_mmu_index X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The code in cpu_mmu_index does not properly honor SR_DME. This bug has workarounds elsewhere in that we flush the tlb more often than necessary, on the state changes that should be reflected in a change of mmu_index. Fixing this means that we can respect the mmu_index that is given to tlb_flush. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 23 +++++++++++++-------- target/openrisc/interrupt.c | 4 ---- target/openrisc/interrupt_helper.c | 15 +++----------- target/openrisc/mmu.c | 33 +++++++++++++++++++++++++++--- target/openrisc/sys_helper.c | 4 ---- target/openrisc/translate.c | 2 +- 6 files changed, 49 insertions(+), 32 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index eaf6cdd40e..c3a968ec4d 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -385,9 +385,12 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu); =20 #include "exec/cpu-all.h" =20 -#define TB_FLAGS_DFLAG 1 -#define TB_FLAGS_R0_0 2 +#define TB_FLAGS_SM SR_SM +#define TB_FLAGS_DME SR_DME +#define TB_FLAGS_IME SR_IME #define TB_FLAGS_OVE SR_OVE +#define TB_FLAGS_DFLAG 2 /* reuse SR_TEE */ +#define TB_FLAGS_R0_0 4 /* reuse SR_IEE */ =20 static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i) { @@ -405,17 +408,21 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCSt= ate *env, { *pc =3D env->pc; *cs_base =3D 0; - *flags =3D (env->dflag - | (cpu_get_gpr(env, 0) =3D=3D 0 ? TB_FLAGS_R0_0 : 0) - | (env->sr & SR_OVE)); + *flags =3D (env->dflag ? TB_FLAGS_DFLAG : 0) + | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) + | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); } =20 static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) { - if (!(env->sr & SR_IME)) { - return MMU_NOMMU_IDX; + int ret =3D MMU_NOMMU_IDX; /* mmu is disabled */ + + if (env->sr & (ifetch ? SR_IME : SR_DME)) { + /* The mmu is enabled; test supervisor state. */ + ret =3D env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; } - return (env->sr & SR_SM) =3D=3D 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX; + + return ret; } =20 static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 23abcf29ed..138ad17f00 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -51,10 +51,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->eear =3D env->pc; } =20 - /* For machine-state changed between user-mode and supervisor mode, - we need flush TLB when we enter&exit EXCP. */ - tlb_flush(cs); - env->esr =3D cpu_get_sr(env); env->sr &=3D ~SR_DME; env->sr &=3D ~SR_IME; diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt= _helper.c index a2e9003969..9c5489f5f7 100644 --- a/target/openrisc/interrupt_helper.c +++ b/target/openrisc/interrupt_helper.c @@ -25,16 +25,7 @@ =20 void HELPER(rfe)(CPUOpenRISCState *env) { - OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); -#ifndef CONFIG_USER_ONLY - int need_flush_tlb =3D (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^ - (cpu->env.esr & (SR_SM | SR_IME | SR_DME)); - if (need_flush_tlb) { - CPUState *cs =3D CPU(cpu); - tlb_flush(cs); - } -#endif - cpu->env.pc =3D cpu->env.epcr; - cpu->env.lock_addr =3D -1; - cpu_set_sr(&cpu->env, cpu->env.esr); + env->pc =3D env->epcr; + env->lock_addr =3D -1; + cpu_set_sr(env, env->esr); } diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 856969a7f2..b293b64e98 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -246,9 +246,36 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, = vaddr addr) void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - int ret =3D openrisc_cpu_handle_mmu_fault(cs, addr, size, - access_type, mmu_idx); - if (ret) { + OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); + int ret, prot =3D 0; + hwaddr physical =3D 0; + + if (mmu_idx =3D=3D MMU_NOMMU_IDX) { + ret =3D get_phys_nommu(&physical, &prot, addr); + } else { + bool super =3D mmu_idx =3D=3D MMU_SUPERVISOR_IDX; + if (access_type =3D=3D MMU_INST_FETCH) { + ret =3D get_phys_code(cpu, &physical, &prot, addr, 2, super); + } else { + ret =3D get_phys_data(cpu, &physical, &prot, addr, + access_type =3D=3D MMU_DATA_STORE, super); + } + } + + if (ret =3D=3D TLBRET_MATCH) { + tlb_set_page(cs, addr & TARGET_PAGE_MASK, + physical & TARGET_PAGE_MASK, prot, + mmu_idx, TARGET_PAGE_SIZE); + } else if (ret < 0) { + int rw; + if (access_type =3D=3D MMU_INST_FETCH) { + rw =3D 2; + } else if (access_type =3D=3D MMU_DATA_STORE) { + rw =3D 1; + } else { + rw =3D 0; + } + cpu_openrisc_raise_mmu_exception(cpu, addr, rw, ret); /* Raise Exception. */ cpu_loop_exit_restore(cs, retaddr); } diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index c9702cd26c..852b219f9b 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -56,10 +56,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong s= pr, target_ulong rb) break; =20 case TO_SPR(0, 17): /* SR */ - if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^ - (rb & (SR_IME | SR_DME | SR_SM))) { - tlb_flush(cs); - } cpu_set_sr(env, rb); break; =20 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 64b5e84630..a271cd3903 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -55,7 +55,7 @@ static inline bool is_user(DisasContext *dc) #ifdef CONFIG_USER_ONLY return true; #else - return dc->mem_idx =3D=3D MMU_USER_IDX; + return !(dc->tb_flags & TB_FLAGS_SM); #endif } =20 --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530155839027200.75808266719184; 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CyPQR5fklj7cg5aYYFaDsmzBUBN/OsOcYQncKmQCROg=; b=SU4cEyZwZ2xYfKe7woV9I1Rn6lGtCtqQYzspzTD+XNQqONDrVLeOdn38ZSL7IXnnmr kkke2iljN29xU1+lA0PnjQh/sTy4JX2fsXd9cJJk+Pz0F4GaVxXWWjsfRb5+OGr6pQ8f 8iPvOpRY2LbVt54/B81ax+Ys59VPiiz0uLni0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CyPQR5fklj7cg5aYYFaDsmzBUBN/OsOcYQncKmQCROg=; b=YnhU+YIFs0K67JPniDSGUsWQpsgx0nZO5cOMIBEAR17vv64D3WQy4/3XuMgzwaUVO/ VQXfbbdHubnSyG5t+AnQiRxW+tV8j0KIJ86dpTw1qzKnGgAxJcfPJko38b33B5/NE1yq zMsoi4XyBpu74hK0RyuIApqvGBl1uONIm5kEbjm4WFSI2AiyHaFZpkNaxtBJ68kmL/I1 zMgyBz4VbhJBMWZje7YUvS4S3QvnayCUWolMDJrytyhUtFJ6gmYcrFrD+AWq1QwNWWfG ZvwdpvohePN6/IDH0f+T/icGexl/fMJOyzqI+6YdEsEndyuXLUV09FoMAPdYMA8PyVPL imgQ== X-Gm-Message-State: APt69E1/NtUPkO0Pm8VLv74vkKyjB0ps7Ygz/qs5GoHLdwmEXaDD3t4r ur3he4jOwQkHJD6ZKP+qJGby5tochUM= X-Google-Smtp-Source: ADUXVKLyAoBRvUo0yTXcySoJye64kpOSThqhjXmkpZQjLyI5To3e7T3uHqVacq5R0j+aTsiTHsaTrg== X-Received: by 2002:a17:902:760d:: with SMTP id k13-v6mr8559810pll.56.1530155036353; Wed, 27 Jun 2018 20:03:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:24 -0700 Message-Id: <20180628030330.15615-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::234 Subject: [Qemu-devel] [PATCH v3 17/23] target/openrisc: Use identical sizes for ITLB and DTLB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 The sizes are already the same, however, we can improve things if they are identical by design. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 10 ++++------ target/openrisc/machine.c | 4 ++-- target/openrisc/mmu.c | 4 ++-- target/openrisc/sys_helper.c | 16 ++++++++-------- 4 files changed, 16 insertions(+), 18 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index c3a968ec4d..47e94659e1 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -222,10 +222,8 @@ enum { =20 /* TLB size */ enum { - DTLB_SIZE =3D 64, - DTLB_MASK =3D (DTLB_SIZE-1), - ITLB_SIZE =3D 64, - ITLB_MASK =3D (ITLB_SIZE-1), + TLB_SIZE =3D 64, + TLB_MASK =3D TLB_SIZE - 1, }; =20 /* TLB prot */ @@ -254,8 +252,8 @@ typedef struct OpenRISCTLBEntry { =20 #ifndef CONFIG_USER_ONLY typedef struct CPUOpenRISCTLBContext { - OpenRISCTLBEntry itlb[ITLB_SIZE]; - OpenRISCTLBEntry dtlb[DTLB_SIZE]; + OpenRISCTLBEntry itlb[TLB_SIZE]; + OpenRISCTLBEntry dtlb[TLB_SIZE]; =20 int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu, hwaddr *physical, diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index b795b56dc6..3fc837b925 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -42,9 +42,9 @@ static const VMStateDescription vmstate_cpu_tlb =3D { .minimum_version_id =3D 1, .minimum_version_id_old =3D 1, .fields =3D (VMStateField[]) { - VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, ITLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), - VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, DTLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, TLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), VMSTATE_END_OF_LIST() } diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index b293b64e98..a4613e9ae4 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -41,7 +41,7 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physic= al, int *prot, target_ulong address, int rw, bool supervisor) { int vpn =3D address >> TARGET_PAGE_BITS; - int idx =3D vpn & ITLB_MASK; + int idx =3D vpn & TLB_MASK; int right =3D 0; uint32_t mr =3D cpu->env.tlb.itlb[idx].mr; uint32_t tr =3D cpu->env.tlb.itlb[idx].tr; @@ -74,7 +74,7 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physic= al, int *prot, target_ulong address, int rw, bool supervisor) { int vpn =3D address >> TARGET_PAGE_BITS; - int idx =3D vpn & DTLB_MASK; + int idx =3D vpn & TLB_MASK; int right =3D 0; uint32_t mr =3D cpu->env.tlb.dtlb[idx].mr; uint32_t tr =3D cpu->env.tlb.dtlb[idx].tr; diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 852b219f9b..541615bfb3 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -80,7 +80,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong sp= r, target_ulong rb) env->shadow_gpr[idx / 32][idx % 32] =3D rb; break; =20 - case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ + case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-1= 27 */ idx =3D spr - TO_SPR(1, 512); mr =3D env->tlb.dtlb[idx].mr; if (mr & 1) { @@ -91,7 +91,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong sp= r, target_ulong rb) } env->tlb.dtlb[idx].mr =3D rb; break; - case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 = */ + case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-1= 27 */ idx =3D spr - TO_SPR(1, 640); env->tlb.dtlb[idx].tr =3D rb; break; @@ -103,7 +103,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong = spr, target_ulong rb) case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ break; =20 - case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-12= 7 */ + case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-1= 27 */ idx =3D spr - TO_SPR(2, 512); mr =3D env->tlb.itlb[idx].mr; if (mr & 1) { @@ -114,7 +114,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong = spr, target_ulong rb) } env->tlb.itlb[idx].mr =3D rb; break; - case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 = */ + case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-1= 27 */ idx =3D spr - TO_SPR(2, 640); env->tlb.itlb[idx].tr =3D rb; break; @@ -247,11 +247,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, tar= get_ulong rd, idx =3D (spr - 1024); return env->shadow_gpr[idx / 32][idx % 32]; =20 - case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ + case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-1= 27 */ idx =3D spr - TO_SPR(1, 512); return env->tlb.dtlb[idx].mr; =20 - case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 = */ + case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-1= 27 */ idx =3D spr - TO_SPR(1, 640); return env->tlb.dtlb[idx].tr; =20 @@ -263,11 +263,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, tar= get_ulong rd, case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ break; =20 - case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 = */ + case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-1= 27 */ idx =3D spr - TO_SPR(2, 512); return env->tlb.itlb[idx].mr; =20 - case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 = */ + case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-1= 27 */ idx =3D spr - TO_SPR(2, 640); return env->tlb.itlb[idx].tr; =20 --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530156009060549.6515860895533; Wed, 27 Jun 2018 20:20:09 -0700 (PDT) Received: from localhost ([::1]:34326 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNTc-0001TG-Av for importer@patchew.org; Wed, 27 Jun 2018 23:20:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40046) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNDz-00058O-Sk for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:04:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNDz-00089S-1n for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:59 -0400 Received: from mail-pl0-x230.google.com ([2607:f8b0:400e:c01::230]:34755) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNDy-000886-R6 for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:58 -0400 Received: by mail-pl0-x230.google.com with SMTP id z9-v6so2018569plo.1 for ; Wed, 27 Jun 2018 20:03:58 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xQ7MuAb0CMxAlY812ETLA9j5/iyPIirofg3K3ekSZ3o=; b=RUPwBz+WpLzm7fsA7unl8mobGoY0aFx2L0aaVdvwxXZ+Zt+Icl2ZVjz62Sgc+3/Try r75qsVCryMgQfndotVMqflAYsd3I1xnAgmD9xC3m6Iu8X6wuTb5ay9ZceTkZbpmWDxyx K0x0CT87m8eWWd1+8KPMFvRWAUBkuwC7BkNHc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xQ7MuAb0CMxAlY812ETLA9j5/iyPIirofg3K3ekSZ3o=; b=TtkRP1TukzLqkeYrudD6g5P1Oc3qHg7r8B9MXbKYtjvSekI28Rlb0k6DxSREHodUer iYeXNQBBe3U3k+kOdN6qxJiuirAO+grg+lxqpIdOxGFNQ7AvbfIfxcqwd0hD/qcMfg/J vHIq7/sNuPxCkfdxj8InO/sH7LXaVv0iAvY9w3P+iQr/XeIUJQTfVtOxN74mYynPPxgE g6FHGNvi6muMVsZWyUEbWES+go7j2b/u3xxBkrTqeff1pZxPBO+9YwMktRJpBWCdcDNe xtvjV5uxMRNyZ9IZaAi/LnGhYicQKMkTv5EYJ+3LxDnAzfm1W5irfb6qvpPIXLnEjp5c mqTQ== X-Gm-Message-State: APt69E34AzaRapFHZHZzMlXExCc3UVCLDdyIP0mfMYclWAzMO59cXy6z 1rgIB3OWQVZuKM7IeFRJLfrfa4VXzL0= X-Google-Smtp-Source: ADUXVKJsEB8qHnnvbociWeTrx9h00fiOhEDyHPa61/dcsUWoUTyoZATfgQNa6pdevmv0FkSRpIekmg== X-Received: by 2002:a17:902:ba87:: with SMTP id k7-v6mr8605435pls.271.1530155037652; Wed, 27 Jun 2018 20:03:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:25 -0700 Message-Id: <20180628030330.15615-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::230 Subject: [Qemu-devel] [PATCH v3 18/23] target/openrisc: Stub out handle_mmu_fault for softmmu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This hook is only used by CONFIG_USER_ONLY. Signed-off-by: Richard Henderson --- target/openrisc/mmu.c | 35 +++++------------------------------ 1 file changed, 5 insertions(+), 30 deletions(-) diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index a4613e9ae4..f4c0a3e217 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -177,42 +177,17 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISC= CPU *cpu, cpu->env.lock_addr =3D -1; } =20 -#ifndef CONFIG_USER_ONLY int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, int mmu_idx) { +#ifdef CONFIG_USER_ONLY OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - int ret =3D 0; - hwaddr physical =3D 0; - int prot =3D 0; - - ret =3D get_phys_addr(cpu, &physical, &prot, address, rw); - - if (ret =3D=3D TLBRET_MATCH) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); - ret =3D 0; - } else if (ret < 0) { - cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret); - ret =3D 1; - } - - return ret; -} + cpu_openrisc_raise_mmu_exception(cpu, address, rw, 0); + return 1; #else -int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - int ret =3D 0; - - cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret); - ret =3D 1; - - return ret; -} + g_assert_not_reached(); #endif +} =20 #ifndef CONFIG_USER_ONLY hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530155839027463.48900849050654; Wed, 27 Jun 2018 20:17:19 -0700 (PDT) Received: from localhost ([::1]:34309 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNQi-0007UN-CA for importer@patchew.org; Wed, 27 Jun 2018 23:17:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40063) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNE1-0005AK-Ky for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:04:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNE0-0008C6-G1 for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:04:01 -0400 Received: from mail-pf0-x22d.google.com ([2607:f8b0:400e:c00::22d]:37281) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNE0-0008Bg-9m for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:04:00 -0400 Received: by mail-pf0-x22d.google.com with SMTP id y5-v6so1890495pfn.4 for ; Wed, 27 Jun 2018 20:04:00 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YC2RVVbcg0kjLTtKougHEu94D19YVoQfzJ/owdisDE8=; b=ZAlE4GCex89QjiWPDukXKxhVIR0/2x8PzP6Nu4ejz7kMDrIJ1jGoJeCIBNKab1ISbO yzmIc26Oa5CW4haqVw4jfozxAu0SX9alFs7HKX4tqyDP7j6HLZOmVh6fggqznAM80dJb D434ZNpjnOq9JEBTWvp6BHX8QaNgfbIK1uFxA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YC2RVVbcg0kjLTtKougHEu94D19YVoQfzJ/owdisDE8=; b=B7va7s+S1kHZqlAugFD21rbxP6KpS/CcWJ6MnvIgX3hr7FDMtlJUuQZMj6U7s7j819 IpytEhbQXKZk/01Qf2WGU4Ta3RK3zmfFXCsyP2scYHal4CO0YA1ZtVcUqSu3znBH7m5f 2Q8SGeOmw7rcIdgepznjB5eym3IThRKp0tTJTm7guxNfKqSWIDNG5KdmH6tVIjv1trGL spPUwG8W1rY3lxWr7pAlWlVxlcB8BIzapxDkr4CWmx3le5vzDQQqfTHVUIJ4MRhOpjBR xp60GAuj2Ymf9DAgz5XUhOa8F3Hz87cYmNhVa2zxvEO0wOnkU5QHDeyghqqq6y37SM3J wwAg== X-Gm-Message-State: APt69E0hopxM+1o8WxZ0sRA0OE4YK4LH5OlBQp8uEt5MJh8SDt70hK1k wTJxWcpmvicWj34GLw+uSFgWPPabGKw= X-Google-Smtp-Source: AAOMgpcdyLf735IDjFeaLQDJE+NRRNLXnx4JCP0qwpuBbtV8AG90B60FHrwuXFgiLt/LPrYkQIVzuQ== X-Received: by 2002:a63:5fc1:: with SMTP id t184-v6mr7046053pgb.183.1530155038947; Wed, 27 Jun 2018 20:03:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:26 -0700 Message-Id: <20180628030330.15615-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22d Subject: [Qemu-devel] [PATCH v3 19/23] target/openrisc: Increase the TLB size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The architecture supports 128 TLB entries. There is no reason not to provide all of them. In the process we need to fix a bug that failed to parameterize the configuration register that tells the operating system the number of entries. Signed-off-by: Richard Henderson --- v2: - Change VMState version. --- target/openrisc/cpu.h | 2 +- target/openrisc/cpu.c | 6 ++++-- target/openrisc/machine.c | 5 ++--- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 47e94659e1..b180e30e9e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -222,7 +222,7 @@ enum { =20 /* TLB size */ enum { - TLB_SIZE =3D 64, + TLB_SIZE =3D 128, TLB_MASK =3D TLB_SIZE - 1, }; =20 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b92de51ecf..e01ce9ed1c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -57,8 +57,10 @@ static void openrisc_cpu_reset(CPUState *s) =20 cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; - cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 <= < 2)); - cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 <= < 2)); + cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) + | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); + cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) + | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); =20 #ifndef CONFIG_USER_ONLY cpu->env.picmr =3D 0x00000000; diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 3fc837b925..1eedbf3dbe 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -38,9 +38,8 @@ static const VMStateDescription vmstate_tlb_entry =3D { =20 static const VMStateDescription vmstate_cpu_tlb =3D { .name =3D "cpu_tlb", - .version_id =3D 1, - .minimum_version_id =3D 1, - .minimum_version_id_old =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530156000407405.75042561524833; Wed, 27 Jun 2018 20:20:00 -0700 (PDT) Received: from localhost ([::1]:34325 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNTT-0001JO-K8 for importer@patchew.org; Wed, 27 Jun 2018 23:19:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40085) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNE3-0005Ee-NG for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:04:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNE2-0008Dq-1P for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:04:03 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:38932) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNE1-0008Cf-PK for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:04:01 -0400 Received: by mail-pg0-x241.google.com with SMTP id n2-v6so1797231pgq.6 for ; Wed, 27 Jun 2018 20:04:01 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gwN/7WgsND7BL7PgsVURX7sh5YIFP5WSPDM5slNfWQM=; b=Ie8oebXhpJNAB1wzv4WWz2hBDwtuty6IyGcVQUTzD0qgno7gBpnnnvErneliihnqLU z37RzlFZZ1tpks0bf5RMY7Rw9aeSOfasQXonGtxw59staMWQ9bA0ZmQ1I6gH03j7CRzw 2HYw57v+x/Vst7gpAUXlhXW22mJotnYH7t/bo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gwN/7WgsND7BL7PgsVURX7sh5YIFP5WSPDM5slNfWQM=; b=Msgxj+oo+vfbrjxnhWE7HUGLNkWsoP3AeVk8FTgp5omKqc3z5iVe1JvaU7a56wPt+d CrUSURGeIXWITTjuC+dkBooj8FRlhB9LLpLOyTP5epyynOUugHrKtWoZQ7GzGZv6oMyM XjE7KURz3ir4mAEyDHWQz4oNyJK6ndL7NS/2nLlwU+d2YqrndPHeHHLS7d6azPFF+g5e aDrQGt3+jrrybCEAbdmXYjnIJ+zxOmKfop9HgN38DLVEqwaSDQN9ymea6GXxJnVjQG+n rivRSBWqpKVypiBgjZiID2UC/Gjk8vbG/IA6lA8zFVFPm+kePiBife6dOcwsAGDVM7pT jiGg== X-Gm-Message-State: APt69E1axWIeqXsPLf8nGmhBkazhx/GfDMwZzRfNTbOtwosbHkJQkk6W Ilx3NcZs0VICoQtveWKTEru5w8JsqnU= X-Google-Smtp-Source: AAOMgpcg4h+juWPBFjy2ocopcwXyjI6ijtMtvy+zj3bCkLfEUHM1JNjF11cjw8tcTfkae7XgXulW8A== X-Received: by 2002:a62:ae08:: with SMTP id q8-v6mr7783467pff.126.1530155040357; Wed, 27 Jun 2018 20:04:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:27 -0700 Message-Id: <20180628030330.15615-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v3 20/23] target/openrisc: Reorg tlb lookup X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" While openrisc has a split i/d tlb, qemu does not. Perform a lookup on both i & d tlbs in parallel and put the composite rights into qemu's tlb. This avoids ping-ponging the qemu tlb between EXEC and READ. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 8 -- target/openrisc/mmu.c | 254 +++++++++++++++--------------------------- 2 files changed, 90 insertions(+), 172 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index b180e30e9e..f1b31bc24a 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -237,14 +237,6 @@ enum { UXE =3D (1 << 7), }; =20 -/* check if tlb available */ -enum { - TLBRET_INVALID =3D -3, - TLBRET_NOMATCH =3D -2, - TLBRET_BADADDR =3D -1, - TLBRET_MATCH =3D 0 -}; - typedef struct OpenRISCTLBEntry { uint32_t mr; uint32_t tr; diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index f4c0a3e217..d3796ae41e 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -29,148 +29,78 @@ #endif =20 #ifndef CONFIG_USER_ONLY -static inline int get_phys_nommu(hwaddr *physical, int *prot, - target_ulong address) +static inline void get_phys_nommu(hwaddr *phys_addr, int *prot, + target_ulong address) { - *physical =3D address; + *phys_addr =3D address; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return TLBRET_MATCH; } =20 -static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot, - target_ulong address, int rw, bool supervisor) +static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot, + target_ulong addr, int need, bool super) { - int vpn =3D address >> TARGET_PAGE_BITS; - int idx =3D vpn & TLB_MASK; - int right =3D 0; - uint32_t mr =3D cpu->env.tlb.itlb[idx].mr; - uint32_t tr =3D cpu->env.tlb.itlb[idx].tr; + int idx =3D (addr >> TARGET_PAGE_BITS) & TLB_MASK; + uint32_t imr =3D cpu->env.tlb.itlb[idx].mr; + uint32_t itr =3D cpu->env.tlb.itlb[idx].tr; + uint32_t dmr =3D cpu->env.tlb.dtlb[idx].mr; + uint32_t dtr =3D cpu->env.tlb.dtlb[idx].tr; + int right, match, valid; =20 - if ((mr >> TARGET_PAGE_BITS) !=3D vpn) { - return TLBRET_NOMATCH; - } - if (!(mr & 1)) { - return TLBRET_INVALID; - } - if (supervisor) { - if (tr & SXE) { - right |=3D PAGE_EXEC; - } - } else { - if (tr & UXE) { - right |=3D PAGE_EXEC; + /* If the ITLB and DTLB indexes map to the same page, we want to + load all permissions all at once. If the destination pages do + not match, zap the one we don't need. */ + if (unlikely((itr ^ dtr) & TARGET_PAGE_MASK)) { + if (need & PAGE_EXEC) { + dmr =3D dtr =3D 0; + } else { + imr =3D itr =3D 0; } } - if ((rw & 2) && ((right & PAGE_EXEC) =3D=3D 0)) { - return TLBRET_BADADDR; - } =20 - *physical =3D (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK); + /* Check if either of the entries matches the source address. */ + match =3D (imr ^ addr) & TARGET_PAGE_MASK ? 0 : PAGE_EXEC; + match |=3D (dmr ^ addr) & TARGET_PAGE_MASK ? 0 : PAGE_READ | PAGE_WRIT= E; + + /* Check if either of the entries is valid. */ + valid =3D imr & 1 ? PAGE_EXEC : 0; + valid |=3D dmr & 1 ? PAGE_READ | PAGE_WRITE : 0; + valid &=3D match; + + /* Collect the permissions from the entries. */ + right =3D itr & (super ? SXE : UXE) ? PAGE_EXEC : 0; + right |=3D dtr & (super ? SRE : URE) ? PAGE_READ : 0; + right |=3D dtr & (super ? SWE : UWE) ? PAGE_WRITE : 0; + right &=3D valid; + + /* Note that above we validated that itr and dtr match on page. + So oring them together changes nothing without having to + check which one we needed. We also want to store to these + variables even on failure, as it avoids compiler warnings. */ + *phys_addr =3D ((itr | dtr) & TARGET_PAGE_MASK) | (addr & ~TARGET_PAGE= _MASK); *prot =3D right; - return TLBRET_MATCH; -} =20 -static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot, - target_ulong address, int rw, bool supervisor) -{ - int vpn =3D address >> TARGET_PAGE_BITS; - int idx =3D vpn & TLB_MASK; - int right =3D 0; - uint32_t mr =3D cpu->env.tlb.dtlb[idx].mr; - uint32_t tr =3D cpu->env.tlb.dtlb[idx].tr; + qemu_log_mask(CPU_LOG_MMU, + "MMU lookup: need %d match %d valid %d right %d -> %s\n", + need, match, valid, right, (need & right) ? "OK" : "FAIL= "); =20 - if ((mr >> TARGET_PAGE_BITS) !=3D vpn) { - return TLBRET_NOMATCH; + /* Check the collective permissions are present. */ + if (likely(need & right)) { + return 0; /* success! */ } - if (!(mr & 1)) { - return TLBRET_INVALID; - } - if (supervisor) { - if (tr & SRE) { - right |=3D PAGE_READ; - } - if (tr & SWE) { - right |=3D PAGE_WRITE; - } + + /* Determine what kind of failure we have. */ + if (need & valid) { + return need & PAGE_EXEC ? EXCP_IPF : EXCP_DPF; } else { - if (tr & URE) { - right |=3D PAGE_READ; - } - if (tr & UWE) { - right |=3D PAGE_WRITE; - } + return need & PAGE_EXEC ? EXCP_ITLBMISS : EXCP_DTLBMISS; } - - if (!(rw & 1) && ((right & PAGE_READ) =3D=3D 0)) { - return TLBRET_BADADDR; - } - if ((rw & 1) && ((right & PAGE_WRITE) =3D=3D 0)) { - return TLBRET_BADADDR; - } - - *physical =3D (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK); - *prot =3D right; - return TLBRET_MATCH; -} - -static int get_phys_addr(OpenRISCCPU *cpu, hwaddr *physical, - int *prot, target_ulong address, int rw) -{ - bool supervisor =3D (cpu->env.sr & SR_SM) !=3D 0; - int ret; - - /* Assume nommu results for a moment. */ - ret =3D get_phys_nommu(physical, prot, address); - - /* Overwrite with TLB lookup if enabled. */ - if (rw =3D=3D MMU_INST_FETCH) { - if (cpu->env.sr & SR_IME) { - ret =3D get_phys_code(cpu, physical, prot, address, rw, superv= isor); - } - } else { - if (cpu->env.sr & SR_DME) { - ret =3D get_phys_data(cpu, physical, prot, address, rw, superv= isor); - } - } - - return ret; } #endif =20 -static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu, - target_ulong address, - int rw, int tlb_error) +static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, + int exception) { CPUState *cs =3D CPU(cpu); - int exception =3D 0; - - switch (tlb_error) { - default: - if (rw =3D=3D 2) { - exception =3D EXCP_IPF; - } else { - exception =3D EXCP_DPF; - } - break; -#ifndef CONFIG_USER_ONLY - case TLBRET_BADADDR: - if (rw =3D=3D 2) { - exception =3D EXCP_IPF; - } else { - exception =3D EXCP_DPF; - } - break; - case TLBRET_INVALID: - case TLBRET_NOMATCH: - /* No TLB match for a mapped address */ - if (rw =3D=3D 2) { - exception =3D EXCP_ITLBMISS; - } else { - exception =3D EXCP_DTLBMISS; - } - break; -#endif - } =20 cs->exception_index =3D exception; cpu->env.eear =3D address; @@ -182,7 +112,7 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr a= ddress, int size, { #ifdef CONFIG_USER_ONLY OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - cpu_openrisc_raise_mmu_exception(cpu, address, rw, 0); + raise_mmu_exception(cpu, address, EXCP_DPF); return 1; #else g_assert_not_reached(); @@ -193,27 +123,32 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr= address, int size, hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); + int prot, excp, sr =3D cpu->env.sr; hwaddr phys_addr; - int prot; - int miss; =20 - /* Check memory for any kind of address, since during debug the - gdb can ask for anything, check data tlb for address */ - miss =3D get_phys_addr(cpu, &phys_addr, &prot, addr, 0); + switch (sr & (SR_DME | SR_IME)) { + case SR_DME | SR_IME: + /* The mmu is definitely enabled. */ + excp =3D get_phys_mmu(cpu, &phys_addr, &prot, addr, + PROT_EXEC | PROT_READ | PROT_WRITE, + (sr & SR_SM) !=3D 0); + return excp ? -1 : phys_addr; =20 - /* Check instruction tlb */ - if (miss) { - miss =3D get_phys_addr(cpu, &phys_addr, &prot, addr, MMU_INST_FETC= H); - } + default: + /* The mmu is partially enabled, and we don't really have + a "real" access type. Begin by trying the mmu, but if + that fails try again without. */ + excp =3D get_phys_mmu(cpu, &phys_addr, &prot, addr, + PROT_EXEC | PROT_READ | PROT_WRITE, + (sr & SR_SM) !=3D 0); + if (!excp) { + return phys_addr; + } + /* fallthru */ =20 - /* Last, fall back to a plain address */ - if (miss) { - miss =3D get_phys_nommu(&phys_addr, &prot, addr); - } - - if (miss) { - return -1; - } else { + case 0: + /* The mmu is definitely disabled; lookups never fail. */ + get_phys_nommu(&phys_addr, &prot, addr); return phys_addr; } } @@ -222,37 +157,28 @@ void tlb_fill(CPUState *cs, target_ulong addr, int si= ze, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - int ret, prot =3D 0; - hwaddr physical =3D 0; + int prot, excp; + hwaddr phys_addr; =20 if (mmu_idx =3D=3D MMU_NOMMU_IDX) { - ret =3D get_phys_nommu(&physical, &prot, addr); + /* The mmu is disabled; lookups never fail. */ + get_phys_nommu(&phys_addr, &prot, addr); + excp =3D 0; } else { bool super =3D mmu_idx =3D=3D MMU_SUPERVISOR_IDX; - if (access_type =3D=3D MMU_INST_FETCH) { - ret =3D get_phys_code(cpu, &physical, &prot, addr, 2, super); - } else { - ret =3D get_phys_data(cpu, &physical, &prot, addr, - access_type =3D=3D MMU_DATA_STORE, super); - } + int need =3D (access_type =3D=3D MMU_INST_FETCH ? PROT_EXEC + : access_type =3D=3D MMU_DATA_STORE ? PROT_WRITE + : PROT_READ); + excp =3D get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super); } =20 - if (ret =3D=3D TLBRET_MATCH) { - tlb_set_page(cs, addr & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); - } else if (ret < 0) { - int rw; - if (access_type =3D=3D MMU_INST_FETCH) { - rw =3D 2; - } else if (access_type =3D=3D MMU_DATA_STORE) { - rw =3D 1; - } else { - rw =3D 0; - } - cpu_openrisc_raise_mmu_exception(cpu, addr, rw, ret); - /* Raise Exception. */ + if (unlikely(excp)) { + raise_mmu_exception(cpu, addr, excp); cpu_loop_exit_restore(cs, retaddr); } + + tlb_set_page(cs, addr & TARGET_PAGE_MASK, + phys_addr & TARGET_PAGE_MASK, prot, + mmu_idx, TARGET_PAGE_SIZE); } #endif --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530155891738450.8173165932119; Wed, 27 Jun 2018 20:18:11 -0700 (PDT) Received: from localhost ([::1]:34312 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNRi-0008J3-VH for importer@patchew.org; Wed, 27 Jun 2018 23:18:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40087) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNE4-0005FA-4K for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:04:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNE3-0008Ej-5h for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:04:04 -0400 Received: from mail-pg0-x230.google.com ([2607:f8b0:400e:c05::230]:37754) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNE3-0008EZ-0i for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:04:03 -0400 Received: by mail-pg0-x230.google.com with SMTP id o11-v6so1798012pgv.4 for ; Wed, 27 Jun 2018 20:04:02 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.04.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:04:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yIn6TyEZ6/crkb0RZ7okyByW0TTgtJ88YNc4nTVzFQw=; b=C6dQG8g9WjT/1BzuKArrJC9XHzbe1kb7SBJap+2mOwxtzwu9Lf0hoU+qjOA3eIWfzA mpC2j0EoRHm2Z58zsfhQUAYCXDC9alzptLCr75DzdRxpGtjK0gOKN5AAQQ3xjwtX/oWi t1W9PKqDD0BteTZ9sfh7arNUU2wxRl8S/1Nas= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yIn6TyEZ6/crkb0RZ7okyByW0TTgtJ88YNc4nTVzFQw=; b=pQCpuZzTTkIGs7UEZ35RrE7zQgcTaMxkcxsCSIpuZ0xq9UIFNeqSvi4eTy6H1Dl0x5 mgw/ldHdyc7vqVp1Q0P0dEsSJqy7xtkw9OfICmzXQ8R6BfZIK9beamj3mH16wC486HSQ klZDpRojJA1ttnQrV9zbS6m5qCwMFMIeiVHvX7oMiIzROaBBkq26CUFqq0zzkPry2UnV PePPgN5OQQj8BWSZOwEBFiTzR8lpHxWnyWLKYujuYH5llc+oK7MlO89kGAcAJ+JCIZas B4wTEapPQ62zeY6WiNAZAWTgUiS0B+lVZcE765HnXR4+bmJNHYE40ba/enx9UnGHV/yx LveQ== X-Gm-Message-State: APt69E1tPXqZkHP+2pXCjo+G9EVUQ+xCfii7hVEhHsx+euhzbVwHfqBQ SIRgNNsBAwyIJTJcUcEFX8pIWgg3qOo= X-Google-Smtp-Source: ADUXVKLVhgmrWo5s9xCoYjHkzAZvHu16P8Mec8WyE2oNTfSvXxWgKDwj72Q59W1U+VSIP4ZTxYUt3A== X-Received: by 2002:a63:3c4a:: with SMTP id i10-v6mr7228482pgn.415.1530155041762; Wed, 27 Jun 2018 20:04:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:28 -0700 Message-Id: <20180628030330.15615-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::230 Subject: [Qemu-devel] [PATCH v3 21/23] target/openrisc: Add support in scripts/qemu-binfmt-conf.sh X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- scripts/qemu-binfmt-conf.sh | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh index d7eefda0b8..a5cb96d79a 100755 --- a/scripts/qemu-binfmt-conf.sh +++ b/scripts/qemu-binfmt-conf.sh @@ -1,10 +1,10 @@ #!/bin/sh -# enable automatic i386/ARM/M68K/MIPS/SPARC/PPC/s390/HPPA/Xtensa/microblaze -# program execution by the kernel +# Enable automatic program execution by the kernel. =20 qemu_target_list=3D"i386 i486 alpha arm armeb sparc32plus ppc ppc64 ppc64l= e m68k \ mips mipsel mipsn32 mipsn32el mips64 mips64el \ -sh4 sh4eb s390x aarch64 aarch64_be hppa riscv32 riscv64 xtensa xtensaeb mi= croblaze microblazeel" +sh4 sh4eb s390x aarch64 aarch64_be hppa riscv32 riscv64 xtensa xtensaeb \ +microblaze microblazeel or1k" =20 i386_magic=3D'\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\= x00\x03\x00' i386_mask=3D'\xff\xff\xff\xff\xff\xfe\xfe\x00\xff\xff\xff\xff\xff\xff\xff\= xff\xfe\xff\xff\xff' @@ -124,6 +124,10 @@ microblazeel_magic=3D'\x7fELF\x01\x01\x01\x00\x00\x00\= x00\x00\x00\x00\x00\x00\x02\ microblazeel_mask=3D'\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\= xff\xff\xff\xfe\xff\xff\xff' microblazeel_family=3Dmicroblazeel =20 +or1k_magic=3D'\x7fELF\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\= x02\x00\x5c' +or1k_mask=3D'\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\= xff\xff\xfe\xff\xff' +or1k_family=3Dor1k + qemu_get_family() { cpu=3D${HOST_ARCH:-$(uname -m)} case "$cpu" in --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530156112248694.7300213320451; Wed, 27 Jun 2018 20:21:52 -0700 (PDT) Received: from localhost ([::1]:34342 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNVH-0002wd-If for importer@patchew.org; Wed, 27 Jun 2018 23:21:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40116) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNE8-0005Iz-4x for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:04:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNE4-0008Gx-IH for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:04:08 -0400 Received: from mail-pg0-x234.google.com ([2607:f8b0:400e:c05::234]:39544) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNE4-0008GB-AJ for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:04:04 -0400 Received: by mail-pg0-x234.google.com with SMTP id n2-v6so1797288pgq.6 for ; Wed, 27 Jun 2018 20:04:04 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.04.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:04:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IqPETO/Jq5PSNTaUXXZrAP2OsLqa2P3bXXogxLvwuEY=; b=Auo+zJTjCuNrZIFd9s+cfBBDz2Qsar3ChraX5+n2vKLnKkXZiUBVhrxSocz1YUOFoO gxIFQnD7MjAIPZWPVbG86jwF3nxVq3dCOOhVBnLU2x64CX2J2sX8oFmyy57n6Z/Wok1t mbAmx+xSL3Odt52SkLjLvji7QCb/LoEGsMgWY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IqPETO/Jq5PSNTaUXXZrAP2OsLqa2P3bXXogxLvwuEY=; b=ZPSSRwVnMEXg3aSSM6vtHwOMQ7XQwmfxjUUQ0plf3p1yOxsnT9ZtMBP6NMYO/7GBKI 7jfkotJV0BxO7p+T8O4IUZl40yLHscwplzaIxbI6sm4m8OT1YdS4WkddShAHLJJxn3Xs VHHzilOOxxaTzstCWLVefloN7SMB6l4x7lSeobsvj2HYetuAszDYC7RjUhyrDa/ernFb /M3eAD5vU/XQBGjZkvbmyn9+KytYL34GZIoCkI+gIjZM8pGPwEt+OCQyilYbEJ/C8Qtd x4QNF1q3ThhmX1/UxzpLpMMW4Bhpmo19C5GfQpRxF0UdD6gcPbn5QjtsMiE9XkvlP6Z7 0MVQ== X-Gm-Message-State: APt69E1YJQNey2dnTDoW1P0cr2YVUDf2uaIhkXK++rBcSIL1/Cn7z6vZ /F0hTT7kXYkvxBLcDSLLvFJq7hWjP28= X-Google-Smtp-Source: ADUXVKLEEFyTeEJUucCHzu9rKPCJ/vGDI3MhoE7rPKiEvqzbr7YH+u+K/chQjOeMKlIrYBBAWMolag== X-Received: by 2002:a65:444f:: with SMTP id e15-v6mr7438778pgq.348.1530155043024; Wed, 27 Jun 2018 20:04:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:29 -0700 Message-Id: <20180628030330.15615-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::234 Subject: [Qemu-devel] [PATCH v3 22/23] linux-user: Implement signals for openrisc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" All of the existing code was boilerplate from elsewhere, and would crash the guest upon the first signal. Signed-off-by: Richard Henderson --- v2: Add a comment to the new definition of target_pt_regs. Install the signal mask into the ucontext. v3: Incorporate feedback from Laurent. --- linux-user/openrisc/target_syscall.h | 28 +--- linux-user/openrisc/signal.c | 213 +++++++++++---------------- linux-user/signal.c | 2 +- target/openrisc/cpu.c | 1 + 4 files changed, 92 insertions(+), 152 deletions(-) diff --git a/linux-user/openrisc/target_syscall.h b/linux-user/openrisc/tar= get_syscall.h index 03104f80af..d586d2a018 100644 --- a/linux-user/openrisc/target_syscall.h +++ b/linux-user/openrisc/target_syscall.h @@ -1,27 +1,15 @@ #ifndef OPENRISC_TARGET_SYSCALL_H #define OPENRISC_TARGET_SYSCALL_H =20 +/* Note that in linux/arch/openrisc/include/uapi/asm/ptrace.h, + * this is called user_regs_struct. Given that this is what + * is used within struct sigcontext we need this definition. + * However, elfload.c wants this name. + */ struct target_pt_regs { - union { - struct { - /* Named registers */ - uint32_t sr; /* Stored in place of r0 */ - target_ulong sp; /* r1 */ - }; - struct { - /* Old style */ - target_ulong offset[2]; - target_ulong gprs[30]; - }; - struct { - /* New style */ - target_ulong gpr[32]; - }; - }; - target_ulong pc; - target_ulong orig_gpr11; /* For restarting system calls */ - uint32_t syscallno; /* Syscall number (used by strace) */ - target_ulong dummy; /* Cheap alignment fix */ + abi_ulong gpr[32]; + abi_ulong pc; + abi_ulong sr; }; =20 #define UNAME_MACHINE "openrisc" diff --git a/linux-user/openrisc/signal.c b/linux-user/openrisc/signal.c index 8be0b74001..232ad82b98 100644 --- a/linux-user/openrisc/signal.c +++ b/linux-user/openrisc/signal.c @@ -21,124 +21,69 @@ #include "signal-common.h" #include "linux-user/trace.h" =20 -struct target_sigcontext { +typedef struct target_sigcontext { struct target_pt_regs regs; abi_ulong oldmask; - abi_ulong usp; -}; +} target_sigcontext; =20 -struct target_ucontext { +typedef struct target_ucontext { abi_ulong tuc_flags; abi_ulong tuc_link; target_stack_t tuc_stack; - struct target_sigcontext tuc_mcontext; + target_sigcontext tuc_mcontext; target_sigset_t tuc_sigmask; /* mask last for extensibility */ -}; +} target_ucontext; =20 -struct target_rt_sigframe { - abi_ulong pinfo; - uint64_t puc; +typedef struct target_rt_sigframe { struct target_siginfo info; - struct target_sigcontext sc; - struct target_ucontext uc; - unsigned char retcode[16]; /* trampoline code */ -}; + target_ucontext uc; + uint32_t retcode[4]; /* trampoline code */ +} target_rt_sigframe; =20 -/* This is the asm-generic/ucontext.h version */ -#if 0 -static int restore_sigcontext(CPUOpenRISCState *regs, - struct target_sigcontext *sc) +static void restore_sigcontext(CPUOpenRISCState *env, target_sigcontext *s= c) { - unsigned int err =3D 0; - unsigned long old_usp; + int i; + abi_ulong v; =20 - /* Alwys make any pending restarted system call return -EINTR */ - current_thread_info()->restart_block.fn =3D do_no_restart_syscall; - - /* restore the regs from &sc->regs (same as sc, since regs is first) - * (sc is already checked for VERIFY_READ since the sigframe was - * checked in sys_sigreturn previously) - */ - - if (copy_from_user(regs, &sc, sizeof(struct target_pt_regs))) { - goto badframe; + for (i =3D 0; i < 32; ++i) { + __get_user(v, &sc->regs.gpr[i]); + cpu_set_gpr(env, i, v); } + __get_user(env->pc, &sc->regs.pc); =20 - /* make sure the U-flag is set so user-mode cannot fool us */ - - regs->sr &=3D ~SR_SM; - - /* restore the old USP as it was before we stacked the sc etc. - * (we cannot just pop the sigcontext since we aligned the sp and - * stuff after pushing it) - */ - - __get_user(old_usp, &sc->usp); - phx_signal("old_usp 0x%lx", old_usp); - - __PHX__ REALLY /* ??? */ - wrusp(old_usp); - regs->gpr[1] =3D old_usp; - - /* TODO: the other ports use regs->orig_XX to disable syscall checks - * after this completes, but we don't use that mechanism. maybe we can - * use it now ? - */ - - return err; - -badframe: - return 1; + /* Make sure the supervisor flag is clear. */ + __get_user(v, &sc->regs.sr); + cpu_set_sr(env, v & ~SR_SM); } -#endif =20 /* Set up a signal frame. */ =20 -static void setup_sigcontext(struct target_sigcontext *sc, - CPUOpenRISCState *regs, - unsigned long mask) +static void setup_sigcontext(target_sigcontext *sc, CPUOpenRISCState *env) { - unsigned long usp =3D cpu_get_gpr(regs, 1); + int i; =20 - /* copy the regs. they are first in sc so we can use sc directly */ + for (i =3D 0; i < 32; ++i) { + __put_user(cpu_get_gpr(env, i), &sc->regs.gpr[i]); + } =20 - /*copy_to_user(&sc, regs, sizeof(struct target_pt_regs));*/ - - /* Set the frametype to CRIS_FRAME_NORMAL for the execution of - the signal handler. The frametype will be restored to its previous - value in restore_sigcontext. */ - /*regs->frametype =3D CRIS_FRAME_NORMAL;*/ - - /* then some other stuff */ - __put_user(mask, &sc->oldmask); - __put_user(usp, &sc->usp); -} - -static inline unsigned long align_sigframe(unsigned long sp) -{ - return sp & ~3UL; + __put_user(env->pc, &sc->regs.pc); + __put_user(cpu_get_sr(env), &sc->regs.sr); } =20 static inline abi_ulong get_sigframe(struct target_sigaction *ka, - CPUOpenRISCState *regs, + CPUOpenRISCState *env, size_t frame_size) { - unsigned long sp =3D get_sp_from_cpustate(regs); - int onsigstack =3D on_sig_stack(sp); + target_ulong sp =3D get_sp_from_cpustate(env); =20 - /* redzone */ - sp =3D target_sigsp(sp, ka); - - sp =3D align_sigframe(sp - frame_size); - - /* - * If we are on the alternate signal stack and would overflow it, don'= t. - * Return an always-bogus address instead so we will die with SIGSEGV. + /* Honor redzone now. If we swap to signal stack, no need to waste + * the 128 bytes by subtracting afterward. */ + sp -=3D 128; =20 - if (onsigstack && !likely(on_sig_stack(sp))) { - return -1L; - } + sp =3D target_sigsp(sp, ka); + sp -=3D frame_size; + sp =3D QEMU_ALIGN_DOWN(sp, 4); =20 return sp; } @@ -147,11 +92,9 @@ void setup_rt_frame(int sig, struct target_sigaction *k= a, target_siginfo_t *info, target_sigset_t *set, CPUOpenRISCState *env) { - int err =3D 0; abi_ulong frame_addr; - unsigned long return_ip; - struct target_rt_sigframe *frame; - abi_ulong info_addr, uc_addr; + target_rt_sigframe *frame; + int i; =20 frame_addr =3D get_sigframe(ka, env, sizeof(*frame)); trace_user_setup_rt_frame(env, frame_addr); @@ -159,47 +102,37 @@ void setup_rt_frame(int sig, struct target_sigaction = *ka, goto give_sigsegv; } =20 - info_addr =3D frame_addr + offsetof(struct target_rt_sigframe, info); - __put_user(info_addr, &frame->pinfo); - uc_addr =3D frame_addr + offsetof(struct target_rt_sigframe, uc); - __put_user(uc_addr, &frame->puc); - if (ka->sa_flags & SA_SIGINFO) { tswap_siginfo(&frame->info, info); } =20 - /*err |=3D __clear_user(&frame->uc, offsetof(ucontext_t, uc_mcontext))= ;*/ __put_user(0, &frame->uc.tuc_flags); __put_user(0, &frame->uc.tuc_link); + target_save_altstack(&frame->uc.tuc_stack, env); - setup_sigcontext(&frame->sc, env, set->sig[0]); - - /*err |=3D copy_to_user(frame->uc.tuc_sigmask, set, sizeof(*set));*/ - - /* trampoline - the desired return ip is the retcode itself */ - return_ip =3D (unsigned long)&frame->retcode; - /* This is l.ori r11,r0,__NR_sigreturn, l.sys 1 */ - __put_user(0xa960, (short *)(frame->retcode + 0)); - __put_user(TARGET_NR_rt_sigreturn, (short *)(frame->retcode + 2)); - __put_user(0x20000001, (unsigned long *)(frame->retcode + 4)); - __put_user(0x15000000, (unsigned long *)(frame->retcode + 8)); - - if (err) { - goto give_sigsegv; + setup_sigcontext(&frame->uc.tuc_mcontext, env); + for (i =3D 0; i < TARGET_NSIG_WORDS; ++i) { + __put_user(set->sig[i], &frame->uc.tuc_sigmask.sig[i]); } =20 - /* TODO what is the current->exec_domain stuff and invmap ? */ + /* This is l.ori r11,r0,__NR_sigreturn; l.sys 1; l.nop; l.nop */ + __put_user(0xa9600000 | TARGET_NR_rt_sigreturn, frame->retcode + 0); + __put_user(0x20000001, frame->retcode + 1); + __put_user(0x15000000, frame->retcode + 2); + __put_user(0x15000000, frame->retcode + 3); =20 /* Set up registers for signal handler */ - env->pc =3D (unsigned long)ka->_sa_handler; /* what we enter NOW */ - cpu_set_gpr(env, 9, (unsigned long)return_ip); /* what we enter LA= TER */ - cpu_set_gpr(env, 3, (unsigned long)sig); /* arg 1: signo */ - cpu_set_gpr(env, 4, (unsigned long)&frame->info); /* arg 2: (siginfo_= t*) */ - cpu_set_gpr(env, 5, (unsigned long)&frame->uc); /* arg 3: ucontext = */ - - /* actually move the usp to reflect the stacked frame */ - cpu_set_gpr(env, 1, (unsigned long)frame); + cpu_set_gpr(env, 9, frame_addr + offsetof(target_rt_sigframe, retcode)= ); + cpu_set_gpr(env, 3, sig); + cpu_set_gpr(env, 4, frame_addr + offsetof(target_rt_sigframe, info)); + cpu_set_gpr(env, 5, frame_addr + offsetof(target_rt_sigframe, uc)); + cpu_set_gpr(env, 1, frame_addr); =20 + /* For debugging convenience, set ppc to the insn that faulted. */ + env->ppc =3D env->pc; + /* When setting the PC for the signal handler, exit delay slot. */ + env->pc =3D ka->_sa_handler; + env->dflag =3D 0; return; =20 give_sigsegv: @@ -207,16 +140,34 @@ give_sigsegv: force_sigsegv(sig); } =20 -long do_sigreturn(CPUOpenRISCState *env) -{ - trace_user_do_sigreturn(env, 0); - fprintf(stderr, "do_sigreturn: not implemented\n"); - return -TARGET_ENOSYS; -} - long do_rt_sigreturn(CPUOpenRISCState *env) { + abi_ulong frame_addr =3D get_sp_from_cpustate(env); + target_rt_sigframe *frame; + sigset_t set; + trace_user_do_rt_sigreturn(env, 0); - fprintf(stderr, "do_rt_sigreturn: not implemented\n"); - return -TARGET_ENOSYS; + if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) { + goto badframe; + } + if (frame_addr & 3) { + goto badframe; + } + + target_to_host_sigset(&set, &frame->uc.tuc_sigmask); + set_sigmask(&set); + + restore_sigcontext(env, &frame->uc.tuc_mcontext); + if (do_sigaltstack(frame_addr + offsetof(target_rt_sigframe, uc.tuc_st= ack), + 0, frame_addr) =3D=3D -EFAULT) { + goto badframe; + } + + unlock_user_struct(frame, frame_addr, 0); + return cpu_get_gpr(env, 11); + + badframe: + unlock_user_struct(frame, frame_addr, 0); + force_sig(TARGET_SIGSEGV); + return 0; } diff --git a/linux-user/signal.c b/linux-user/signal.c index be2815b45d..602b631b92 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -236,7 +236,7 @@ int do_sigprocmask(int how, const sigset_t *set, sigset= _t *oldset) return 0; } =20 -#if !defined(TARGET_OPENRISC) && !defined(TARGET_NIOS2) +#if !defined(TARGET_NIOS2) /* Just set the guest's signal mask to the specified value; the * caller is assumed to have called block_signals() already. */ diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index e01ce9ed1c..fb7cb5c507 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -27,6 +27,7 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); =20 cpu->env.pc =3D value; + cpu->env.dflag =3D 0; } =20 static bool openrisc_cpu_has_work(CPUState *cs) --=20 2.17.1 From nobody Fri May 17 12:56:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530156057989920.9217701717287; Wed, 27 Jun 2018 20:20:57 -0700 (PDT) Received: from localhost ([::1]:34332 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNUP-00028Q-8J for importer@patchew.org; Wed, 27 Jun 2018 23:20:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40115) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNE8-0005Ix-4d for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:04:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNE5-0008JF-N1 for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:04:08 -0400 Received: from mail-pl0-x234.google.com ([2607:f8b0:400e:c01::234]:36059) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNE5-0008IG-GM for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:04:05 -0400 Received: by mail-pl0-x234.google.com with SMTP id a7-v6so2013080plp.3 for ; Wed, 27 Jun 2018 20:04:05 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c01::234 Subject: [Qemu-devel] [PATCH v3 23/23] linux-user: Fix struct sigaltstack for openrisc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- linux-user/openrisc/target_signal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux-user/openrisc/target_signal.h b/linux-user/openrisc/targ= et_signal.h index c352a8b333..8283eaf544 100644 --- a/linux-user/openrisc/target_signal.h +++ b/linux-user/openrisc/target_signal.h @@ -5,8 +5,8 @@ =20 typedef struct target_sigaltstack { abi_long ss_sp; + abi_int ss_flags; abi_ulong ss_size; - abi_long ss_flags; } target_stack_t; =20 /* sigaltstack controls */ --=20 2.17.1