From nobody Tue Apr 30 03:23:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529720668071773.0602197798457; Fri, 22 Jun 2018 19:24:28 -0700 (PDT) Received: from localhost ([::1]:36914 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWYDp-0006jM-8g for importer@patchew.org; Fri, 22 Jun 2018 22:24:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50238) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWYCs-0006P9-1E for qemu-devel@nongnu.org; Fri, 22 Jun 2018 22:23:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWYCo-0000mq-1p for qemu-devel@nongnu.org; Fri, 22 Jun 2018 22:23:18 -0400 Received: from mail-it0-x242.google.com ([2607:f8b0:4001:c0b::242]:40005) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fWYCn-0000mH-RO; Fri, 22 Jun 2018 22:23:13 -0400 Received: by mail-it0-x242.google.com with SMTP id 188-v6so5373001ita.5; Fri, 22 Jun 2018 19:23:13 -0700 (PDT) Received: from localhost.localdomain ([69.14.184.20]) by smtp.gmail.com with ESMTPSA id d130-v6sm2719797iog.84.2018.06.22.19.23.10 (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 22 Jun 2018 19:23:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=apddxmW5Nuvv8NjhNpsD1EyInRf/aR8YOMJ89Qlm9c8=; b=dCPcyvitSJVBnOpBb6vDGo/PYXYVe8hhnxM8N5318NdZKUmelewvzbiLwkfPTVR8i7 aWgDArnnNOKjDOPqGH56cCho1yhAloJfcAe1x+H84LjB1ISYDGYmJeCoKcTUFiPfNwYo rxF6zZ/JYgidG/29l1bZjzxbGVTLQG6PKao9i2M/FkPr4ZVLHwvAtFOyL3aZML/ljaNP cNf2FWRmHKqPU9goYEeM3zfTUcCLP5Z4zMFH4pPqQm6ccfqHEQqeSefx5VhWnXj6ik9x ySB8S1jIt3XTXz7E4+b3qF2HEGSiTIH4Hp8mbPD7hwpKiF9rJUpw4RlxuI9X9LVTSOGz GRvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=apddxmW5Nuvv8NjhNpsD1EyInRf/aR8YOMJ89Qlm9c8=; b=AmC6F31C6GQnIkO6I9ezutfeUQjeQxe0dMN7YFOM3acmjXOG93JMTVL5gW13BcRhw9 D4GbSy1Wq/CmbzrgCQIIm+IQsDBQ4nWMAUPyc9Vl2/O2OW4aMW0p1MNj3/JMATyZZXBA oANIB6aeXCsFxn/vIFpeFZTWgUZHTII4e/g1kWuIL1UwzgSJL+bJJRGEyR5eHNO0tgnp C5OfeeWmZF3cILuCtw6gGvFNGyySQzoV5mF+fpQ5J6crW/v6BwrUKeaB/ZGU1GddGqCG H6haSVuGCyj5zTEn5D1AXZznOQqvtMHi/BMMg6MvNiTFuhbPWxKDLIAXK7b/1iMg3Xib hp1w== X-Gm-Message-State: APt69E01s8T0X84SprAMsYh9/CoItWI08E2wUZ7G653qd4thpGmvg1hQ rXG70yg3EeFC9emUPCcNB/8= X-Google-Smtp-Source: ADUXVKJnJQWp4EzXUoCbZOQcR7mM2gOWfu6B2T1KDx4gahboLFtEMcHBFrNvCyOj4/1cZ3hlIxR8YA== X-Received: by 2002:a24:6ed0:: with SMTP id w199-v6mr3509918itc.65.1529720593189; Fri, 22 Jun 2018 19:23:13 -0700 (PDT) From: John Arbuckle To: david@gibson.dropbear.id.au, qemu-devel@nongnu.org, qemu-ppc@nongnu.org Date: Fri, 22 Jun 2018 22:22:58 -0400 Message-Id: <20180623022258.22158-1-programmingkidx@gmail.com> X-Mailer: git-send-email 2.14.3 (Apple Git-98) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::242 Subject: [Qemu-devel] [PATCH] fix fdiv instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Arbuckle Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When the fdiv instruction divides a finite number by zero, the result actually depends on the FPSCR[ZE] bit. If this bit is set, the return value is zero. If it is not set the result should be either positive or negative infinity. The sign of this result would depend on the sign of the two inputs. What currently happens is only infinity is returned even if the FPSCR[ZE] bit is set. This patch fixes this problem by actually checking the FPSCR[ZE] bit when deciding what the answer should be. fdiv is suppose to only set the FPSCR's FPRF bits during a division by zero situation when the FPSCR[ZE] is not set. What currently happens is these bits are always set. This patch fixes this problem by checking the FPSCR[ZE] bit to decide if the FPRF bits should be set.=20 https://www.pdfdrive.net/powerpc-microprocessor-family-the-programming-envi= ronments-for-32-e3087633.html This document has the information on the fdiv. Page 133 has the information= on what action is executed when a division by zero situation takes place.=20 Signed-off-by: John Arbuckle --- target/ppc/fpu_helper.c | 16 ++++++++++++++++ target/ppc/translate/fp-impl.inc.c | 28 +++++++++++++++++++++++++++- 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 7714bfe0f9..de694604fb 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -658,6 +658,20 @@ uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, = uint64_t arg2) } else if (unlikely(float64_is_zero(farg1.d) && float64_is_zero(farg2.= d))) { /* Division of zero by zero */ farg1.ll =3D float_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1); + } else if (arg2 =3D=3D 0) { + /* Division by zero */ + float_zero_divide_excp(env, GETPC()); + if (fpscr_ze) { /* if zero divide exception is enabled */ + farg1.ll =3D 0; + } else { + uint64_t sign =3D (farg1.ll ^ farg2.ll) >> 63; + if (sign) { /* Negative sign bit */ + farg1.ll =3D 0xfff0000000000000; /* Negative Infinity */ + } else { /* Positive sign bit */ + farg1.ll =3D 0x7ff0000000000000; /* Positive Infinity */ + } + helper_compute_fprf_float64(env, farg1.d); + } } else { if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) || float64_is_signaling_nan(farg2.d, &env->fp_status))) { @@ -665,6 +679,8 @@ uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, u= int64_t arg2) float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); } farg1.d =3D float64_div(farg1.d, farg2.d, &env->fp_status); + helper_compute_fprf_float64(env, farg1.d); + helper_float_check_status(env); } =20 return farg1.ll; diff --git a/target/ppc/translate/fp-impl.inc.c b/target/ppc/translate/fp-i= mpl.inc.c index 2fbd4d4f38..4e20bcceb4 100644 --- a/target/ppc/translate/fp-impl.inc.c +++ b/target/ppc/translate/fp-impl.inc.c @@ -84,6 +84,32 @@ static void gen_f##name(DisasContext *ctx) = \ _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); = \ _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); =20 + +#define _GEN_FLOAT_DIV(name, op, op1, op2, inval, isfloat, set_fprf, type)= \ +static void gen_f##name(DisasContext *ctx) = \ +{ = \ + if (unlikely(!ctx->fpu_enabled)) { = \ + gen_exception(ctx, POWERPC_EXCP_FPU); = \ + return; = \ + } = \ + gen_reset_fpstatus(); = \ + gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, = \ + cpu_fpr[rA(ctx->opcode)], = \ + cpu_fpr[rB(ctx->opcode)]); = \ + if (isfloat) { = \ + gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, = \ + cpu_fpr[rD(ctx->opcode)]); = \ + } = \ + if (unlikely(Rc(ctx->opcode) !=3D 0)) { = \ + gen_set_cr1_from_fpscr(ctx); = \ + } = \ +} + +#define GEN_FLOAT_DIV(name, op2, inval, set_fprf, type) = \ +_GEN_FLOAT_DIV(name, name, 0x3F, op2, inval, 0, set_fprf, type); = \ +_GEN_FLOAT_DIV(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); + + #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) = \ static void gen_f##name(DisasContext *ctx) = \ { = \ @@ -149,7 +175,7 @@ static void gen_f##name(DisasContext *ctx) = \ /* fadd - fadds */ GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); /* fdiv - fdivs */ -GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); +GEN_FLOAT_DIV(div, 0x12, 0x000007C0, 1, PPC_FLOAT); /* fmul - fmuls */ GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); =20 --=20 2.14.3 (Apple Git-98)