From nobody Wed May 1 22:43:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529654680626754.4051710275395; Fri, 22 Jun 2018 01:04:40 -0700 (PDT) Received: from localhost ([::1]:59940 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWH3f-00033Z-UL for importer@patchew.org; Fri, 22 Jun 2018 04:04:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44111) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWH1a-0001r1-Kt for qemu-devel@nongnu.org; Fri, 22 Jun 2018 04:02:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWH1X-0002Pz-I5 for qemu-devel@nongnu.org; Fri, 22 Jun 2018 04:02:30 -0400 Received: from smtp58.i.mail.ru ([217.69.128.38]:46694) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fWH1X-0002PN-AH for qemu-devel@nongnu.org; Fri, 22 Jun 2018 04:02:27 -0400 Received: by smtp58.i.mail.ru with esmtpa (envelope-from ) id 1fWH1V-0004R4-E9; Fri, 22 Jun 2018 11:02:25 +0300 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=X3YJTrjK3YnX8knf4QtA/yo8i9CI/JeXbCj8Crn/ym0=; b=Kk/XnjhzRFlPf49oGktxTIT39xP2pDUFAqO+hdUhzFbNHZHswHuk64+gBEv/YcWCvjMrPD8v2gfPQROIWDmKNf9nJOf7EncEl+NM9kcCAjd3Xn7sjHN4Zgk8jS/v/AOoh815KUsXoMIRlPlgQZQEqJbl0BLn2DX5SweBg9ld5ik=; To: qemu-devel Date: Fri, 22 Jun 2018 11:01:37 +0300 Message-Id: <20180622080138.17702-2-jusual@mail.ru> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180622080138.17702-1-jusual@mail.ru> References: <20180622080138.17702-1-jusual@mail.ru> Authentication-Results: smtp58.i.mail.ru; auth=pass smtp.auth=jusual@mail.ru smtp.mailfrom=jusual@mail.ru X-7FA49CB5: 0D63561A33F958A51F7D5FABFF5C10AAEA96F0A908EBB418D887B81FA16162DD0A6AB1C7CE11FEE34AF66DFF1D4D208B76E601842F6C81A1F004C906525384306FED454B719173D6725E5C173C3A84C3AC6EB6EE67F779AC77D690E8945E457E6D8C47C27EEC5E9FB5C8C57E37DE458B4C7702A67D5C3316FA3894348FB808DB5CDE6EBCCF0779B2574AF45C6390F7469DAA53EE0834AAEE X-Mailru-Sender: 7766D515518070DE138AAC7428EA760D788743B276775BD5690CF8C0787FE22E75268CCE79D7902D7C4160E8B47E48163DDE9B364B0DF2898CB68AF7A628805D594FB4C9F0DBF412AE208404248635DF X-Mras: OK X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 217.69.128.38 Subject: [Qemu-devel] [PATCH v2 1/2] target/arm: Introduce ARM_FEATURE_M_MAIN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Julia Suvorova via Qemu-devel Reply-To: Julia Suvorova Cc: Peter Maydell , Jim Mussared , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Stefan Hajnoczi , Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This feature is intended to distinguish ARMv8-M variants: Baseline and Mainline. ARMv7-M compatibility requires the Main Extension. ARMv6-M compatibility is provided by all ARMv8-M implementations. Signed-off-by: Julia Suvorova --- target/arm/cpu.c | 3 +++ target/arm/cpu.h | 1 + 2 files changed, 4 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 788883073c..c8bba94b06 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1248,6 +1248,7 @@ static void cortex_m3_initfn(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); cpu->midr =3D 0x410fc231; cpu->pmsav7_dregion =3D 8; cpu->id_pfr0 =3D 0x00000030; @@ -1272,6 +1273,7 @@ static void cortex_m4_initfn(Object *obj) =20 set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); cpu->midr =3D 0x410fc240; /* r0p0 */ cpu->pmsav7_dregion =3D 8; @@ -1297,6 +1299,7 @@ static void cortex_m33_initfn(Object *obj) =20 set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); cpu->midr =3D 0x410fd213; /* r0p3 */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8488273c5b..a4507a2d6f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1482,6 +1482,7 @@ enum arm_features { ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ + ARM_FEATURE_M_MAIN, /* M profile Main Extension */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) --=20 2.17.0 From nobody Wed May 1 22:43:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529654849178250.03481338611607; Fri, 22 Jun 2018 01:07:29 -0700 (PDT) Received: from localhost ([::1]:59962 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWH6O-0005IH-Ch for importer@patchew.org; Fri, 22 Jun 2018 04:07:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44165) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWH1v-00028c-Sl for qemu-devel@nongnu.org; Fri, 22 Jun 2018 04:02:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWH1s-0002f0-Jc for qemu-devel@nongnu.org; Fri, 22 Jun 2018 04:02:51 -0400 Received: from smtp58.i.mail.ru ([217.69.128.38]:40232) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fWH1s-0002eN-CU for qemu-devel@nongnu.org; Fri, 22 Jun 2018 04:02:48 -0400 Received: by smtp58.i.mail.ru with esmtpa (envelope-from ) id 1fWH1q-0004R4-GX; Fri, 22 Jun 2018 11:02:46 +0300 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=rmrN6ddKFOMDNj2HIqA8Q0vndviCGYIfx93ugaGXnD0=; b=oiLAZHH0SkmJmhX+PSnAe/MFPwQxEqSF8fudeIjVl/mFt+hlb4CL+YilMvPHeW76fTE5YjFvd8tsLALJnWq9NPASBz5L4gvV7X8t+r9fhnntQeg8Jt1YVenUGN1k3CSIxaAd5jVbG0ipFlBtbYAplaZa9hy5cm6uloyieXToYYo=; To: qemu-devel Date: Fri, 22 Jun 2018 11:01:38 +0300 Message-Id: <20180622080138.17702-3-jusual@mail.ru> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180622080138.17702-1-jusual@mail.ru> References: <20180622080138.17702-1-jusual@mail.ru> Authentication-Results: smtp58.i.mail.ru; auth=pass smtp.auth=jusual@mail.ru smtp.mailfrom=jusual@mail.ru X-7FA49CB5: 0D63561A33F958A518027DEEC90702E2EA96F0A908EBB418BB1D46B6EA3127FA0A6AB1C7CE11FEE35EF3C447179F0106BA3038C0950A5D36B5C8C57E37DE458B4C7702A67D5C33162DBA43225CD8A89F0A35B161A8BF67C1144B866374EF19647D149460FF1CF91843847C11F186F3C5E7DDDDC251EA7DABCC89B49CDF41148F458B267F216095A92623479134186CDE6BA297DBC24807EABDAD6C7F3747799A X-Mailru-Sender: 7766D515518070DE138AAC7428EA760D6A54089C9B27E474E82940826AC19BF0C5BB865C0339F0897C4160E8B47E48163DDE9B364B0DF2898CB68AF7A628805D594FB4C9F0DBF412AE208404248635DF X-Mras: OK X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 217.69.128.38 Subject: [Qemu-devel] [PATCH v2 2/2] target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Julia Suvorova via Qemu-devel Reply-To: Julia Suvorova Cc: Peter Maydell , Jim Mussared , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Stefan Hajnoczi , Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Unlike ARMv7-M, ARMv6-M and ARMv8-M Baseline only supports naturally aligned memory accesses for load/store instructions. Signed-off-by: Julia Suvorova --- target/arm/translate.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b988d379e7..2a3e4f5d4c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1100,7 +1100,14 @@ static inline TCGv gen_aa32_addr(DisasContext *s, TC= Gv_i32 a32, TCGMemOp op) static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, TCGMemOp opc) { - TCGv addr =3D gen_aa32_addr(s, a32, opc); + TCGv addr; + + if (arm_dc_feature(s, ARM_FEATURE_M) && + !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) { + opc |=3D MO_ALIGN; + } + + addr =3D gen_aa32_addr(s, a32, opc); tcg_gen_qemu_ld_i32(val, addr, index, opc); tcg_temp_free(addr); } @@ -1108,7 +1115,14 @@ static void gen_aa32_ld_i32(DisasContext *s, TCGv_i3= 2 val, TCGv_i32 a32, static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, TCGMemOp opc) { - TCGv addr =3D gen_aa32_addr(s, a32, opc); + TCGv addr; + + if (arm_dc_feature(s, ARM_FEATURE_M) && + !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) { + opc |=3D MO_ALIGN; + } + + addr =3D gen_aa32_addr(s, a32, opc); tcg_gen_qemu_st_i32(val, addr, index, opc); tcg_temp_free(addr); } --=20 2.17.0