[Qemu-devel] [PATCH v3 0/8] arm: implement TZ MPC

Peter Maydell posted 8 patches 5 years, 10 months ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20180620132032.28865-1-peter.maydell@linaro.org
Test checkpatch failed
Test docker-mingw@fedora passed
Test docker-quick@centos7 passed
Test s390x passed
hw/misc/Makefile.objs           |   1 +
include/hw/arm/iotkit.h         |   8 +
include/hw/misc/iotkit-secctl.h |   8 +
include/hw/misc/tz-mpc.h        |  80 ++++
hw/arm/iotkit.c                 | 112 +++++-
hw/arm/mps2-tz.c                |  71 ++--
hw/misc/iotkit-secctl.c         |  38 +-
hw/misc/tz-mpc.c                | 628 ++++++++++++++++++++++++++++++++
MAINTAINERS                     |   2 +
default-configs/arm-softmmu.mak |   1 +
hw/misc/trace-events            |   8 +
11 files changed, 917 insertions(+), 40 deletions(-)
create mode 100644 include/hw/misc/tz-mpc.h
create mode 100644 hw/misc/tz-mpc.c
[Qemu-devel] [PATCH v3 0/8] arm: implement TZ MPC
Posted by Peter Maydell 5 years, 10 months ago
Hi; this is v3 of my iommu patchset. All the IOMMU stuff is now
in master, so the remaining part is just implementing and using
the Trustzone Memory Protection Controller in the mps2-an505.

Changes from v2 to v3 (all fairly minor):
 * add new variable to clarify sense of LUT bits
 * only autoinc the IDX register if CTRL.AUTOINC is set
 * NS accesses should see IDregs only
   (The datasheet is unclear on the exact behaviour on an
   NS access to a non-ID register, so I've made a best guess
   and had them RAZ/WI. This behaviour is not reachable for
   the mps2-an505 anyway, so it doesn't really matter.)

Patches still needing review: 2, 4, 5

thanks
-- PMM

Peter Maydell (8):
  hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection
    Controller
  hw/misc/tz-mpc.c: Implement registers
  hw/misc/tz-mpc.c: Implement correct blocked-access behaviour
  hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate
  hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS
  hw/arm/iotkit: Instantiate MPC
  hw/arm/iotkit: Wire up MPC interrupt lines
  hw/arm/mps2-tz.c: Instantiate MPCs

 hw/misc/Makefile.objs           |   1 +
 include/hw/arm/iotkit.h         |   8 +
 include/hw/misc/iotkit-secctl.h |   8 +
 include/hw/misc/tz-mpc.h        |  80 ++++
 hw/arm/iotkit.c                 | 112 +++++-
 hw/arm/mps2-tz.c                |  71 ++--
 hw/misc/iotkit-secctl.c         |  38 +-
 hw/misc/tz-mpc.c                | 628 ++++++++++++++++++++++++++++++++
 MAINTAINERS                     |   2 +
 default-configs/arm-softmmu.mak |   1 +
 hw/misc/trace-events            |   8 +
 11 files changed, 917 insertions(+), 40 deletions(-)
 create mode 100644 include/hw/misc/tz-mpc.h
 create mode 100644 hw/misc/tz-mpc.c

-- 
2.17.1


Re: [Qemu-devel] [PATCH v3 0/8] arm: implement TZ MPC
Posted by no-reply@patchew.org 5 years, 10 months ago
Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20180620132032.28865-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH v3 0/8] arm: implement TZ MPC

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
ff1d3de2bd hw/arm/mps2-tz.c: Instantiate MPCs
5e8ef7e70e hw/arm/iotkit: Wire up MPC interrupt lines
e628d6a2fd hw/arm/iotkit: Instantiate MPC
97fd882413 hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS
b890499e67 hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate
4a900664be hw/misc/tz-mpc.c: Implement correct blocked-access behaviour
db71eee1b0 hw/misc/tz-mpc.c: Implement registers
f702ef6f8e hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller

=== OUTPUT BEGIN ===
Checking PATCH 1/8: hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#85: 
new file mode 100644

total: 0 errors, 1 warnings, 504 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 2/8: hw/misc/tz-mpc.c: Implement registers...
Checking PATCH 3/8: hw/misc/tz-mpc.c: Implement correct blocked-access behaviour...
Checking PATCH 4/8: hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate...
Checking PATCH 5/8: hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS...
ERROR: spaces required around that '*' (ctx:VxV)
#91: FILE: hw/misc/iotkit-secctl.c:711:
+    .subsections = (const VMStateDescription*[]) {
                                             ^

total: 1 errors, 0 warnings, 100 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 6/8: hw/arm/iotkit: Instantiate MPC...
Checking PATCH 7/8: hw/arm/iotkit: Wire up MPC interrupt lines...
Checking PATCH 8/8: hw/arm/mps2-tz.c: Instantiate MPCs...
=== OUTPUT END ===

Test command exited with code: 1


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Re: [Qemu-devel] [Qemu-arm] [PATCH v3 0/8] arm: implement TZ MPC
Posted by Peter Maydell 5 years, 10 months ago
On 20 June 2018 at 14:20, Peter Maydell <peter.maydell@linaro.org> wrote:
> Hi; this is v3 of my iommu patchset. All the IOMMU stuff is now
> in master, so the remaining part is just implementing and using
> the Trustzone Memory Protection Controller in the mps2-an505.
>
> Changes from v2 to v3 (all fairly minor):
>  * add new variable to clarify sense of LUT bits
>  * only autoinc the IDX register if CTRL.AUTOINC is set
>  * NS accesses should see IDregs only
>    (The datasheet is unclear on the exact behaviour on an
>    NS access to a non-ID register, so I've made a best guess
>    and had them RAZ/WI. This behaviour is not reachable for
>    the mps2-an505 anyway, so it doesn't really matter.)



Applied to target-arm.next, thanks.

-- PMM