From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529496542567914.1319795434478; Wed, 20 Jun 2018 05:09:02 -0700 (PDT) Received: from localhost ([::1]:48993 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbuz-0003LZ-7T for importer@patchew.org; Wed, 20 Jun 2018 08:08:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34850) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbtC-0002Vr-CE for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:07:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbt8-0003Jp-De for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:07:06 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.150.224]:33281) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbt8-0003HG-7L for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:07:02 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx4.ess.sfj.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:06:54 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:06:43 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:05:46 +0100 Message-ID: <20180620120620.12806-2-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496400-298555-14288-41748-2 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.150.224 Subject: [Qemu-devel] [PATCH 01/35] target/mips: Raise a RI when given fs is n/a from CTC1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Fix to raise a Reserved Instruction exception when given fs is not available from CTC1. Signed-off-by: Yongbok Kim Reviewed-by: Aleksandar Markovic --- target/mips/op_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 9025f42..41d3634 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2627,6 +2627,9 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1= , uint32_t fs, uint32_t rt) (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask= )); break; default: + if (env->insn_flags & ISA_MIPS32R6) { + do_raise_exception(env, EXCP_RI, GETPC()); + } return; } restore_fp_status(env); --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529496689152157.38243285007638; Wed, 20 Jun 2018 05:11:29 -0700 (PDT) Received: from localhost ([::1]:49011 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbxQ-0005nD-BE for importer@patchew.org; Wed, 20 Jun 2018 08:11:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34867) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbtI-0002WU-Sg for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:07:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbtH-0003Nb-GO for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:07:12 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.150.224]:40989) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbtH-0003Ks-AV for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:07:11 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx4.ess.sfj.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:07:03 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:06:47 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:05:47 +0100 Message-ID: <20180620120620.12806-3-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496400-298555-14288-41748-3 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.150.224 Subject: [Qemu-devel] [PATCH 02/35] target/mips: Fix microMIPS on reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Fix to activate microMIPS (and nanoMIPS) on reset when Config3.ISA =3D=3D {= 1, 3} Signed-off-by: Yongbok Kim Reviewed-by: Aleksandar Markovic --- target/mips/translate.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index e57d71e..bfbc300 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20713,6 +20713,11 @@ void cpu_state_reset(CPUMIPSState *env) env->CP0_Status |=3D (1 << CP0St_FR); } =20 + if (env->CP0_Config3 & (1 << CP0C3_ISA)) { + /* microMIPS/nanoMIPS on reset when Config3.ISA =3D=3D {1, 3} */ + env->hflags |=3D MIPS_HFLAG_M16; + } + /* MSA */ if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { msa_reset(env); --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529496563280480.56064618229107; Wed, 20 Jun 2018 05:09:23 -0700 (PDT) Received: from localhost ([::1]:48994 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbvJ-0003ac-H7 for importer@patchew.org; Wed, 20 Jun 2018 08:09:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34894) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbtS-0002cN-Cb for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:07:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbtQ-0003SA-38 for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:07:22 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.150.224]:32784) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbtP-0003Q3-RT for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:07:20 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx4.ess.sfj.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:07:12 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:06:50 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:05:48 +0100 Message-ID: <20180620120620.12806-4-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496400-298555-14288-41748-4 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 1.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound 0.50 BSF_RULE_7582B META: Custom Rule 7582B X-BESS-Outbound-Spam-Status: SCORE=1.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND, BSF_RULE_7582B X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.150.224 Subject: [Qemu-devel] [PATCH 03/35] target/mips: Add nanoMIPS OPCODE table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add nanoMIPS OPCODE table Reference: nanoMIPS Base ISA Technical Reference Manual Signed-off-by: Yongbok Kim Reviewed-by: Richard Henderson --- target/mips/mips-defs.h | 4 + target/mips/translate.c | 670 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 674 insertions(+) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index d239069..eadc1d8 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -39,6 +39,7 @@ #define ISA_MIPS64R5 0x00001000 #define ISA_MIPS32R6 0x00002000 #define ISA_MIPS64R6 0x00004000 +#define ISA_NANOMIPS32 0x00008000 =20 /* MIPS ASEs. */ #define ASE_MIPS16 0x00010000 @@ -87,6 +88,9 @@ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) =20 +/* MIPS Technologies "nanoMIPS" */ +#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) + /* Strictly follow the architecture standard: - Disallow "special" instruction handling for PMON/SPIM. Note that we still maintain Count/Compare to match the host clock. */ diff --git a/target/mips/translate.c b/target/mips/translate.c index bfbc300..27d5fb2 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -15530,6 +15530,676 @@ static int decode_micromips_opc (CPUMIPSState *en= v, DisasContext *ctx) return 2; } =20 +/* nanoMIPS */ + +/* Major opcode */ +enum { + NM_P_ADDIU =3D 0x00, + NM_ADDIUPC =3D 0x01, + NM_MOVE_BALC =3D 0x02, + NM_P16_MV =3D 0x04, + NM_LW16 =3D 0x05, + NM_BC16 =3D 0x06, + NM_P16_SR =3D 0x07, + + NM_POOL32A =3D 0x08, + NM_P_BAL =3D 0x0a, + NM_P16_SHIFT =3D 0x0c, + NM_LWSP16 =3D 0x0d, + NM_BALC16 =3D 0x0e, + NM_P16_4X4 =3D 0x0f, + + NM_P_GP_W =3D 0x10, + NM_P_GP_BH =3D 0x11, + NM_P_J =3D 0x12, + NM_P16C =3D 0x14, + NM_LWGP16 =3D 0x15, + NM_P16_LB =3D 0x17, + + NM_P48I =3D 0x18, + NM_P16_A1 =3D 0x1c, + NM_LW4X4 =3D 0x1d, + NM_P16_LH =3D 0x1f, + + NM_P_U12 =3D 0x20, + NM_P_LS_U12 =3D 0x21, + NM_P_BR1 =3D 0x22, + NM_P16_A2 =3D 0x24, + NM_SW16 =3D 0x25, + NM_BEQZC16 =3D 0x26, + + NM_POOL32F =3D 0x28, + NM_P_LS_S9 =3D 0x29, + NM_P_BR2 =3D 0x2a, + + NM_P16_ADDU =3D 0x2c, + NM_SWSP16 =3D 0x2d, + NM_BNEZC16 =3D 0x2e, + NM_MOVEP =3D 0x2f, + + NM_POOL32S =3D 0x30, + NM_P_BRI =3D 0x32, + NM_LI16 =3D 0x34, + NM_SWGP16 =3D 0x35, + NM_P16_BR =3D 0x36, + + NM_P_LUI =3D 0x38, + NM_ANDI16 =3D 0x3c, + NM_SW4X4 =3D 0x3d, + NM_MOVEPREV =3D 0x3f +}; + +/* POOL32A instruction pool */ +enum { + NM_POOL32A0 =3D 0x00, + NM_SPECIAL2 =3D 0x01, + NM_COP2_1 =3D 0x02, + NM_UDI =3D 0x03, + NM_POOL32A5 =3D 0x05, + NM_POOL32A7 =3D 0x07 +}; + +/* P.GP.W instruction pool */ +enum { + NM_ADDIUGP_W =3D 0x00, + NM_LWGP =3D 0x02, + NM_SWGP =3D 0x03 +}; + +/* P48I instruction pool */ +enum { + NM_LI48 =3D 0x00, + NM_ADDIU48 =3D 0x01, + NM_ADDIUGP48 =3D 0x02, + NM_ADDIUPC48 =3D 0x03, + NM_LWPC48 =3D 0x0b, + NM_SWPC48 =3D 0x0f, +}; + +/* P.U12 instruction pool */ +enum { + NM_ORI =3D 0x00, + NM_XORI =3D 0x01, + NM_ANDI =3D 0x02, + NM_P_SR =3D 0x03, + NM_SLTI =3D 0x04, + NM_SLTIU =3D 0x05, + NM_SEQI =3D 0x06, + NM_ADDIUNEG =3D 0x08, + NM_P_SHIFT =3D 0x0c, + NM_P_ROTX =3D 0x0d, + NM_P_INS =3D 0x0e, + NM_P_EXT =3D 0x0f +}; + +/* POOL32F instruction pool */ +enum { + NM_POOL32F_0 =3D 0x00, + NM_POOL32F_3 =3D 0x03, + NM_POOL32F_5 =3D 0x05 +}; + +/* POOL32S instruction pool */ +enum { + NM_POOL32S_0 =3D 0x00, + NM_POOL32S_4 =3D 0x04 +}; + +/* P.LUI instruction pool */ +enum { + NM_LUI =3D 0x00, + NM_ALUIPC =3D 0x01 +}; + +/* P.GP.BH instruction pool */ +enum { + NM_LBGP =3D 0x00, + NM_SBGP =3D 0x01, + NM_LBUGP =3D 0x02, + NM_ADDIUGP_B =3D 0x03, + NM_P_GP_LH =3D 0x04, + NM_P_GP_SH =3D 0x05, + NM_P_GP_CP1 =3D 0x06, +}; + +/* P.LS.U12 instruction pool */ +enum { + NM_LB =3D 0x00, + NM_SB =3D 0x01, + NM_LBU =3D 0x02, + NM_P_PREFU12 =3D 0x03, + NM_LH =3D 0x04, + NM_SH =3D 0x05, + NM_LHU =3D 0x06, + NM_LWU =3D 0x07, + NM_LW =3D 0x08, + NM_SW =3D 0x09, + NM_LWC1 =3D 0x0a, + NM_SWC1 =3D 0x0b, + NM_LDC1 =3D 0x0e, + NM_SDC1 =3D 0x0f +}; + +/* P.LS.S9 instruction pool */ +enum { + NM_P_LS_S0 =3D 0x00, + NM_P_LS_S1 =3D 0x01, + NM_P_LS_E0 =3D 0x02, + NM_P_LS_WM =3D 0x04, + NM_P_LS_UAWM =3D 0x05 +}; + +/* P.BAL instruction pool */ +enum { + NM_BC =3D 0x00, + NM_BALC =3D 0x01 +}; + +/* P.J instruction pool */ +enum { + NM_JALRC =3D 0x00, + NM_JALRC_HB =3D 0x01, + NM_P_BALRSC =3D 0x08 +}; + +/* P.BR1 instruction pool */ +enum { + NM_BEQC =3D 0x00, + NM_P_BR3A =3D 0x01, + NM_BGEC =3D 0x02, + NM_BGEUC =3D 0x03 +}; + +/* P.BR2 instruction pool */ +enum { + NM_BNEC =3D 0x00, + NM_BLTC =3D 0x02, + NM_BLTUC =3D 0x03 +}; + +/* P.BRI instruction pool */ +enum { + NM_BEQIC =3D 0x00, + NM_BBEQZC =3D 0x01, + NM_BGEIC =3D 0x02, + NM_BGEIUC =3D 0x03, + NM_BNEIC =3D 0x04, + NM_BBNEZC =3D 0x05, + NM_BLTIC =3D 0x06, + NM_BLTIUC =3D 0x07 +}; + +/* P16.SHIFT instruction pool */ +enum { + NM_SLL16 =3D 0x00, + NM_SRL16 =3D 0x01 +}; + +/* POOL16C instruction pool */ +enum { + NM_POOL16C_0 =3D 0x00, + NM_LWXS16 =3D 0x01 +}; + +/* P16.A1 instruction pool */ +enum { + NM_ADDIUR1SP =3D 0x01 +}; + +/* P16.A2 instruction pool */ +enum { + NM_ADDIUR2 =3D 0x00, + NM_P_ADDIURS5 =3D 0x01 +}; + +/* P16.ADDU instruction pool */ +enum { + NM_ADDU16 =3D 0x00, + NM_SUBU16 =3D 0x01 +}; + +/* P16.SR instruction pool */ +enum { + NM_SAVE16 =3D 0x00, + NM_RESTORE_JRC16 =3D 0x01 +}; + +/* P16.4X4 instruction pool */ +enum { + NM_ADDU4X4 =3D 0x00, + NM_MUL4X4 =3D 0x01 +}; + +/* P16.LB instruction pool */ +enum { + NM_LB16 =3D 0x00, + NM_SB16 =3D 0x01, + NM_LBU16 =3D 0x02 +}; + +/* P16.LH instruction pool */ +enum { + NM_LH16 =3D 0x00, + NM_SH16 =3D 0x01, + NM_LHU16 =3D 0x02 +}; + +/* P.RI instruction pool */ +enum { + NM_SIGRIE =3D 0x00, + NM_P_SYSCALL =3D 0x01, + NM_BREAK =3D 0x02, + NM_SDBBP =3D 0x03 +}; + +/* POOL32A0 instruction pool */ +enum { + NM_P_TRAP =3D 0x00, + NM_SEB =3D 0x01, + NM_SLLV =3D 0x02, + NM_MUL =3D 0x03, + NM_MFC0 =3D 0x06, + NM_MFHC0 =3D 0x07, + NM_SEH =3D 0x09, + NM_SRLV =3D 0x0a, + NM_MUH =3D 0x0b, + NM_MTC0 =3D 0x0e, + NM_MTHC0 =3D 0x0f, + NM_SRAV =3D 0x12, + NM_MULU =3D 0x13, + NM_MFGC0 =3D 0x16, + NM_MFHGC0 =3D 0x17, + NM_ROTRV =3D 0x1a, + NM_MUHU =3D 0x1b, + NM_MTGC0 =3D 0x1e, + NM_MTHGC0 =3D 0x1f, + NM_ADD =3D 0x22, + NM_DIV =3D 0x23, + NM_ADDU =3D 0x2a, + NM_MOD =3D 0x2b, + NM_SUB =3D 0x32, + NM_DIVU =3D 0x33, + NM_RDHWR =3D 0x38, + NM_SUBU =3D 0x3a, + NM_MODU =3D 0x3b, + NM_P_CMOVE =3D 0x42, + NM_FORK =3D 0x45, + NM_MFTR =3D 0x46, + NM_MFHTR =3D 0x47, + NM_AND =3D 0x4a, + NM_YIELD =3D 0x4d, + NM_MTTR =3D 0x4e, + NM_MTHTR =3D 0x4f, + NM_OR =3D 0x52, + NM_D_E_MT_VPE =3D 0x56, + NM_NOR =3D 0x5a, + NM_XOR =3D 0x62, + NM_SLT =3D 0x6a, + NM_P_SLTU =3D 0x72, + NM_SOV =3D 0x7a, +}; + +/* POOL32A7 instruction pool */ +enum { + NM_P_LSX =3D 0x00, + NM_LSA =3D 0x01, + NM_EXTW =3D 0x03, + NM_POOL32AXF =3D 0x07 +}; + +/* P.SR instruction pool */ +enum { + NM_PP_SR =3D 0x00, + NM_P_SR_F =3D 0x01 +}; + +/* P.SHIFT instruction pool */ +enum { + NM_P_SLL =3D 0x00, + NM_SRL =3D 0x02, + NM_SRA =3D 0x04, + NM_ROTR =3D 0x06, +}; + +/* P.ROTX instruction pool */ +enum { + NM_ROTX =3D 0x00 +}; + +/* P.INS instruction pool */ +enum { + NM_INS =3D 0x00 +}; + +/* P.EXT instruction pool */ +enum { + NM_EXT =3D 0x00 +}; + +/* POOL32F_0 (fmt) instruction pool */ +enum { + NM_RINT_S =3D 0x04, + NM_RINT_D =3D 0x44, + NM_ADD_S =3D 0x06, + NM_SELEQZ_S =3D 0x07, + NM_SELEQZ_D =3D 0x47, + NM_CLASS_S =3D 0x0c, + NM_CLASS_D =3D 0x4c, + NM_SUB_S =3D 0x0e, + NM_SELNEZ_S =3D 0x0f, + NM_SELNEZ_D =3D 0x4f, + NM_MUL_S =3D 0x16, + NM_SEL_S =3D 0x17, + NM_SEL_D =3D 0x57, + NM_DIV_S =3D 0x1e, + NM_ADD_D =3D 0x26, + NM_SUB_D =3D 0x2e, + NM_MUL_D =3D 0x36, + NM_MADDF_S =3D 0x37, + NM_MADDF_D =3D 0x77, + NM_DIV_D =3D 0x3e, + NM_MSUBF_S =3D 0x3f, + NM_MSUBF_D =3D 0x7f +}; + +/* POOL32F_3 instruction pool */ +enum { + NM_MIN_FMT =3D 0x00, + NM_MAX_FMT =3D 0x01, + NM_MINA_FMT =3D 0x04, + NM_MAXA_FMT =3D 0x05, + NM_POOL32FXF =3D 0x07 +}; + +/* POOL32F_5 instruction pool */ +enum { + NM_CMP_CONDN_S =3D 0x00, + NM_CMP_CONDN_D =3D 0x02 +}; + +/* P.GP.LH instruction pool */ +enum { + NM_LHGP =3D 0x00, + NM_LHUGP =3D 0x01 +}; + +/* P.GP.SH instruction pool */ +enum { + NM_SHGP =3D 0x00 +}; + +/* P.GP.CP1 instruction pool */ +enum { + NM_LWC1GP =3D 0x00, + NM_SWC1GP =3D 0x01, + NM_LDC1GP =3D 0x02, + NM_SDC1GP =3D 0x03 +}; + +/* P.LS.S0 instruction pool */ +enum { + NM_LBS9 =3D 0x00, + NM_LHS9 =3D 0x04, + NM_LWS9 =3D 0x08, + NM_LDS9 =3D 0x0c, + + NM_SBS9 =3D 0x01, + NM_SHS9 =3D 0x05, + NM_SWS9 =3D 0x09, + NM_SDS9 =3D 0x0d, + + NM_LBUS9 =3D 0x02, + NM_LHUS9 =3D 0x06, + NM_LWC1S9 =3D 0x0a, + NM_LDC1S9 =3D 0x0e, + + NM_P_PREFS9 =3D 0x03, + NM_LWUS9 =3D 0x07, + NM_SWC1S9 =3D 0x0b, + NM_SDC1S9 =3D 0x0f +}; + +/* P.LS.S1 instruction pool */ +enum { + NM_ASET_ACLR =3D 0x02, + NM_UALH =3D 0x04, + NM_UASH =3D 0x05, + NM_CACHE =3D 0x07, + NM_P_LL =3D 0x0a, + NM_P_SC =3D 0x0b, +}; + +/* P.LS.WM instruction pool */ +enum { + NM_LWM =3D 0x00, + NM_SWM =3D 0x01 +}; + +/* P.LS.UAWM instruction pool */ +enum { + NM_UALWM =3D 0x00, + NM_UASWM =3D 0x01 +}; + +/* P.BR3A instruction pool */ +enum { + NM_BC1EQZC =3D 0x00, + NM_BC1NEZC =3D 0x01, + NM_BC2EQZC =3D 0x02, + NM_BC2NEZC =3D 0x03, + NM_BPOSGE32C =3D 0x04 +}; + +/* P16.RI instruction pool */ +enum { + NM_P16_SYSCALL =3D 0x01, + NM_BREAK16 =3D 0x02, + NM_SDBBP16 =3D 0x03 +}; + +/* POOL16C_0 instruction pool */ +enum { + NM_POOL16C_00 =3D 0x00 +}; + +/* P16.JRC instruction pool */ +enum { + NM_JRC =3D 0x00, + NM_JALRC16 =3D 0x01 +}; + +/* P.SYSCALL instruction pool */ +enum { + NM_SYSCALL =3D 0x00, + NM_HYPCALL =3D 0x01 +}; + +/* P.TRAP instruction pool */ +enum { + NM_TEQ =3D 0x00, + NM_TNE =3D 0x01 +}; + +/* P.CMOVE instruction pool */ +enum { + NM_MOVZ =3D 0x00, + NM_MOVN =3D 0x01 +}; + +/* POOL32Axf instruction pool */ +enum { + NM_POOL32AXF_4 =3D 0x04, + NM_POOL32AXF_5 =3D 0x05 +}; + +/* POOL32Axf_{4, 5} instruction pool */ +enum { + NM_CLO =3D 0x25, + NM_CLZ =3D 0x2d, + + NM_TLBP =3D 0x01, + NM_TLBR =3D 0x09, + NM_TLBWI =3D 0x11, + NM_TLBWR =3D 0x19, + NM_TLBINV =3D 0x03, + NM_TLBINVF =3D 0x0b, + NM_DI =3D 0x23, + NM_EI =3D 0x2b, + NM_RDPGPR =3D 0x70, + NM_WRPGPR =3D 0x78, + NM_WAIT =3D 0x61, + NM_DERET =3D 0x71, + NM_ERETX =3D 0x79 +}; + +/* PP.SR instruction pool */ +enum { + NM_SAVE =3D 0x00, + NM_RESTORE =3D 0x02, + NM_RESTORE_JRC =3D 0x03 +}; + +/* P.SR.F instruction pool */ +enum { + NM_SAVEF =3D 0x00, + NM_RESTOREF =3D 0x01, +}; + +/* P16.SYSCALL instruction pool */ +enum { + NM_SYSCALL16 =3D 0x00, + NM_HYPCALL16 =3D 0x01 +}; + +/* POOL16C_00 instruction pool */ +enum { + NM_NOT16 =3D 0x00, + NM_XOR16 =3D 0x01, + NM_AND16 =3D 0x02, + NM_OR16 =3D 0x03 +}; + +/* PP.LSX and PP.LSXS instruction pool */ +enum { + NM_LBX =3D 0x00, + NM_LHX =3D 0x04, + NM_LWX =3D 0x08, + NM_LDX =3D 0x0c, + + NM_SBX =3D 0x01, + NM_SHX =3D 0x05, + NM_SWX =3D 0x09, + NM_SDX =3D 0x0d, + + NM_LBUX =3D 0x02, + NM_LHUX =3D 0x06, + NM_LWC1X =3D 0x0a, + NM_LDC1X =3D 0x0e, + + NM_LWUX =3D 0x07, + NM_SWC1X =3D 0x0b, + NM_SDC1X =3D 0x0f, + + NM_LHXS =3D 0x04, + NM_LWXS =3D 0x08, + NM_LDXS =3D 0x0c, + + NM_SHXS =3D 0x05, + NM_SWXS =3D 0x09, + NM_SDXS =3D 0x0d, + + NM_LHUXS =3D 0x06, + NM_LWC1XS =3D 0x0a, + NM_LDC1XS =3D 0x0e, + + NM_LWUXS =3D 0x07, + NM_SWC1XS =3D 0x0b, + NM_SDC1XS =3D 0x0f +}; + +/* ERETx instruction pool */ +enum { + NM_ERET =3D 0x00, + NM_ERETNC =3D 0x01 +}; + +/* POOL32FxF_{0, 1} insturction pool */ +enum { + NM_CFC1 =3D 0x40, + NM_CTC1 =3D 0x60, + NM_MFC1 =3D 0x80, + NM_MTC1 =3D 0xa0, + NM_MFHC1 =3D 0xc0, + NM_MTHC1 =3D 0xe0, + + NM_CVT_S_PL =3D 0x84, + NM_CVT_S_PU =3D 0xa4, + + NM_CVT_L_S =3D 0x004, + NM_CVT_L_D =3D 0x104, + NM_CVT_W_S =3D 0x024, + NM_CVT_W_D =3D 0x124, + + NM_RSQRT_S =3D 0x008, + NM_RSQRT_D =3D 0x108, + + NM_SQRT_S =3D 0x028, + NM_SQRT_D =3D 0x128, + + NM_RECIP_S =3D 0x048, + NM_RECIP_D =3D 0x148, + + NM_FLOOR_L_S =3D 0x00c, + NM_FLOOR_L_D =3D 0x10c, + + NM_FLOOR_W_S =3D 0x02c, + NM_FLOOR_W_D =3D 0x12c, + + NM_CEIL_L_S =3D 0x04c, + NM_CEIL_L_D =3D 0x14c, + NM_CEIL_W_S =3D 0x06c, + NM_CEIL_W_D =3D 0x16c, + NM_TRUNC_L_S =3D 0x08c, + NM_TRUNC_L_D =3D 0x18c, + NM_TRUNC_W_S =3D 0x0ac, + NM_TRUNC_W_D =3D 0x1ac, + NM_ROUND_L_S =3D 0x0cc, + NM_ROUND_L_D =3D 0x1cc, + NM_ROUND_W_S =3D 0x0ec, + NM_ROUND_W_D =3D 0x1ec, + + NM_MOV_S =3D 0x01, + NM_MOV_D =3D 0x81, + NM_ABS_S =3D 0x0d, + NM_ABS_D =3D 0x8d, + NM_NEG_S =3D 0x2d, + NM_NEG_D =3D 0xad, + NM_CVT_D_S =3D 0x04d, + NM_CVT_D_W =3D 0x0cd, + NM_CVT_D_L =3D 0x14d, + NM_CVT_S_D =3D 0x06d, + NM_CVT_S_W =3D 0x0ed, + NM_CVT_S_L =3D 0x16d +}; + +/* P.LL instruction pool */ +enum { + NM_LL =3D 0x00, + NM_LLWP =3D 0x01 +}; + +/* P.SC instruction pool */ +enum { + NM_SC =3D 0x00, + NM_SCWP =3D 0x01 +}; + +/* P.DVP instruction pool */ +enum { + NM_DVP =3D 0x00, + NM_EVP =3D 0x01 +}; + /* SmartMIPS extension to MIPS32 */ =20 #if defined(TARGET_MIPS64) --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529496716548368.01056192392093; Wed, 20 Jun 2018 05:11:56 -0700 (PDT) Received: from localhost ([::1]:49012 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbxr-00068y-MN for importer@patchew.org; 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Wed, 20 Jun 2018 05:06:55 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:05:49 +0100 Message-ID: <20180620120620.12806-5-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496400-298555-14288-41748-5 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 1.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.50 BSF_RULE_7582B META: Custom Rule 7582B 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=1.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_RULE_7582B, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.150.224 Subject: [Qemu-devel] [PATCH 04/35] target/mips: Add decode_nanomips_opc() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nanoMIPS decoder. It covers P16 pool arithmetic and branch instructions. Signed-off-by: Yongbok Kim --- target/mips/translate.c | 293 ++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 292 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 27d5fb2..633d0b4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16200,6 +16200,293 @@ enum { NM_EVP =3D 0x01 }; =20 +static int mmreg_nanomips(int r) +{ + static const int map[] =3D { 16, 17, 18, 19, 4, 5, 6, 7 }; + + return map[r & 0x7]; +} + +static int mmreg4_nanomips(int r) +{ + static const int map[] =3D { 8, 9, 10, 11, 4, 5, 6, 7, + 16, 17, 18, 19, 20, 21, 22, 23 }; + + return map[r & 0xf]; +} + +/* Used for 16-bit store instructions. */ +static int mmreg4z_nanomips(int r) +{ + static const int map[] =3D { 8, 9, 10, 0, 4, 5, 6, 7, + 16, 17, 18, 19, 20, 21, 22, 23 }; + + return map[r & 0xf]; +} + +static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t op; + int rt =3D mmreg_nanomips(uMIPS_RD(ctx->opcode)); + int rs =3D mmreg_nanomips(uMIPS_RS(ctx->opcode)); + int rd =3D mmreg_nanomips(uMIPS_RS1(ctx->opcode)); + + /* make sure instructions are on a halfword boundary */ + if (ctx->base.pc_next & 0x1) { + env->CP0_BadVAddr =3D ctx->base.pc_next; + generate_exception_end(ctx, EXCP_AdEL); + return 2; + } + + op =3D (ctx->opcode >> 10) & 0x3f; + switch (op) { + case NM_P16_MV: + { + int rt =3D uMIPS_RD5(ctx->opcode); + if (rt !=3D 0) { + /* MOVE */ + int rs =3D uMIPS_RS5(ctx->opcode); + gen_arith(ctx, OPC_ADDU, rt, rs, 0); + } else { + /* P16.RI */ + switch ((ctx->opcode >> 3) & 0x3) { + case NM_P16_SYSCALL: + generate_exception_end(ctx, EXCP_SYSCALL); + break; + case NM_BREAK16: + generate_exception_end(ctx, EXCP_BREAK); + break; + case NM_SDBBP16: + if (is_uhi(extract32(ctx->opcode, 0, 3))) { + gen_helper_do_semihosting(cpu_env); + } else { + if (ctx->hflags & MIPS_HFLAG_SBRI) { + generate_exception_end(ctx, EXCP_RI); + } else { + generate_exception_end(ctx, EXCP_DBp); + } + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } + } + break; + case NM_P16_SHIFT: + { + int shift =3D (ctx->opcode) & 0x7; + uint32_t opc =3D 0; + shift =3D (shift =3D=3D 0) ? 8 : shift; + + switch ((ctx->opcode >> 3) & 1) { + case NM_SLL16: + opc =3D OPC_SLL; + break; + case NM_SRL16: + opc =3D OPC_SRL; + break; + } + gen_shift_imm(ctx, opc, rt, rs, shift); + } + break; + case NM_P16C: + break; + case NM_P16_A1: + switch ((ctx->opcode >> 6) & 1) { + case NM_ADDIUR1SP: + gen_arith_imm(ctx, OPC_ADDIU, rt, 29, + extract32(ctx->opcode, 0, 6) << 2); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_P16_A2: + switch ((ctx->opcode >> 3) & 1) { + case NM_ADDIUR2: + { + uint8_t u =3D (uint8_t) extract32(ctx->opcode, 0, 3) << 2; + gen_arith_imm(ctx, OPC_ADDIU, rt, rs, u); + } + break; + case NM_P_ADDIURS5: + { + int rt =3D extract32(ctx->opcode, 5, 5); + if (rt !=3D 0) { + int s =3D (sextract32(ctx->opcode, 4, 1) << 3) | + extract32(ctx->opcode, 0, 3); + /* s =3D sign_extend( s[3] . s[2:0] , from_nbits =3D 4)*/ + gen_arith_imm(ctx, OPC_ADDIU, rt, rt, s); + } + } + break; + } + break; + case NM_P16_ADDU: + switch (ctx->opcode & 0x1) { + case NM_ADDU16: + gen_arith(ctx, OPC_ADDU, rd, rs, rt); + break; + case NM_SUBU16: + gen_arith(ctx, OPC_SUBU, rd, rs, rt); + break; + } + break; + case NM_P16_4X4: + { + int rt =3D (extract32(ctx->opcode, 9, 1) << 3) | + extract32(ctx->opcode, 5, 3); + int rs =3D (extract32(ctx->opcode, 4, 1) << 3) | + extract32(ctx->opcode, 0, 3); + rt =3D mmreg4_nanomips(rt); + rs =3D mmreg4_nanomips(rs); + + switch (((ctx->opcode >> 7) & 0x2) | ((ctx->opcode >> 3) & 0x1)) { + case NM_ADDU4X4: + gen_arith(ctx, OPC_ADDU, rt, rs, rt); + break; + case NM_MUL4X4: + gen_r6_muldiv(ctx, R6_OPC_MUL, rt, rs, rt); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } + break; + case NM_LI16: + { + int imm =3D extract32(ctx->opcode, 0, 7); + imm =3D (imm =3D=3D 0x7f ? -1 : imm); + if (rt !=3D 0) { + tcg_gen_movi_tl(cpu_gpr[rt], imm); + } + } + break; + case NM_ANDI16: + { + uint32_t u =3D extract32(ctx->opcode, 0, 4); + u =3D (u =3D=3D 12) ? 0xff : + (u =3D=3D 13) ? 0xffff : u; + gen_logic_imm(ctx, OPC_ANDI, rt, rs, u); + } + break; + case NM_P16_LB: + break; + case NM_P16_LH: + break; + case NM_LW16: + break; + case NM_LWSP16: + break; + case NM_LW4X4: + break; + case NM_SW4X4: + break; + case NM_LWGP16: + break; + case NM_SWSP16: + break; + case NM_SW16: + break; + case NM_SWGP16: + break; + case NM_BC16: + gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, + (sextract32(ctx->opcode, 0, 1) << 10) | + (extract32(ctx->opcode, 1, 9) << 1), + 0); + break; + case NM_BALC16: + gen_compute_branch(ctx, OPC_BGEZAL, 2, 0, 0, + (sextract32(ctx->opcode, 0, 1) << 10) | + (extract32(ctx->opcode, 1, 9) << 1), + 0); + break; + case NM_BEQZC16: + case NM_BNEZC16: + gen_compute_branch(ctx, op =3D=3D NM_BNEZC16 ? OPC_BNE : OPC_BEQ, = 2, + rt, 0, + (sextract32(ctx->opcode, 0, 1) << 7) | + (extract32(ctx->opcode, 1, 6) << 1), + 0); + break; + case NM_P16_BR: + switch (ctx->opcode & 0xf) { + case 0: + /* P16.JRC */ + switch ((ctx->opcode >> 4) & 1) { + case NM_JRC: + gen_compute_branch(ctx, OPC_JR, 2, + extract32(ctx->opcode, 5, 5), 0, 0, 0); + break; + case NM_JALRC16: + gen_compute_branch(ctx, OPC_JALR, 2, + extract32(ctx->opcode, 5, 5), 31, 0, 0); + break; + } + break; + default: + /* P16.BRI */ + if (extract32(ctx->opcode, 4, 3) < extract32(ctx->opcode, 7, 3= )) { + /* BEQC16 */ + gen_compute_branch(ctx, OPC_BEQ, 2, rs, rt, + extract32(ctx->opcode, 0, 4) << 1, 0); + } else { + /* BNEC16 */ + gen_compute_branch(ctx, OPC_BNE, 2, rs, rt, + extract32(ctx->opcode, 0, 4) << 1, 0); + } + break; + } + break; + case NM_P16_SR: + break; + case NM_MOVEP: + case NM_MOVEPREV: + { + static const int gpr2reg1[] =3D {4, 5, 6, 7}; + static const int gpr2reg2[] =3D {5, 6, 7, 8}; + int re; + int rd2 =3D extract32(ctx->opcode, 3, 1) << 1 | + extract32(ctx->opcode, 8, 1); + int r1 =3D gpr2reg1[rd2]; + int r2 =3D gpr2reg2[rd2]; + int r3 =3D extract32(ctx->opcode, 4, 1) << 3 | + extract32(ctx->opcode, 0, 3); + int r4 =3D extract32(ctx->opcode, 9, 1) << 3 | + extract32(ctx->opcode, 5, 3); + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + if (op =3D=3D NM_MOVEP) { + rd =3D r1; + re =3D r2; + rs =3D mmreg4z_nanomips(r3); + rt =3D mmreg4z_nanomips(r4); + } else { + rd =3D mmreg4_nanomips(r3); + re =3D mmreg4_nanomips(r4); + rs =3D r1; + rt =3D r2; + } + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + tcg_gen_mov_tl(cpu_gpr[rd], t0); + tcg_gen_mov_tl(cpu_gpr[re], t1); + tcg_temp_free(t0); + tcg_temp_free(t1); + } + break; + default: + break; + } + + return 2; +} + /* SmartMIPS extension to MIPS32 */ =20 #if defined(TARGET_MIPS64) @@ -20950,7 +21237,11 @@ static void mips_tr_translate_insn(DisasContextBas= e *dcbase, CPUState *cs) decode_opc(env, ctx); } else if (ctx->insn_flags & ASE_MICROMIPS) { ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); - insn_bytes =3D decode_micromips_opc(env, ctx); + if (env->insn_flags & ISA_NANOMIPS32) { + insn_bytes =3D decode_nanomips_opc(env, ctx); + } else { + insn_bytes =3D decode_micromips_opc(env, ctx); + } } else if (ctx->insn_flags & ASE_MIPS16) { ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); insn_bytes =3D decode_mips16_opc(env, ctx); --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529496919510433.53834168026845; Wed, 20 Jun 2018 05:15:19 -0700 (PDT) Received: from localhost ([::1]:49030 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVc18-0000dY-JB for importer@patchew.org; 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Wed, 20 Jun 2018 05:08:01 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:05:50 +0100 Message-ID: <20180620120620.12806-6-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496484-298553-23331-42495-1 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.150.224 Subject: [Qemu-devel] [PATCH 05/35] target/mips: Add nanoMIPS 16bit ld/st instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nanoMIPS 16bit load and store instructions Signed-off-by: Yongbok Kim --- target/mips/translate.c | 110 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 110 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 633d0b4..f5b7e14 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16207,6 +16207,14 @@ static int mmreg_nanomips(int r) return map[r & 0x7]; } =20 +/* Used for 16-bit store instructions. */ +static int mmreg2_nanomips(int r) +{ + static const int map[] =3D { 0, 17, 18, 19, 4, 5, 6, 7 }; + + return map[r & 0x7]; +} + static int mmreg4_nanomips(int r) { static const int map[] =3D { 8, 9, 10, 11, 4, 5, 6, 7, @@ -16292,6 +16300,13 @@ static int decode_nanomips_opc(CPUMIPSState *env, = DisasContext *ctx) } break; case NM_P16C: + switch (ctx->opcode & 1) { + case NM_POOL16C_0: + break; + case NM_LWXS16: + gen_ldxs(ctx, rt, rs, rd); + break; + } break; case NM_P16_A1: switch ((ctx->opcode >> 6) & 1) { @@ -16375,24 +16390,119 @@ static int decode_nanomips_opc(CPUMIPSState *env= , DisasContext *ctx) } break; case NM_P16_LB: + { + uint32_t u =3D extract32(ctx->opcode, 0, 2); + switch (((ctx->opcode) >> 2) & 0x03) { + case NM_LB16: + gen_ld(ctx, OPC_LB, rt, rs, u); + break; + case NM_SB16: + { + int rt =3D mmreg2_nanomips(uMIPS_RD(ctx->opcode)); + gen_st(ctx, OPC_SB, rt, rs, u); + } + break; + case NM_LBU16: + gen_ld(ctx, OPC_LBU, rt, rs, u); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } break; case NM_P16_LH: + { + uint32_t u =3D extract32(ctx->opcode, 1, 2) << 1; + switch ((((ctx->opcode >> 3) & 1) << 1) | (ctx->opcode & 1)) { + case NM_LH16: + gen_ld(ctx, OPC_LH, rt, rs, u); + break; + case NM_SH16: + { + int rt =3D mmreg2_nanomips(uMIPS_RD(ctx->opcode)); + gen_st(ctx, OPC_SH, rt, rs, u); + } + break; + case NM_LHU16: + gen_ld(ctx, OPC_LHU, rt, rs, u); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } break; case NM_LW16: + { + int u =3D extract32(ctx->opcode, 0, 4) << 2; + gen_ld(ctx, OPC_LW, rt, rs, u); + } break; case NM_LWSP16: + { + int rt =3D uMIPS_RD5(ctx->opcode); + int u =3D extract32(ctx->opcode, 0, 5) << 2; + + gen_ld(ctx, OPC_LW, rt, 29, u); + } break; case NM_LW4X4: + { + int rt =3D (extract32(ctx->opcode, 9, 1) << 3) | + extract32(ctx->opcode, 5, 3); + int rs =3D (extract32(ctx->opcode, 4, 1) << 3) | + extract32(ctx->opcode, 0, 3); + int u =3D (extract32(ctx->opcode, 3, 1) << 3) | + (extract32(ctx->opcode, 8, 1) << 2); + rt =3D mmreg4_nanomips(rt); + rs =3D mmreg4_nanomips(rs); + gen_ld(ctx, OPC_LW, rt, rs, u); + } break; case NM_SW4X4: + { + int rt =3D (extract32(ctx->opcode, 9, 1) << 3) | + extract32(ctx->opcode, 5, 3); + int rs =3D (extract32(ctx->opcode, 4, 1) << 3) | + extract32(ctx->opcode, 0, 3); + int u =3D (extract32(ctx->opcode, 3, 1) << 3) | + (extract32(ctx->opcode, 8, 1) << 2); + rt =3D mmreg4z_nanomips(rt); + rs =3D mmreg4_nanomips(rs); + gen_st(ctx, OPC_SW, rt, rs, u); + } break; case NM_LWGP16: + { + int u =3D extract32(ctx->opcode, 0, 7) << 2; + gen_ld(ctx, OPC_LW, rt, 28, u); + } break; case NM_SWSP16: + { + int rt =3D uMIPS_RD5(ctx->opcode); + int u =3D extract32(ctx->opcode, 0, 5) << 2; + + gen_st(ctx, OPC_SW, rt, 29, u); + } break; case NM_SW16: + { + int rt =3D mmreg2_nanomips(uMIPS_RD(ctx->opcode)); + int rs =3D mmreg_nanomips(uMIPS_RS(ctx->opcode)); + int u =3D extract32(ctx->opcode, 0, 4) << 2; + + gen_st(ctx, OPC_SW, rt, rs, u); + } break; case NM_SWGP16: + { + int rt =3D mmreg2_nanomips(uMIPS_RD(ctx->opcode)); + int u =3D extract32(ctx->opcode, 0, 7) << 2; + + gen_st(ctx, OPC_SW, rt, 28, u); + } break; case NM_BC16: gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497102636361.5870235488734; Wed, 20 Jun 2018 05:18:22 -0700 (PDT) Received: from localhost ([::1]:49050 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVc45-00032E-QO for importer@patchew.org; Wed, 20 Jun 2018 08:18:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35092) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbub-0003UR-Tp for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:08:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbua-000448-Bc for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:08:33 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.150.224]:54729) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbua-0003z5-5P for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:08:32 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx2.ess.sfj.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:08:16 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:08:04 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:05:51 +0100 Message-ID: <20180620120620.12806-7-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496484-298553-23331-42495-2 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.150.224 Subject: [Qemu-devel] [PATCH 06/35] target/mips: Add nanoMIPS pool16c instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nanoMIPS pool16c instructions Signed-off-by: Yongbok Kim Reviewed-by: Richard Henderson --- target/mips/translate.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index f5b7e14..c1a98da 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16232,6 +16232,27 @@ static int mmreg4z_nanomips(int r) return map[r & 0xf]; } =20 +static void gen_pool16c_nanomips_insn(DisasContext *ctx) +{ + int rt =3D mmreg_nanomips(uMIPS_RD(ctx->opcode)); + int rs =3D mmreg_nanomips(uMIPS_RS(ctx->opcode)); + + switch ((ctx->opcode >> 2) & 0x3) { + case NM_NOT16: + gen_logic(ctx, OPC_NOR, rt, rs, 0); + break; + case NM_AND16: + gen_logic(ctx, OPC_AND, rt, rt, rs); + break; + case NM_XOR16: + gen_logic(ctx, OPC_XOR, rt, rt, rs); + break; + case NM_OR16: + gen_logic(ctx, OPC_OR, rt, rt, rs); + break; + } +} + static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) { uint32_t op; @@ -16302,6 +16323,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, D= isasContext *ctx) case NM_P16C: switch (ctx->opcode & 1) { case NM_POOL16C_0: + gen_pool16c_nanomips_insn(ctx); break; case NM_LWXS16: gen_ldxs(ctx, rt, rs, rd); --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 152949689291884.08351359623725; Wed, 20 Jun 2018 05:14:52 -0700 (PDT) Received: from localhost ([::1]:49027 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVc0Z-0008Uo-AF for importer@patchew.org; Wed, 20 Jun 2018 08:14:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35106) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbum-0003c0-Lk for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:08:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbui-00047v-LQ for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:08:44 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.150.224]:33913) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbui-00046D-EO for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:08:40 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx2.ess.sfj.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:08:33 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:08:06 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:05:52 +0100 Message-ID: <20180620120620.12806-8-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496484-298553-23331-42495-3 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.150.224 Subject: [Qemu-devel] [PATCH 07/35] target/mips: Add nanoMIPS save and restore X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Matthew Fortune Add nanoMIPS save and restore instructions Signed-off-by: Yongbok Kim --- target/mips/translate.c | 74 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 74 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index c1a98da..4ce80bf 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16232,6 +16232,66 @@ static int mmreg4z_nanomips(int r) return map[r & 0xf]; } =20 +static void gen_adjust_sp(DisasContext *ctx, int u) +{ + TCGv tsp =3D tcg_temp_new(); + gen_base_offset_addr(ctx, tsp, 29, u); + gen_store_gpr(tsp, 29); + tcg_temp_free(tsp); +} + +static void gen_save(DisasContext *ctx, uint8_t rt, uint8_t count, + uint8_t gp, uint16_t u) +{ + int counter =3D 0; + TCGv va =3D tcg_temp_new(); + TCGv t0 =3D tcg_temp_new(); + /* fprintf(stderr, "save %d, %d, %d, %d\n", rt, count, gp, u); */ + + while (counter !=3D count) { + bool use_gp =3D gp && (counter =3D=3D count - 1); + int this_rt =3D use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f= ); + int this_offset =3D -((counter + 1) << 2); + gen_base_offset_addr(ctx, va, 29, this_offset); + gen_load_gpr(t0, this_rt); + tcg_gen_qemu_st_tl(t0, va, ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); + counter++; + } + + /* adjust stack pointer */ + gen_adjust_sp(ctx, -u); + + tcg_temp_free(t0); + tcg_temp_free(va); +} + +static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count, + uint8_t gp, uint16_t u) +{ + int counter =3D 0; + TCGv va =3D tcg_temp_new(); + TCGv t0 =3D tcg_temp_new(); + + while (counter !=3D count) { + bool use_gp =3D gp && (counter =3D=3D count - 1); + int this_rt =3D use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f= ); + int this_offset =3D u - ((counter + 1) << 2); + gen_base_offset_addr(ctx, va, 29, this_offset); + tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TESL | + ctx->default_tcg_memop_mask); + tcg_gen_ext32s_tl(t0, t0); + gen_store_gpr(t0, this_rt); + counter++; + } + + /* adjust stack pointer */ + gen_adjust_sp(ctx, u); + + tcg_temp_free(t0); + tcg_temp_free(va); +} + static void gen_pool16c_nanomips_insn(DisasContext *ctx) { int rt =3D mmreg_nanomips(uMIPS_RD(ctx->opcode)); @@ -16576,6 +16636,20 @@ static int decode_nanomips_opc(CPUMIPSState *env, = DisasContext *ctx) } break; case NM_P16_SR: + { + int count =3D extract32(ctx->opcode, 0, 4); + int u =3D extract32(ctx->opcode, 4, 4) << 4; + int rt =3D 30 + ((ctx->opcode >> 9) & 1); + switch ((ctx->opcode >> 8) & 1) { + case NM_SAVE16: + gen_save(ctx, rt, count, 0, u); + break; + case NM_RESTORE_JRC16: + gen_restore(ctx, rt, count, 0, u); + gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0); + break; + } + } break; case NM_MOVEP: case NM_MOVEPREV: --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497285685905.1209128962963; Wed, 20 Jun 2018 05:21:25 -0700 (PDT) Received: from localhost ([::1]:49067 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVc72-0005ax-Qg for importer@patchew.org; Wed, 20 Jun 2018 08:21:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35140) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbut-0003i9-Dh for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:08:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbur-0004ED-Rj for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:08:51 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.150.224]:34471) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbur-0004A7-Kn for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:08:49 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx2.ess.sfj.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:08:41 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:08:09 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:05:53 +0100 Message-ID: <20180620120620.12806-9-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496484-298553-23331-42495-4 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.150.224 Subject: [Qemu-devel] [PATCH 08/35] target/mips: Add nanoMIPS 32bit instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nanoMIPS 32bit instructions Signed-off-by: Yongbok Kim --- target/mips/translate.c | 285 ++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 284 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 4ce80bf..c9b46dd 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16313,6 +16313,289 @@ static void gen_pool16c_nanomips_insn(DisasContex= t *ctx) } } =20 +static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) +{ + uint16_t insn; + int rt, rs; + uint32_t op; + + insn =3D cpu_lduw_code(env, ctx->base.pc_next + 2); + ctx->opcode =3D (ctx->opcode << 16) | insn; + + rt =3D (ctx->opcode >> 21) & 0x1f; + rs =3D (ctx->opcode >> 16) & 0x1f; + + op =3D (ctx->opcode >> 26) & 0x3f; + switch (op) { + case NM_P_ADDIU: + if (rt =3D=3D 0) { + /* P.RI */ + switch ((ctx->opcode >> 19) & 0x03) { + case NM_SIGRIE: + default: + generate_exception_end(ctx, EXCP_RI); + break; + case NM_P_SYSCALL: + if (((ctx->opcode >> 18) & 0x01) =3D=3D NM_SYSCALL) { + generate_exception_end(ctx, EXCP_SYSCALL); + } else { + generate_exception_end(ctx, EXCP_RI); + } + break; + case NM_BREAK: + generate_exception_end(ctx, EXCP_BREAK); + break; + case NM_SDBBP: + if (is_uhi(extract32(ctx->opcode, 0, 19))) { + gen_helper_do_semihosting(cpu_env); + } else { + if (ctx->hflags & MIPS_HFLAG_SBRI) { + generate_exception_end(ctx, EXCP_RI); + } else { + generate_exception_end(ctx, EXCP_DBp); + } + } + break; + } + } else { + uint16_t imm; + imm =3D (uint16_t) extract32(ctx->opcode, 0, 16); + if (rs !=3D 0) { + tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } else { + tcg_gen_movi_tl(cpu_gpr[rt], imm); + } + } + break; + case NM_ADDIUPC: + if (rt !=3D 0) { + int32_t offset =3D sextract32(ctx->opcode, 0, 1) << 21 + | extract32(ctx->opcode, 1, 20) << 1; + target_long addr =3D addr_add(ctx, ctx->base.pc_next + 4, offs= et); + tcg_gen_movi_tl(cpu_gpr[rt], addr); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } + break; + case NM_POOL32A: + break; + case NM_P_GP_W: + switch (ctx->opcode & 0x03) { + case NM_ADDIUGP_W: + if (rt !=3D 0) { + uint32_t offset =3D extract32(ctx->opcode, 0, 21); + if (offset =3D=3D 0) { + gen_load_gpr(cpu_gpr[rt], 28); + } else { + TCGv t0; + t0 =3D tcg_temp_new(); + tcg_gen_movi_tl(t0, offset); + gen_op_addr_add(ctx, cpu_gpr[rt], cpu_gpr[28], t0); + tcg_temp_free(t0); + } + } + break; + case NM_LWGP: + gen_ld(ctx, OPC_LW, rt, 28, extract32(ctx->opcode, 2, 19) << 2= ); + break; + case NM_SWGP: + gen_st(ctx, OPC_SW, rt, 28, extract32(ctx->opcode, 2, 19) << 2= ); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_P48I: + return 6; + case NM_P_U12: + switch ((ctx->opcode >> 12) & 0x0f) { + case NM_ORI: + gen_logic_imm(ctx, OPC_ORI, rt, rs, extract32(ctx->opcode, 0, = 12)); + break; + case NM_XORI: + gen_logic_imm(ctx, OPC_XORI, rt, rs, extract32(ctx->opcode, 0,= 12)); + break; + case NM_ANDI: + gen_logic_imm(ctx, OPC_ANDI, rt, rs, extract32(ctx->opcode, 0,= 12)); + break; + case NM_P_SR: + switch ((ctx->opcode >> 20) & 1) { + case NM_PP_SR: + switch (ctx->opcode & 3) { + case NM_SAVE: + gen_save(ctx, rt, extract32(ctx->opcode, 16, 4), + (ctx->opcode >> 2) & 1, + extract32(ctx->opcode, 3, 9) << 3); + break; + case NM_RESTORE: + case NM_RESTORE_JRC: + gen_restore(ctx, rt, extract32(ctx->opcode, 16, 4), + (ctx->opcode >> 2) & 1, + extract32(ctx->opcode, 3, 9) << 3); + if ((ctx->opcode & 3) =3D=3D NM_RESTORE_JRC) { + gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0); + } + break; + } + break; + case NM_P_SR_F: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_SLTI: + gen_slt_imm(ctx, OPC_SLTI, rt, rs, extract32(ctx->opcode, 0, 1= 2)); + break; + case NM_SLTIU: + gen_slt_imm(ctx, OPC_SLTIU, rt, rs, extract32(ctx->opcode, 0, = 12)); + break; + case NM_SEQI: + { + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv t2 =3D tcg_temp_local_new(); + TCGLabel *l1 =3D gen_new_label(); + + gen_load_gpr(t0, rs); + tcg_gen_movi_tl(t1, extract32(ctx->opcode, 0, 12)); + tcg_gen_movi_tl(t2, 0); + tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1); + tcg_gen_movi_tl(t2, 1); + gen_set_label(l1); + gen_store_gpr(t2, rt); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + } + break; + case NM_ADDIUNEG: + { + int16_t imm; + imm =3D (int16_t) extract32(ctx->opcode, 0, 12); + gen_arith_imm(ctx, OPC_ADDIU, rt, rs, -imm); + } + break; + case NM_P_SHIFT: + { + int shift =3D extract32(ctx->opcode, 0, 5); + switch ((ctx->opcode >> 5) & 0x0f) { + case NM_P_SLL: + if (rt =3D=3D 0 && shift =3D=3D 0) { + /* NOP */ + } else if (rt =3D=3D 0 && shift =3D=3D 3) { + /* EHB treat as NOP */ + } else if (rt =3D=3D 0 && shift =3D=3D 5) { + /* PAUSE */ + if (ctx->hflags & MIPS_HFLAG_BMASK) { + generate_exception_end(ctx, EXCP_RI); + } + } else if (rt =3D=3D 0 && shift =3D=3D 6) { + /* SYNC */ + check_insn(ctx, ISA_MIPS2); + /* Treat as NOP. */ + } else { + /* SLL */ + gen_shift_imm(ctx, OPC_SLL, rt, rs, + extract32(ctx->opcode, 0, 5)); + } + break; + case NM_SRL: + gen_shift_imm(ctx, OPC_SRL, rt, rs, + extract32(ctx->opcode, 0, 5)); + break; + case NM_SRA: + gen_shift_imm(ctx, OPC_SRA, rt, rs, + extract32(ctx->opcode, 0, 5)); + break; + case NM_ROTR: + gen_shift_imm(ctx, OPC_ROTR, rt, rs, + extract32(ctx->opcode, 0, 5)); + break; + } + } + break; + case NM_P_ROTX: + break; + case NM_P_INS: + switch (((ctx->opcode >> 10) & 2) | ((ctx->opcode >> 5) & 1)) { + case NM_INS: + gen_bitops(ctx, OPC_INS, rt, rs, extract32(ctx->opcode, 0,= 5), + extract32(ctx->opcode, 6, 5)); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_P_EXT: + switch (((ctx->opcode >> 10) & 2) | ((ctx->opcode >> 5) & 1)) { + case NM_EXT: + gen_bitops(ctx, OPC_EXT, rt, rs, extract32(ctx->opcode, 0,= 5), + extract32(ctx->opcode, 6, 5)); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_POOL32F: + break; + case NM_POOL32S: + break; + case NM_P_LUI: + switch ((ctx->opcode >> 1) & 1) { + case NM_LUI: + if (rt !=3D 0) { + tcg_gen_movi_tl(cpu_gpr[rt], + sextract32(ctx->opcode, 0, 1) << 31 | + extract32(ctx->opcode, 2, 10) << 21 | + extract32(ctx->opcode, 12, 9) << 12); + } + break; + case NM_ALUIPC: + if (rt !=3D 0) { + int offset =3D sextract32(ctx->opcode, 0, 1) << 31 | + extract32(ctx->opcode, 2, 10) << 21 | + extract32(ctx->opcode, 12, 9) << 12; + target_long addr; + addr =3D ~0xFFF & addr_add(ctx, ctx->base.pc_next + 4, off= set); + tcg_gen_movi_tl(cpu_gpr[rt], addr); + } + break; + } + break; + case NM_P_GP_BH: + break; + case NM_P_LS_U12: + break; + case NM_P_LS_S9: + break; + case NM_MOVE_BALC: + break; + case NM_P_BAL: + break; + case NM_P_J: + break; + case NM_P_BR1: + break; + case NM_P_BR2: + break; + case NM_P_BRI: + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + return 4; +} + static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) { uint32_t op; @@ -16687,7 +16970,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, D= isasContext *ctx) } break; default: - break; + return decode_nanomips_32_48_opc(env, ctx); } =20 return 2; --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529496669003647.770241315188; Wed, 20 Jun 2018 05:11:09 -0700 (PDT) Received: from localhost ([::1]:49010 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbx6-0005TW-7U for importer@patchew.org; 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Wed, 20 Jun 2018 05:08:11 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:05:54 +0100 Message-ID: <20180620120620.12806-10-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496484-298553-23331-42495-5 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.150.224 Subject: [Qemu-devel] [PATCH 09/35] target/mips: Add nanoMIPS 48bit instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nanoMIPS 48bit instructions Signed-off-by: Yongbok Kim --- target/mips/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 66 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index c9b46dd..f3a8845 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16407,6 +16407,72 @@ static int decode_nanomips_32_48_opc(CPUMIPSState = *env, DisasContext *ctx) } break; case NM_P48I: + insn =3D cpu_lduw_code(env, ctx->base.pc_next + 4); + switch ((ctx->opcode >> 16) & 0x1f) { + case NM_LI48: + if (rt !=3D 0) { + tcg_gen_movi_tl(cpu_gpr[rt], + extract32(ctx->opcode, 0, 16) | insn << 16= ); + } + break; + case NM_ADDIU48: + if (rt !=3D 0) { + tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rt], + extract32(ctx->opcode, 0, 16) | insn << 16= ); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } + break; + case NM_ADDIUGP48: + if (rt !=3D 0) { + tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[28], + extract32(ctx->opcode, 0, 16) | insn << 16= ); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } + break; + case NM_ADDIUPC48: + if (rt !=3D 0) { + int32_t offset =3D extract32(ctx->opcode, 0, 16) | insn <<= 16; + target_long addr =3D addr_add(ctx, ctx->base.pc_next + 6, = offset); + + tcg_gen_movi_tl(cpu_gpr[rt], addr); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } + break; + case NM_LWPC48: + if (rt !=3D 0) { + TCGv t0; + t0 =3D tcg_temp_new(); + + int32_t offset =3D extract32(ctx->opcode, 0, 16) | insn <<= 16; + target_long addr =3D addr_add(ctx, ctx->base.pc_next + 6, = offset); + + tcg_gen_movi_tl(t0, addr); + tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_TESL); + tcg_temp_free(t0); + } + break; + case NM_SWPC48: + { + TCGv t0, t1; + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + + int32_t offset =3D extract32(ctx->opcode, 0, 16) | insn << 16; + target_long addr =3D addr_add(ctx, ctx->base.pc_next + 6, offs= et); + + tcg_gen_movi_tl(t0, addr); + gen_load_gpr(t1, rt); + + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); + + tcg_temp_free(t0); + tcg_temp_free(t1); + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } return 6; case NM_P_U12: switch ((ctx->opcode >> 12) & 0x0f) { --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497111488930.6221200300773; Wed, 20 Jun 2018 05:18:31 -0700 (PDT) Received: from localhost ([::1]:49051 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVc4E-00037B-JH for importer@patchew.org; Wed, 20 Jun 2018 08:18:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35366) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbve-0004kC-0S for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:09:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbvZ-0004Xx-Uh for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:09:37 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.154.211]:37147) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbvZ-0004Ra-M8 for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:09:33 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx1413.ess.rzc.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:09:23 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:09:20 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:05:55 +0100 Message-ID: <20180620120620.12806-11-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496563-531715-22533-46370-1 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.211 Subject: [Qemu-devel] [PATCH 10/35] target/mips: Add nanoMIPS pool32f instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nanoMIPS pool32f floating point instructions. Signed-off-by: Yongbok Kim --- target/mips/translate.c | 300 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 300 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index f3a8845..0175a57 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16313,6 +16313,305 @@ static void gen_pool16c_nanomips_insn(DisasContex= t *ctx) } } =20 +static void gen_pool32f_nanomips_insn(DisasContext *ctx) +{ + int rt, rs, rd; + + rt =3D (ctx->opcode >> 21) & 0x1f; + rs =3D (ctx->opcode >> 16) & 0x1f; + rd =3D (ctx->opcode >> 11) & 0x1f; + + if (!(ctx->CP0_Config1 & (1 << CP0C1_FP))) { + generate_exception_end(ctx, EXCP_RI); + return; + } + check_cp1_enabled(ctx); + switch (ctx->opcode & 0x07) { + case NM_POOL32F_0: + switch ((ctx->opcode >> 3) & 0x7f) { + case NM_RINT_S: + gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0); + break; + case NM_RINT_D: + gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0); + break; + case NM_CLASS_S: + gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0); + break; + case NM_CLASS_D: + gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0); + break; + case NM_ADD_S: + gen_farith(ctx, OPC_ADD_S, rt, rs, rd, 0); + break; + case NM_ADD_D: + gen_farith(ctx, OPC_ADD_D, rt, rs, rd, 0); + break; + case NM_SUB_S: + gen_farith(ctx, OPC_SUB_S, rt, rs, rd, 0); + break; + case NM_SUB_D: + gen_farith(ctx, OPC_SUB_D, rt, rs, rd, 0); + break; + case NM_MUL_S: + gen_farith(ctx, OPC_MUL_S, rt, rs, rd, 0); + break; + case NM_MUL_D: + gen_farith(ctx, OPC_MUL_D, rt, rs, rd, 0); + break; + case NM_DIV_S: + gen_farith(ctx, OPC_DIV_S, rt, rs, rd, 0); + break; + case NM_DIV_D: + gen_farith(ctx, OPC_DIV_D, rt, rs, rd, 0); + break; + case NM_SELEQZ_S: + gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs); + break; + case NM_SELEQZ_D: + gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs); + break; + case NM_SELNEZ_S: + gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs); + break; + case NM_SELNEZ_D: + gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs); + break; + case NM_SEL_S: + gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs); + break; + case NM_SEL_D: + gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs); + break; + case NM_MADDF_S: + gen_farith(ctx, OPC_MADDF_S, rt, rs, rd, 0); + break; + case NM_MADDF_D: + gen_farith(ctx, OPC_MADDF_D, rt, rs, rd, 0); + break; + case NM_MSUBF_S: + gen_farith(ctx, OPC_MSUBF_S, rt, rs, rd, 0); + break; + case NM_MSUBF_D: + gen_farith(ctx, OPC_MSUBF_D, rt, rs, rd, 0); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_POOL32F_3: + switch ((ctx->opcode >> 3) & 0x07) { + case NM_MIN_FMT: + switch ((ctx->opcode >> 9) & 1) { + case FMT_SDPS_S: + gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0); + break; + case FMT_SDPS_D: + gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0); + break; + } + break; + case NM_MAX_FMT: + switch ((ctx->opcode >> 9) & 1) { + case FMT_SDPS_S: + gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0); + break; + case FMT_SDPS_D: + gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0); + break; + } + break; + case NM_MINA_FMT: + switch ((ctx->opcode >> 9) & 1) { + case FMT_SDPS_S: + gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0); + break; + case FMT_SDPS_D: + gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0); + break; + } + break; + case NM_MAXA_FMT: + switch ((ctx->opcode >> 9) & 1) { + case FMT_SDPS_S: + gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0); + break; + case FMT_SDPS_D: + gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0); + break; + } + break; + case NM_POOL32FXF: + switch ((ctx->opcode >> 6) & 0xff) { + case NM_CFC1: + gen_cp1(ctx, OPC_CFC1, rt, rs); + break; + case NM_CTC1: + gen_cp1(ctx, OPC_CTC1, rt, rs); + break; + case NM_MFC1: + gen_cp1(ctx, OPC_MFC1, rt, rs); + break; + case NM_MTC1: + gen_cp1(ctx, OPC_MTC1, rt, rs); + break; + case NM_MFHC1: + gen_cp1(ctx, OPC_MFHC1, rt, rs); + break; + case NM_MTHC1: + gen_cp1(ctx, OPC_MTHC1, rt, rs); + break; + case NM_CVT_S_PL: + gen_farith(ctx, OPC_CVT_S_PL, -1, rs, rt, 0); + break; + case NM_CVT_S_PU: + gen_farith(ctx, OPC_CVT_S_PU, -1, rs, rt, 0); + break; + default: + switch ((ctx->opcode >> 6) & 0x1ff) { + case NM_CVT_L_S: + gen_farith(ctx, OPC_CVT_L_S, -1, rs, rt, 0); + break; + case NM_CVT_L_D: + gen_farith(ctx, OPC_CVT_L_D, -1, rs, rt, 0); + break; + case NM_CVT_W_S: + gen_farith(ctx, OPC_CVT_W_S, -1, rs, rt, 0); + break; + case NM_CVT_W_D: + gen_farith(ctx, OPC_CVT_W_D, -1, rs, rt, 0); + break; + case NM_RSQRT_S: + gen_farith(ctx, OPC_RSQRT_S, -1, rs, rt, 0); + break; + case NM_RSQRT_D: + gen_farith(ctx, OPC_RSQRT_D, -1, rs, rt, 0); + break; + case NM_SQRT_S: + gen_farith(ctx, OPC_SQRT_S, -1, rs, rt, 0); + break; + case NM_SQRT_D: + gen_farith(ctx, OPC_SQRT_D, -1, rs, rt, 0); + break; + case NM_RECIP_S: + gen_farith(ctx, OPC_RECIP_S, -1, rs, rt, 0); + break; + case NM_RECIP_D: + gen_farith(ctx, OPC_RECIP_D, -1, rs, rt, 0); + break; + case NM_FLOOR_L_S: + gen_farith(ctx, OPC_FLOOR_L_S, -1, rs, rt, 0); + break; + case NM_FLOOR_L_D: + gen_farith(ctx, OPC_FLOOR_L_D, -1, rs, rt, 0); + break; + case NM_FLOOR_W_S: + gen_farith(ctx, OPC_FLOOR_W_S, -1, rs, rt, 0); + break; + case NM_FLOOR_W_D: + gen_farith(ctx, OPC_FLOOR_W_D, -1, rs, rt, 0); + break; + case NM_CEIL_L_S: + gen_farith(ctx, OPC_CEIL_L_S, -1, rs, rt, 0); + break; + case NM_CEIL_L_D: + gen_farith(ctx, OPC_CEIL_L_D, -1, rs, rt, 0); + break; + case NM_CEIL_W_S: + gen_farith(ctx, OPC_CEIL_W_S, -1, rs, rt, 0); + break; + case NM_CEIL_W_D: + gen_farith(ctx, OPC_CEIL_W_D, -1, rs, rt, 0); + break; + case NM_TRUNC_L_S: + gen_farith(ctx, OPC_TRUNC_L_S, -1, rs, rt, 0); + break; + case NM_TRUNC_L_D: + gen_farith(ctx, OPC_TRUNC_L_D, -1, rs, rt, 0); + break; + case NM_TRUNC_W_S: + gen_farith(ctx, OPC_TRUNC_W_S, -1, rs, rt, 0); + break; + case NM_TRUNC_W_D: + gen_farith(ctx, OPC_TRUNC_W_D, -1, rs, rt, 0); + break; + case NM_ROUND_L_S: + gen_farith(ctx, OPC_ROUND_L_S, -1, rs, rt, 0); + break; + case NM_ROUND_L_D: + gen_farith(ctx, OPC_ROUND_L_D, -1, rs, rt, 0); + break; + case NM_ROUND_W_S: + gen_farith(ctx, OPC_ROUND_W_S, -1, rs, rt, 0); + break; + case NM_ROUND_W_D: + gen_farith(ctx, OPC_ROUND_W_D, -1, rs, rt, 0); + break; + case NM_MOV_S: + gen_farith(ctx, OPC_MOV_S, -1, rs, rt, 0); + break; + case NM_MOV_D: + gen_farith(ctx, OPC_MOV_D, -1, rs, rt, 0); + break; + case NM_ABS_S: + gen_farith(ctx, OPC_ABS_S, -1, rs, rt, 0); + break; + case NM_ABS_D: + gen_farith(ctx, OPC_ABS_D, -1, rs, rt, 0); + break; + case NM_NEG_S: + gen_farith(ctx, OPC_NEG_S, -1, rs, rt, 0); + break; + case NM_NEG_D: + gen_farith(ctx, OPC_NEG_D, -1, rs, rt, 0); + break; + case NM_CVT_D_S: + gen_farith(ctx, OPC_CVT_D_S, -1, rs, rt, 0); + break; + case NM_CVT_D_W: + gen_farith(ctx, OPC_CVT_D_W, -1, rs, rt, 0); + break; + case NM_CVT_D_L: + gen_farith(ctx, OPC_CVT_D_L, -1, rs, rt, 0); + break; + case NM_CVT_S_D: + gen_farith(ctx, OPC_CVT_S_D, -1, rs, rt, 0); + break; + case NM_CVT_S_W: + gen_farith(ctx, OPC_CVT_S_W, -1, rs, rt, 0); + break; + case NM_CVT_S_L: + gen_farith(ctx, OPC_CVT_S_L, -1, rs, rt, 0); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + } + break; + } + break; + case NM_POOL32F_5: + switch ((ctx->opcode >> 3) & 0x07) { + case NM_CMP_CONDN_S: + gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd); + break; + case NM_CMP_CONDN_D: + gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } +} + static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) { uint16_t insn; @@ -16612,6 +16911,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case NM_POOL32F: + gen_pool32f_nanomips_insn(ctx); break; case NM_POOL32S: break; --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497456370906.817945226561; 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Wed, 20 Jun 2018 05:09:24 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:05:56 +0100 Message-ID: <20180620120620.12806-12-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496563-531715-22533-46370-2 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.211 Subject: [Qemu-devel] [PATCH 11/35] target/mips: Add nanoMIPS pool32a0 instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nanoMIPS pool32a0 instructions Signed-off-by: Yongbok Kim --- target/mips/translate.c | 190 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 190 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 0175a57..0c261c7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16313,6 +16313,186 @@ static void gen_pool16c_nanomips_insn(DisasContex= t *ctx) } } =20 +static void gen_pool32a0_nanomips_insn(DisasContext *ctx) +{ + int rt =3D (ctx->opcode >> 21) & 0x1f; + int rs =3D (ctx->opcode >> 16) & 0x1f; + int rd =3D (ctx->opcode >> 11) & 0x1f; + + switch ((ctx->opcode >> 3) & 0x7f) { + case NM_P_TRAP: + switch ((ctx->opcode >> 10) & 0x1) { + case NM_TEQ: + gen_trap(ctx, OPC_TEQ, rs, rt, -1); + break; + case NM_TNE: + gen_trap(ctx, OPC_TNE, rs, rt, -1); + break; + } + break; + case NM_RDHWR: + gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3)); + break; + case NM_SEB: + gen_bshfl(ctx, OPC_SEB, rs, rt); + break; + case NM_SEH: + gen_bshfl(ctx, OPC_SEH, rs, rt); + break; + case NM_SLLV: + gen_shift(ctx, OPC_SLLV, rd, rt, rs); + break; + case NM_SRLV: + gen_shift(ctx, OPC_SRLV, rd, rt, rs); + break; + case NM_SRAV: + gen_shift(ctx, OPC_SRAV, rd, rt, rs); + break; + case NM_ROTRV: + gen_shift(ctx, OPC_ROTRV, rd, rt, rs); + break; + case NM_ADD: + gen_arith(ctx, OPC_ADD, rd, rs, rt); + break; + case NM_ADDU: + gen_arith(ctx, OPC_ADDU, rd, rs, rt); + break; + case NM_SUB: + gen_arith(ctx, OPC_SUB, rd, rs, rt); + break; + case NM_SUBU: + gen_arith(ctx, OPC_SUBU, rd, rs, rt); + break; + case NM_P_CMOVE: + switch ((ctx->opcode >> 10) & 1) { + case NM_MOVZ: + gen_cond_move(ctx, OPC_MOVZ, rd, rs, rt); + break; + case NM_MOVN: + gen_cond_move(ctx, OPC_MOVN, rd, rs, rt); + break; + } + break; + case NM_AND: + gen_logic(ctx, OPC_AND, rd, rs, rt); + break; + case NM_OR: + gen_logic(ctx, OPC_OR, rd, rs, rt); + break; + case NM_NOR: + gen_logic(ctx, OPC_NOR, rd, rs, rt); + break; + case NM_XOR: + gen_logic(ctx, OPC_XOR, rd, rs, rt); + break; + case NM_SLT: + gen_slt(ctx, OPC_SLT, rd, rs, rt); + break; + case NM_P_SLTU: + if (rd =3D=3D 0) { + /* P_DVP */ +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + switch ((ctx->opcode >> 10) & 1) { + case NM_DVP: + if (ctx->vp) { + check_cp0_enabled(ctx); + gen_helper_dvp(t0, cpu_env); + gen_store_gpr(t0, rt); + } + break; + case NM_EVP: + if (ctx->vp) { + check_cp0_enabled(ctx); + gen_helper_evp(t0, cpu_env); + gen_store_gpr(t0, rt); + } + break; + } + tcg_temp_free(t0); +#endif + } else { + gen_slt(ctx, OPC_SLTU, rd, rs, rt); + } + break; + case NM_SOV: + { + TCGv t0 =3D tcg_temp_local_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv t2 =3D tcg_temp_new(); + TCGLabel *l1 =3D gen_new_label(); + + gen_load_gpr(t1, rs); + gen_load_gpr(t2, rt); + tcg_gen_add_tl(t0, t1, t2); + tcg_gen_ext32s_tl(t0, t0); + tcg_gen_xor_tl(t1, t1, t2); + tcg_gen_xor_tl(t2, t0, t2); + tcg_gen_andc_tl(t1, t2, t1); + + tcg_gen_movi_tl(t0, 0); + tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); + /* operands of same sign, result different sign */ + + tcg_gen_movi_tl(t0, 1); + gen_set_label(l1); + gen_store_gpr(t0, rd); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + } + break; + case NM_MUL: + gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt); + break; + case NM_MUH: + gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt); + break; + case NM_MULU: + gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt); + break; + case NM_MUHU: + gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt); + break; + case NM_DIV: + gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt); + break; + case NM_MOD: + gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt); + break; + case NM_DIVU: + gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt); + break; + case NM_MODU: + gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt); + break; +#ifndef CONFIG_USER_ONLY + case NM_MFC0: + check_cp0_enabled(ctx); + if (rt =3D=3D 0) { + /* Treat as NOP. */ + break; + } + gen_mfc0(ctx, cpu_gpr[rt], rs, (ctx->opcode >> 11) & 0x7); + break; + case NM_MTC0: + check_cp0_enabled(ctx); + { + TCGv t0 =3D tcg_temp_new(); + + gen_load_gpr(t0, rt); + gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7); + tcg_temp_free(t0); + } + break; +#endif + default: + generate_exception_end(ctx, EXCP_RI); + break; + } +} + static void gen_pool32f_nanomips_insn(DisasContext *ctx) { int rt, rs, rd; @@ -16677,6 +16857,16 @@ static int decode_nanomips_32_48_opc(CPUMIPSState = *env, DisasContext *ctx) } break; case NM_POOL32A: + switch (ctx->opcode & 0x07) { + case NM_POOL32A0: + gen_pool32a0_nanomips_insn(ctx); + break; + case NM_POOL32A7: + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } break; case NM_P_GP_W: switch (ctx->opcode & 0x03) { --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152949673322342.214086609384594; Wed, 20 Jun 2018 05:12:13 -0700 (PDT) Received: from localhost ([::1]:49013 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVby8-0006On-EI for importer@patchew.org; Wed, 20 Jun 2018 08:12:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35467) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbvz-00051G-LW for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:10:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbvv-0004lE-MG for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:09:59 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.154.211]:60207) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbvv-0004gG-C8 for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:09:55 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx1413.ess.rzc.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:09:47 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:09:26 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:05:57 +0100 Message-ID: <20180620120620.12806-13-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496563-531715-22533-46370-3 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.211 Subject: [Qemu-devel] [PATCH 12/35] target/mips: Add nanoMIPS pool32axf instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nanoMIPS pool32axf instructions Signed-off-by: Yongbok Kim --- target/mips/translate.c | 94 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 94 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 0c261c7..60d9287 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16493,6 +16493,93 @@ static void gen_pool32a0_nanomips_insn(DisasContex= t *ctx) } } =20 +static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *c= tx) +{ + int rt =3D (ctx->opcode >> 21) & 0x1f; + int rs =3D (ctx->opcode >> 16) & 0x1f; + + switch ((ctx->opcode >> 6) & 0x07) { + case NM_POOL32AXF_4: + case NM_POOL32AXF_5: + switch ((ctx->opcode >> 9) & 0x7f) { + case NM_CLO: + gen_cl(ctx, OPC_CLO, rt, rs); + break; + case NM_CLZ: + gen_cl(ctx, OPC_CLZ, rt, rs); + break; +#ifndef CONFIG_USER_ONLY + case NM_TLBP: + gen_cp0(env, ctx, OPC_TLBP, 0, 0); + break; + case NM_TLBR: + gen_cp0(env, ctx, OPC_TLBR, 0, 0); + break; + case NM_TLBWI: + gen_cp0(env, ctx, OPC_TLBWI, 0, 0); + break; + case NM_TLBWR: + gen_cp0(env, ctx, OPC_TLBWR, 0, 0); + break; + case NM_TLBINV: + gen_cp0(env, ctx, OPC_TLBINV, 0, 0); + break; + case NM_TLBINVF: + gen_cp0(env, ctx, OPC_TLBINVF, 0, 0); + break; + case NM_DI: + check_cp0_enabled(ctx); + { + TCGv t0 =3D tcg_temp_new(); + + save_cpu_state(ctx, 1); + gen_helper_di(t0, cpu_env); + gen_store_gpr(t0, rt); + /* Stop translation as we may have switched the execution mode= */ + ctx->base.is_jmp =3D DISAS_STOP; + tcg_temp_free(t0); + } + break; + case NM_EI: + check_cp0_enabled(ctx); + { + TCGv t0 =3D tcg_temp_new(); + + save_cpu_state(ctx, 1); + gen_helper_ei(t0, cpu_env); + gen_store_gpr(t0, rt); + /* Stop translation as we may have switched the execution mode= */ + ctx->base.is_jmp =3D DISAS_STOP; + tcg_temp_free(t0); + } + break; + case NM_RDPGPR: + gen_load_srsgpr(rs, rt); + break; + case NM_WRPGPR: + gen_store_srsgpr(rs, rt); + break; + case NM_WAIT: + gen_cp0(env, ctx, OPC_WAIT, 0, 0); + break; + case NM_DERET: + gen_cp0(env, ctx, OPC_DERET, 0, 0); + break; + case NM_ERETX: + gen_cp0(env, ctx, OPC_ERET, 0, 0); + break; +#endif + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } +} + static void gen_pool32f_nanomips_insn(DisasContext *ctx) { int rt, rs, rd; @@ -16862,6 +16949,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState = *env, DisasContext *ctx) gen_pool32a0_nanomips_insn(ctx); break; case NM_POOL32A7: + { + switch ((ctx->opcode >> 3) & 0x07) { + case NM_POOL32AXF: + gen_pool32axf_nanomips_insn(env, ctx); + break; + } + } break; default: generate_exception_end(ctx, EXCP_RI); --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497295117597.6062361666798; Wed, 20 Jun 2018 05:21:35 -0700 (PDT) Received: from localhost ([::1]:49068 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVc77-0005gQ-EE for importer@patchew.org; Wed, 20 Jun 2018 08:21:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35505) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbw9-00059t-VM for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:10:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbw5-0004tt-VS for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:10:09 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.154.211]:56595) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbw5-0004m8-MW for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:10:05 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx1413.ess.rzc.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:09:57 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:09:29 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:05:58 +0100 Message-ID: <20180620120620.12806-14-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496563-531715-22533-46370-4 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.211 Subject: [Qemu-devel] [PATCH 13/35] target/mips: Update gen_flt_ldst() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update gen_flt_ldst() in order to reuse the functions for nanoMIPS Signed-off-by: Yongbok Kim Reviewed-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 60d9287..a581330 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2433,11 +2433,8 @@ static void gen_st_cond (DisasContext *ctx, uint32_t= opc, int rt, =20 /* Load and store */ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, - int base, int16_t offset) + TCGv t0) { - TCGv t0 =3D tcg_temp_new(); - - gen_base_offset_addr(ctx, t0, base, offset); /* Don't do NOP if destination is zero: we must perform the actual memory access. */ switch (opc) { @@ -2480,15 +2477,15 @@ static void gen_flt_ldst (DisasContext *ctx, uint32= _t opc, int ft, default: MIPS_INVAL("flt_ldst"); generate_exception_end(ctx, EXCP_RI); - goto out; + break; } - out: - tcg_temp_free(t0); } =20 static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt, int rs, int16_t imm) { + TCGv t0 =3D tcg_temp_new(); + if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); switch (op) { @@ -2497,11 +2494,13 @@ static void gen_cop1_ldst(DisasContext *ctx, uint32= _t op, int rt, check_insn(ctx, ISA_MIPS2); /* Fallthrough */ default: - gen_flt_ldst(ctx, op, rt, rs, imm); + gen_base_offset_addr(ctx, t0, rs, imm); + gen_flt_ldst(ctx, op, rt, t0); } } else { generate_exception_err(ctx, EXCP_CpU, 1); } + tcg_temp_free(t0); } =20 /* Arithmetic with immediate operand */ --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497461239834.0982359389652; Wed, 20 Jun 2018 05:24:21 -0700 (PDT) Received: from localhost ([::1]:49082 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVc9s-0008Eb-Er for importer@patchew.org; Wed, 20 Jun 2018 08:24:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35561) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbwN-0005LA-DD for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:10:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbwH-00056a-3V for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:10:23 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.154.211]:47081) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbwG-0004xD-KG for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:10:16 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx1413.ess.rzc.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:10:07 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:09:32 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:05:59 +0100 Message-ID: <20180620120620.12806-15-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496563-531715-22533-46370-5 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.211 Subject: [Qemu-devel] [PATCH 14/35] target/mips: Add nanoMIPS p_lsx instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nanoMIPS p_lsx and LSA instructions Signed-off-by: Yongbok Kim --- target/mips/translate.c | 139 ++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 138 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index a581330..819cfd9 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16579,6 +16579,132 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSSt= ate *env, DisasContext *ctx) } } =20 + +static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt) +{ + TCGv t0, t1; + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + tcg_gen_movi_tl(t1, 0); + if (rs =3D=3D 0) { + tcg_gen_movi_tl(t0, 0); + } else { + gen_load_gpr(t0, rs); + } + if (rt =3D=3D 0) { + tcg_gen_movi_tl(t1, 0); + } else { + gen_load_gpr(t1, rt); + } + if (((ctx->opcode >> 6) & 1) =3D=3D 1) { + /* PP.LSXS instructions require shifting */ + switch ((ctx->opcode >> 7) & 0xf) { + case NM_LHXS: + case NM_SHXS: + case NM_LHUXS: + tcg_gen_shli_tl(t0, t0, 1); + break; + case NM_LWXS: + case NM_SWXS: + case NM_LWC1XS: + case NM_SWC1XS: + tcg_gen_shli_tl(t0, t0, 2); + break; + case NM_LDC1XS: + case NM_SDC1XS: + tcg_gen_shli_tl(t0, t0, 3); + break; + } + } + gen_op_addr_add(ctx, t0, t0, t1); + + switch ((ctx->opcode >> 7) & 0xf) { + case NM_LBX: + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, + MO_SB); + gen_store_gpr(t0, rd); + break; + case NM_LHX: + /*case NM_LHXS:*/ + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, + MO_TESW); + gen_store_gpr(t0, rd); + break; + case NM_LWX: + /*case NM_LWXS:*/ + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, + MO_TESL); + gen_store_gpr(t0, rd); + break; + case NM_LBUX: + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, + MO_UB); + gen_store_gpr(t0, rd); + break; + case NM_LHUX: + /*case NM_LHUXS:*/ + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, + MO_TEUW); + gen_store_gpr(t0, rd); + break; + case NM_SBX: + gen_load_gpr(t1, rd); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, + MO_8); + break; + case NM_SHX: + /*case NM_SHXS:*/ + gen_load_gpr(t1, rd); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, + MO_TEUW); + break; + case NM_SWX: + /*case NM_SWXS:*/ + gen_load_gpr(t1, rd); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, + MO_TEUL); + break; + case NM_LWC1X: + /*case NM_LWC1XS:*/ + case NM_LDC1X: + /*case NM_LDC1XS:*/ + case NM_SWC1X: + /*case NM_SWC1XS:*/ + case NM_SDC1X: + /*case NM_SDC1XS:*/ + if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { + check_cp1_enabled(ctx); + switch ((ctx->opcode >> 7) & 0xf) { + case NM_LWC1X: + /*case NM_LWC1XS:*/ + gen_flt_ldst(ctx, OPC_LWC1, rd, t0); + break; + case NM_LDC1X: + /*case NM_LDC1XS:*/ + gen_flt_ldst(ctx, OPC_LDC1, rd, t0); + break; + case NM_SWC1X: + /*case NM_SWC1XS:*/ + gen_flt_ldst(ctx, OPC_SWC1, rd, t0); + break; + case NM_SDC1X: + /*case NM_SDC1XS:*/ + gen_flt_ldst(ctx, OPC_SDC1, rd, t0); + break; + } + } else { + generate_exception_err(ctx, EXCP_CpU, 1); + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + + tcg_temp_free(t0); + tcg_temp_free(t1); +} + static void gen_pool32f_nanomips_insn(DisasContext *ctx) { int rt, rs, rd; @@ -16881,7 +17007,7 @@ static void gen_pool32f_nanomips_insn(DisasContext = *ctx) static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) { uint16_t insn; - int rt, rs; + int rt, rs, rd; uint32_t op; =20 insn =3D cpu_lduw_code(env, ctx->base.pc_next + 2); @@ -16889,6 +17015,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) =20 rt =3D (ctx->opcode >> 21) & 0x1f; rs =3D (ctx->opcode >> 16) & 0x1f; + rd =3D (ctx->opcode >> 11) & 0x1f; =20 op =3D (ctx->opcode >> 26) & 0x3f; switch (op) { @@ -16950,6 +17077,16 @@ static int decode_nanomips_32_48_opc(CPUMIPSState = *env, DisasContext *ctx) case NM_POOL32A7: { switch ((ctx->opcode >> 3) & 0x07) { + case NM_P_LSX: + gen_p_lsx(ctx, rd, rs, rt); + break; + case NM_LSA: + /* In nanoMIPS, the shift field directly encodes the shift + * amount, meaning that the supported shift values are in + * the range 0 to 3 (instead of 1 to 4 in MIPSR6). */ + gen_lsa(ctx, OPC_LSA, rd, rs, rt, + extract32(ctx->opcode, 9, 2) - 1); + break; case NM_POOL32AXF: gen_pool32axf_nanomips_insn(env, ctx); break; --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497632048455.01875416884366; Wed, 20 Jun 2018 05:27:12 -0700 (PDT) Received: from localhost ([::1]:49102 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVcCd-0002qq-6D for importer@patchew.org; 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Wed, 20 Jun 2018 05:10:40 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:00 +0100 Message-ID: <20180620120620.12806-16-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496643-382908-26669-47935-1 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.210 Subject: [Qemu-devel] [PATCH 15/35] target/mips: Implement nanoMIPS EXTW instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: James Hogan Implement the nanoMIPS EXTW instruction, which is similar to the MIPS r6 ALIGN instruction except that it counts the other way and in bits instead of bytes. We therefore generalise gen_align() into gen_align_bits() (which counts in bits instead of bytes and optimises when bits =3D size of the word), and implement gen_align() and a new gen_ext() based on that. Since we need to know the word size to check for when the number of bits =3D=3D the word size, the opc argument is replaced with a wordsz argument (either 32 or 64). Signed-off-by: James Hogan Signed-off-by: Yongbok Kim --- target/mips/translate.c | 53 +++++++++++++++++++++++++++++++++------------= ---- 1 file changed, 36 insertions(+), 17 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 819cfd9..bd50281 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4723,8 +4723,8 @@ static void gen_lsa(DisasContext *ctx, int opc, int r= d, int rs, int rt, return; } =20 -static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt, - int bp) +static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs, + int rt, int bits) { TCGv t0; if (rd =3D=3D 0) { @@ -4732,35 +4732,40 @@ static void gen_align(DisasContext *ctx, int opc, i= nt rd, int rs, int rt, return; } t0 =3D tcg_temp_new(); - gen_load_gpr(t0, rt); - if (bp =3D=3D 0) { - switch (opc) { - case OPC_ALIGN: + if (bits =3D=3D 0 || bits =3D=3D wordsz) { + if (bits =3D=3D 0) { + gen_load_gpr(t0, rt); + } else { + gen_load_gpr(t0, rs); + } + switch (wordsz) { + case 32: tcg_gen_ext32s_tl(cpu_gpr[rd], t0); break; #if defined(TARGET_MIPS64) - case OPC_DALIGN: + case 64: tcg_gen_mov_tl(cpu_gpr[rd], t0); break; #endif } } else { TCGv t1 =3D tcg_temp_new(); + gen_load_gpr(t0, rt); gen_load_gpr(t1, rs); - switch (opc) { - case OPC_ALIGN: + switch (wordsz) { + case 32: { TCGv_i64 t2 =3D tcg_temp_new_i64(); tcg_gen_concat_tl_i64(t2, t1, t0); - tcg_gen_shri_i64(t2, t2, 8 * (4 - bp)); + tcg_gen_shri_i64(t2, t2, 32 - bits); gen_move_low32(cpu_gpr[rd], t2); tcg_temp_free_i64(t2); } break; #if defined(TARGET_MIPS64) - case OPC_DALIGN: - tcg_gen_shli_tl(t0, t0, 8 * bp); - tcg_gen_shri_tl(t1, t1, 8 * (8 - bp)); + case 64: + tcg_gen_shli_tl(t0, t0, bits); + tcg_gen_shri_tl(t1, t1, 64 - bits); tcg_gen_or_tl(cpu_gpr[rd], t1, t0); break; #endif @@ -4771,6 +4776,18 @@ static void gen_align(DisasContext *ctx, int opc, in= t rd, int rs, int rt, tcg_temp_free(t0); } =20 +static void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int r= t, + int bp) +{ + gen_align_bits(ctx, wordsz, rd, rs, rt, bp * 8); +} + +static void gen_ext(DisasContext *ctx, int wordsz, int rd, int rs, int rt, + int shift) +{ + gen_align_bits(ctx, wordsz, rd, rs, rt, wordsz - shift); +} + static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt) { TCGv t0; @@ -14118,8 +14135,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) break; case ALIGN: check_insn(ctx, ISA_MIPS32R6); - gen_align(ctx, OPC_ALIGN, rd, rs, rt, - extract32(ctx->opcode, 9, 2)); + gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2)); break; case EXT: gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd); @@ -17087,6 +17103,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_lsa(ctx, OPC_LSA, rd, rs, rt, extract32(ctx->opcode, 9, 2) - 1); break; + case NM_EXTW: + gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5)); + break; case NM_POOL32AXF: gen_pool32axf_nanomips_insn(env, ctx); break; @@ -19939,7 +19958,7 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) op2 =3D MASK_BSHFL(ctx->opcode); switch (op2) { case OPC_ALIGN ... OPC_ALIGN_END: - gen_align(ctx, OPC_ALIGN, rd, rs, rt, sa & 3); + gen_align(ctx, 32, rd, rs, rt, sa & 3); break; case OPC_BITSWAP: gen_bitswap(ctx, op2, rd, rt); @@ -19964,7 +19983,7 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) op2 =3D MASK_DBSHFL(ctx->opcode); switch (op2) { case OPC_DALIGN ... OPC_DALIGN_END: - gen_align(ctx, OPC_DALIGN, rd, rs, rt, sa & 7); + gen_align(ctx, 64, rd, rs, rt, sa & 7); break; case OPC_DBITSWAP: gen_bitswap(ctx, op2, rd, rt); --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497797610505.6489756298115; Wed, 20 Jun 2018 05:29:57 -0700 (PDT) Received: from localhost ([::1]:49115 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVcFI-0005I0-Qg for importer@patchew.org; Wed, 20 Jun 2018 08:29:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35719) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbx8-00060f-JO for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:11:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbx2-0005am-Kr for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:11:10 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.154.210]:54268) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbx2-0005X5-AU for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:11:04 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx1404.ess.rzc.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:10:54 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:10:43 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:01 +0100 Message-ID: <20180620120620.12806-17-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496643-382908-26669-47935-2 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.210 Subject: [Qemu-devel] [PATCH 16/35] target/mips: Add has_isa_mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Matthew Fortune ISA mode bit (LSB of address) is no longer required but is also masked to allow for tools transition. Signed-off-by: Yongbok Kim --- target/mips/translate.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index bd50281..2e794da 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1458,6 +1458,7 @@ typedef struct DisasContext { bool mrp; bool nan2008; bool abs2008; + bool has_isa_mode; } DisasContext; =20 #define DISAS_STOP DISAS_TARGET_0 @@ -4538,7 +4539,7 @@ static void gen_compute_branch (DisasContext *ctx, ui= nt32_t opc, =20 if (blink > 0) { int post_delay =3D insn_bytes + delayslot_size; - int lowbit =3D !!(ctx->hflags & MIPS_HFLAG_M16); + int lowbit =3D ctx->has_isa_mode && !!(ctx->hflags & MIPS_HFLAG_M1= 6); =20 tcg_gen_movi_tl(cpu_gpr[blink], ctx->base.pc_next + post_delay + lowbit); @@ -10876,7 +10877,8 @@ static void gen_branch(DisasContext *ctx, int insn_= bytes) break; case MIPS_HFLAG_BR: /* unconditional branch to register */ - if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) { + if (ctx->has_isa_mode && + (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS))) { TCGv t0 =3D tcg_temp_new(); TCGv_i32 t1 =3D tcg_temp_new_i32(); =20 @@ -10912,7 +10914,7 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, int bcond_compute =3D 0; TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - int m16_lowbit =3D (ctx->hflags & MIPS_HFLAG_M16) !=3D 0; + int m16_lowbit =3D ctx->has_isa_mode && ((ctx->hflags & MIPS_HFLAG_M16= ) !=3D 0); =20 if (ctx->hflags & MIPS_HFLAG_BMASK) { #ifdef MIPS_DEBUG_DISAS @@ -22476,6 +22478,7 @@ static void mips_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) ctx->mrp =3D (env->CP0_Config5 >> CP0C5_MRP) & 1; ctx->nan2008 =3D (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; ctx->abs2008 =3D (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; + ctx->has_isa_mode =3D ((env->CP0_Config3 >> CP0C3_MMAR) & 0x7) !=3D 3; restore_cpu_state(env, ctx); #ifdef CONFIG_USER_ONLY ctx->mem_idx =3D MIPS_HFLAG_UM; --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529496907934308.2540574803628; Wed, 20 Jun 2018 05:15:07 -0700 (PDT) Received: from localhost ([::1]:49028 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVc0u-0000Oo-0x for importer@patchew.org; Wed, 20 Jun 2018 08:15:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35758) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbxH-00069A-Cw for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:11:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbxD-0005jP-Bs for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:11:19 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.154.210]:57340) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbxD-0005bt-1O for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:11:15 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx1404.ess.rzc.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:11:06 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:10:45 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:02 +0100 Message-ID: <20180620120620.12806-18-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496643-382908-26669-47935-3 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.210 Subject: [Qemu-devel] [PATCH 17/35] target/mips: Add nanoMIPS load store instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nanoMIPS load and store instructions Signed-off-by: Yongbok Kim --- target/mips/translate.c | 271 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 271 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 2e794da..08765a7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -17379,10 +17379,281 @@ static int decode_nanomips_32_48_opc(CPUMIPSStat= e *env, DisasContext *ctx) } break; case NM_P_GP_BH: + { + uint32_t u =3D extract32(ctx->opcode, 0, 18); + switch ((ctx->opcode >> 18) & 0x7) { + case NM_LBGP: + gen_ld(ctx, OPC_LB, rt, 28, u); + break; + case NM_SBGP: + gen_st(ctx, OPC_SB, rt, 28, u); + break; + case NM_LBUGP: + gen_ld(ctx, OPC_LBU, rt, 28, u); + break; + case NM_ADDIUGP_B: + gen_arith_imm(ctx, OPC_ADDIU, rt, 28, u); + break; + case NM_P_GP_LH: + u &=3D ~1; + switch (ctx->opcode & 1) { + case NM_LHGP: + gen_ld(ctx, OPC_LH, rt, 28, u); + break; + case NM_LHUGP: + gen_ld(ctx, OPC_LHU, rt, 28, u); + break; + } + break; + case NM_P_GP_SH: + u &=3D ~1; + switch (ctx->opcode & 1) { + case NM_SHGP: + gen_st(ctx, OPC_SH, rt, 28, u); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_P_GP_CP1: + u &=3D ~0x3; + switch ((ctx->opcode & 0x3)) { + case NM_LWC1GP: + gen_cop1_ldst(ctx, OPC_LWC1, rt, 28, u); + break; + case NM_LDC1GP: + gen_cop1_ldst(ctx, OPC_LDC1, rt, 28, u); + break; + case NM_SWC1GP: + gen_cop1_ldst(ctx, OPC_SWC1, rt, 28, u); + break; + case NM_SDC1GP: + gen_cop1_ldst(ctx, OPC_SDC1, rt, 28, u); + break; + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } break; case NM_P_LS_U12: + { + uint32_t u =3D extract32(ctx->opcode, 0, 12); + switch ((ctx->opcode >> 12) & 0x0f) { + case NM_P_PREFU12: + if (rt =3D=3D 31) { + /* SYNCI */ + /* Break the TB to be able to sync copied instructions + immediately */ + ctx->base.is_jmp =3D DISAS_STOP; + } else { + /* PREF */ + /* Treat as NOP. */ + } + break; + case NM_LB: + gen_ld(ctx, OPC_LB, rt, rs, u); + break; + case NM_LH: + gen_ld(ctx, OPC_LH, rt, rs, u); + break; + case NM_LW: + gen_ld(ctx, OPC_LW, rt, rs, u); + break; + case NM_LBU: + gen_ld(ctx, OPC_LBU, rt, rs, u); + break; + case NM_LHU: + gen_ld(ctx, OPC_LHU, rt, rs, u); + break; + case NM_SB: + gen_st(ctx, OPC_SB, rt, rs, u); + break; + case NM_SH: + gen_st(ctx, OPC_SH, rt, rs, u); + break; + case NM_SW: + gen_st(ctx, OPC_SW, rt, rs, u); + break; + case NM_LWC1: + gen_cop1_ldst(ctx, OPC_LWC1, rt, rs, u); + break; + case NM_LDC1: + gen_cop1_ldst(ctx, OPC_LDC1, rt, rs, u); + break; + case NM_SWC1: + gen_cop1_ldst(ctx, OPC_SWC1, rt, rs, u); + break; + case NM_SDC1: + gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, u); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } break; case NM_P_LS_S9: + { + int32_t s =3D (sextract32(ctx->opcode, 15, 1) << 8) | + extract32(ctx->opcode, 0, 8); + switch ((ctx->opcode >> 8) & 0x07) { + case NM_P_LS_S0: + switch ((ctx->opcode >> 11) & 0x0f) { + case NM_LBS9: + gen_ld(ctx, OPC_LB, rt, rs, s); + break; + case NM_LHS9: + gen_ld(ctx, OPC_LH, rt, rs, s); + break; + case NM_LWS9: + gen_ld(ctx, OPC_LW, rt, rs, s); + break; + case NM_LBUS9: + gen_ld(ctx, OPC_LBU, rt, rs, s); + break; + case NM_LHUS9: + gen_ld(ctx, OPC_LHU, rt, rs, s); + break; + case NM_SBS9: + gen_st(ctx, OPC_SB, rt, rs, s); + break; + case NM_SHS9: + gen_st(ctx, OPC_SH, rt, rs, s); + break; + case NM_SWS9: + gen_st(ctx, OPC_SW, rt, rs, s); + break; + case NM_LWC1S9: + gen_cop1_ldst(ctx, OPC_LWC1, rt, rs, s); + break; + case NM_LDC1S9: + gen_cop1_ldst(ctx, OPC_LDC1, rt, rs, s); + break; + case NM_SWC1S9: + gen_cop1_ldst(ctx, OPC_SWC1, rt, rs, s); + break; + case NM_SDC1S9: + gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, s); + break; + case NM_P_PREFS9: + if (rt =3D=3D 31) { + /* SYNCI */ + /* Break the TB to be able to sync copied instructions + immediately */ + ctx->base.is_jmp =3D DISAS_STOP; + } else { + /* PREF */ + /* Treat as NOP. */ + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_P_LS_S1: + switch ((ctx->opcode >> 11) & 0x0f) { + case NM_UALH: + case NM_UASH: + { + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + + gen_base_offset_addr(ctx, t0, rs, s); + + switch ((ctx->opcode >> 11) & 0x0f) { + case NM_UALH: + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW | + MO_UNALN); + gen_store_gpr(t0, rt); + break; + case NM_UASH: + gen_load_gpr(t1, rt); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW | + MO_UNALN); + break; + } + tcg_temp_free(t0); + tcg_temp_free(t1); + } + break; + case NM_P_LL: + switch (ctx->opcode & 0x03) { + case NM_LL: + gen_ld(ctx, OPC_LL, rt, rs, s); + break; + case NM_LLWP: + break; + } + break; + case NM_P_SC: + switch (ctx->opcode & 0x03) { + case NM_SC: + gen_st_cond(ctx, OPC_SC, rt, rs, s); + break; + case NM_SCWP: + break; + } + break; + case NM_CACHE: + check_cp0_enabled(ctx); + if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { + gen_cache_operation(ctx, rt, rs, s); + } + break; + } + break; + case NM_P_LS_WM: + case NM_P_LS_UAWM: + { + int32_t offset =3D sextract32(ctx->opcode, 15, 1) << 8 | + extract32(ctx->opcode, 0, 8); + int count =3D extract32(ctx->opcode, 12, 3); + int counter =3D 0; + TCGv va =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGMemOp memop =3D ((ctx->opcode >> 8) & 0x07) =3D=3D NM_P_LS_= UAWM ? + MO_UNALN : 0; + + count =3D (count =3D=3D 0) ? 8 : count; + while (counter !=3D count) { + int this_rt =3D ((rt + counter) & 0x1f) | (rt & 0x10); + int32_t this_offset =3D offset + (counter << 2); + + gen_base_offset_addr(ctx, va, rs, this_offset); + + switch (extract32(ctx->opcode, 11, 1)) { + case NM_LWM: + tcg_gen_qemu_ld_tl(t1, va, ctx->mem_idx, + memop | MO_TESL); + gen_store_gpr(t1, this_rt); + if ((this_rt =3D=3D rs) && + (counter !=3D (count - 1))) { + /* UNPREDICTABLE */ + } + break; + case NM_SWM: + this_rt =3D (rt =3D=3D 0) ? 0 : this_rt; + gen_load_gpr(t1, this_rt); + tcg_gen_qemu_st_tl(t1, va, ctx->mem_idx, + memop | MO_TEUL); + break; + } + counter++; + } + tcg_temp_free(va); + tcg_temp_free(t1); + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } break; case NM_MOVE_BALC: break; --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15294971476241011.1132504663804; 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Wed, 20 Jun 2018 05:10:48 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:03 +0100 Message-ID: <20180620120620.12806-19-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496643-382908-26669-47935-4 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.210 Subject: [Qemu-devel] [PATCH 18/35] target/mips: Add nanoMIPS branch instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nanoMIPS branch instructions Signed-off-by: Yongbok Kim --- target/mips/translate.c | 277 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 277 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 08765a7..948d3d5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16597,6 +16597,168 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSSt= ate *env, DisasContext *ctx) } } =20 +/* Immediate Value Compact Branches */ +static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, + int rt, int32_t imm, int32_t offset) +{ + int bcond_compute =3D 0; + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { +#ifdef MIPS_DEBUG_DISAS + LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx + "\n", ctx->base.pc_next); +#endif + generate_exception_end(ctx, EXCP_RI); + goto out; + } + + gen_load_gpr(t0, rt); + tcg_gen_movi_tl(t1, imm); + ctx->btarget =3D addr_add(ctx, ctx->base.pc_next + 4, offset); + + /* Load needed operands and calculate btarget */ + switch (opc) { + case NM_BEQIC: + if (rt =3D=3D 0 && imm =3D=3D 0) { + /* Unconditional branch */ + } else if (rt =3D=3D 0 && imm !=3D 0) { + /* Treat as NOP */ + goto out; + } else { + bcond_compute =3D 1; + } + break; + case NM_BBEQZC: + case NM_BBNEZC: + if (imm >=3D 32 && !(ctx->hflags & MIPS_HFLAG_64)) { + generate_exception_end(ctx, EXCP_RI); + goto out; + } else if (rt =3D=3D 0 && opc =3D=3D NM_BBEQZC) { + /* Unconditional branch */ + } else if (rt =3D=3D 0 && opc =3D=3D NM_BBNEZC) { + /* Treat as NOP */ + goto out; + } else { + tcg_gen_shri_tl(t0, t0, imm); + tcg_gen_andi_tl(t0, t0, 1); + tcg_gen_movi_tl(t1, 0); + bcond_compute =3D 1; + } + break; + case NM_BNEIC: + if (rt =3D=3D 0 && imm =3D=3D 0) { + /* Treat as NOP */ + goto out; + } else if (rt =3D=3D 0 && imm !=3D 0) { + /* Unconditional branch */ + } else { + bcond_compute =3D 1; + } + break; + case NM_BGEIC: + if (rt =3D=3D 0 && imm =3D=3D 0) { + /* Unconditional branch */ + } else { + bcond_compute =3D 1; + } + break; + case NM_BLTIC: + bcond_compute =3D 1; + break; + case NM_BGEIUC: + if (rt =3D=3D 0 && imm =3D=3D 0) { + /* Unconditional branch */ + } else { + bcond_compute =3D 1; + } + break; + case NM_BLTIUC: + bcond_compute =3D 1; + break; + default: + MIPS_INVAL("Immediate Value Compact branch"); + generate_exception_end(ctx, EXCP_RI); + goto out; + } + + if (bcond_compute =3D=3D 0) { + /* Uncoditional compact branch */ + ctx->hflags |=3D MIPS_HFLAG_B; + /* Generating branch here as compact branches don't have delay slo= t */ + gen_branch(ctx, 4); + } else { + /* Conditional compact branch */ + TCGLabel *fs =3D gen_new_label(); + save_cpu_state(ctx, 0); + + switch (opc) { + case NM_BEQIC: + tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs); + break; + case NM_BBEQZC: + tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs); + break; + case NM_BNEIC: + tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs); + break; + case NM_BBNEZC: + tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs); + break; + case NM_BGEIC: + tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs); + break; + case NM_BLTIC: + tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT), t0, t1, fs); + break; + case NM_BGEIUC: + tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU), t0, t1, fs); + break; + case NM_BLTIUC: + tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU), t0, t1, fs); + break; + } + + /* Generating branch here as compact branches don't have delay slo= t */ + gen_goto_tb(ctx, 1, ctx->btarget); + gen_set_label(fs); + + ctx->hflags |=3D MIPS_HFLAG_FBNSLOT; + } + +out: + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +/* P.BALRSC type nanoMIPS R6 branches: BALRSC and BRSC */ +static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs, + int rt) +{ + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + + /* load rs */ + gen_load_gpr(t0, rs); + + /* link */ + if (rt !=3D 0) { + tcg_gen_movi_tl(cpu_gpr[rt], ctx->base.pc_next + 4); + } + + /* calculate btarget */ + tcg_gen_shli_tl(t0, t0, 1); + tcg_gen_movi_tl(t1, ctx->base.pc_next + 4); + gen_op_addr_add(ctx, btarget, t1, t0); + + ctx->hflags |=3D MIPS_HFLAG_BR; + /* Generating branch here as compact branches don't have delay slot */ + gen_branch(ctx, 4); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} =20 static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt) { @@ -17656,16 +17818,131 @@ static int decode_nanomips_32_48_opc(CPUMIPSStat= e *env, DisasContext *ctx) } break; case NM_MOVE_BALC: + { + TCGv t0 =3D tcg_temp_new(); + int32_t s =3D sextract32(ctx->opcode, 0, 1) << 21 | + extract32(ctx->opcode, 1, 20) << 1; + rd =3D ((ctx->opcode >> 24) & 1) =3D=3D 0 ? 4 : 5; + rt =3D mmreg4z_nanomips(extract32(ctx->opcode, 25, 1) << 3 | + extract32(ctx->opcode, 21, 3)); + gen_load_gpr(t0, rt); + tcg_gen_mov_tl(cpu_gpr[rd], t0); + gen_compute_branch(ctx, OPC_BGEZAL, 4, 0, 0, s, 0); + tcg_temp_free(t0); + } break; case NM_P_BAL: + { + int32_t s =3D sextract32(ctx->opcode, 0, 1) << 25 | + extract32(ctx->opcode, 1, 24) << 1; + + if (((ctx->opcode >> 25) & 1) =3D=3D 0) { + /* BC */ + gen_compute_branch(ctx, OPC_BEQ, 4, 0, 0, s, 0); + } else { + /* BALC */ + gen_compute_branch(ctx, OPC_BGEZAL, 4, 0, 0, s, 0); + } + } break; case NM_P_J: + switch ((ctx->opcode >> 12) & 0x0f) { + case NM_JALRC: + case NM_JALRC_HB: + gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0); + break; + case NM_P_BALRSC: + gen_compute_nanomips_pbalrsc_branch(ctx, rs, rt); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } break; case NM_P_BR1: + { + int32_t s =3D sextract32(ctx->opcode, 0, 1) << 14 | + extract32(ctx->opcode, 1, 13) << 1; + switch ((ctx->opcode >> 14) & 0x03) { + case NM_BEQC: + gen_compute_branch(ctx, OPC_BEQ, 4, rs, rt, s, 0); + break; + case NM_P_BR3A: + { + int32_t s =3D sextract32(ctx->opcode, 0, 1) << 14 | + extract32(ctx->opcode, 1, 13) << 1; + check_cp1_enabled(ctx); + switch ((ctx->opcode >> 16) & 0x1f) { + case NM_BC1EQZC: + gen_compute_branch1_r6(ctx, OPC_BC1EQZ, rt, s, 0); + break; + case NM_BC1NEZC: + gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rt, s, 0); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } + break; + case NM_BGEC: + if (rs =3D=3D rt) { + gen_compute_compact_branch(ctx, OPC_BC, rs, rt, s); + } else { + gen_compute_compact_branch(ctx, OPC_BGEC, rs, rt, s); + } + break; + case NM_BGEUC: + if (rs =3D=3D rt || rt =3D=3D 0) { + gen_compute_compact_branch(ctx, OPC_BC, 0, 0, s); + } else if (rs =3D=3D 0) { + gen_compute_compact_branch(ctx, OPC_BEQZC, rt, 0, s); + } else { + gen_compute_compact_branch(ctx, OPC_BGEUC, rs, rt, s); + } + break; + } + } break; case NM_P_BR2: + { + int32_t s =3D sextract32(ctx->opcode, 0, 1) << 14 | + extract32(ctx->opcode, 1, 13) << 1; + switch ((ctx->opcode >> 14) & 0x03) { + case NM_BNEC: + gen_compute_branch(ctx, OPC_BNE, 4, rs, rt, s, 0); + break; + case NM_BLTC: + if (rs !=3D 0 && rt !=3D 0 && rs =3D=3D rt) { + /* NOP */ + ctx->hflags |=3D MIPS_HFLAG_FBNSLOT; + } else { + gen_compute_compact_branch(ctx, OPC_BLTC, rs, rt, s); + } + break; + case NM_BLTUC: + if (rs =3D=3D 0 || rs =3D=3D rt) { + /* NOP */ + ctx->hflags |=3D MIPS_HFLAG_FBNSLOT; + } else { + gen_compute_compact_branch(ctx, OPC_BLTUC, rs, rt, s); + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } break; case NM_P_BRI: + { + int32_t s =3D sextract32(ctx->opcode, 0, 1) << 11 | + extract32(ctx->opcode, 1, 10) << 1; + uint32_t u =3D extract32(ctx->opcode, 11, 7); + + gen_compute_imm_branch(ctx, extract32(ctx->opcode, 18, 3), + rt, u, s); + } break; default: generate_exception_end(ctx, EXCP_RI); --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497327654228.20803148038715; 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Wed, 20 Jun 2018 05:10:51 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:04 +0100 Message-ID: <20180620120620.12806-20-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496643-382908-26669-47935-5 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.210 Subject: [Qemu-devel] [PATCH 19/35] target/mips: Implement nanoMIPS LLWP/SCWP pair X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Implement nanoMIPS LLWP and SCWP instruction pair. Signed-off-by: Yongbok Kim --- linux-user/mips/cpu_loop.c | 25 ++++++++--- target/mips/cpu.h | 2 + target/mips/helper.h | 2 + target/mips/op_helper.c | 35 +++++++++++++++ target/mips/translate.c | 107 +++++++++++++++++++++++++++++++++++++++++= ++++ 5 files changed, 166 insertions(+), 5 deletions(-) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 084ad6a..1d3dc9e 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -397,10 +397,13 @@ static int do_store_exclusive(CPUMIPSState *env) target_ulong addr; target_ulong page_addr; target_ulong val; + uint32_t val_wp =3D 0; + uint32_t llnewval_wp =3D 0; int flags; int segv =3D 0; int reg; int d; + int wp; =20 addr =3D env->lladdr; page_addr =3D addr & TARGET_PAGE_MASK; @@ -412,19 +415,31 @@ static int do_store_exclusive(CPUMIPSState *env) } else { reg =3D env->llreg & 0x1f; d =3D (env->llreg & 0x20) !=3D 0; - if (d) { - segv =3D get_user_s64(val, addr); + wp =3D (env->llreg & 0x40) !=3D 0; + if (!wp) { + if (d) { + segv =3D get_user_s64(val, addr); + } else { + segv =3D get_user_s32(val, addr); + } } else { segv =3D get_user_s32(val, addr); + segv |=3D get_user_s32(val_wp, addr); + llnewval_wp =3D env->llnewval_wp; } if (!segv) { - if (val !=3D env->llval) { + if (val !=3D env->llval && val_wp =3D=3D llnewval_wp) { env->active_tc.gpr[reg] =3D 0; } else { - if (d) { - segv =3D put_user_u64(env->llnewval, addr); + if (!wp) { + if (d) { + segv =3D put_user_u64(env->llnewval, addr); + } else { + segv =3D put_user_u32(env->llnewval, addr); + } } else { segv =3D put_user_u32(env->llnewval, addr); + segv |=3D put_user_u32(env->llnewval_wp, addr + 4); } if (!segv) { env->active_tc.gpr[reg] =3D 1; diff --git a/target/mips/cpu.h b/target/mips/cpu.h index cfe1735..18f193d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -486,6 +486,8 @@ struct CPUMIPSState { uint64_t lladdr; target_ulong llval; target_ulong llnewval; + uint32_t llval_wp; + uint32_t llnewval_wp; target_ulong llreg; uint64_t CP0_LLAddr_rw_bitmask; int CP0_LLAddr_shift; diff --git a/target/mips/helper.h b/target/mips/helper.h index 5f49234..b239adc 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -14,6 +14,8 @@ DEF_HELPER_4(swr, void, env, tl, tl, int) #ifndef CONFIG_USER_ONLY DEF_HELPER_3(ll, tl, env, tl, int) DEF_HELPER_4(sc, tl, env, tl, tl, int) +DEF_HELPER_5(llwp, void, env, tl, i32, i32, i32) +DEF_HELPER_4(scwp, tl, env, tl, i64, int) #ifdef TARGET_MIPS64 DEF_HELPER_3(lld, tl, env, tl, int) DEF_HELPER_4(scd, tl, env, tl, tl, int) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 41d3634..71a9d66 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -284,6 +284,19 @@ HELPER_LD_ATOMIC(lld, ld, 0x7) #endif #undef HELPER_LD_ATOMIC =20 +void helper_llwp(CPUMIPSState *env, target_ulong addr, uint32_t reg1, + uint32_t reg2, uint32_t mem_idx) +{ + if (addr & 0x7) { + env->CP0_BadVAddr =3D addr; + do_raise_exception(env, EXCP_AdEL, GETPC()); + } + env->lladdr =3D do_translate_address(env, addr, 0, GETPC()); + env->active_tc.gpr[reg1] =3D env->llval =3D do_lw(env, addr, mem_idx, = GETPC()); + env->active_tc.gpr[reg2] =3D env->llval_wp =3D do_lw(env, addr + 4, me= m_idx, + GETPC()); +} + #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) = \ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, = \ target_ulong arg2, int mem_idx) = \ @@ -308,6 +321,28 @@ HELPER_ST_ATOMIC(sc, lw, sw, 0x3) HELPER_ST_ATOMIC(scd, ld, sd, 0x7) #endif #undef HELPER_ST_ATOMIC + +target_ulong helper_scwp(CPUMIPSState *env, target_ulong addr, + uint64_t data, int mem_idx) +{ + uint32_t tmp; + uint32_t tmp2; + + if (addr & 0x7) { + env->CP0_BadVAddr =3D addr; + do_raise_exception(env, EXCP_AdES, GETPC()); + } + if (do_translate_address(env, addr, 1, GETPC()) =3D=3D env->lladdr) { + tmp =3D do_lw(env, addr, mem_idx, GETPC()); + tmp2 =3D do_lw(env, addr + 4, mem_idx, GETPC()); + if (tmp =3D=3D env->llval && tmp2 =3D=3D env->llval_wp) { + do_sw(env, addr, (uint32_t) data, mem_idx, GETPC()); + do_sw(env, addr + 4, (uint32_t) *(&data + 4), mem_idx, GETPC()= ); + return 1; + } + } + return 0; +} #endif =20 #ifdef TARGET_WORDS_BIGENDIAN diff --git a/target/mips/translate.c b/target/mips/translate.c index 948d3d5..6237f97 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1459,6 +1459,7 @@ typedef struct DisasContext { bool nan2008; bool abs2008; bool has_isa_mode; + bool xnp; } DisasContext; =20 #define DISAS_STOP DISAS_TARGET_0 @@ -2336,6 +2337,44 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_temp_free(t0); } =20 +static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset, + uint32_t reg1, uint32_t reg2) +{ +#ifdef CONFIG_USER_ONLY + TCGv taddr =3D tcg_temp_new(); + TCGv tval =3D tcg_temp_new(); + + gen_base_offset_addr(ctx, taddr, base, offset); + tcg_gen_qemu_ld32s(tval, taddr, ctx->mem_idx); + tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, lladdr)); + tcg_gen_st_tl(tval, cpu_env, offsetof(CPUMIPSState, llval)); + tcg_gen_ext32s_tl(tval, tval); + gen_store_gpr(tval, reg1); + + gen_base_offset_addr(ctx, taddr, base, offset + 4); + tcg_gen_qemu_ld32s(tval, taddr, ctx->mem_idx); + tcg_gen_st_tl(tval, cpu_env, offsetof(CPUMIPSState, llval_wp)); + tcg_gen_ext32s_tl(tval, tval); + gen_store_gpr(tval, reg2); + + tcg_temp_free(taddr); + tcg_temp_free(tval); +#else + TCGv taddr =3D tcg_temp_new(); + TCGv_i32 helper_mem_idx =3D tcg_const_i32(ctx->mem_idx); + TCGv_i32 helper_reg1 =3D tcg_const_i32(reg1); + TCGv_i32 helper_reg2 =3D tcg_const_i32(reg2); + + gen_base_offset_addr(ctx, taddr, base, offset); + gen_helper_llwp(cpu_env, taddr, helper_reg1, helper_reg2, helper_mem_i= dx); + + tcg_temp_free(taddr); + tcg_temp_free_i32(helper_mem_idx); + tcg_temp_free_i32(helper_reg1); + tcg_temp_free_i32(helper_reg2); +#endif +} + /* Store */ static void gen_st (DisasContext *ctx, uint32_t opc, int rt, int base, int16_t offset) @@ -2432,6 +2471,63 @@ static void gen_st_cond (DisasContext *ctx, uint32_t= opc, int rt, tcg_temp_free(t0); } =20 +static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, + uint32_t reg1, uint32_t reg2) +{ +#ifdef CONFIG_USER_ONLY + TCGv taddr =3D tcg_temp_local_new(); + TCGv t0 =3D tcg_temp_new(); + TCGLabel *l1 =3D gen_new_label(); + TCGLabel *l2 =3D gen_new_label(); + + gen_base_offset_addr(ctx, taddr, base, offset); + tcg_gen_andi_tl(t0, taddr, 0x7); + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); + tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); + generate_exception(ctx, EXCP_AdES); + gen_set_label(l1); + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); + tcg_gen_brcond_tl(TCG_COND_NE, taddr, t0, l2); + tcg_gen_movi_tl(t0, reg1 | 0x60); + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llreg)); + gen_load_gpr(t0, reg1); + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llnewval)); + gen_load_gpr(t0, reg2); + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llnewval_wp)); + generate_exception_end(ctx, EXCP_SC); + gen_set_label(l2); + tcg_gen_movi_tl(t0, 0); + gen_store_gpr(t0, reg1); + tcg_temp_free(t0); + tcg_temp_free(taddr); +#else + TCGv taddr =3D tcg_temp_new(); + TCGv_i64 tdata =3D tcg_temp_new_i64(); + TCGv_i32 helper_mem_idx =3D tcg_const_i32(ctx->mem_idx); + + TCGv t0 =3D tcg_temp_new(); + TCGv_i64 t1_64 =3D tcg_temp_new_i64(); + + gen_load_gpr(t0, reg2); + tcg_gen_ext_tl_i64(tdata, t0); + tcg_gen_shli_i64(tdata, tdata, 32); + + gen_load_gpr(t0, reg1); + tcg_gen_ext_tl_i64(t1_64, t0); + tcg_gen_or_i64(tdata, tdata, t1_64); + + gen_base_offset_addr(ctx, taddr, base, offset); + gen_helper_scwp(cpu_gpr[reg1], cpu_env, taddr, tdata, helper_mem_idx); + + tcg_temp_free(taddr); + tcg_temp_free_i64(tdata); + tcg_temp_free_i32(helper_mem_idx); + + tcg_temp_free(t0); + tcg_temp_free_i64(t1_64); +#endif +} + /* Load and store */ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, TCGv t0) @@ -17749,6 +17845,11 @@ static int decode_nanomips_32_48_opc(CPUMIPSState = *env, DisasContext *ctx) gen_ld(ctx, OPC_LL, rt, rs, s); break; case NM_LLWP: + if (ctx->xnp) { + generate_exception_end(ctx, EXCP_RI); + } else { + gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3,= 5)); + } break; } break; @@ -17758,6 +17859,11 @@ static int decode_nanomips_32_48_opc(CPUMIPSState = *env, DisasContext *ctx) gen_st_cond(ctx, OPC_SC, rt, rs, s); break; case NM_SCWP: + if (ctx->xnp) { + generate_exception_end(ctx, EXCP_RI); + } else { + gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3,= 5)); + } break; } break; @@ -23027,6 +23133,7 @@ static void mips_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) ctx->nan2008 =3D (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; ctx->abs2008 =3D (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; ctx->has_isa_mode =3D ((env->CP0_Config3 >> CP0C3_MMAR) & 0x7) !=3D 3; + ctx->xnp =3D (env->CP0_Config5 >> CP0C5_XNP) & 1; restore_cpu_state(env, ctx); #ifdef CONFIG_USER_ONLY ctx->mem_idx =3D MIPS_HFLAG_UM; --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152949763403256.53497816109916; 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Wed, 20 Jun 2018 05:11:59 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:05 +0100 Message-ID: <20180620120620.12806-21-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496721-321459-12806-48465-1 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.211 Subject: [Qemu-devel] [PATCH 20/35] target/mips: Fix not to update BadVAddr in Debug Mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yongbok Kim BadVaddr shouldn't be updated in Debug Mode Signed-off-by: Yongbok Kim Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/helper.c | 4 +++- target/mips/op_helper.c | 20 +++++++++++++++----- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index 8cf91ce..e215af9 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -502,7 +502,9 @@ static void raise_mmu_exception(CPUMIPSState *env, targ= et_ulong address, break; } /* Raise exception */ - env->CP0_BadVAddr =3D address; + if (!(env->hflags & MIPS_HFLAG_DM)) { + env->CP0_BadVAddr =3D address; + } env->CP0_Context =3D (env->CP0_Context & ~0x007fffff) | ((address >> 9) & 0x007ffff0); env->CP0_EntryHi =3D (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) | diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 71a9d66..c9a111c 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -271,7 +271,9 @@ static inline hwaddr do_translate_address(CPUMIPSState = *env, target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_id= x) \ { = \ if (arg & almask) { = \ - env->CP0_BadVAddr =3D arg; = \ + if (!(env->hflags & MIPS_HFLAG_DM)) { = \ + env->CP0_BadVAddr =3D arg; = \ + } = \ do_raise_exception(env, EXCP_AdEL, GETPC()); = \ } = \ env->lladdr =3D do_translate_address(env, arg, 0, GETPC()); = \ @@ -288,7 +290,9 @@ void helper_llwp(CPUMIPSState *env, target_ulong addr, = uint32_t reg1, uint32_t reg2, uint32_t mem_idx) { if (addr & 0x7) { - env->CP0_BadVAddr =3D addr; + if (!(env->hflags & MIPS_HFLAG_DM)) { + env->CP0_BadVAddr =3D addr; + } do_raise_exception(env, EXCP_AdEL, GETPC()); } env->lladdr =3D do_translate_address(env, addr, 0, GETPC()); @@ -304,7 +308,9 @@ target_ulong helper_##name(CPUMIPSState *env, target_ul= ong arg1, \ target_long tmp; = \ = \ if (arg2 & almask) { = \ - env->CP0_BadVAddr =3D arg2; = \ + if (!(env->hflags & MIPS_HFLAG_DM)) { = \ + env->CP0_BadVAddr =3D arg2; = \ + } = \ do_raise_exception(env, EXCP_AdES, GETPC()); = \ } = \ if (do_translate_address(env, arg2, 1, GETPC()) =3D=3D env->lladdr) { = \ @@ -329,7 +335,9 @@ target_ulong helper_scwp(CPUMIPSState *env, target_ulon= g addr, uint32_t tmp2; =20 if (addr & 0x7) { - env->CP0_BadVAddr =3D addr; + if (!(env->hflags & MIPS_HFLAG_DM)) { + env->CP0_BadVAddr =3D addr; + } do_raise_exception(env, EXCP_AdES, GETPC()); } if (do_translate_address(env, addr, 1, GETPC()) =3D=3D env->lladdr) { @@ -2472,7 +2480,9 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr= addr, int error_code =3D 0; int excp; =20 - env->CP0_BadVAddr =3D addr; + if (!(env->hflags & MIPS_HFLAG_DM)) { + env->CP0_BadVAddr =3D addr; + } =20 if (access_type =3D=3D MMU_DATA_STORE) { excp =3D EXCP_AdES; --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497088852493.3257091958503; Wed, 20 Jun 2018 05:18:08 -0700 (PDT) Received: from localhost ([::1]:49049 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVc3s-0002rW-2n for importer@patchew.org; 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Wed, 20 Jun 2018 05:12:03 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:06 +0100 Message-ID: <20180620120620.12806-22-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496721-321459-12806-48465-2 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.211 Subject: [Qemu-devel] [PATCH 21/35] target/mips: Add nanoMIPS rotx instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Matthew Fortune Added a helper for rotx based on the pseudocode from the arch spec. Signed-off-by: Yongbok Kim Reviewed-by: Richard Henderson --- target/mips/helper.h | 2 ++ target/mips/op_helper.c | 94 +++++++++++++++++++++++++++++++++++++++++++++= ++++ target/mips/translate.c | 15 ++++++++ 3 files changed, 111 insertions(+) diff --git a/target/mips/helper.h b/target/mips/helper.h index b239adc..deca307 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -42,6 +42,8 @@ DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl) #endif =20 +DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32) + #ifndef CONFIG_USER_ONLY /* CP0 helpers */ DEF_HELPER_1(mfc0_mvpcontrol, tl, env) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index c9a111c..102a039 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -249,6 +249,100 @@ target_ulong helper_bitswap(target_ulong rt) return (int32_t)bitswap(rt); } =20 +target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx, + uint32_t stripe) +{ + int i; + uint64_t tmp0 =3D ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff); + uint64_t tmp1 =3D tmp0; + for (i =3D 0; i <=3D 46; i++) { + int s; + if (i & 0x8) { + s =3D shift; + } else { + s =3D shiftx; + } + + if (stripe !=3D 0 && !(i & 0x4)) { + s =3D ~s; + } + if (s & 0x10) { + if (tmp0 & (1LL << (i + 16))) { + tmp1 |=3D 1LL << i; + } else { + tmp1 &=3D ~(1LL << i); + } + } + } + + uint64_t tmp2 =3D tmp1; + for (i =3D 0; i <=3D 38; i++) { + int s; + if (i & 0x4) { + s =3D shift; + } else { + s =3D shiftx; + } + + if (s & 0x8) { + if (tmp1 & (1LL << (i + 8))) { + tmp2 |=3D 1LL << i; + } else { + tmp2 &=3D ~(1LL << i); + } + } + } + + uint64_t tmp3 =3D tmp2; + for (i =3D 0; i <=3D 34; i++) { + int s; + if (i & 0x2) { + s =3D shift; + } else { + s =3D shiftx; + } + if (s & 0x4) { + if (tmp2 & (1LL << (i + 4))) { + tmp3 |=3D 1LL << i; + } else { + tmp3 &=3D ~(1LL << i); + } + } + } + + uint64_t tmp4 =3D tmp3; + for (i =3D 0; i <=3D 32; i++) { + int s; + if (i & 0x1) { + s =3D shift; + } else { + s =3D shiftx; + } + if (s & 0x2) { + if (tmp3 & (1LL << (i + 2))) { + tmp4 |=3D 1LL << i; + } else { + tmp4 &=3D ~(1LL << i); + } + } + } + + uint64_t tmp5 =3D tmp4; + for (i =3D 0; i <=3D 31; i++) { + int s; + s =3D shift; + if (s & 0x1) { + if (tmp4 & (1LL << (i + 1))) { + tmp5 |=3D 1LL << i; + } else { + tmp5 &=3D ~(1LL << i); + } + } + } + + return (int64_t)(int32_t)(uint32_t)tmp5; +} + #ifndef CONFIG_USER_ONLY =20 static inline hwaddr do_translate_address(CPUMIPSState *env, diff --git a/target/mips/translate.c b/target/mips/translate.c index 6237f97..9e29dd7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -17581,6 +17581,21 @@ static int decode_nanomips_32_48_opc(CPUMIPSState = *env, DisasContext *ctx) } break; case NM_P_ROTX: + if (rt !=3D 0) { + TCGv t0 =3D tcg_temp_new(); + TCGv_i32 shift =3D tcg_const_i32(extract32(ctx->opcode, 0,= 5)); + TCGv_i32 shiftx =3D tcg_const_i32(extract32(ctx->opcode, 7= , 4) + << 1); + TCGv_i32 stripe =3D tcg_const_i32((ctx->opcode >> 6) & 1); + + gen_load_gpr(t0, rs); + gen_helper_rotx(cpu_gpr[rt], t0, shift, shiftx, stripe); + tcg_temp_free(t0); + + tcg_temp_free_i32(shift); + tcg_temp_free_i32(shiftx); + tcg_temp_free_i32(stripe); + } break; case NM_P_INS: switch (((ctx->opcode >> 10) & 2) | ((ctx->opcode >> 5) & 1)) { --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497277632176.0983932726483; Wed, 20 Jun 2018 05:21:17 -0700 (PDT) Received: from localhost ([::1]:49066 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVc6l-0005QZ-VW for importer@patchew.org; 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Wed, 20 Jun 2018 05:12:06 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:07 +0100 Message-ID: <20180620120620.12806-23-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496721-321459-12806-48465-3 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.211 Subject: [Qemu-devel] [PATCH 22/35] target/mips: Fix data type for offset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Offset can be larger than 16 bit from nanoMIPS, and immediate field can be larger than 16 bits as well. Signed-off-by: Yongbok Kim Reviewed-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 9e29dd7..8c20ba3 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2114,7 +2114,7 @@ OP_ST_ATOMIC(scd,st64,ld64,0x7); #undef OP_ST_ATOMIC =20 static void gen_base_offset_addr (DisasContext *ctx, TCGv addr, - int base, int16_t offset) + int base, int offset) { if (base =3D=3D 0) { tcg_gen_movi_tl(addr, offset); @@ -2142,7 +2142,7 @@ static target_ulong pc_relative_pc (DisasContext *ctx) =20 /* Load */ static void gen_ld(DisasContext *ctx, uint32_t opc, - int rt, int base, int16_t offset) + int rt, int base, int offset) { TCGv t0, t1, t2; int mem_idx =3D ctx->mem_idx; @@ -2377,7 +2377,7 @@ static void gen_llwp(DisasContext *ctx, uint32_t base= , int16_t offset, =20 /* Store */ static void gen_st (DisasContext *ctx, uint32_t opc, int rt, - int base, int16_t offset) + int base, int offset) { TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); @@ -2602,7 +2602,7 @@ static void gen_cop1_ldst(DisasContext *ctx, uint32_t= op, int rt, =20 /* Arithmetic with immediate operand */ static void gen_arith_imm(DisasContext *ctx, uint32_t opc, - int rt, int rs, int16_t imm) + int rt, int rs, int imm) { target_ulong uimm =3D (target_long)imm; /* Sign extend to 32/64 bits */ =20 --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497790861333.66363440522264; Wed, 20 Jun 2018 05:29:50 -0700 (PDT) Received: from localhost ([::1]:49114 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVcFC-0005Cc-48 for importer@patchew.org; Wed, 20 Jun 2018 08:29:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36137) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbyg-0007Jm-DT for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:12:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbyd-0006ni-7E for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:12:46 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.154.211]:43704) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbyc-0006fu-UV for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:12:43 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx1403.ess.rzc.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:12:33 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:12:10 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:08 +0100 Message-ID: <20180620120620.12806-24-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496721-321459-12806-48465-4 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.211 Subject: [Qemu-devel] [PATCH 23/35] target/mips: Update BadInstr{P} regs on nanoMIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Update BadInstr{P} registers on nanoMIPS Signed-off-by: Yongbok Kim --- target/mips/helper.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index e215af9..5299f21 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -683,7 +683,28 @@ static void set_hflags_for_handler (CPUMIPSState *env) static inline void set_badinstr_registers(CPUMIPSState *env) { if (env->hflags & MIPS_HFLAG_M16) { - /* TODO: add BadInstr support for microMIPS */ + uint32_t instr; + if (!(env->insn_flags & ISA_NANOMIPS32)) { + /* TODO: add BadInstr support for pre-nanoMIPS */ + return; + } + if (env->CP0_Config3 & (1 << CP0C3_BI)) { + instr =3D (cpu_lduw_code(env, env->active_tc.PC)) << 16; + if ((env->insn_flags & ISA_NANOMIPS32) && + ((instr & 0x10000000) =3D=3D 0)) { + instr |=3D cpu_lduw_code(env, env->active_tc.PC + 2); + } + env->CP0_BadInstr =3D instr; + } + if ((env->CP0_Config3 & (1 << CP0C3_BP)) && + (env->hflags & MIPS_HFLAG_BMASK)) { + if (!(env->hflags & MIPS_HFLAG_B16)) { + env->CP0_BadInstrP =3D cpu_ldl_code(env, env->active_tc.PC= - 4); + } else { + env->CP0_BadInstrP =3D + (cpu_lduw_code(env, env->active_tc.PC - 2)) << 16; + } + } return; } if (env->CP0_Config3 & (1 << CP0C3_BI)) { --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497444016137.82735340372585; Wed, 20 Jun 2018 05:24:04 -0700 (PDT) Received: from localhost ([::1]:49080 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVc9b-000802-6p for importer@patchew.org; Wed, 20 Jun 2018 08:24:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36173) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbyq-0007Ut-Mr for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:12:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbyn-0006wW-Fh for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:12:56 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.154.211]:43058) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbyn-0006pp-5e for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:12:53 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx1403.ess.rzc.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:12:44 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:12:15 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:09 +0100 Message-ID: <20180620120620.12806-25-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496721-321459-12806-48465-5 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.211 Subject: [Qemu-devel] [PATCH 24/35] target/mips: Add nanoMIPS CP0_BadInstrX register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Add nanoMIPS CP0_BadInstrX register Signed-off-by: Stefan Markovic Signed-off-by: Yongbok Kim --- target/mips/cpu.h | 1 + target/mips/helper.c | 6 ++++++ target/mips/machine.c | 1 + target/mips/translate.c | 18 ++++++++++++++++++ 4 files changed, 26 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 18f193d..c87184f 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -323,6 +323,7 @@ struct CPUMIPSState { target_ulong CP0_BadVAddr; uint32_t CP0_BadInstr; uint32_t CP0_BadInstrP; + uint32_t CP0_BadInstrX; int32_t CP0_Count; target_ulong CP0_EntryHi; #define CP0EnHi_EHINV 10 diff --git a/target/mips/helper.c b/target/mips/helper.c index 5299f21..9535131 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -695,6 +695,12 @@ static inline void set_badinstr_registers(CPUMIPSState= *env) instr |=3D cpu_lduw_code(env, env->active_tc.PC + 2); } env->CP0_BadInstr =3D instr; + + if ((env->insn_flags & ISA_NANOMIPS32) && + ((instr & 0xFC000000) =3D=3D 0x60000000)) { + instr =3D cpu_lduw_code(env, env->active_tc.PC + 4) << 16; + env->CP0_BadInstrX =3D instr; + } } if ((env->CP0_Config3 & (1 << CP0C3_BP)) && (env->hflags & MIPS_HFLAG_BMASK)) { diff --git a/target/mips/machine.c b/target/mips/machine.c index 20100d5..58f3255 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -266,6 +266,7 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU), VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU), VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU), + VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU), VMSTATE_INT32(env.CP0_Count, MIPSCPU), VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU), VMSTATE_INT32(env.CP0_Compare, MIPSCPU), diff --git a/target/mips/translate.c b/target/mips/translate.c index 8c20ba3..ece2293 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -5429,6 +5429,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP)); rn =3D "BadInstrP"; break; + case 3: + CP0_CHECK(ctx->bi); + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX)); + rn =3D "BadInstrX"; + break; default: goto cp0_unimplemented; } @@ -6098,6 +6103,10 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) /* ignored */ rn =3D "BadInstrP"; break; + case 3: + /* ignored */ + rn =3D "BadInstrX"; + break; default: goto cp0_unimplemented; } @@ -6781,6 +6790,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP)); rn =3D "BadInstrP"; break; + case 3: + CP0_CHECK(ctx->bi); + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX)); + rn =3D "BadInstrX"; + break; default: goto cp0_unimplemented; } @@ -7433,6 +7447,10 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) /* ignored */ rn =3D "BadInstrP"; break; + case 3: + /* ignored */ + rn =3D "BadInstrX"; + break; default: goto cp0_unimplemented; } --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497619421840.8378421404572; Wed, 20 Jun 2018 05:26:59 -0700 (PDT) Received: from localhost ([::1]:49099 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVcCI-0002XA-KQ for importer@patchew.org; Wed, 20 Jun 2018 08:26:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36413) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbzb-000888-Tu for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:13:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbzY-0007hN-Mi for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:13:43 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.154.210]:32786) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbzY-0007aR-Ci for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:13:40 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx1402.ess.rzc.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:13:31 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:13:29 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:10 +0100 Message-ID: <20180620120620.12806-26-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496811-321458-26242-48411-1 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.210 Subject: [Qemu-devel] [PATCH 25/35] target/mips: Config3.ISAOnExc is read only in nanoMIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Config3.ISAOnExc is read only in nanoMIPS Signed-off-by: Yongbok Kim --- target/mips/op_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 102a039..9946f77 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1734,7 +1734,8 @@ void helper_mtc0_config2(CPUMIPSState *env, target_ul= ong arg1) =20 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1) { - if (env->insn_flags & ASE_MICROMIPS) { + if ((env->insn_flags & ASE_MICROMIPS) && + !(env->insn_flags & ISA_NANOMIPS32)) { env->CP0_Config3 =3D (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC))= | (arg1 & (1 << CP0C3_ISA_ON_EXC)); } --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497495446915.6743840666885; Wed, 20 Jun 2018 05:24:55 -0700 (PDT) Received: from localhost ([::1]:49083 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVcAQ-0000I5-NZ for importer@patchew.org; Wed, 20 Jun 2018 08:24:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36490) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbzo-0008Kb-0w for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:13:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbzk-0007rW-Qf for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:13:56 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.154.210]:50615) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbzk-0007mm-Hy for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:13:52 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx1402.ess.rzc.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:13:42 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:13:31 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:11 +0100 Message-ID: <20180620120620.12806-27-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496811-321458-26242-48411-2 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.210 Subject: [Qemu-devel] [PATCH 26/35] target/mips: Fix nanoMIPS exception_resume_pc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: James Hogan We shouldn't set the ISA bit in CP0_EPC for nanoMIPS. Signed-off-by: James Hogan Signed-off-by: Yongbok Kim --- target/mips/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index 9535131..20a81aa 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -656,7 +656,8 @@ target_ulong exception_resume_pc (CPUMIPSState *env) target_ulong bad_pc; target_ulong isa_mode; =20 - isa_mode =3D !!(env->hflags & MIPS_HFLAG_M16); + isa_mode =3D env->hflags & MIPS_HFLAG_M16 && + !(env->insn_flags & ISA_NANOMIPS32); bad_pc =3D env->active_tc.PC | isa_mode; if (env->hflags & MIPS_HFLAG_BMASK) { /* If the exception was raised from a delay slot, come back to --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497980852377.7117031578789; Wed, 20 Jun 2018 05:33:00 -0700 (PDT) Received: from localhost ([::1]:49133 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVcIB-0007eK-TI for importer@patchew.org; Wed, 20 Jun 2018 08:32:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36542) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbzy-0008TF-87 for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:14:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbzv-0007y1-0I for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:14:06 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.154.210]:59138) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbzu-0007tv-NI for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:14:02 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx1402.ess.rzc.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:13:54 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:13:33 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:12 +0100 Message-ID: <20180620120620.12806-28-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496811-321458-26242-48411-3 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.210 Subject: [Qemu-devel] [PATCH 27/35] target/mips: Fix nanoMIPS set_hflags_for_handler X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: James Hogan We shouldn't clear M16 mode when entering an interrupt on nanoMIPS, otherwise we'll start interpreting the code as normal MIPS code. Signed-off-by: James Hogan Signed-off-by: Yongbok Kim --- target/mips/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/mips/helper.c b/target/mips/helper.c index 20a81aa..efc3f25 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -671,6 +671,9 @@ target_ulong exception_resume_pc (CPUMIPSState *env) #if !defined(CONFIG_USER_ONLY) static void set_hflags_for_handler (CPUMIPSState *env) { + if (env->insn_flags & ISA_NANOMIPS32) { + return; + } /* Exception handlers are entered in 32-bit mode. */ env->hflags &=3D ~(MIPS_HFLAG_M16); /* ...except that microMIPS lets you choose. */ --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497773564939.8127809597163; Wed, 20 Jun 2018 05:29:33 -0700 (PDT) Received: from localhost ([::1]:49111 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVcEu-0004zC-PU for importer@patchew.org; Wed, 20 Jun 2018 08:29:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36596) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVc09-0000BF-Cv for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:14:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVc06-00084X-5Q for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:14:17 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.154.210]:55708) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVc05-00080i-Rl for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:14:14 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx1402.ess.rzc.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:14:05 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:13:36 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:13 +0100 Message-ID: <20180620120620.12806-29-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496811-321458-26242-48411-4 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.210 Subject: [Qemu-devel] [PATCH 28/35] target/mips: Fix nanoMIPS set_pc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: James Hogan ERET and ERETNC shouldn't clear MIPS_HFLAG_M16 for nanoMIPS since there is no ISA bit, so fix set_pc() to skip the hflags update. Signed-off-by: James Hogan Signed-off-by: Yongbok Kim --- target/mips/op_helper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 9946f77..6f5e5a3 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2432,6 +2432,10 @@ static void debug_post_eret(CPUMIPSState *env) static void set_pc(CPUMIPSState *env, target_ulong error_pc) { env->active_tc.PC =3D error_pc & ~(target_ulong)1; + if (env->insn_flags & ISA_NANOMIPS32) { + /* Don't clear MIPS_HFLAG_M16 */ + return; + } if (error_pc & 1) { env->hflags |=3D MIPS_HFLAG_M16; } else { --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497960239205.21315589206017; Wed, 20 Jun 2018 05:32:40 -0700 (PDT) Received: from localhost ([::1]:49129 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVcHs-0007QM-E2 for importer@patchew.org; Wed, 20 Jun 2018 08:32:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36631) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVc0K-0000NB-3X for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:14:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVc0G-00089H-T1 for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:14:28 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.154.210]:37198) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVc0G-000863-JQ for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:14:24 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx1402.ess.rzc.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:14:15 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:13:38 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:14 +0100 Message-ID: <20180620120620.12806-30-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496811-321458-26242-48411-5 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.210 Subject: [Qemu-devel] [PATCH 29/35] target/mips: Fix ERET/ERETNC can cause ADEL exception X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Fix ERET/ERETNC can cause ADEL exception Signed-off-by: Yongbok Kim --- target/mips/op_helper.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 6f5e5a3..09ec20a 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2434,6 +2434,13 @@ static void set_pc(CPUMIPSState *env, target_ulong e= rror_pc) env->active_tc.PC =3D error_pc & ~(target_ulong)1; if (env->insn_flags & ISA_NANOMIPS32) { /* Don't clear MIPS_HFLAG_M16 */ + if (error_pc & 1) { + if (!(env->hflags & MIPS_HFLAG_DM)) { + env->CP0_BadVAddr =3D error_pc; + } + env->active_tc.PC =3D error_pc; + do_raise_exception(env, EXCP_AdEL, 0); + } return; } if (error_pc & 1) { @@ -2471,10 +2478,12 @@ void helper_eretnc(CPUMIPSState *env) void helper_deret(CPUMIPSState *env) { debug_pre_eret(env); - set_pc(env, env->CP0_DEPC); =20 env->hflags &=3D ~MIPS_HFLAG_DM; compute_hflags(env); + + set_pc(env, env->CP0_DEPC); + debug_post_eret(env); } #endif /* !CONFIG_USER_ONLY */ --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529497868679546.1358784893151; Wed, 20 Jun 2018 05:31:08 -0700 (PDT) Received: from localhost ([::1]:49121 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVcGR-0006Fr-RV for importer@patchew.org; Wed, 20 Jun 2018 08:31:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37004) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVc0t-0000xu-UF for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:15:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVc0q-00005H-K8 for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:15:03 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.150.225]:50551) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVc0q-0008T6-DF for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:15:00 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx27.ess.sfj.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:14:52 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:14:49 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:15 +0100 Message-ID: <20180620120620.12806-31-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496891-637137-2574-35451-1 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.150.225 Subject: [Qemu-devel] [PATCH 30/35] hw/mips: Add basic nanoMIPS boot code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Matthew Fortune Added very very basic R7 boot code but this is hacked in unconditionally currently. Yongbok: Fix to use right boot loader Signed-off-by: Yongbok Kim --- hw/mips/mips_malta.c | 75 +++++++++++++++++++++++++++++++++++++++++++++++-= ---- include/elf.h | 1 + 2 files changed, 70 insertions(+), 6 deletions(-) diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 494f84e..39f4c5b 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -619,6 +619,58 @@ static void network_init(PCIBus *pci_bus) a2 - 32-bit address of the environment variables table a3 - RAM size in bytes */ +static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr, + int64_t kernel_entry) +{ + uint16_t *p; + + /* Small bootloader */ + p =3D (uint16_t *)base; + +#define NM_HI1(VAL) (((VAL) >> 16) & 0x1f) +#define NM_HI2(VAL) \ + (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) &= 0x1)) +#define NM_LO(VAL) ((VAL) & 0xfff) + + stw_p(p++, 0x2800); stw_p(p++, 0x001c); /* bc to_here */ + stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */ + stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */ + stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */ + stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */ + stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */ + stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */ + stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */ + + /* to_here: */ + stw_p(p++, 0x0080); stw_p(p++, 0x0002); /* li a0,2 */ + stw_p(p++, 0xe3a0 | NM_HI1(ENVP_ADDR - 64)); + stw_p(p++, NM_HI2(ENVP_ADDR - 64)); + /* lui sp,%hi(ENVP_ADDR - 64) */ + stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_ADDR - 64)); + /* ori sp,sp,%lo(ENVP_ADDR - 64) */ + stw_p(p++, 0xe0a0 | NM_HI1(ENVP_ADDR)); + stw_p(p++, NM_HI2(ENVP_ADDR)); + /* lui a1,%hi(ENVP_ADDR) */ + stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_ADDR)); + /* ori a1,a1,%lo(ENVP_ADDR) */ + stw_p(p++, 0xe0c0 | NM_HI1(ENVP_ADDR + 8)); + stw_p(p++, NM_HI2(ENVP_ADDR + 8)); + /* lui a2,%hi(ENVP_ADDR + 8) */ + stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_ADDR + 8)); + /* ori a2,a2,%lo(ENVP_ADDR + 8) */ + stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size)); + stw_p(p++, NM_HI2(loaderparams.ram_low_size)); + /* lui a3,%hi(loaderparams.ram_low_size) */ + stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size)); + /* ori a3,a3,%lo(loaderparams.ram_low_size= ) */ + stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); + stw_p(p++, NM_HI2(kernel_entry)); + /* lui t9,%hi(kernel_entry) */ + stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry)); + /* ori t9,t9,%lo(kernel_entry) */ + stw_p(p++, 0x4bf9); stw_p(p++, 0x0000); + /* jalrc t8 */ +} =20 static void write_bootloader(uint8_t *base, int64_t run_addr, int64_t kernel_entry) @@ -812,10 +864,16 @@ static int64_t load_kernel (void) NULL, (uint64_t *)&kernel_entry, NULL, (uint64_t *)&kernel_high, big_endian, EM_MIPS, = 1, 0); if (kernel_size < 0) { - error_report("could not load kernel '%s': %s", - loaderparams.kernel_filename, - load_elf_strerror(kernel_size)); - exit(1); + kernel_size =3D load_elf(loaderparams.kernel_filename, + cpu_mips_kseg0_to_phys, NULL, + (uint64_t *)&kernel_entry, NULL, + (uint64_t *)&kernel_high, big_endian, EM_NANOMIPS, 1, = 0); + if (kernel_size < 0) { + error_report("could not load kernel '%s': %s", + loaderparams.kernel_filename, + load_elf_strerror(kernel_size)); + exit(1); + } } =20 /* Check where the kernel has been linked */ @@ -1093,8 +1151,13 @@ void mips_malta_init(MachineState *machine) loaderparams.initrd_filename =3D initrd_filename; kernel_entry =3D load_kernel(); =20 - write_bootloader(memory_region_get_ram_ptr(bios), - bootloader_run_addr, kernel_entry); + if (!cpu_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { + write_bootloader(memory_region_get_ram_ptr(bios), + bootloader_run_addr, kernel_entry); + } else { + write_bootloader_nanomips(memory_region_get_ram_ptr(bios), + bootloader_run_addr, kernel_entry); + } if (kvm_enabled()) { /* Write the bootloader code @ the end of RAM, 1MB reserved */ write_bootloader(memory_region_get_ram_ptr(ram_low_preio) + diff --git a/include/elf.h b/include/elf.h index 934dbbd..2f9c2e2 100644 --- a/include/elf.h +++ b/include/elf.h @@ -121,6 +121,7 @@ typedef int64_t Elf64_Sxword; =20 #define EM_RISCV 243 /* RISC-V */ =20 +#define EM_NANOMIPS 249 /* MIPS Tech nanoMIPS */ /* * This is an interim value that we will use until the committee comes * up with a final number. --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529498718242168.79861171685684; Wed, 20 Jun 2018 05:45:18 -0700 (PDT) Received: from localhost ([::1]:49215 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVcU7-0001Ez-Cy for importer@patchew.org; Wed, 20 Jun 2018 08:45:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37042) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVc12-000150-NB for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:15:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVc0z-0000DU-Fu for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:15:12 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.150.225]:51975) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVc0z-000076-9O for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:15:09 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx27.ess.sfj.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:15:02 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:14:51 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:16 +0100 Message-ID: <20180620120620.12806-32-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496891-637137-2574-35451-2 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.150.225 Subject: [Qemu-devel] [PATCH 31/35] mips_malta: Setup GT64120 BARs in nanoMIPS bootloader X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Paul Burton Setup the GT64120 BARs in the nanoMIPS bootloader, in the same way that they are setup in the MIPS32 bootloader. This is necessary for Linux to be able to access peripherals, including the UART. Signed-off-by: Paul Burton Signed-off-by: Yongbok Kim --- hw/mips/mips_malta.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 73 insertions(+) diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 39f4c5b..c4139d6 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -663,6 +663,79 @@ static void write_bootloader_nanomips(uint8_t *base, i= nt64_t run_addr, /* lui a3,%hi(loaderparams.ram_low_size) */ stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size)); /* ori a3,a3,%lo(loaderparams.ram_low_size= ) */ + + /* Load BAR registers as done by YAMON */ + stw_p(p++, 0xe040); stw_p(p++, 0x0681); + /* lui t1, %hi(0xb4000000) */ +#ifdef TARGET_WORDS_BIGENDIAN + stw_p(p++, 0xe020); stw_p(p++, 0x0be1); + /* lui t0, %hi(0xdf000000) */ +#else + stw_p(p++, 0x0020); stw_p(p++, 0x00df); + /* addiu[32] t0, $0, 0xdf */ +#endif + stw_p(p++, 0x8422); stw_p(p++, 0x9068); + /* sw t0, 0x68(t1) */ + + stw_p(p++, 0xe040); stw_p(p++, 0x077d); + /* lui t1, %hi(0xbbe00000) */ +#ifdef TARGET_WORDS_BIGENDIAN + stw_p(p++, 0xe020); stw_p(p++, 0x0801); + /* lui t0, %hi(0xc0000000) */ +#else + stw_p(p++, 0x0020); stw_p(p++, 0x00c0); + /* addiu[32] t0, $0, 0xc0 */ +#endif + stw_p(p++, 0x8422); stw_p(p++, 0x9048); + /* sw t0, 0x48(t1) */ +#ifdef TARGET_WORDS_BIGENDIAN + stw_p(p++, 0xe020); stw_p(p++, 0x0800); + /* lui t0, %hi(0x40000000) */ +#else + stw_p(p++, 0x0020); stw_p(p++, 0x0040); + /* addiu[32] t0, $0, 0x40 */ +#endif + stw_p(p++, 0x8422); stw_p(p++, 0x9050); + /* sw t0, 0x50(t1) */ + +#ifdef TARGET_WORDS_BIGENDIAN + stw_p(p++, 0xe020); stw_p(p++, 0x0001); + /* lui t0, %hi(0x80000000) */ +#else + stw_p(p++, 0x0020); stw_p(p++, 0x0080); + /* addiu[32] t0, $0, 0x80 */ +#endif + stw_p(p++, 0x8422); stw_p(p++, 0x9058); + /* sw t0, 0x58(t1) */ +#ifdef TARGET_WORDS_BIGENDIAN + stw_p(p++, 0xe020); stw_p(p++, 0x07e0); + /* lui t0, %hi(0x3f000000) */ +#else + stw_p(p++, 0x0020); stw_p(p++, 0x003f); + /* addiu[32] t0, $0, 0x3f */ +#endif + stw_p(p++, 0x8422); stw_p(p++, 0x9060); + /* sw t0, 0x60(t1) */ + +#ifdef TARGET_WORDS_BIGENDIAN + stw_p(p++, 0xe020); stw_p(p++, 0x0821); + /* lui t0, %hi(0xc1000000) */ +#else + stw_p(p++, 0x0020); stw_p(p++, 0x00c1); + /* addiu[32] t0, $0, 0xc1 */ +#endif + stw_p(p++, 0x8422); stw_p(p++, 0x9080); + /* sw t0, 0x80(t1) */ +#ifdef TARGET_WORDS_BIGENDIAN + stw_p(p++, 0xe020); stw_p(p++, 0x0bc0); + /* lui t0, %hi(0x5e000000) */ +#else + stw_p(p++, 0x0020); stw_p(p++, 0x005e); + /* addiu[32] t0, $0, 0x5e */ +#endif + stw_p(p++, 0x8422); stw_p(p++, 0x9088); + /* sw t0, 0x88(t1) */ + stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); stw_p(p++, NM_HI2(kernel_entry)); /* lui t9,%hi(kernel_entry) */ --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529498655056140.91295621136499; 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Wed, 20 Jun 2018 05:14:53 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:17 +0100 Message-ID: <20180620120620.12806-33-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496891-637137-2574-35451-3 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.150.225 Subject: [Qemu-devel] [PATCH 32/35] hw/mips: Fix semihosting argument passing for nanoMIPS bare metal X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Fix semihosting argument passing for nanoMIPS bare metal Signed-off-by: Yongbok Kim --- hw/mips/mips_malta.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index c4139d6..6207d83 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -642,7 +642,12 @@ static void write_bootloader_nanomips(uint8_t *base, i= nt64_t run_addr, stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */ =20 /* to_here: */ - stw_p(p++, 0x0080); stw_p(p++, 0x0002); /* li a0,2 */ + if (semihosting_get_argc()) { + /* Preserve a0 content as arguments have been passed */ + stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */ + } else { + stw_p(p++, 0x0080); stw_p(p++, 0x0002); /* li a0,2 */ + } stw_p(p++, 0xe3a0 | NM_HI1(ENVP_ADDR - 64)); stw_p(p++, NM_HI2(ENVP_ADDR - 64)); /* lui sp,%hi(ENVP_ADDR - 64) */ --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529498809760845.0195245237667; Wed, 20 Jun 2018 05:46:49 -0700 (PDT) Received: from localhost ([::1]:49228 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVcVa-0002WF-So for importer@patchew.org; Wed, 20 Jun 2018 08:46:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37104) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVc1H-0001Lw-98 for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:15:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVc1G-0000RY-Da for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:15:27 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.150.225]:36213) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVc1G-0000OL-3F for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:15:26 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx27.ess.sfj.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:15:18 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:14:56 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:18 +0100 Message-ID: <20180620120620.12806-34-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496891-637137-2574-35451-4 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.150.225 Subject: [Qemu-devel] [PATCH 33/35] target/mips: Fix gdbstub to read/write 64 bit FP registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Fix gdbstub to read/write 64 bit FP registers Signed-off-by: Yongbok Kim Reviewed-by: Aleksandar Markovic --- target/mips/gdbstub.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index 6d1fb70..18e0e6d 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -39,7 +39,7 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem= _buf, int n) return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0); default: if (env->CP0_Status & (1 << CP0St_FR)) { - return gdb_get_regl(mem_buf, + return gdb_get_reg64(mem_buf, env->active_fpu.fpr[n - 38].d); } else { return gdb_get_regl(mem_buf, @@ -100,6 +100,7 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *= mem_buf, int n) break; default: if (env->CP0_Status & (1 << CP0St_FR)) { + uint64_t tmp =3D ldq_p(mem_buf); env->active_fpu.fpr[n - 38].d =3D tmp; } else { env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] =3D tmp; --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 15294982349521013.7144862084363; Wed, 20 Jun 2018 05:37:14 -0700 (PDT) Received: from localhost ([::1]:49161 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVcMH-0002U8-2l for importer@patchew.org; Wed, 20 Jun 2018 08:37:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37159) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVc1P-0001Qt-SO for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:15:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVc1O-0000Vg-PP for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:15:35 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.150.225]:53349) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVc1O-0000Sw-IQ for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:15:34 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx27.ess.sfj.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:15:27 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:14:59 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:19 +0100 Message-ID: <20180620120620.12806-35-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496891-637137-2574-35451-5 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.150.225 Subject: [Qemu-devel] [PATCH 34/35] target/mips: Disable gdbstub nanoMIPS ISA bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: James Hogan nanoMIPS has no ISA bit in the PC, so remove the handling of the low bit of the PC in the MIPS gdbstub for nanoMIPS. This prevents the PC being read as e.g. 0xbfc00001, and prevents writing to the PC clearing MIPS_HFLAG_M16. Signed-off-by: James Hogan Signed-off-by: Yongbok Kim --- target/mips/gdbstub.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index 18e0e6d..559b69f 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -60,7 +60,8 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem= _buf, int n) return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause); case 37: return gdb_get_regl(mem_buf, env->active_tc.PC | - !!(env->hflags & MIPS_HFLAG_M16)); + (!(env->insn_flags & ISA_NANOMIPS32) = && + env->hflags & MIPS_HFLAG_M16)); case 72: return gdb_get_regl(mem_buf, 0); /* fp */ case 89: @@ -131,10 +132,12 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t= *mem_buf, int n) break; case 37: env->active_tc.PC =3D tmp & ~(target_ulong)1; - if (tmp & 1) { - env->hflags |=3D MIPS_HFLAG_M16; - } else { - env->hflags &=3D ~(MIPS_HFLAG_M16); + if (!(env->insn_flags & ISA_NANOMIPS32)) { + if (tmp & 1) { + env->hflags |=3D MIPS_HFLAG_M16; + } else { + env->hflags &=3D ~(MIPS_HFLAG_M16); + } } break; case 72: /* fp, ignored */ --=20 1.9.1 From nobody Sun Apr 28 19:22:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152949806461443.14179040205238; Wed, 20 Jun 2018 05:34:24 -0700 (PDT) Received: from localhost ([::1]:49138 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVcJb-0000HF-Pl for importer@patchew.org; Wed, 20 Jun 2018 08:34:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37493) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVc2W-0002KJ-MI for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:16:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVc2T-000152-FG for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:16:44 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.150.224]:48424) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVc2T-00012I-9v for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:16:41 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx30.ess.sfj.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:16:33 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:16:30 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:06:20 +0100 Message-ID: <20180620120620.12806-36-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496993-637140-32661-34638-1 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.150.224 Subject: [Qemu-devel] [PATCH 35/35] target/mips: Add I7200 CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Add I7200 CPU Reference: https://www.mips.com/products/warrior/i-class-i7200-multiprocessor-core/ Signed-off-by: Yongbok Kim --- target/mips/translate_init.inc.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.= inc.c index c7ba6ee..262ff29 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -449,6 +449,43 @@ const mips_def_t mips_defs[] =3D .insn_flags =3D CPU_MIPS32R6 | ASE_MICROMIPS, .mmu_type =3D MMU_TYPE_R4000, }, + { + .name =3D "I7200", + .CP0_PRid =3D 0x00010000, + .CP0_Config0 =3D MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR= ) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 =3D MIPS_CONFIG1 | (15 << CP0C1_MMU) | (2 << CP0C1_IS= ) | + (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS)= | + (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC)= | + (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 =3D MIPS_CONFIG2, + .CP0_Config3 =3D MIPS_CONFIG3 | (1 << CP0C3_CMGCR) | (1 << CP0C3_B= I) | + (3 << CP0C3_MMAR) | (1 << CP0C3_ISA_ON_EXC) | + (1 << CP0C3_ISA) | (1 << CP0C3_ULRI) | + (1 << CP0C3_RXI) | + (1 << CP0C3_VInt) | (1U << CP0C3_M) | (1 << CP0C3_M= T), + .CP0_Config4 =3D MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | + (2 << CP0C4_IE) | (1U << CP0C4_M), + .CP0_Config5 =3D MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB= ), + .CP0_Config5_rw_bitmask =3D (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | + (1 << CP0C5_UFE), + .CP0_LLAddr_rw_bitmask =3D 0, + .CP0_LLAddr_shift =3D 0, + .SYNCI_Step =3D 32, + .CCRes =3D 2, + .CP0_Status_rw_bitmask =3D 0x3058FF1F, + .CP0_PageGrain =3D (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | + (1U << CP0PG_RIE), + .CP0_PageGrain_rw_bitmask =3D 0, + .CP1_fcr0 =3D (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_= F64) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV= ), + .CP1_fcr31 =3D (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), + .SEGBITS =3D 32, + .PABITS =3D 32, + .insn_flags =3D CPU_NANOMIPS32 | ASE_MICROMIPS, + .mmu_type =3D MMU_TYPE_R4000, + }, #if defined(TARGET_MIPS64) { .name =3D "R4000", --=20 1.9.1