From nobody Sat May 4 02:20:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529441038305368.68496393310556; Tue, 19 Jun 2018 13:43:58 -0700 (PDT) Received: from localhost ([::1]:44951 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVNTp-000341-LT for importer@patchew.org; Tue, 19 Jun 2018 16:43:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35005) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVNSv-0002nP-8S for qemu-devel@nongnu.org; Tue, 19 Jun 2018 16:43:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVNSs-0003Su-2c for qemu-devel@nongnu.org; Tue, 19 Jun 2018 16:43:01 -0400 Received: from smtp62.i.mail.ru ([217.69.128.42]:33524) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVNSr-0003RB-Ma for qemu-devel@nongnu.org; Tue, 19 Jun 2018 16:42:57 -0400 Received: by smtp62.i.mail.ru with esmtpa (envelope-from ) id 1fVNSp-0003TA-54; Tue, 19 Jun 2018 23:42:55 +0300 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=Message-Id:Date:Subject:Cc:To:From; bh=YQaSsdVoZo4JyPCUuUxZxsRLtOd8ONzJHBWOVhVYSsg=; b=Shr4/8bFoqdmyuyFWnhrXKSBFALXiy+FdHGi5Eb6BnKMec5qw/UdpbMMFFVRCJdO2Id41i1uHRC/f4sJy5kmRQDrhSNxNp/1gWDBhCk0teJWCalvCko615vg/Ks2tyPRUkxUG9F0db9msezkTKcS25nZefzKm0wvYY7rrd4qoWE=; To: qemu-devel Date: Tue, 19 Jun 2018 23:42:37 +0300 Message-Id: <20180619204237.9931-1-jusual@mail.ru> X-Mailer: git-send-email 2.17.0 Authentication-Results: smtp62.i.mail.ru; auth=pass smtp.auth=jusual@mail.ru smtp.mailfrom=jusual@mail.ru X-7FA49CB5: 0D63561A33F958A5DE626CA71EE632E0BF29CFB9BB9A43EDC67AC315686ED4D30A6AB1C7CE11FEE3EB7D890E3377C531BA3038C0950A5D36B5C8C57E37DE458B4C7702A67D5C33162DBA43225CD8A89F0A35B161A8BF67C1DF8DB4D28FFA6F53754BDADB8594F4B043847C11F186F3C5E7DDDDC251EA7DABCC89B49CDF41148F458B267F216095A92623479134186CDE6BA297DBC24807EABDAD6C7F3747799A X-Mailru-Sender: 7766D515518070DE138AAC7428EA760DD8822C1D2024196340760EDE205B89F554FE240C5B5842527C4160E8B47E48163DDE9B364B0DF2898CB68AF7A628805D594FB4C9F0DBF412AE208404248635DF X-Mras: OK X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 217.69.128.42 Subject: [Qemu-devel] [PATCH] target/arm: Set strict alignment for ARMv6-M load/store X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Julia Suvorova via Qemu-devel Reply-To: Julia Suvorova Cc: Peter Maydell , Jim Mussared , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Stefan Hajnoczi , Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Unlike ARMv7-M, ARMv6-M only supports naturally aligned memory accesses for 16-bit halfword and 32-bit word accesses using the LDR, LDRH, LDRSH, STR and STRH instructions. Signed-off-by: Julia Suvorova --- target/arm/translate.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b988d379e7..d923cbe98e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1100,7 +1100,14 @@ static inline TCGv gen_aa32_addr(DisasContext *s, TC= Gv_i32 a32, TCGMemOp op) static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, TCGMemOp opc) { - TCGv addr =3D gen_aa32_addr(s, a32, opc); + TCGv addr; + + if (arm_dc_feature(s, ARM_FEATURE_M) && + !arm_dc_feature(s, ARM_FEATURE_V7)) { + opc |=3D MO_ALIGN; + } + + addr =3D gen_aa32_addr(s, a32, opc); tcg_gen_qemu_ld_i32(val, addr, index, opc); tcg_temp_free(addr); } @@ -1108,7 +1115,14 @@ static void gen_aa32_ld_i32(DisasContext *s, TCGv_i3= 2 val, TCGv_i32 a32, static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, TCGMemOp opc) { - TCGv addr =3D gen_aa32_addr(s, a32, opc); + TCGv addr; + + if (arm_dc_feature(s, ARM_FEATURE_M) && + !arm_dc_feature(s, ARM_FEATURE_V7)) { + opc |=3D MO_ALIGN; + } + + addr =3D gen_aa32_addr(s, a32, opc); tcg_gen_qemu_st_i32(val, addr, index, opc); tcg_temp_free(addr); } --=20 2.17.0