From nobody Thu May 2 09:22:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152934198353283.39937212794564; Mon, 18 Jun 2018 10:13:03 -0700 (PDT) Received: from localhost ([::1]:36104 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fUxiA-0008R4-Gc for importer@patchew.org; Mon, 18 Jun 2018 13:13:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56662) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fUxbM-0003Vx-Jn for qemu-devel@nongnu.org; Mon, 18 Jun 2018 13:06:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fUxbI-0002aa-Dj for qemu-devel@nongnu.org; Mon, 18 Jun 2018 13:06:00 -0400 Received: from 4.mo68.mail-out.ovh.net ([46.105.59.63]:36565) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fUxbI-0002Yh-2e for qemu-devel@nongnu.org; Mon, 18 Jun 2018 13:05:56 -0400 Received: from player729.ha.ovh.net (unknown [10.109.122.111]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id 7B3E3E75C6 for ; Mon, 18 Jun 2018 19:05:54 +0200 (CEST) Received: from zorba.kaod.org (LFbn-TOU-1-49-10.w86-201.abo.wanadoo.fr [86.201.141.10]) (Authenticated sender: clg@kaod.org) by player729.ha.ovh.net (Postfix) with ESMTPSA id 3C1505E0095; Mon, 18 Jun 2018 19:05:50 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org Date: Mon, 18 Jun 2018 19:05:39 +0200 Message-Id: <20180618170540.12143-2-clg@kaod.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20180618170540.12143-1-clg@kaod.org> References: <20180618170540.12143-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 16605334777088346963 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedthedruddtvddguddtjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.59.63 Subject: [Qemu-devel] [PATCH v3 1/2] ppc/pnv: introduce Pnv8Chip and Pnv9Chip models X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" It introduces a base PnvChip class from which the specific processor chip classes, Pnv8Chip and Pnv9Chip, inherit. Each of them needs to define an init and a realize routine which will create the controllers of the target processor. For the moment, the base PnvChip class handles the XSCOM bus and the cores. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv.h | 24 ++++- hw/ppc/pnv.c | 281 ++++++++++++++++++++++++++++++++---------------= ---- 2 files changed, 202 insertions(+), 103 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 563279f3e00c..86d5f54e5459 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -57,12 +57,32 @@ typedef struct PnvChip { MemoryRegion xscom_mmio; MemoryRegion xscom; AddressSpace xscom_as; +} PnvChip; + +#define TYPE_PNV8_CHIP "pnv8-chip" +#define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP) + +typedef struct Pnv8Chip { + /*< private >*/ + PnvChip parent_obj; + + /*< public >*/ MemoryRegion icp_mmio; =20 PnvLpcController lpc; PnvPsi psi; PnvOCC occ; -} PnvChip; +} Pnv8Chip; + +#define TYPE_PNV9_CHIP "pnv9-chip" +#define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP) + +typedef struct Pnv9Chip { + /*< private >*/ + PnvChip parent_obj; + + /*< public >*/ +} Pnv9Chip; =20 typedef struct PnvChipClass { /*< private >*/ @@ -75,6 +95,8 @@ typedef struct PnvChipClass { =20 hwaddr xscom_base; =20 + DeviceRealize parent_realize; + uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); Object *(*intc_create)(PnvChip *chip, Object *child, Error **errp); ISABus *(*isa_create)(PnvChip *chip, Error **errp); diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index ac828d133173..a29ea996b45d 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -531,12 +531,14 @@ static void pnv_reset(void) =20 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) { - return pnv_lpc_isa_create(&chip->lpc, true, errp); + Pnv8Chip *chip8 =3D PNV8_CHIP(chip); + return pnv_lpc_isa_create(&chip8->lpc, true, errp); } =20 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) { - return pnv_lpc_isa_create(&chip->lpc, false, errp); + Pnv8Chip *chip8 =3D PNV8_CHIP(chip); + return pnv_lpc_isa_create(&chip8->lpc, false, errp); } =20 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) @@ -725,6 +727,103 @@ static Object *pnv_chip_power9_intc_create(PnvChip *c= hip, Object *child, */ #define POWER9_CORE_MASK (0xffffffffffffffull) =20 +static void pnv_chip_power8_instance_init(Object *obj) +{ + Pnv8Chip *chip8 =3D PNV8_CHIP(obj); + + object_initialize(&chip8->psi, sizeof(chip8->psi), TYPE_PNV_PSI); + object_property_add_child(obj, "psi", OBJECT(&chip8->psi), NULL); + object_property_add_const_link(OBJECT(&chip8->psi), "xics", + OBJECT(qdev_get_machine()), &error_abor= t); + + object_initialize(&chip8->lpc, sizeof(chip8->lpc), TYPE_PNV_LPC); + object_property_add_child(obj, "lpc", OBJECT(&chip8->lpc), NULL); + object_property_add_const_link(OBJECT(&chip8->lpc), "psi", + OBJECT(&chip8->psi), &error_abort); + + object_initialize(&chip8->occ, sizeof(chip8->occ), TYPE_PNV_OCC); + object_property_add_child(obj, "occ", OBJECT(&chip8->occ), NULL); + object_property_add_const_link(OBJECT(&chip8->occ), "psi", + OBJECT(&chip8->psi), &error_abort); +} + +static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) + { + PnvChip *chip =3D PNV_CHIP(chip8); + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); + const char *typename =3D pnv_chip_core_typename(chip); + size_t typesize =3D object_type_get_instance_size(typename); + int i, j; + char *name; + XICSFabric *xi =3D XICS_FABRIC(qdev_get_machine()); + + name =3D g_strdup_printf("icp-%x", chip->chip_id); + memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); + g_free(name); + + sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); + + /* Map the ICP registers for each thread */ + for (i =3D 0; i < chip->nr_cores; i++) { + PnvCore *pnv_core =3D PNV_CORE(chip->cores + i * typesize); + int core_hwid =3D CPU_CORE(pnv_core)->core_id; + + for (j =3D 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { + uint32_t pir =3D pcc->core_pir(chip, core_hwid) + j; + PnvICPState *icp =3D PNV_ICP(xics_icp_get(xi, pir)); + + memory_region_add_subregion(&chip8->icp_mmio, pir << 12, + &icp->mmio); + } + } +} + +static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) +{ + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(dev); + PnvChip *chip =3D PNV_CHIP(dev); + Pnv8Chip *chip8 =3D PNV8_CHIP(dev); + Error *local_err =3D NULL; + + pcc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + /* Processor Service Interface (PSI) Host Bridge */ + object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), + "bar", &error_fatal); + object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local= _err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip8->psi.xscom_= regs); + + /* Create LPC controller */ + object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", + &error_fatal); + pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_re= gs); + + /* Interrupt Management Area. This is the memory region holding + * all the Interrupt Control Presenter (ICP) registers */ + pnv_chip_icp_realize(chip8, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + /* Create the simplified OCC model */ + object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local= _err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_re= gs); +} + static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -738,6 +837,9 @@ static void pnv_chip_power8e_class_init(ObjectClass *kl= ass, void *data) k->isa_create =3D pnv_chip_power8_isa_create; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8E"; + + device_class_set_parent_realize(dc, pnv_chip_power8_realize, + &k->parent_realize); } =20 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) @@ -753,6 +855,9 @@ static void pnv_chip_power8_class_init(ObjectClass *kla= ss, void *data) k->isa_create =3D pnv_chip_power8_isa_create; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8"; + + device_class_set_parent_realize(dc, pnv_chip_power8_realize, + &k->parent_realize); } =20 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) @@ -768,6 +873,25 @@ static void pnv_chip_power8nvl_class_init(ObjectClass = *klass, void *data) k->isa_create =3D pnv_chip_power8nvl_isa_create; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8NVL"; + + device_class_set_parent_realize(dc, pnv_chip_power8_realize, + &k->parent_realize); +} + +static void pnv_chip_power9_instance_init(Object *obj) +{ +} + +static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) +{ + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(dev); + Error *local_err =3D NULL; + + pcc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } } =20 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) @@ -783,6 +907,9 @@ static void pnv_chip_power9_class_init(ObjectClass *kla= ss, void *data) k->isa_create =3D pnv_chip_power9_isa_create; k->xscom_base =3D 0x00603fc00000000ull; dc->desc =3D "PowerNV Chip POWER9"; + + device_class_set_parent_realize(dc, pnv_chip_power9_realize, + &k->parent_realize); } =20 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) @@ -815,59 +942,9 @@ static void pnv_chip_core_sanitize(PnvChip *chip, Erro= r **errp) } } =20 -static void pnv_chip_init(Object *obj) +static void pnv_chip_instance_init(Object *obj) { - PnvChip *chip =3D PNV_CHIP(obj); - PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); - - chip->xscom_base =3D pcc->xscom_base; - - object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC); - object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL); - - object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI); - object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL); - object_property_add_const_link(OBJECT(&chip->psi), "xics", - OBJECT(qdev_get_machine()), &error_abor= t); - - object_initialize(&chip->occ, sizeof(chip->occ), TYPE_PNV_OCC); - object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL); - object_property_add_const_link(OBJECT(&chip->occ), "psi", - OBJECT(&chip->psi), &error_abort); - - /* The LPC controller needs PSI to generate interrupts */ - object_property_add_const_link(OBJECT(&chip->lpc), "psi", - OBJECT(&chip->psi), &error_abort); -} - -static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) -{ - PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); - const char *typename =3D pnv_chip_core_typename(chip); - size_t typesize =3D object_type_get_instance_size(typename); - int i, j; - char *name; - XICSFabric *xi =3D XICS_FABRIC(qdev_get_machine()); - - name =3D g_strdup_printf("icp-%x", chip->chip_id); - memory_region_init(&chip->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); - sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip->icp_mmio); - g_free(name); - - sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); - - /* Map the ICP registers for each thread */ - for (i =3D 0; i < chip->nr_cores; i++) { - PnvCore *pnv_core =3D PNV_CORE(chip->cores + i * typesize); - int core_hwid =3D CPU_CORE(pnv_core)->core_id; - - for (j =3D 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { - uint32_t pir =3D pcc->core_pir(chip, core_hwid) + j; - PnvICPState *icp =3D PNV_ICP(xics_icp_get(xi, pir)); - - memory_region_add_subregion(&chip->icp_mmio, pir << 12, &icp->= mmio); - } - } + PNV_CHIP(obj)->xscom_base =3D PNV_CHIP_GET_CLASS(obj)->xscom_base; } =20 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) @@ -951,37 +1028,6 @@ static void pnv_chip_realize(DeviceState *dev, Error = **errp) error_propagate(errp, error); return; } - - /* Create LPC controller */ - object_property_set_bool(OBJECT(&chip->lpc), true, "realized", - &error_fatal); - pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_reg= s); - - /* Interrupt Management Area. This is the memory region holding - * all the Interrupt Control Presenter (ICP) registers */ - pnv_chip_icp_realize(chip, &error); - if (error) { - error_propagate(errp, error); - return; - } - - /* Processor Service Interface (PSI) Host Bridge */ - object_property_set_int(OBJECT(&chip->psi), PNV_PSIHB_BASE(chip), - "bar", &error_fatal); - object_property_set_bool(OBJECT(&chip->psi), true, "realized", &error); - if (error) { - error_propagate(errp, error); - return; - } - pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip->psi.xscom_r= egs); - - /* Create the simplified OCC model */ - object_property_set_bool(OBJECT(&chip->occ), true, "realized", &error); - if (error) { - error_propagate(errp, error); - return; - } - pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip->occ.xscom_reg= s); } =20 static Property pnv_chip_properties[] =3D { @@ -1009,8 +1055,10 @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq) int i; =20 for (i =3D 0; i < pnv->num_chips; i++) { - if (ics_valid_irq(&pnv->chips[i]->psi.ics, irq)) { - return &pnv->chips[i]->psi.ics; + Pnv8Chip *chip8 =3D PNV8_CHIP(pnv->chips[i]); + + if (ics_valid_irq(&chip8->psi.ics, irq)) { + return &chip8->psi.ics; } } return NULL; @@ -1022,7 +1070,8 @@ static void pnv_ics_resend(XICSFabric *xi) int i; =20 for (i =3D 0; i < pnv->num_chips; i++) { - ics_resend(&pnv->chips[i]->psi.ics); + Pnv8Chip *chip8 =3D PNV8_CHIP(pnv->chips[i]); + ics_resend(&chip8->psi.ics); } } =20 @@ -1063,7 +1112,8 @@ static void pnv_pic_print_info(InterruptStatsProvider= *obj, } =20 for (i =3D 0; i < pnv->num_chips; i++) { - ics_pic_print_info(&pnv->chips[i]->psi.ics, mon); + Pnv8Chip *chip8 =3D PNV8_CHIP(pnv->chips[i]); + ics_pic_print_info(&chip8->psi.ics, mon); } } =20 @@ -1098,7 +1148,7 @@ static void pnv_set_num_chips(Object *obj, Visitor *v= , const char *name, pnv->num_chips =3D num_chips; } =20 -static void pnv_machine_initfn(Object *obj) +static void pnv_machine_instance_init(Object *obj) { PnvMachineState *pnv =3D PNV_MACHINE(obj); pnv->num_chips =3D 1; @@ -1138,11 +1188,18 @@ static void pnv_machine_class_init(ObjectClass *oc,= void *data) pnv_machine_class_props_init(oc); } =20 -#define DEFINE_PNV_CHIP_TYPE(type, class_initfn) \ - { \ - .name =3D type, \ - .class_init =3D class_initfn, \ - .parent =3D TYPE_PNV_CHIP, \ +#define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ + { \ + .name =3D type, \ + .class_init =3D class_initfn, \ + .parent =3D TYPE_PNV8_CHIP, \ + } + +#define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ + { \ + .name =3D type, \ + .class_init =3D class_initfn, \ + .parent =3D TYPE_PNV9_CHIP, \ } =20 static const TypeInfo types[] =3D { @@ -1150,7 +1207,7 @@ static const TypeInfo types[] =3D { .name =3D TYPE_PNV_MACHINE, .parent =3D TYPE_MACHINE, .instance_size =3D sizeof(PnvMachineState), - .instance_init =3D pnv_machine_initfn, + .instance_init =3D pnv_machine_instance_init, .class_init =3D pnv_machine_class_init, .interfaces =3D (InterfaceInfo[]) { { TYPE_XICS_FABRIC }, @@ -1162,16 +1219,36 @@ static const TypeInfo types[] =3D { .name =3D TYPE_PNV_CHIP, .parent =3D TYPE_SYS_BUS_DEVICE, .class_init =3D pnv_chip_class_init, - .instance_init =3D pnv_chip_init, + .instance_init =3D pnv_chip_instance_init, .instance_size =3D sizeof(PnvChip), .class_size =3D sizeof(PnvChipClass), .abstract =3D true, }, - DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), - DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), - DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_ini= t), - DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, - pnv_chip_power8nvl_class_init), + + /* + * P9 chip and variants + */ + { + .name =3D TYPE_PNV9_CHIP, + .parent =3D TYPE_PNV_CHIP, + .instance_init =3D pnv_chip_power9_instance_init, + .instance_size =3D sizeof(Pnv9Chip), + }, + DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init= ), + + /* + * P8 chip and variants + */ + { + .name =3D TYPE_PNV8_CHIP, + .parent =3D TYPE_PNV_CHIP, + .instance_init =3D pnv_chip_power8_instance_init, + .instance_size =3D sizeof(Pnv8Chip), + }, + DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init= ), + DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_in= it), + DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, + pnv_chip_power8nvl_class_init), }; =20 DEFINE_TYPES(types) --=20 2.13.6 From nobody Thu May 2 09:22:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529342943927616.9653476702001; Mon, 18 Jun 2018 10:29:03 -0700 (PDT) Received: from localhost ([::1]:36210 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fUxxe-0003Gw-MH for importer@patchew.org; Mon, 18 Jun 2018 13:29:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56688) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fUxbQ-0003Zl-GX for qemu-devel@nongnu.org; Mon, 18 Jun 2018 13:06:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fUxbM-0002eV-Fm for qemu-devel@nongnu.org; Mon, 18 Jun 2018 13:06:04 -0400 Received: from 9.mo173.mail-out.ovh.net ([46.105.72.44]:38637) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fUxbM-0002dY-9d for qemu-devel@nongnu.org; Mon, 18 Jun 2018 13:06:00 -0400 Received: from player729.ha.ovh.net (unknown [10.109.122.92]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id B3EA8C5717 for ; Mon, 18 Jun 2018 19:05:58 +0200 (CEST) Received: from zorba.kaod.org (LFbn-TOU-1-49-10.w86-201.abo.wanadoo.fr [86.201.141.10]) (Authenticated sender: clg@kaod.org) by player729.ha.ovh.net (Postfix) with ESMTPSA id 6AAB95E009D; Mon, 18 Jun 2018 19:05:54 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org Date: Mon, 18 Jun 2018 19:05:40 +0200 Message-Id: <20180618170540.12143-3-clg@kaod.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20180618170540.12143-1-clg@kaod.org> References: <20180618170540.12143-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 16606460678812306259 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedthedruddtvddguddtjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.72.44 Subject: [Qemu-devel] [PATCH v3 2/2] ppc/pnv: consolidate the creation of the ISA bus device tree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The device tree node of the ISA bus was being partially done in different places. Move all the nodes creation under the same routine. Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 51 +++++++++++++++++++++++---------------------------- 1 file changed, 23 insertions(+), 28 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index a29ea996b45d..7401ffe5b01c 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -265,18 +265,6 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint3= 2_t pir, g_free(reg); } =20 -static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt) -{ - char *name; - int offset; - - name =3D g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", - (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_= BASE); - offset =3D fdt_path_offset(fdt, name); - g_free(name); - return offset; -} - static void pnv_dt_chip(PnvChip *chip, void *fdt) { const char *typename =3D pnv_chip_core_typename(chip); @@ -285,16 +273,6 @@ static void pnv_dt_chip(PnvChip *chip, void *fdt) =20 pnv_dt_xscom(chip, fdt, 0); =20 - /* The default LPC bus of a multichip system is on chip 0. It's - * recognized by the firmware (skiboot) using a "primary" - * property. - */ - if (chip->chip_id =3D=3D 0x0) { - int lpc_offset =3D pnv_chip_lpc_offset(chip, fdt); - - _FDT((fdt_setprop(fdt, lpc_offset, "primary", NULL, 0))); - } - for (i =3D 0; i < chip->nr_cores; i++) { PnvCore *pnv_core =3D PNV_CORE(chip->cores + i * typesize); =20 @@ -418,16 +396,35 @@ static int pnv_dt_isa_device(DeviceState *dev, void *= opaque) return 0; } =20 -static void pnv_dt_isa(ISABus *bus, void *fdt, int lpc_offset) +static int pnv_chip_isa_offset(PnvChip *chip, void *fdt) +{ + char *name; + int offset; + + name =3D g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", + (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_= BASE); + offset =3D fdt_path_offset(fdt, name); + g_free(name); + return offset; +} + +/* The default LPC bus of a multichip system is on chip 0. It's + * recognized by the firmware (skiboot) using a "primary" property. + */ +static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) { + int isa_offset =3D pnv_chip_isa_offset(pnv->chips[0], fdt); ForeachPopulateArgs args =3D { .fdt =3D fdt, - .offset =3D lpc_offset, + .offset =3D isa_offset, }; =20 + _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); + /* ISA devices are not necessarily parented to the ISA bus so we * can not use object_child_foreach() */ - qbus_walk_children(BUS(bus), pnv_dt_isa_device, NULL, NULL, NULL, &arg= s); + qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, N= ULL, + &args); } =20 static void *pnv_dt_create(MachineState *machine) @@ -438,7 +435,6 @@ static void *pnv_dt_create(MachineState *machine) char *buf; int off; int i; - int lpc_offset; =20 fdt =3D g_malloc0(FDT_MAX_SIZE); _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); @@ -480,8 +476,7 @@ static void *pnv_dt_create(MachineState *machine) } =20 /* Populate ISA devices on chip 0 */ - lpc_offset =3D pnv_chip_lpc_offset(pnv->chips[0], fdt); - pnv_dt_isa(pnv->isa_bus, fdt, lpc_offset); + pnv_dt_isa(pnv, fdt); =20 if (pnv->bmc) { pnv_dt_bmc_sensors(pnv->bmc, fdt); --=20 2.13.6