From nobody Mon Apr 29 12:35:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152907899148924.857745710982954; Fri, 15 Jun 2018 09:09:51 -0700 (PDT) Received: from localhost ([::1]:47858 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTrIL-00063L-RF for importer@patchew.org; Fri, 15 Jun 2018 12:09:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50391) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTqbp-0003sD-8C for qemu-devel@nongnu.org; Fri, 15 Jun 2018 11:25:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fTqbm-0006ZX-2v for qemu-devel@nongnu.org; Fri, 15 Jun 2018 11:25:53 -0400 Received: from 12.mo5.mail-out.ovh.net ([46.105.39.65]:56395) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fTqbl-0006Ym-PV for qemu-devel@nongnu.org; Fri, 15 Jun 2018 11:25:49 -0400 Received: from player794.ha.ovh.net (unknown [10.109.120.58]) by mo5.mail-out.ovh.net (Postfix) with ESMTP id 6C0ED1C1D6A for ; Fri, 15 Jun 2018 17:25:47 +0200 (CEST) Received: from zorba.kaod.org (LFbn-TOU-1-49-10.w86-201.abo.wanadoo.fr [86.201.141.10]) (Authenticated sender: clg@kaod.org) by player794.ha.ovh.net (Postfix) with ESMTPSA id 23C121400AF; Fri, 15 Jun 2018 17:25:43 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org Date: Fri, 15 Jun 2018 17:25:33 +0200 Message-Id: <20180615152536.30093-2-clg@kaod.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20180615152536.30093-1-clg@kaod.org> References: <20180615152536.30093-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 15743176925332605779 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedthedrleeigdekudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.39.65 Subject: [Qemu-devel] [PATCH v2 1/4] ppc/pnv: introduce a new intc_create() operation to the chip model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On Power9, the thread interrupt presenter has a different type and is linked to the chip owning the cores. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv.h | 1 + hw/ppc/pnv.c | 21 +++++++++++++++++++-- hw/ppc/pnv_core.c | 18 +++++++++--------- 3 files changed, 29 insertions(+), 11 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 90759240a7b1..e934e84f555e 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -76,6 +76,7 @@ typedef struct PnvChipClass { hwaddr xscom_base; =20 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); + Object *(*intc_create)(PnvChip *chip, Object *child, Error **errp); } PnvChipClass; =20 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0d2b79f7980f..c7e127ae97db 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -671,6 +671,13 @@ static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, ui= nt32_t core_id) return (chip->chip_id << 7) | (core_id << 3); } =20 +static Object *pnv_chip_power8_intc_create(PnvChip *chip, Object *child, + Error **errp) +{ + return icp_create(child, TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), + errp); +} + /* * 0:48 Reserved - Read as zeroes * 49:52 Node ID @@ -686,6 +693,12 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, ui= nt32_t core_id) return (chip->chip_id << 8) | (core_id << 2); } =20 +static Object *pnv_chip_power9_intc_create(PnvChip *chip, Object *child, + Error **errp) +{ + return NULL; +} + /* Allowed core identifiers on a POWER8 Processor Chip : * * @@ -721,6 +734,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *kl= ass, void *data) k->chip_cfam_id =3D 0x221ef04980000000ull; /* P8 Murano DD2.1 */ k->cores_mask =3D POWER8E_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p8; + k->intc_create =3D pnv_chip_power8_intc_create; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8E"; } @@ -734,6 +748,7 @@ static void pnv_chip_power8_class_init(ObjectClass *kla= ss, void *data) k->chip_cfam_id =3D 0x220ea04980000000ull; /* P8 Venice DD2.0 */ k->cores_mask =3D POWER8_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p8; + k->intc_create =3D pnv_chip_power8_intc_create; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8"; } @@ -747,6 +762,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *= klass, void *data) k->chip_cfam_id =3D 0x120d304980000000ull; /* P8 Naples DD1.0 */ k->cores_mask =3D POWER8_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p8; + k->intc_create =3D pnv_chip_power8_intc_create; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8NVL"; } @@ -760,6 +776,7 @@ static void pnv_chip_power9_class_init(ObjectClass *kla= ss, void *data) k->chip_cfam_id =3D 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ k->cores_mask =3D POWER9_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p9; + k->intc_create =3D pnv_chip_power9_intc_create; k->xscom_base =3D 0x00603fc00000000ull; dc->desc =3D "PowerNV Chip POWER9"; } @@ -892,8 +909,8 @@ static void pnv_chip_core_realize(PnvChip *chip, Error = **errp) object_property_set_int(OBJECT(pnv_core), pcc->core_pir(chip, core_hwid), "pir", &error_fatal); - object_property_add_const_link(OBJECT(pnv_core), "xics", - qdev_get_machine(), &error_fatal); + object_property_add_const_link(OBJECT(pnv_core), "chip", + OBJECT(chip), &error_fatal); object_property_set_bool(OBJECT(pnv_core), true, "realized", &error_fatal); object_unref(OBJECT(pnv_core)); diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index f7cf33f547a5..a9f129fc2c5f 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -99,13 +99,14 @@ static const MemoryRegionOps pnv_core_xscom_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 -static void pnv_realize_vcpu(PowerPCCPU *cpu, XICSFabric *xi, Error **errp) +static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp) { CPUPPCState *env =3D &cpu->env; int core_pir; int thread_index =3D 0; /* TODO: TCG supports only one thread */ ppc_spr_t *pir =3D &env->spr_cb[SPR_PIR]; Error *local_err =3D NULL; + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); =20 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); if (local_err) { @@ -113,7 +114,7 @@ static void pnv_realize_vcpu(PowerPCCPU *cpu, XICSFabri= c *xi, Error **errp) return; } =20 - cpu->intc =3D icp_create(OBJECT(cpu), TYPE_PNV_ICP, xi, &local_err); + cpu->intc =3D pcc->intc_create(chip, OBJECT(cpu), &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -143,13 +144,12 @@ static void pnv_core_realize(DeviceState *dev, Error = **errp) void *obj; int i, j; char name[32]; - Object *xi; + Object *chip; =20 - xi =3D object_property_get_link(OBJECT(dev), "xics", &local_err); - if (!xi) { - error_setg(errp, "%s: required link 'xics' not found: %s", - __func__, error_get_pretty(local_err)); - return; + chip =3D object_property_get_link(OBJECT(dev), "chip", &local_err); + if (!chip) { + error_propagate(errp, local_err); + error_prepend(errp, "required link 'chip' not found: "); } =20 pc->threads =3D g_new(PowerPCCPU *, cc->nr_threads); @@ -166,7 +166,7 @@ static void pnv_core_realize(DeviceState *dev, Error **= errp) } =20 for (j =3D 0; j < cc->nr_threads; j++) { - pnv_realize_vcpu(pc->threads[j], XICS_FABRIC(xi), &local_err); + pnv_realize_vcpu(pc->threads[j], PNV_CHIP(chip), &local_err); if (local_err) { goto err; } --=20 2.13.6 From nobody Mon Apr 29 12:35:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529077290305652.4799832079512; Fri, 15 Jun 2018 08:41:30 -0700 (PDT) Received: from localhost ([::1]:47633 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTqqv-0008Ik-9e for importer@patchew.org; Fri, 15 Jun 2018 11:41:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50426) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTqbs-0003vp-Uw for qemu-devel@nongnu.org; Fri, 15 Jun 2018 11:25:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fTqbp-0006dL-Pt for qemu-devel@nongnu.org; Fri, 15 Jun 2018 11:25:56 -0400 Received: from 6.mo68.mail-out.ovh.net ([46.105.63.100]:45507) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fTqbp-0006bM-Ft for qemu-devel@nongnu.org; Fri, 15 Jun 2018 11:25:53 -0400 Received: from player794.ha.ovh.net (unknown [10.109.108.22]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id E139CE7C91 for ; Fri, 15 Jun 2018 17:25:51 +0200 (CEST) Received: from zorba.kaod.org (LFbn-TOU-1-49-10.w86-201.abo.wanadoo.fr [86.201.141.10]) (Authenticated sender: clg@kaod.org) by player794.ha.ovh.net (Postfix) with ESMTPSA id 51FDA1400B1; Fri, 15 Jun 2018 17:25:47 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org Date: Fri, 15 Jun 2018 17:25:34 +0200 Message-Id: <20180615152536.30093-3-clg@kaod.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20180615152536.30093-1-clg@kaod.org> References: <20180615152536.30093-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 15744302823166348115 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedthedrleeigdekudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.63.100 Subject: [Qemu-devel] [PATCH v2 2/4] ppc/pnv: introduce a new isa_create() operation to the chip model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This moves the details of the ISA bus creation under the LPC model but more important, the new PnvChip operation will let us choose the chip class to use when we introduce the different chip classes for Power9 and Power8. It hides away the processor chip controllers from the machine. Signed-off-by: C=C3=A9dric Le Goater --- pnv_isa_create() is a onliner but it looks better like that than to use it directly with pnv->chips[0] include/hw/ppc/pnv.h | 1 + include/hw/ppc/pnv_lpc.h | 3 +-- hw/ppc/pnv.c | 34 +++++++++++++++++++--------------- hw/ppc/pnv_lpc.c | 30 +++++++++++++++++++++++++----- 4 files changed, 46 insertions(+), 22 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index e934e84f555e..563279f3e00c 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -77,6 +77,7 @@ typedef struct PnvChipClass { =20 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); Object *(*intc_create)(PnvChip *chip, Object *child, Error **errp); + ISABus *(*isa_create)(PnvChip *chip, Error **errp); } PnvChipClass; =20 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 53fdd5bb6450..d657489b07ce 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -70,7 +70,6 @@ typedef struct PnvLpcController { PnvPsi *psi; } PnvLpcController; =20 -qemu_irq *pnv_lpc_isa_irq_create(PnvLpcController *lpc, int chip_type, - int nirqs); +ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **e= rrp); =20 #endif /* _PPC_PNV_LPC_H */ diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index c7e127ae97db..ac828d133173 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -529,24 +529,24 @@ static void pnv_reset(void) cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); } =20 -static ISABus *pnv_isa_create(PnvChip *chip) +static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) { - PnvLpcController *lpc =3D &chip->lpc; - ISABus *isa_bus; - qemu_irq *irqs; - PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); + return pnv_lpc_isa_create(&chip->lpc, true, errp); +} =20 - /* let isa_bus_new() create its own bridge on SysBus otherwise - * devices speficied on the command line won't find the bus and - * will fail to create. - */ - isa_bus =3D isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, - &error_fatal); +static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) +{ + return pnv_lpc_isa_create(&chip->lpc, false, errp); +} =20 - irqs =3D pnv_lpc_isa_irq_create(lpc, pcc->chip_type, ISA_NUM_IRQS); +static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) +{ + return NULL; +} =20 - isa_bus_irqs(isa_bus, irqs); - return isa_bus; +static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) +{ + return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); } =20 static void pnv_init(MachineState *machine) @@ -646,7 +646,7 @@ static void pnv_init(MachineState *machine) g_free(chip_typename); =20 /* Instantiate ISA bus on chip 0 */ - pnv->isa_bus =3D pnv_isa_create(pnv->chips[0]); + pnv->isa_bus =3D pnv_isa_create(pnv->chips[0], &error_fatal); =20 /* Create serial port */ serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); @@ -735,6 +735,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *kl= ass, void *data) k->cores_mask =3D POWER8E_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p8; k->intc_create =3D pnv_chip_power8_intc_create; + k->isa_create =3D pnv_chip_power8_isa_create; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8E"; } @@ -749,6 +750,7 @@ static void pnv_chip_power8_class_init(ObjectClass *kla= ss, void *data) k->cores_mask =3D POWER8_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p8; k->intc_create =3D pnv_chip_power8_intc_create; + k->isa_create =3D pnv_chip_power8_isa_create; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8"; } @@ -763,6 +765,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *= klass, void *data) k->cores_mask =3D POWER8_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p8; k->intc_create =3D pnv_chip_power8_intc_create; + k->isa_create =3D pnv_chip_power8nvl_isa_create; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8NVL"; } @@ -777,6 +780,7 @@ static void pnv_chip_power9_class_init(ObjectClass *kla= ss, void *data) k->cores_mask =3D POWER9_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p9; k->intc_create =3D pnv_chip_power9_intc_create; + k->isa_create =3D pnv_chip_power9_isa_create; k->xscom_base =3D 0x00603fc00000000ull; dc->desc =3D "PowerNV Chip POWER9"; } diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 402c4fefa886..d7721320a25b 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -22,6 +22,7 @@ #include "target/ppc/cpu.h" #include "qapi/error.h" #include "qemu/log.h" +#include "hw/isa/isa.h" =20 #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_lpc.h" @@ -535,16 +536,35 @@ static void pnv_lpc_isa_irq_handler(void *opaque, int= n, int level) } } =20 -qemu_irq *pnv_lpc_isa_irq_create(PnvLpcController *lpc, int chip_type, - int nirqs) +ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **e= rrp) { + Error *local_err =3D NULL; + ISABus *isa_bus; + qemu_irq *irqs; + qemu_irq_handler handler; + + /* let isa_bus_new() create its own bridge on SysBus otherwise + * devices speficied on the command line won't find the bus and + * will fail to create. + */ + isa_bus =3D isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return NULL; + } + /* Not all variants have a working serial irq decoder. If not, * handling of LPC interrupts becomes a platform issue (some * platforms have a CPLD to do it). */ - if (chip_type =3D=3D PNV_CHIP_POWER8NVL) { - return qemu_allocate_irqs(pnv_lpc_isa_irq_handler, lpc, nirqs); + if (use_cpld) { + handler =3D pnv_lpc_isa_irq_handler_cpld; } else { - return qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, lpc, nirqs= ); + handler =3D pnv_lpc_isa_irq_handler; } + + irqs =3D qemu_allocate_irqs(handler, lpc, ISA_NUM_IRQS); + + isa_bus_irqs(isa_bus, irqs); + return isa_bus; } --=20 2.13.6 From nobody Mon Apr 29 12:35:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529078626829586.2317609405208; Fri, 15 Jun 2018 09:03:46 -0700 (PDT) Received: from localhost ([::1]:47805 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTrCT-0001Kl-UD for importer@patchew.org; Fri, 15 Jun 2018 12:03:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50456) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTqbw-0003zP-V6 for qemu-devel@nongnu.org; Fri, 15 Jun 2018 11:26:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fTqbt-0006ir-Lp for qemu-devel@nongnu.org; Fri, 15 Jun 2018 11:26:00 -0400 Received: from 6.mo69.mail-out.ovh.net ([46.105.50.107]:38511) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fTqbt-0006gj-BH for qemu-devel@nongnu.org; Fri, 15 Jun 2018 11:25:57 -0400 Received: from player794.ha.ovh.net (unknown [10.109.120.29]) by mo69.mail-out.ovh.net (Postfix) with ESMTP id D334219692 for ; Fri, 15 Jun 2018 17:25:55 +0200 (CEST) Received: from zorba.kaod.org (LFbn-TOU-1-49-10.w86-201.abo.wanadoo.fr [86.201.141.10]) (Authenticated sender: clg@kaod.org) by player794.ha.ovh.net (Postfix) with ESMTPSA id 8042E1400AF; Fri, 15 Jun 2018 17:25:51 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org Date: Fri, 15 Jun 2018 17:25:35 +0200 Message-Id: <20180615152536.30093-4-clg@kaod.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20180615152536.30093-1-clg@kaod.org> References: <20180615152536.30093-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 15745428723075812179 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedthedrleeigdekudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.50.107 Subject: [Qemu-devel] [PATCH v2 3/4] ppc/pnv: introduce Pnv8Chip and Pnv9Chip models X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This is a major reshuffle of the PowerNV machine and chip models to introduce a machine type per processor. It is quite noisy but it doesn't change much the code flow. It introduces a base PnvChip class from which the specific processor chip classes, Pnv8Chip and Pnv9Chip, inherit. Each of them needs to define an init and a realize routine which will create the controllers of the target processor. For the moment, the base PnvChip class handles the XSCOM bus and the cores but the core creation will surely move to the specific processor chip classes because of the new XIVE interrupt controller in Power9. From there, we introduce two different machines : "powernv8" and "powernv9" but, a part from the XICSFabric interface, this is not strictly needed as it is the cpu type which determines the PnvChip class. Something to discuss. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv.h | 23 +++- hw/ppc/pnv.c | 322 +++++++++++++++++++++++++++++++++--------------= ---- 2 files changed, 231 insertions(+), 114 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 563279f3e00c..244856414580 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -57,12 +57,32 @@ typedef struct PnvChip { MemoryRegion xscom_mmio; MemoryRegion xscom; AddressSpace xscom_as; +} PnvChip; + +#define TYPE_PNV8_CHIP "pnv8-chip" +#define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP) + +typedef struct Pnv8Chip { + /*< private >*/ + PnvChip parent_obj; + + /*< public >*/ MemoryRegion icp_mmio; =20 PnvLpcController lpc; PnvPsi psi; PnvOCC occ; -} PnvChip; +} Pnv8Chip; + +#define TYPE_PNV9_CHIP "pnv9-chip" +#define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP) + +typedef struct Pnv9Chip { + /*< private >*/ + PnvChip parent_obj; + + /*< public >*/ +} Pnv9Chip; =20 typedef struct PnvChipClass { /*< private >*/ @@ -75,6 +95,7 @@ typedef struct PnvChipClass { =20 hwaddr xscom_base; =20 + void (*realize)(PnvChip *chip, Error **errp); uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); Object *(*intc_create)(PnvChip *chip, Object *child, Error **errp); ISABus *(*isa_create)(PnvChip *chip, Error **errp); diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index ac828d133173..b416a1a6ed63 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -531,12 +531,14 @@ static void pnv_reset(void) =20 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) { - return pnv_lpc_isa_create(&chip->lpc, true, errp); + Pnv8Chip *chip8 =3D PNV8_CHIP(chip); + return pnv_lpc_isa_create(&chip8->lpc, true, errp); } =20 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) { - return pnv_lpc_isa_create(&chip->lpc, false, errp); + Pnv8Chip *chip8 =3D PNV8_CHIP(chip); + return pnv_lpc_isa_create(&chip8->lpc, false, errp); } =20 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) @@ -725,6 +727,97 @@ static Object *pnv_chip_power9_intc_create(PnvChip *ch= ip, Object *child, */ #define POWER9_CORE_MASK (0xffffffffffffffull) =20 +static void pnv_chip_power8_instance_init(Object *obj) +{ + Pnv8Chip *chip8 =3D PNV8_CHIP(obj); + + object_initialize(&chip8->lpc, sizeof(chip8->lpc), TYPE_PNV_LPC); + object_property_add_child(obj, "lpc", OBJECT(&chip8->lpc), NULL); + + object_initialize(&chip8->psi, sizeof(chip8->psi), TYPE_PNV_PSI); + object_property_add_child(obj, "psi", OBJECT(&chip8->psi), NULL); + object_property_add_const_link(OBJECT(&chip8->psi), "xics", + OBJECT(qdev_get_machine()), &error_abor= t); + + object_initialize(&chip8->occ, sizeof(chip8->occ), TYPE_PNV_OCC); + object_property_add_child(obj, "occ", OBJECT(&chip8->occ), NULL); + object_property_add_const_link(OBJECT(&chip8->occ), "psi", + OBJECT(&chip8->psi), &error_abort); + + /* The LPC controller needs PSI to generate interrupts */ + object_property_add_const_link(OBJECT(&chip8->lpc), "psi", + OBJECT(&chip8->psi), &error_abort); +} + +static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) + { + PnvChip *chip =3D PNV_CHIP(chip8); + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); + const char *typename =3D pnv_chip_core_typename(chip); + size_t typesize =3D object_type_get_instance_size(typename); + int i, j; + char *name; + XICSFabric *xi =3D XICS_FABRIC(qdev_get_machine()); + + name =3D g_strdup_printf("icp-%x", chip->chip_id); + memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); + g_free(name); + + sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); + + /* Map the ICP registers for each thread */ + for (i =3D 0; i < chip->nr_cores; i++) { + PnvCore *pnv_core =3D PNV_CORE(chip->cores + i * typesize); + int core_hwid =3D CPU_CORE(pnv_core)->core_id; + + for (j =3D 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { + uint32_t pir =3D pcc->core_pir(chip, core_hwid) + j; + PnvICPState *icp =3D PNV_ICP(xics_icp_get(xi, pir)); + + memory_region_add_subregion(&chip8->icp_mmio, pir << 12, + &icp->mmio); + } + } +} + +static void pnv_chip_power8_realize(PnvChip *chip, Error **errp) + { + Pnv8Chip *chip8 =3D PNV8_CHIP(chip); + Error *error =3D NULL; + + /* Create LPC controller */ + object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", + &error_fatal); + pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_re= gs); + + /* Interrupt Management Area. This is the memory region holding + * all the Interrupt Control Presenter (ICP) registers */ + pnv_chip_icp_realize(chip8, &error); + if (error) { + error_propagate(errp, error); + return; + } + + /* Processor Service Interface (PSI) Host Bridge */ + object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), + "bar", &error_fatal); + object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &error= ); + if (error) { + error_propagate(errp, error); + return; + } + pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip8->psi.xscom_= regs); + + /* Create the simplified OCC model */ + object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &error= ); + if (error) { + error_propagate(errp, error); + return; + } + pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_re= gs); +} + static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -736,6 +829,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *kl= ass, void *data) k->core_pir =3D pnv_chip_core_pir_p8; k->intc_create =3D pnv_chip_power8_intc_create; k->isa_create =3D pnv_chip_power8_isa_create; + k->realize =3D pnv_chip_power8_realize; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8E"; } @@ -751,6 +845,7 @@ static void pnv_chip_power8_class_init(ObjectClass *kla= ss, void *data) k->core_pir =3D pnv_chip_core_pir_p8; k->intc_create =3D pnv_chip_power8_intc_create; k->isa_create =3D pnv_chip_power8_isa_create; + k->realize =3D pnv_chip_power8_realize; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8"; } @@ -766,10 +861,20 @@ static void pnv_chip_power8nvl_class_init(ObjectClass= *klass, void *data) k->core_pir =3D pnv_chip_core_pir_p8; k->intc_create =3D pnv_chip_power8_intc_create; k->isa_create =3D pnv_chip_power8nvl_isa_create; + k->realize =3D pnv_chip_power8_realize; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8NVL"; } =20 +static void pnv_chip_power9_instance_init(Object *obj) +{ +} + +static void pnv_chip_power9_realize(PnvChip *chip, Error **errp) +{ + +} + static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -781,6 +886,7 @@ static void pnv_chip_power9_class_init(ObjectClass *kla= ss, void *data) k->core_pir =3D pnv_chip_core_pir_p9; k->intc_create =3D pnv_chip_power9_intc_create; k->isa_create =3D pnv_chip_power9_isa_create; + k->realize =3D pnv_chip_power9_realize; k->xscom_base =3D 0x00603fc00000000ull; dc->desc =3D "PowerNV Chip POWER9"; } @@ -815,59 +921,9 @@ static void pnv_chip_core_sanitize(PnvChip *chip, Erro= r **errp) } } =20 -static void pnv_chip_init(Object *obj) +static void pnv_chip_instance_init(Object *obj) { - PnvChip *chip =3D PNV_CHIP(obj); - PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); - - chip->xscom_base =3D pcc->xscom_base; - - object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC); - object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL); - - object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI); - object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL); - object_property_add_const_link(OBJECT(&chip->psi), "xics", - OBJECT(qdev_get_machine()), &error_abor= t); - - object_initialize(&chip->occ, sizeof(chip->occ), TYPE_PNV_OCC); - object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL); - object_property_add_const_link(OBJECT(&chip->occ), "psi", - OBJECT(&chip->psi), &error_abort); - - /* The LPC controller needs PSI to generate interrupts */ - object_property_add_const_link(OBJECT(&chip->lpc), "psi", - OBJECT(&chip->psi), &error_abort); -} - -static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) -{ - PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); - const char *typename =3D pnv_chip_core_typename(chip); - size_t typesize =3D object_type_get_instance_size(typename); - int i, j; - char *name; - XICSFabric *xi =3D XICS_FABRIC(qdev_get_machine()); - - name =3D g_strdup_printf("icp-%x", chip->chip_id); - memory_region_init(&chip->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); - sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip->icp_mmio); - g_free(name); - - sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); - - /* Map the ICP registers for each thread */ - for (i =3D 0; i < chip->nr_cores; i++) { - PnvCore *pnv_core =3D PNV_CORE(chip->cores + i * typesize); - int core_hwid =3D CPU_CORE(pnv_core)->core_id; - - for (j =3D 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { - uint32_t pir =3D pcc->core_pir(chip, core_hwid) + j; - PnvICPState *icp =3D PNV_ICP(xics_icp_get(xi, pir)); - - memory_region_add_subregion(&chip->icp_mmio, pir << 12, &icp->= mmio); - } - } + PNV_CHIP(obj)->xscom_base =3D PNV_CHIP_GET_CLASS(obj)->xscom_base; } =20 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) @@ -935,6 +991,7 @@ static void pnv_chip_core_realize(PnvChip *chip, Error = **errp) static void pnv_chip_realize(DeviceState *dev, Error **errp) { PnvChip *chip =3D PNV_CHIP(dev); + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); Error *error =3D NULL; =20 /* XSCOM bridge */ @@ -952,36 +1009,7 @@ static void pnv_chip_realize(DeviceState *dev, Error = **errp) return; } =20 - /* Create LPC controller */ - object_property_set_bool(OBJECT(&chip->lpc), true, "realized", - &error_fatal); - pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_reg= s); - - /* Interrupt Management Area. This is the memory region holding - * all the Interrupt Control Presenter (ICP) registers */ - pnv_chip_icp_realize(chip, &error); - if (error) { - error_propagate(errp, error); - return; - } - - /* Processor Service Interface (PSI) Host Bridge */ - object_property_set_int(OBJECT(&chip->psi), PNV_PSIHB_BASE(chip), - "bar", &error_fatal); - object_property_set_bool(OBJECT(&chip->psi), true, "realized", &error); - if (error) { - error_propagate(errp, error); - return; - } - pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip->psi.xscom_r= egs); - - /* Create the simplified OCC model */ - object_property_set_bool(OBJECT(&chip->occ), true, "realized", &error); - if (error) { - error_propagate(errp, error); - return; - } - pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip->occ.xscom_reg= s); + pcc->realize(chip, errp); } =20 static Property pnv_chip_properties[] =3D { @@ -1003,26 +1031,29 @@ static void pnv_chip_class_init(ObjectClass *klass,= void *data) dc->desc =3D "PowerNV Chip"; } =20 -static ICSState *pnv_ics_get(XICSFabric *xi, int irq) +static ICSState *pnv8_ics_get(XICSFabric *xi, int irq) { PnvMachineState *pnv =3D PNV_MACHINE(xi); int i; =20 for (i =3D 0; i < pnv->num_chips; i++) { - if (ics_valid_irq(&pnv->chips[i]->psi.ics, irq)) { - return &pnv->chips[i]->psi.ics; + Pnv8Chip *chip8 =3D PNV8_CHIP(pnv->chips[i]); + + if (ics_valid_irq(&chip8->psi.ics, irq)) { + return &chip8->psi.ics; } } return NULL; } =20 -static void pnv_ics_resend(XICSFabric *xi) +static void pnv8_ics_resend(XICSFabric *xi) { PnvMachineState *pnv =3D PNV_MACHINE(xi); int i; =20 for (i =3D 0; i < pnv->num_chips; i++) { - ics_resend(&pnv->chips[i]->psi.ics); + Pnv8Chip *chip8 =3D PNV8_CHIP(pnv->chips[i]); + ics_resend(&chip8->psi.ics); } } =20 @@ -1042,15 +1073,14 @@ static PowerPCCPU *ppc_get_vcpu_by_pir(int pir) return NULL; } =20 -static ICPState *pnv_icp_get(XICSFabric *xi, int pir) +static ICPState *pnv8_icp_get(XICSFabric *xi, int pir) { PowerPCCPU *cpu =3D ppc_get_vcpu_by_pir(pir); =20 return cpu ? ICP(cpu->intc) : NULL; } =20 -static void pnv_pic_print_info(InterruptStatsProvider *obj, - Monitor *mon) +static void pnv8_pic_print_info(InterruptStatsProvider *obj, Monitor *mon) { PnvMachineState *pnv =3D PNV_MACHINE(obj); int i; @@ -1063,7 +1093,8 @@ static void pnv_pic_print_info(InterruptStatsProvider= *obj, } =20 for (i =3D 0; i < pnv->num_chips; i++) { - ics_pic_print_info(&pnv->chips[i]->psi.ics, mon); + Pnv8Chip *chip8 =3D PNV8_CHIP(pnv->chips[i]); + ics_pic_print_info(&chip8->psi.ics, mon); } } =20 @@ -1098,7 +1129,7 @@ static void pnv_set_num_chips(Object *obj, Visitor *v= , const char *name, pnv->num_chips =3D num_chips; } =20 -static void pnv_machine_initfn(Object *obj) +static void pnv_machine_instance_init(Object *obj) { PnvMachineState *pnv =3D PNV_MACHINE(obj); pnv->num_chips =3D 1; @@ -1117,8 +1148,6 @@ static void pnv_machine_class_props_init(ObjectClass = *oc) static void pnv_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); - XICSFabricClass *xic =3D XICS_FABRIC_CLASS(oc); - InterruptStatsProviderClass *ispc =3D INTERRUPT_STATS_PROVIDER_CLASS(o= c); =20 mc->desc =3D "IBM PowerNV (Non-Virtualized)"; mc->init =3D pnv_init; @@ -1130,48 +1159,115 @@ static void pnv_machine_class_init(ObjectClass *oc= , void *data) mc->no_parallel =3D 1; mc->default_boot_order =3D NULL; mc->default_ram_size =3D 1 * G_BYTE; - xic->icp_get =3D pnv_icp_get; - xic->ics_get =3D pnv_ics_get; - xic->ics_resend =3D pnv_ics_resend; - ispc->print_info =3D pnv_pic_print_info; =20 pnv_machine_class_props_init(oc); } =20 -#define DEFINE_PNV_CHIP_TYPE(type, class_initfn) \ - { \ - .name =3D type, \ - .class_init =3D class_initfn, \ - .parent =3D TYPE_PNV_CHIP, \ +static void pnv8_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + XICSFabricClass *xic =3D XICS_FABRIC_CLASS(oc); + InterruptStatsProviderClass *ispc =3D INTERRUPT_STATS_PROVIDER_CLASS(o= c); + + /* Power8 is the default */ + mc->desc =3D "IBM PowerNV (Non-Virtualized) Power8"; + mc->alias =3D "powernv"; + mc->is_default =3D 1; + + xic->icp_get =3D pnv8_icp_get; + xic->ics_get =3D pnv8_ics_get; + xic->ics_resend =3D pnv8_ics_resend; + ispc->print_info =3D pnv8_pic_print_info; +} + +static void pnv9_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "IBM PowerNV (Non-Virtualized) Power9"; + mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power9_v2.0"); +} + +#define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ + { \ + .name =3D type, \ + .class_init =3D class_initfn, \ + .parent =3D TYPE_PNV8_CHIP, \ + } + +#define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ + { \ + .name =3D type, \ + .class_init =3D class_initfn, \ + .parent =3D TYPE_PNV9_CHIP, \ } =20 static const TypeInfo types[] =3D { + /* + * PowerNV machines and variants + */ { .name =3D TYPE_PNV_MACHINE, .parent =3D TYPE_MACHINE, + .abstract =3D true, .instance_size =3D sizeof(PnvMachineState), - .instance_init =3D pnv_machine_initfn, + .instance_init =3D pnv_machine_instance_init, .class_init =3D pnv_machine_class_init, .interfaces =3D (InterfaceInfo[]) { - { TYPE_XICS_FABRIC }, { TYPE_INTERRUPT_STATS_PROVIDER }, { }, }, }, { + .name =3D MACHINE_TYPE_NAME("powernv9"), + .parent =3D TYPE_PNV_MACHINE, + .class_init =3D pnv9_machine_class_init, + }, + { + .name =3D MACHINE_TYPE_NAME("powernv8"), + .parent =3D TYPE_PNV_MACHINE, + .class_init =3D pnv8_machine_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_XICS_FABRIC }, + { }, + }, + }, + + /* Power Chip */ + { .name =3D TYPE_PNV_CHIP, .parent =3D TYPE_SYS_BUS_DEVICE, .class_init =3D pnv_chip_class_init, - .instance_init =3D pnv_chip_init, + .instance_init =3D pnv_chip_instance_init, .instance_size =3D sizeof(PnvChip), .class_size =3D sizeof(PnvChipClass), .abstract =3D true, }, - DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), - DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), - DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_ini= t), - DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, - pnv_chip_power8nvl_class_init), + + /* + * P9 chips and variants + */ + { + .name =3D TYPE_PNV9_CHIP, + .parent =3D TYPE_PNV_CHIP, + .instance_init =3D pnv_chip_power9_instance_init, + .instance_size =3D sizeof(Pnv9Chip), + }, + DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init= ), + + /* + * P8 chips and variants + */ + { + .name =3D TYPE_PNV8_CHIP, + .parent =3D TYPE_PNV_CHIP, + .instance_init =3D pnv_chip_power8_instance_init, + .instance_size =3D sizeof(Pnv8Chip), + }, + DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init= ), + DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_in= it), + DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, + pnv_chip_power8nvl_class_init), }; =20 DEFINE_TYPES(types) --=20 2.13.6 From nobody Mon Apr 29 12:35:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529078834906753.5978935800539; Fri, 15 Jun 2018 09:07:14 -0700 (PDT) Received: from localhost ([::1]:47828 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTrFp-0003xZ-6x for importer@patchew.org; Fri, 15 Jun 2018 12:07:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50488) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTqc0-00042a-Cv for qemu-devel@nongnu.org; Fri, 15 Jun 2018 11:26:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fTqbx-0006mv-8E for qemu-devel@nongnu.org; Fri, 15 Jun 2018 11:26:04 -0400 Received: from 10.mo177.mail-out.ovh.net ([46.105.73.133]:53177) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fTqbx-0006mH-29 for qemu-devel@nongnu.org; Fri, 15 Jun 2018 11:26:01 -0400 Received: from player794.ha.ovh.net (unknown [10.109.122.50]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id EA3BAB68D6 for ; Fri, 15 Jun 2018 17:25:59 +0200 (CEST) Received: from zorba.kaod.org (LFbn-TOU-1-49-10.w86-201.abo.wanadoo.fr [86.201.141.10]) (Authenticated sender: clg@kaod.org) by player794.ha.ovh.net (Postfix) with ESMTPSA id B0DB51400B4; Fri, 15 Jun 2018 17:25:55 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org Date: Fri, 15 Jun 2018 17:25:36 +0200 Message-Id: <20180615152536.30093-5-clg@kaod.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20180615152536.30093-1-clg@kaod.org> References: <20180615152536.30093-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 15746554626117372755 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedthedrleeigdekudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.73.133 Subject: [Qemu-devel] [PATCH v2 4/4] ppc/pnv: consolidate the creation of the ISA bus device tree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The device tree node of the ISA bus was being partially done in different places. Move all the nodes creation under the same routine. Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 51 +++++++++++++++++++++++---------------------------- 1 file changed, 23 insertions(+), 28 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index b416a1a6ed63..8969ccdd7ba3 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -265,18 +265,6 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint3= 2_t pir, g_free(reg); } =20 -static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt) -{ - char *name; - int offset; - - name =3D g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", - (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_= BASE); - offset =3D fdt_path_offset(fdt, name); - g_free(name); - return offset; -} - static void pnv_dt_chip(PnvChip *chip, void *fdt) { const char *typename =3D pnv_chip_core_typename(chip); @@ -285,16 +273,6 @@ static void pnv_dt_chip(PnvChip *chip, void *fdt) =20 pnv_dt_xscom(chip, fdt, 0); =20 - /* The default LPC bus of a multichip system is on chip 0. It's - * recognized by the firmware (skiboot) using a "primary" - * property. - */ - if (chip->chip_id =3D=3D 0x0) { - int lpc_offset =3D pnv_chip_lpc_offset(chip, fdt); - - _FDT((fdt_setprop(fdt, lpc_offset, "primary", NULL, 0))); - } - for (i =3D 0; i < chip->nr_cores; i++) { PnvCore *pnv_core =3D PNV_CORE(chip->cores + i * typesize); =20 @@ -418,16 +396,35 @@ static int pnv_dt_isa_device(DeviceState *dev, void *= opaque) return 0; } =20 -static void pnv_dt_isa(ISABus *bus, void *fdt, int lpc_offset) +static int pnv_chip_isa_offset(PnvChip *chip, void *fdt) +{ + char *name; + int offset; + + name =3D g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", + (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_= BASE); + offset =3D fdt_path_offset(fdt, name); + g_free(name); + return offset; +} + +/* The default LPC bus of a multichip system is on chip 0. It's + * recognized by the firmware (skiboot) using a "primary" property. + */ +static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) { + int isa_offset =3D pnv_chip_isa_offset(pnv->chips[0], fdt); ForeachPopulateArgs args =3D { .fdt =3D fdt, - .offset =3D lpc_offset, + .offset =3D isa_offset, }; =20 + _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); + /* ISA devices are not necessarily parented to the ISA bus so we * can not use object_child_foreach() */ - qbus_walk_children(BUS(bus), pnv_dt_isa_device, NULL, NULL, NULL, &arg= s); + qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, N= ULL, + &args); } =20 static void *pnv_dt_create(MachineState *machine) @@ -438,7 +435,6 @@ static void *pnv_dt_create(MachineState *machine) char *buf; int off; int i; - int lpc_offset; =20 fdt =3D g_malloc0(FDT_MAX_SIZE); _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); @@ -480,8 +476,7 @@ static void *pnv_dt_create(MachineState *machine) } =20 /* Populate ISA devices on chip 0 */ - lpc_offset =3D pnv_chip_lpc_offset(pnv->chips[0], fdt); - pnv_dt_isa(pnv->isa_bus, fdt, lpc_offset); + pnv_dt_isa(pnv, fdt); =20 if (pnv->bmc) { pnv_dt_bmc_sensors(pnv->bmc, fdt); --=20 2.13.6