From nobody Sat May 4 23:59:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529048121580794.0448086862261; Fri, 15 Jun 2018 00:35:21 -0700 (PDT) Received: from localhost ([::1]:44806 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTjGS-0007EH-OH for importer@patchew.org; Fri, 15 Jun 2018 03:35:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48984) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTjEU-0006BV-Ee for qemu-devel@nongnu.org; Fri, 15 Jun 2018 03:33:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fTjES-0003ZT-0g for qemu-devel@nongnu.org; Fri, 15 Jun 2018 03:33:18 -0400 Received: from chuckie.co.uk ([82.165.15.123]:36408 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fTjER-0003Z3-Ml for qemu-devel@nongnu.org; Fri, 15 Jun 2018 03:33:15 -0400 Received: from host86-191-128-6.range86-191.btcentralplus.com ([86.191.128.6] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1fTjEd-0006UD-Rj; Fri, 15 Jun 2018 08:33:29 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com, richard.henderson@linaro.org, cota@braap.org Date: Fri, 15 Jun 2018 08:33:03 +0100 Message-Id: <20180615073303.502-2-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180615073303.502-1-mark.cave-ayland@ilande.co.uk> References: <20180615073303.502-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.191.128.6 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [RFC PATCH v4 1/1] SPARC64: add icount support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds gen_io_start()/gen_io_end() to various instructions as requ= ired in order to boot my OpenBIOS test images on qemu-system-sparc64 with icount enabled. Signed-off-by: Mark Cave-Ayland Acked-by: Artyom Tarasenko Reviewed-by: Richard Henderson --- target/sparc/translate.c | 111 +++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 110 insertions(+), 1 deletion(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index f3d430c1b2..74315cdf09 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -41,6 +41,8 @@ #define JUMP_PC 2 /* dynamic pc value which takes only two values according to jump_pc[T2] */ =20 +#define DISAS_EXIT DISAS_TARGET_0 + /* global register indexes */ static TCGv_ptr cpu_regwptr; static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst; @@ -3400,11 +3402,17 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) r_const =3D tcg_const_i32(dc->mem_idx); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, tick)); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_tick_get_count(cpu_dst, cpu_env, r_tick= ptr, r_const); tcg_temp_free_ptr(r_tickptr); tcg_temp_free_i32(r_const); gen_store_gpr(dc, rd, cpu_dst); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } } break; case 0x5: /* V9 rdpc */ @@ -3447,11 +3455,17 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) r_const =3D tcg_const_i32(dc->mem_idx); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, stick)); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_tick_get_count(cpu_dst, cpu_env, r_tick= ptr, r_const); tcg_temp_free_ptr(r_tickptr); tcg_temp_free_i32(r_const); gen_store_gpr(dc, rd, cpu_dst); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } } break; case 0x19: /* System tick compare */ @@ -3576,10 +3590,16 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) r_const =3D tcg_const_i32(dc->mem_idx); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, tick)); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_tick_get_count(cpu_tmp0, cpu_env, r_tickptr, r_const); tcg_temp_free_ptr(r_tickptr); tcg_temp_free_i32(r_const); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } } break; case 5: // tba @@ -4385,9 +4405,19 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) r_tickptr =3D tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState,= tick)); + if (tb_cflags(dc->base.tb) & + CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_tick_set_limit(r_tickptr, cpu_tick_cmp= r); tcg_temp_free_ptr(r_tickptr); + if (tb_cflags(dc->base.tb) & + CF_USE_ICOUNT) { + gen_io_end(); + } + /* End TB to handle timer interrupt */ + dc->base.is_jmp =3D DISAS_EXIT; } break; case 0x18: /* System tick */ @@ -4403,9 +4433,19 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) r_tickptr =3D tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState,= stick)); + if (tb_cflags(dc->base.tb) & + CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_tick_set_count(r_tickptr, cpu_tmp0); tcg_temp_free_ptr(r_tickptr); + if (tb_cflags(dc->base.tb) & + CF_USE_ICOUNT) { + gen_io_end(); + } + /* End TB to handle timer interrupt */ + dc->base.is_jmp =3D DISAS_EXIT; } break; case 0x19: /* System tick compare */ @@ -4421,9 +4461,19 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) r_tickptr =3D tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState,= stick)); + if (tb_cflags(dc->base.tb) & + CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_tick_set_limit(r_tickptr, cpu_stick_cm= pr); tcg_temp_free_ptr(r_tickptr); + if (tb_cflags(dc->base.tb) & + CF_USE_ICOUNT) { + gen_io_end(); + } + /* End TB to handle timer interrupt */ + dc->base.is_jmp =3D DISAS_EXIT; } break; =20 @@ -4531,9 +4581,19 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) r_tickptr =3D tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState,= tick)); + if (tb_cflags(dc->base.tb) & + CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_tick_set_count(r_tickptr, cpu_tmp0); tcg_temp_free_ptr(r_tickptr); + if (tb_cflags(dc->base.tb) & + CF_USE_ICOUNT) { + gen_io_end(); + } + /* End TB to handle timer interrupt */ + dc->base.is_jmp =3D DISAS_EXIT; } break; case 5: // tba @@ -4541,7 +4601,13 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) break; case 6: // pstate save_state(dc); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT= ) { + gen_io_start(); + } gen_helper_wrpstate(cpu_env, cpu_tmp0); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT= ) { + gen_io_end(); + } dc->npc =3D DYNAMIC_PC; break; case 7: // tl @@ -4551,7 +4617,13 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) dc->npc =3D DYNAMIC_PC; break; case 8: // pil + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT= ) { + gen_io_start(); + } gen_helper_wrpil(cpu_env, cpu_tmp0); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT= ) { + gen_io_end(); + } break; case 9: // cwp gen_helper_wrcwp(cpu_env, cpu_tmp0); @@ -4642,9 +4714,19 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) r_tickptr =3D tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState,= hstick)); + if (tb_cflags(dc->base.tb) & + CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_tick_set_limit(r_tickptr, cpu_hstick_c= mpr); tcg_temp_free_ptr(r_tickptr); + if (tb_cflags(dc->base.tb) & + CF_USE_ICOUNT) { + gen_io_end(); + } + /* End TB to handle timer interrupt */ + dc->base.is_jmp =3D DISAS_EXIT; } break; case 6: // hver readonly @@ -5265,14 +5347,26 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) goto priv_insn; dc->npc =3D DYNAMIC_PC; dc->pc =3D DYNAMIC_PC; + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_done(cpu_env); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } goto jmp_insn; case 1: if (!supervisor(dc)) goto priv_insn; dc->npc =3D DYNAMIC_PC; dc->pc =3D DYNAMIC_PC; + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_retry(cpu_env); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } goto jmp_insn; default: goto illegal_insn; @@ -5822,7 +5916,9 @@ static void sparc_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - if (dc->base.is_jmp !=3D DISAS_NORETURN) { + switch (dc->base.is_jmp) { + case DISAS_NEXT: + case DISAS_TOO_MANY: if (dc->pc !=3D DYNAMIC_PC && (dc->npc !=3D DYNAMIC_PC && dc->npc !=3D JUMP_PC)) { /* static PC and NPC: we can use direct chaining */ @@ -5834,6 +5930,19 @@ static void sparc_tr_tb_stop(DisasContextBase *dcbas= e, CPUState *cs) save_npc(dc); tcg_gen_exit_tb(NULL, 0); } + break; + + case DISAS_NORETURN: + break; + + case DISAS_EXIT: + /* Exit TB */ + save_state(dc); + tcg_gen_exit_tb(NULL, 0); + break; + + default: + g_assert_not_reached(); } } =20 --=20 2.11.0