From nobody Thu May 2 21:33:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528985017169935.9993153028164; Thu, 14 Jun 2018 07:03:37 -0700 (PDT) Received: from localhost ([::1]:40857 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTSqV-0000WN-8u for importer@patchew.org; Thu, 14 Jun 2018 10:03:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54401) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTSoD-0007fI-0c for qemu-devel@nongnu.org; Thu, 14 Jun 2018 10:01:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fTSo9-0008Sw-Tk for qemu-devel@nongnu.org; Thu, 14 Jun 2018 10:01:05 -0400 Received: from 3.mo1.mail-out.ovh.net ([46.105.60.232]:55450) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fTSo9-0008Rg-MT for qemu-devel@nongnu.org; Thu, 14 Jun 2018 10:01:01 -0400 Received: from player738.ha.ovh.net (unknown [10.109.105.21]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 1FBEE108439 for ; Thu, 14 Jun 2018 16:01:00 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-TOU-1-49-10.w86-201.abo.wanadoo.fr [86.201.141.10]) (Authenticated sender: clg@kaod.org) by player738.ha.ovh.net (Postfix) with ESMTPSA id D001A595; Thu, 14 Jun 2018 16:00:55 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org Date: Thu, 14 Jun 2018 16:00:38 +0200 Message-Id: <20180614140043.9231-2-clg@kaod.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20180614140043.9231-1-clg@kaod.org> References: <20180614140043.9231-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 8438338329175755603 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedthedrleefgdejudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.60.232 Subject: [Qemu-devel] [PATCH 1/6] ppc/pnv: introduce a 'primary' field under the LPC model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" When a PowerNV system is started, the firmware (skiboot) looks for a "primary" property to determine which LPC bus is the default on a multichip system. This property is currently populated in the main routine creating the device tree of a chip, which is the not the right place to do so. Check the chip id to flag the LPC controller as "primary", or not, and use that to add the property in the LPC device tree routine. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv_lpc.h | 2 ++ hw/ppc/pnv.c | 19 ++++++------------- hw/ppc/pnv_lpc.c | 29 ++++++++++++++++++++--------- 3 files changed, 28 insertions(+), 22 deletions(-) diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 53fdd5bb6450..fddcb1c054b3 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -68,6 +68,8 @@ typedef struct PnvLpcController { =20 /* PSI to generate interrupts */ PnvPsi *psi; + + bool primary; } PnvLpcController; =20 qemu_irq *pnv_lpc_isa_irq_create(PnvLpcController *lpc, int chip_type, diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 031488131629..b419d3323100 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -285,16 +285,6 @@ static void pnv_dt_chip(PnvChip *chip, void *fdt) =20 pnv_dt_xscom(chip, fdt, 0); =20 - /* The default LPC bus of a multichip system is on chip 0. It's - * recognized by the firmware (skiboot) using a "primary" - * property. - */ - if (chip->chip_id =3D=3D 0x0) { - int lpc_offset =3D pnv_chip_lpc_offset(chip, fdt); - - _FDT((fdt_setprop(fdt, lpc_offset, "primary", NULL, 0))); - } - for (i =3D 0; i < chip->nr_cores; i++) { PnvCore *pnv_core =3D PNV_CORE(chip->cores + i * typesize); =20 @@ -814,9 +804,12 @@ static void pnv_chip_init(Object *obj) object_property_add_const_link(OBJECT(&chip->occ), "psi", OBJECT(&chip->psi), &error_abort); =20 - /* The LPC controller needs PSI to generate interrupts */ - object_property_add_const_link(OBJECT(&chip->lpc), "psi", - OBJECT(&chip->psi), &error_abort); + /* + * The LPC controller needs a few things from the chip : to know + * if it's primary and PSI to generate interrupts + */ + object_property_add_const_link(OBJECT(&chip->lpc), "chip", + OBJECT(chip), &error_abort); } =20 static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 402c4fefa886..1e70c8c19d52 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -113,6 +113,14 @@ static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, vo= id *fdt, int xscom_offset) _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); + + /* + * The default LPC bus of a multichip system is on chip 0. It's + * recognized by the firmware (skiboot) using a "primary" property. + */ + if (PNV_LPC(dev)->primary) { + _FDT((fdt_setprop(fdt, offset, "primary", NULL, 0))); + } return 0; } =20 @@ -416,6 +424,18 @@ static void pnv_lpc_realize(DeviceState *dev, Error **= errp) PnvLpcController *lpc =3D PNV_LPC(dev); Object *obj; Error *error =3D NULL; + PnvChip *chip; + + /* get PSI object from chip */ + obj =3D object_property_get_link(OBJECT(dev), "chip", &error); + if (!obj) { + error_propagate(errp, error); + error_prepend(errp, "required link 'chip' not found: "); + return; + } + chip =3D PNV_CHIP(obj); + lpc->psi =3D &chip->psi; + lpc->primary =3D chip->chip_id =3D=3D 0; =20 /* Reg inits */ lpc->lpc_hc_fw_rd_acc_size =3D LPC_HC_FW_RD_4B; @@ -460,15 +480,6 @@ static void pnv_lpc_realize(DeviceState *dev, Error **= errp) pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev), &pnv_lpc_xscom_ops, lpc, "xscom-lpc", PNV_XSCOM_LPC_SIZE); - - /* get PSI object from chip */ - obj =3D object_property_get_link(OBJECT(dev), "psi", &error); - if (!obj) { - error_setg(errp, "%s: required link 'psi' not found: %s", - __func__, error_get_pretty(error)); - return; - } - lpc->psi =3D PNV_PSI(obj); } =20 static void pnv_lpc_class_init(ObjectClass *klass, void *data) --=20 2.13.6 From nobody Thu May 2 21:33:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528985019669755.5184747336882; Thu, 14 Jun 2018 07:03:39 -0700 (PDT) Received: from localhost ([::1]:40860 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTSqg-0000hl-Ru for importer@patchew.org; Thu, 14 Jun 2018 10:03:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54453) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTSoK-0007mj-Fq for qemu-devel@nongnu.org; Thu, 14 Jun 2018 10:01:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fTSoE-0008WC-GM for qemu-devel@nongnu.org; Thu, 14 Jun 2018 10:01:12 -0400 Received: from 9.mo3.mail-out.ovh.net ([87.98.184.141]:43515) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fTSoE-0008V7-9Z for qemu-devel@nongnu.org; Thu, 14 Jun 2018 10:01:06 -0400 Received: from player738.ha.ovh.net (unknown [10.109.122.87]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 6B9221BA287 for ; Thu, 14 Jun 2018 16:01:04 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-TOU-1-49-10.w86-201.abo.wanadoo.fr [86.201.141.10]) (Authenticated sender: clg@kaod.org) by player738.ha.ovh.net (Postfix) with ESMTPSA id 164A95913; Thu, 14 Jun 2018 16:01:00 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org Date: Thu, 14 Jun 2018 16:00:39 +0200 Message-Id: <20180614140043.9231-3-clg@kaod.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20180614140043.9231-1-clg@kaod.org> References: <20180614140043.9231-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 8439745705223686995 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedthedrleefgdejudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.184.141 Subject: [Qemu-devel] [PATCH 2/6] ppc/pnv: move the details of the ISA bus creation under the LPC model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This is a small cleanup to hide to the machine the gory details of the creation of the ISA bus. When time comes, the 'qemu_irq_handler' should become a LPC controller class attribute. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv_lpc.h | 3 +-- hw/ppc/pnv.c | 15 +-------------- hw/ppc/pnv_lpc.c | 24 ++++++++++++++++++++---- 3 files changed, 22 insertions(+), 20 deletions(-) diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index fddcb1c054b3..fb4b7b83d798 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -72,7 +72,6 @@ typedef struct PnvLpcController { bool primary; } PnvLpcController; =20 -qemu_irq *pnv_lpc_isa_irq_create(PnvLpcController *lpc, int chip_type, - int nirqs); +ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, int chip_type); =20 #endif /* _PPC_PNV_LPC_H */ diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index b419d3323100..d2126ee4affc 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -521,22 +521,9 @@ static void pnv_reset(void) =20 static ISABus *pnv_isa_create(PnvChip *chip) { - PnvLpcController *lpc =3D &chip->lpc; - ISABus *isa_bus; - qemu_irq *irqs; PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); =20 - /* let isa_bus_new() create its own bridge on SysBus otherwise - * devices speficied on the command line won't find the bus and - * will fail to create. - */ - isa_bus =3D isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, - &error_fatal); - - irqs =3D pnv_lpc_isa_irq_create(lpc, pcc->chip_type, ISA_NUM_IRQS); - - isa_bus_irqs(isa_bus, irqs); - return isa_bus; + return pnv_lpc_isa_create(&chip->lpc, pcc->chip_type); } =20 static void pnv_init(MachineState *machine) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 1e70c8c19d52..7c6c012d5176 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -22,6 +22,7 @@ #include "target/ppc/cpu.h" #include "qapi/error.h" #include "qemu/log.h" +#include "hw/isa/isa.h" =20 #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_lpc.h" @@ -546,16 +547,31 @@ static void pnv_lpc_isa_irq_handler(void *opaque, int= n, int level) } } =20 -qemu_irq *pnv_lpc_isa_irq_create(PnvLpcController *lpc, int chip_type, - int nirqs) +ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, int chip_type) { + ISABus *isa_bus; + qemu_irq *irqs; + qemu_irq_handler handler; + + /* let isa_bus_new() create its own bridge on SysBus otherwise + * devices speficied on the command line won't find the bus and + * will fail to create. + */ + isa_bus =3D isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, + &error_fatal); + /* Not all variants have a working serial irq decoder. If not, * handling of LPC interrupts becomes a platform issue (some * platforms have a CPLD to do it). */ if (chip_type =3D=3D PNV_CHIP_POWER8NVL) { - return qemu_allocate_irqs(pnv_lpc_isa_irq_handler, lpc, nirqs); + handler =3D pnv_lpc_isa_irq_handler; } else { - return qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, lpc, nirqs= ); + handler =3D pnv_lpc_isa_irq_handler_cpld; } + + irqs =3D qemu_allocate_irqs(handler, lpc, ISA_NUM_IRQS); + + isa_bus_irqs(isa_bus, irqs); + return isa_bus; } --=20 2.13.6 From nobody Thu May 2 21:33:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528985038996503.40131037026003; Thu, 14 Jun 2018 07:03:58 -0700 (PDT) Received: from localhost ([::1]:40861 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTSqt-0000ve-Ek for importer@patchew.org; Thu, 14 Jun 2018 10:03:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54468) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTSoM-0007oL-AQ for qemu-devel@nongnu.org; Thu, 14 Jun 2018 10:01:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fTSoI-000088-EG for qemu-devel@nongnu.org; Thu, 14 Jun 2018 10:01:14 -0400 Received: from 20.mo7.mail-out.ovh.net ([46.105.49.208]:58053) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fTSoI-00007p-6y for qemu-devel@nongnu.org; Thu, 14 Jun 2018 10:01:10 -0400 Received: from player738.ha.ovh.net (unknown [10.109.108.37]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 9043FB3829 for ; Thu, 14 Jun 2018 16:01:08 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-TOU-1-49-10.w86-201.abo.wanadoo.fr [86.201.141.10]) (Authenticated sender: clg@kaod.org) by player738.ha.ovh.net (Postfix) with ESMTPSA id 55774592B; Thu, 14 Jun 2018 16:01:04 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org Date: Thu, 14 Jun 2018 16:00:40 +0200 Message-Id: <20180614140043.9231-4-clg@kaod.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20180614140043.9231-1-clg@kaod.org> References: <20180614140043.9231-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 8440871603320032083 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedthedrleefgdejudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.49.208 Subject: [Qemu-devel] [PATCH 3/6] ppc/pnv: introduce an 'isa_bus_name' field under the LPC model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This is again a small cleanup to hide to the machine the details of the ISA bus. The ISA bus device tree nodename will be different on Power9. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv_lpc.h | 1 + hw/ppc/pnv.c | 9 +-------- hw/ppc/pnv_lpc.c | 4 ++++ 3 files changed, 6 insertions(+), 8 deletions(-) diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index fb4b7b83d798..e8f7dcb9bfe9 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -70,6 +70,7 @@ typedef struct PnvLpcController { PnvPsi *psi; =20 bool primary; + char *isa_bus_name; } PnvLpcController; =20 ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, int chip_type); diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index d2126ee4affc..72cfe4c2627c 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -267,14 +267,7 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint3= 2_t pir, =20 static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt) { - char *name; - int offset; - - name =3D g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", - (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_= BASE); - offset =3D fdt_path_offset(fdt, name); - g_free(name); - return offset; + return fdt_path_offset(fdt, chip->lpc.isa_bus_name); } =20 static void pnv_dt_chip(PnvChip *chip, void *fdt) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 7c6c012d5176..7f13c4bcf52c 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -481,6 +481,10 @@ static void pnv_lpc_realize(DeviceState *dev, Error **= errp) pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev), &pnv_lpc_xscom_ops, lpc, "xscom-lpc", PNV_XSCOM_LPC_SIZE); + + lpc->isa_bus_name =3D g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", + (uint64_t) PNV_XSCOM_BASE(chip), + PNV_XSCOM_LPC_BASE); } =20 static void pnv_lpc_class_init(ObjectClass *klass, void *data) --=20 2.13.6 From nobody Thu May 2 21:33:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528985212162660.2160143040453; Thu, 14 Jun 2018 07:06:52 -0700 (PDT) Received: from localhost ([::1]:40881 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTStn-0003TG-Bp for importer@patchew.org; Thu, 14 Jun 2018 10:06:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54517) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTSoS-0007tK-Ga for qemu-devel@nongnu.org; Thu, 14 Jun 2018 10:01:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fTSoM-00009p-GJ for qemu-devel@nongnu.org; Thu, 14 Jun 2018 10:01:20 -0400 Received: from 13.mo6.mail-out.ovh.net ([188.165.56.124]:37352) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fTSoM-00009D-9x for qemu-devel@nongnu.org; Thu, 14 Jun 2018 10:01:14 -0400 Received: from player738.ha.ovh.net (unknown [10.109.108.77]) by mo6.mail-out.ovh.net (Postfix) with ESMTP id BD535160540 for ; Thu, 14 Jun 2018 16:01:12 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-TOU-1-49-10.w86-201.abo.wanadoo.fr [86.201.141.10]) (Authenticated sender: clg@kaod.org) by player738.ha.ovh.net (Postfix) with ESMTPSA id 84AC4595; Thu, 14 Jun 2018 16:01:08 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org Date: Thu, 14 Jun 2018 16:00:41 +0200 Message-Id: <20180614140043.9231-5-clg@kaod.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20180614140043.9231-1-clg@kaod.org> References: <20180614140043.9231-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 8441997502859479891 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedthedrleefgdejudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 188.165.56.124 Subject: [Qemu-devel] [PATCH 4/6] ppc/pnv: introduce a pnv_chip_core_realize() routine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This extracts from the PvChip realize routine the part creating the cores. On Power9, we will need to create the cores after the Xive interrupt controller is created. Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 72cfe4c2627c..b3b0dd44582f 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -822,9 +822,8 @@ static void pnv_chip_icp_realize(PnvChip *chip, Error *= *errp) } } =20 -static void pnv_chip_realize(DeviceState *dev, Error **errp) +static void pnv_chip_core_realize(PnvChip *chip, Error **errp) { - PnvChip *chip =3D PNV_CHIP(dev); Error *error =3D NULL; PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); const char *typename =3D pnv_chip_core_typename(chip); @@ -836,14 +835,6 @@ static void pnv_chip_realize(DeviceState *dev, Error *= *errp) return; } =20 - /* XSCOM bridge */ - pnv_xscom_realize(chip, &error); - if (error) { - error_propagate(errp, error); - return; - } - sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); - /* Cores */ pnv_chip_core_sanitize(chip, &error); if (error) { @@ -891,6 +882,27 @@ static void pnv_chip_realize(DeviceState *dev, Error *= *errp) &PNV_CORE(pnv_core)->xscom_regs); i++; } +} + +static void pnv_chip_realize(DeviceState *dev, Error **errp) +{ + PnvChip *chip =3D PNV_CHIP(dev); + Error *error =3D NULL; + + /* XSCOM bridge */ + pnv_xscom_realize(chip, &error); + if (error) { + error_propagate(errp, error); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); + + /* Cores */ + pnv_chip_core_realize(chip, &error); + if (error) { + error_propagate(errp, error); + return; + } =20 /* Create LPC controller */ object_property_set_bool(OBJECT(&chip->lpc), true, "realized", --=20 2.13.6 From nobody Thu May 2 21:33:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528985204718525.0915608303333; Thu, 14 Jun 2018 07:06:44 -0700 (PDT) Received: from localhost ([::1]:40880 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTStd-0003OJ-SN for importer@patchew.org; Thu, 14 Jun 2018 10:06:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54563) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTSoW-0007wz-SQ for qemu-devel@nongnu.org; Thu, 14 Jun 2018 10:01:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fTSoR-0000CY-0B for qemu-devel@nongnu.org; Thu, 14 Jun 2018 10:01:24 -0400 Received: from 8.mo173.mail-out.ovh.net ([46.105.46.122]:50519) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fTSoQ-0000BZ-Mt for qemu-devel@nongnu.org; Thu, 14 Jun 2018 10:01:18 -0400 Received: from player738.ha.ovh.net (unknown [10.109.120.28]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id 18C36C5524 for ; Thu, 14 Jun 2018 16:01:16 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-TOU-1-49-10.w86-201.abo.wanadoo.fr [86.201.141.10]) (Authenticated sender: clg@kaod.org) by player738.ha.ovh.net (Postfix) with ESMTPSA id B6F7713B0; Thu, 14 Jun 2018 16:01:12 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org Date: Thu, 14 Jun 2018 16:00:42 +0200 Message-Id: <20180614140043.9231-6-clg@kaod.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20180614140043.9231-1-clg@kaod.org> References: <20180614140043.9231-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 8443123404376542035 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedthedrleefgdejudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.46.122 Subject: [Qemu-devel] [PATCH 5/6] ppc/pnv: introduce a new intc_create() operation to the chip model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On Power9, the thread interrupt presenter has a different type and is linked to the chip owning the cores. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- include/hw/ppc/pnv.h | 1 + hw/ppc/pnv.c | 21 +++++++++++++++++++-- hw/ppc/pnv_core.c | 18 +++++++++--------- 3 files changed, 29 insertions(+), 11 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 90759240a7b1..e934e84f555e 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -76,6 +76,7 @@ typedef struct PnvChipClass { hwaddr xscom_base; =20 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); + Object *(*intc_create)(PnvChip *chip, Object *child, Error **errp); } PnvChipClass; =20 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index b3b0dd44582f..7d99366daf90 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -641,6 +641,13 @@ static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, ui= nt32_t core_id) return (chip->chip_id << 7) | (core_id << 3); } =20 +static Object *pnv_chip_power8_intc_create(PnvChip *chip, Object *child, + Error **errp) +{ + return icp_create(child, TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), + errp); +} + /* * 0:48 Reserved - Read as zeroes * 49:52 Node ID @@ -656,6 +663,12 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, ui= nt32_t core_id) return (chip->chip_id << 8) | (core_id << 2); } =20 +static Object *pnv_chip_power9_intc_create(PnvChip *chip, Object *child, + Error **errp) +{ + return NULL; +} + /* Allowed core identifiers on a POWER8 Processor Chip : * * @@ -691,6 +704,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *kl= ass, void *data) k->chip_cfam_id =3D 0x221ef04980000000ull; /* P8 Murano DD2.1 */ k->cores_mask =3D POWER8E_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p8; + k->intc_create =3D pnv_chip_power8_intc_create; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8E"; } @@ -704,6 +718,7 @@ static void pnv_chip_power8_class_init(ObjectClass *kla= ss, void *data) k->chip_cfam_id =3D 0x220ea04980000000ull; /* P8 Venice DD2.0 */ k->cores_mask =3D POWER8_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p8; + k->intc_create =3D pnv_chip_power8_intc_create; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8"; } @@ -717,6 +732,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *= klass, void *data) k->chip_cfam_id =3D 0x120d304980000000ull; /* P8 Naples DD1.0 */ k->cores_mask =3D POWER8_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p8; + k->intc_create =3D pnv_chip_power8_intc_create; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8NVL"; } @@ -730,6 +746,7 @@ static void pnv_chip_power9_class_init(ObjectClass *kla= ss, void *data) k->chip_cfam_id =3D 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ k->cores_mask =3D POWER9_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p9; + k->intc_create =3D pnv_chip_power9_intc_create; k->xscom_base =3D 0x00603fc00000000ull; dc->desc =3D "PowerNV Chip POWER9"; } @@ -865,8 +882,8 @@ static void pnv_chip_core_realize(PnvChip *chip, Error = **errp) object_property_set_int(OBJECT(pnv_core), pcc->core_pir(chip, core_hwid), "pir", &error_fatal); - object_property_add_const_link(OBJECT(pnv_core), "xics", - qdev_get_machine(), &error_fatal); + object_property_add_const_link(OBJECT(pnv_core), "chip", + OBJECT(chip), &error_fatal); object_property_set_bool(OBJECT(pnv_core), true, "realized", &error_fatal); object_unref(OBJECT(pnv_core)); diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 13ad7d9e0470..5805bcd10abf 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -121,11 +121,12 @@ static const MemoryRegionOps pnv_core_xscom_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 -static void pnv_core_realize_child(Object *child, XICSFabric *xi, Error **= errp) +static void pnv_core_realize_child(Object *child, PnvChip *chip, Error **e= rrp) { Error *local_err =3D NULL; CPUState *cs =3D CPU(child); PowerPCCPU *cpu =3D POWERPC_CPU(cs); + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); =20 object_property_set_bool(child, true, "realized", &local_err); if (local_err) { @@ -133,7 +134,7 @@ static void pnv_core_realize_child(Object *child, XICSF= abric *xi, Error **errp) return; } =20 - cpu->intc =3D icp_create(child, TYPE_PNV_ICP, xi, &local_err); + cpu->intc =3D pcc->intc_create(chip, child, &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -156,13 +157,12 @@ static void pnv_core_realize(DeviceState *dev, Error = **errp) void *obj; int i, j; char name[32]; - Object *xi; + Object *chip; =20 - xi =3D object_property_get_link(OBJECT(dev), "xics", &local_err); - if (!xi) { - error_setg(errp, "%s: required link 'xics' not found: %s", - __func__, error_get_pretty(local_err)); - return; + chip =3D object_property_get_link(OBJECT(dev), "chip", &local_err); + if (!chip) { + error_propagate(errp, local_err); + error_prepend(errp, "required link 'chip' not found: "); } =20 pc->threads =3D g_malloc0(size * cc->nr_threads); @@ -184,7 +184,7 @@ static void pnv_core_realize(DeviceState *dev, Error **= errp) for (j =3D 0; j < cc->nr_threads; j++) { obj =3D pc->threads + j * size; =20 - pnv_core_realize_child(obj, XICS_FABRIC(xi), &local_err); + pnv_core_realize_child(obj, PNV_CHIP(chip), &local_err); if (local_err) { goto err; } --=20 2.13.6 From nobody Thu May 2 21:33:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528985353394723.1592694004838; Thu, 14 Jun 2018 07:09:13 -0700 (PDT) Received: from localhost ([::1]:40895 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTSw3-0005EG-5H for importer@patchew.org; Thu, 14 Jun 2018 10:09:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54599) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTSob-00081o-H9 for qemu-devel@nongnu.org; Thu, 14 Jun 2018 10:01:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fTSoV-0000Ft-IT for qemu-devel@nongnu.org; Thu, 14 Jun 2018 10:01:29 -0400 Received: from 10.mo68.mail-out.ovh.net ([46.105.79.203]:49363) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fTSoV-0000F6-6q for qemu-devel@nongnu.org; Thu, 14 Jun 2018 10:01:23 -0400 Received: from player738.ha.ovh.net (unknown [10.109.108.92]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id 51A4BE475E for ; Thu, 14 Jun 2018 16:01:21 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-TOU-1-49-10.w86-201.abo.wanadoo.fr [86.201.141.10]) (Authenticated sender: clg@kaod.org) by player738.ha.ovh.net (Postfix) with ESMTPSA id E9BA954A5; Thu, 14 Jun 2018 16:01:16 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org Date: Thu, 14 Jun 2018 16:00:43 +0200 Message-Id: <20180614140043.9231-7-clg@kaod.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20180614140043.9231-1-clg@kaod.org> References: <20180614140043.9231-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 8444530779712883539 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedthedrleefgdejudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.79.203 Subject: [Qemu-devel] [PATCH 6/6] ppc/pnv: introduce Pnv8Chip and Pnv9Chip models X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This is a major reshuffle of the PowerNV machine and chip models to introduce a machine type per processor. It is quite noisy but it doesn't change much the code flow. It introduces a base PnvChip class from which the specific processor chip classes, Pnv8Chip and Pnv9Chip, inherit. Each of them needs to define an init and a realize routine which will create the controllers of the target processor. For the moment, the base PnvChip class handles the XSCOM bus and the cores but the core creation will surely move to the specific processor chip classes because of the new XIVE interrupt controller in Power9. The base class also has pointers on the main controllers of the chip which are common to all processors : PSI, LPC, OCC. These controllers have some subtil differences in each processor version, but, globally, they are very similar and provide the same feature. This is how we have a console for instance. From there, we introduce two different machines : "powernv8" and "powernv9" but, a part from the XICSFabric interface, this is not strictly needed as it is the cpu type which determines the PnvChip class. Something to discuss. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv.h | 28 ++++- hw/ppc/pnv.c | 322 +++++++++++++++++++++++++++++++++--------------= ---- hw/ppc/pnv_lpc.c | 2 +- 3 files changed, 236 insertions(+), 116 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index e934e84f555e..4942add9458a 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -57,12 +57,37 @@ typedef struct PnvChip { MemoryRegion xscom_mmio; MemoryRegion xscom; AddressSpace xscom_as; + + /* Base class controllers */ + PnvLpcController *lpc; + PnvPsi *psi; + PnvOCC *occ; +} PnvChip; + +#define TYPE_PNV8_CHIP "pnv8-chip" +#define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP) + +typedef struct Pnv8Chip { + /*< private >*/ + PnvChip parent_obj; + + /*< public >*/ MemoryRegion icp_mmio; =20 PnvLpcController lpc; PnvPsi psi; PnvOCC occ; -} PnvChip; +} Pnv8Chip; + +#define TYPE_PNV9_CHIP "pnv9-chip" +#define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP) + +typedef struct Pnv9Chip { + /*< private >*/ + PnvChip parent_obj; + + /*< public >*/ +} Pnv9Chip; =20 typedef struct PnvChipClass { /*< private >*/ @@ -75,6 +100,7 @@ typedef struct PnvChipClass { =20 hwaddr xscom_base; =20 + void (*realize)(PnvChip *chip, Error **errp); uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); Object *(*intc_create)(PnvChip *chip, Object *child, Error **errp); } PnvChipClass; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 7d99366daf90..60b56c7fe07b 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -267,7 +267,7 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32= _t pir, =20 static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt) { - return fdt_path_offset(fdt, chip->lpc.isa_bus_name); + return fdt_path_offset(fdt, chip->lpc->isa_bus_name); } =20 static void pnv_dt_chip(PnvChip *chip, void *fdt) @@ -516,7 +516,7 @@ static ISABus *pnv_isa_create(PnvChip *chip) { PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); =20 - return pnv_lpc_isa_create(&chip->lpc, pcc->chip_type); + return pnv_lpc_isa_create(chip->lpc, pcc->chip_type); } =20 static void pnv_init(MachineState *machine) @@ -695,6 +695,106 @@ static Object *pnv_chip_power9_intc_create(PnvChip *c= hip, Object *child, */ #define POWER9_CORE_MASK (0xffffffffffffffull) =20 +static void pnv_chip_power8_initfn(Object *obj) +{ + Pnv8Chip *chip8 =3D PNV8_CHIP(obj); + PnvChip *chip =3D PNV_CHIP(obj); + + object_initialize(&chip8->lpc, sizeof(chip8->lpc), TYPE_PNV_LPC); + object_property_add_child(obj, "lpc", OBJECT(&chip8->lpc), NULL); + + object_initialize(&chip8->psi, sizeof(chip8->psi), TYPE_PNV_PSI); + object_property_add_child(obj, "psi", OBJECT(&chip8->psi), NULL); + object_property_add_const_link(OBJECT(&chip8->psi), "xics", + OBJECT(qdev_get_machine()), &error_abor= t); + + object_initialize(&chip8->occ, sizeof(chip8->occ), TYPE_PNV_OCC); + object_property_add_child(obj, "occ", OBJECT(&chip8->occ), NULL); + object_property_add_const_link(OBJECT(&chip8->occ), "psi", + OBJECT(&chip8->psi), &error_abort); + + /* + * The LPC controller needs a few things from the chip : to know + * if it's primary and PSI to generate interrupts + */ + object_property_add_const_link(OBJECT(&chip8->lpc), "chip", + OBJECT(chip8), &error_abort); + + /* Intialize the controllers in the base class also */ + chip->lpc =3D &chip8->lpc; + chip->psi =3D &chip8->psi; + chip->occ =3D &chip8->occ; +} + +static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) + { + PnvChip *chip =3D PNV_CHIP(chip8); + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); + const char *typename =3D pnv_chip_core_typename(chip); + size_t typesize =3D object_type_get_instance_size(typename); + int i, j; + char *name; + XICSFabric *xi =3D XICS_FABRIC(qdev_get_machine()); + + name =3D g_strdup_printf("icp-%x", chip->chip_id); + memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); + g_free(name); + + sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); + + /* Map the ICP registers for each thread */ + for (i =3D 0; i < chip->nr_cores; i++) { + PnvCore *pnv_core =3D PNV_CORE(chip->cores + i * typesize); + int core_hwid =3D CPU_CORE(pnv_core)->core_id; + + for (j =3D 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { + uint32_t pir =3D pcc->core_pir(chip, core_hwid) + j; + PnvICPState *icp =3D PNV_ICP(xics_icp_get(xi, pir)); + + memory_region_add_subregion(&chip8->icp_mmio, pir << 12, + &icp->mmio); + } + } +} + +static void pnv_chip_power8_realize(PnvChip *chip, Error **errp) + { + Pnv8Chip *chip8 =3D PNV8_CHIP(chip); + Error *error =3D NULL; + + /* Create LPC controller */ + object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", + &error_fatal); + pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_re= gs); + + /* Interrupt Management Area. This is the memory region holding + * all the Interrupt Control Presenter (ICP) registers */ + pnv_chip_icp_realize(chip8, &error); + if (error) { + error_propagate(errp, error); + return; + } + + /* Processor Service Interface (PSI) Host Bridge */ + object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), + "bar", &error_fatal); + object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &error= ); + if (error) { + error_propagate(errp, error); + return; + } + pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip8->psi.xscom_= regs); + + /* Create the simplified OCC model */ + object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &error= ); + if (error) { + error_propagate(errp, error); + return; + } + pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_re= gs); +} + static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -719,6 +819,7 @@ static void pnv_chip_power8_class_init(ObjectClass *kla= ss, void *data) k->cores_mask =3D POWER8_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p8; k->intc_create =3D pnv_chip_power8_intc_create; + k->realize =3D pnv_chip_power8_realize; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8"; } @@ -733,10 +834,20 @@ static void pnv_chip_power8nvl_class_init(ObjectClass= *klass, void *data) k->cores_mask =3D POWER8_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p8; k->intc_create =3D pnv_chip_power8_intc_create; + k->realize =3D pnv_chip_power8_realize; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8NVL"; } =20 +static void pnv_chip_power9_initfn(Object *obj) +{ +} + +static void pnv_chip_power9_realize(PnvChip *chip, Error **errp) +{ + +} + static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -747,6 +858,7 @@ static void pnv_chip_power9_class_init(ObjectClass *kla= ss, void *data) k->cores_mask =3D POWER9_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p9; k->intc_create =3D pnv_chip_power9_intc_create; + k->realize =3D pnv_chip_power9_realize; k->xscom_base =3D 0x00603fc00000000ull; dc->desc =3D "PowerNV Chip POWER9"; } @@ -781,62 +893,9 @@ static void pnv_chip_core_sanitize(PnvChip *chip, Erro= r **errp) } } =20 -static void pnv_chip_init(Object *obj) +static void pnv_chip_initfn(Object *obj) { - PnvChip *chip =3D PNV_CHIP(obj); - PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); - - chip->xscom_base =3D pcc->xscom_base; - - object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC); - object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL); - - object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI); - object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL); - object_property_add_const_link(OBJECT(&chip->psi), "xics", - OBJECT(qdev_get_machine()), &error_abor= t); - - object_initialize(&chip->occ, sizeof(chip->occ), TYPE_PNV_OCC); - object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL); - object_property_add_const_link(OBJECT(&chip->occ), "psi", - OBJECT(&chip->psi), &error_abort); - - /* - * The LPC controller needs a few things from the chip : to know - * if it's primary and PSI to generate interrupts - */ - object_property_add_const_link(OBJECT(&chip->lpc), "chip", - OBJECT(chip), &error_abort); -} - -static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) -{ - PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); - const char *typename =3D pnv_chip_core_typename(chip); - size_t typesize =3D object_type_get_instance_size(typename); - int i, j; - char *name; - XICSFabric *xi =3D XICS_FABRIC(qdev_get_machine()); - - name =3D g_strdup_printf("icp-%x", chip->chip_id); - memory_region_init(&chip->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); - sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip->icp_mmio); - g_free(name); - - sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); - - /* Map the ICP registers for each thread */ - for (i =3D 0; i < chip->nr_cores; i++) { - PnvCore *pnv_core =3D PNV_CORE(chip->cores + i * typesize); - int core_hwid =3D CPU_CORE(pnv_core)->core_id; - - for (j =3D 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { - uint32_t pir =3D pcc->core_pir(chip, core_hwid) + j; - PnvICPState *icp =3D PNV_ICP(xics_icp_get(xi, pir)); - - memory_region_add_subregion(&chip->icp_mmio, pir << 12, &icp->= mmio); - } - } + PNV_CHIP(obj)->xscom_base =3D PNV_CHIP_GET_CLASS(obj)->xscom_base; } =20 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) @@ -904,6 +963,7 @@ static void pnv_chip_core_realize(PnvChip *chip, Error = **errp) static void pnv_chip_realize(DeviceState *dev, Error **errp) { PnvChip *chip =3D PNV_CHIP(dev); + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); Error *error =3D NULL; =20 /* XSCOM bridge */ @@ -921,36 +981,7 @@ static void pnv_chip_realize(DeviceState *dev, Error *= *errp) return; } =20 - /* Create LPC controller */ - object_property_set_bool(OBJECT(&chip->lpc), true, "realized", - &error_fatal); - pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_reg= s); - - /* Interrupt Management Area. This is the memory region holding - * all the Interrupt Control Presenter (ICP) registers */ - pnv_chip_icp_realize(chip, &error); - if (error) { - error_propagate(errp, error); - return; - } - - /* Processor Service Interface (PSI) Host Bridge */ - object_property_set_int(OBJECT(&chip->psi), PNV_PSIHB_BASE(chip), - "bar", &error_fatal); - object_property_set_bool(OBJECT(&chip->psi), true, "realized", &error); - if (error) { - error_propagate(errp, error); - return; - } - pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip->psi.xscom_r= egs); - - /* Create the simplified OCC model */ - object_property_set_bool(OBJECT(&chip->occ), true, "realized", &error); - if (error) { - error_propagate(errp, error); - return; - } - pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip->occ.xscom_reg= s); + pcc->realize(chip, errp); } =20 static Property pnv_chip_properties[] =3D { @@ -972,26 +1003,29 @@ static void pnv_chip_class_init(ObjectClass *klass, = void *data) dc->desc =3D "PowerNV Chip"; } =20 -static ICSState *pnv_ics_get(XICSFabric *xi, int irq) +static ICSState *pnv8_ics_get(XICSFabric *xi, int irq) { PnvMachineState *pnv =3D PNV_MACHINE(xi); int i; =20 for (i =3D 0; i < pnv->num_chips; i++) { - if (ics_valid_irq(&pnv->chips[i]->psi.ics, irq)) { - return &pnv->chips[i]->psi.ics; + Pnv8Chip *chip =3D PNV8_CHIP(pnv->chips[i]); + + if (ics_valid_irq(&chip->psi.ics, irq)) { + return &chip->psi.ics; } } return NULL; } =20 -static void pnv_ics_resend(XICSFabric *xi) +static void pnv8_ics_resend(XICSFabric *xi) { PnvMachineState *pnv =3D PNV_MACHINE(xi); int i; =20 for (i =3D 0; i < pnv->num_chips; i++) { - ics_resend(&pnv->chips[i]->psi.ics); + Pnv8Chip *chip =3D PNV8_CHIP(pnv->chips[i]); + ics_resend(&chip->psi.ics); } } =20 @@ -1011,15 +1045,14 @@ static PowerPCCPU *ppc_get_vcpu_by_pir(int pir) return NULL; } =20 -static ICPState *pnv_icp_get(XICSFabric *xi, int pir) +static ICPState *pnv8_icp_get(XICSFabric *xi, int pir) { PowerPCCPU *cpu =3D ppc_get_vcpu_by_pir(pir); =20 return cpu ? ICP(cpu->intc) : NULL; } =20 -static void pnv_pic_print_info(InterruptStatsProvider *obj, - Monitor *mon) +static void pnv8_pic_print_info(InterruptStatsProvider *obj, Monitor *mon) { PnvMachineState *pnv =3D PNV_MACHINE(obj); int i; @@ -1032,7 +1065,8 @@ static void pnv_pic_print_info(InterruptStatsProvider= *obj, } =20 for (i =3D 0; i < pnv->num_chips; i++) { - ics_pic_print_info(&pnv->chips[i]->psi.ics, mon); + Pnv8Chip *chip =3D PNV8_CHIP(pnv->chips[i]); + ics_pic_print_info(&chip->psi.ics, mon); } } =20 @@ -1086,8 +1120,6 @@ static void pnv_machine_class_props_init(ObjectClass = *oc) static void pnv_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); - XICSFabricClass *xic =3D XICS_FABRIC_CLASS(oc); - InterruptStatsProviderClass *ispc =3D INTERRUPT_STATS_PROVIDER_CLASS(o= c); =20 mc->desc =3D "IBM PowerNV (Non-Virtualized)"; mc->init =3D pnv_init; @@ -1099,48 +1131,110 @@ static void pnv_machine_class_init(ObjectClass *oc= , void *data) mc->no_parallel =3D 1; mc->default_boot_order =3D NULL; mc->default_ram_size =3D 1 * G_BYTE; - xic->icp_get =3D pnv_icp_get; - xic->ics_get =3D pnv_ics_get; - xic->ics_resend =3D pnv_ics_resend; - ispc->print_info =3D pnv_pic_print_info; =20 pnv_machine_class_props_init(oc); } =20 -#define DEFINE_PNV_CHIP_TYPE(type, class_initfn) \ - { \ - .name =3D type, \ - .class_init =3D class_initfn, \ - .parent =3D TYPE_PNV_CHIP, \ +static void pnv8_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + XICSFabricClass *xic =3D XICS_FABRIC_CLASS(oc); + InterruptStatsProviderClass *ispc =3D INTERRUPT_STATS_PROVIDER_CLASS(o= c); + + /* Power8 is the default */ + mc->alias =3D "powernv"; + mc->is_default =3D 1; + + xic->icp_get =3D pnv8_icp_get; + xic->ics_get =3D pnv8_ics_get; + xic->ics_resend =3D pnv8_ics_resend; + ispc->print_info =3D pnv8_pic_print_info; +} + +static void pnv9_machine_class_init(ObjectClass *oc, void *data) +{ +} + +#define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ + { \ + .name =3D type, \ + .class_init =3D class_initfn, \ + .parent =3D TYPE_PNV8_CHIP, \ + } + +#define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ + { \ + .name =3D type, \ + .class_init =3D class_initfn, \ + .parent =3D TYPE_PNV9_CHIP, \ } =20 static const TypeInfo types[] =3D { + /* + * PowerNV machines and variants + */ { .name =3D TYPE_PNV_MACHINE, .parent =3D TYPE_MACHINE, + .abstract =3D true, .instance_size =3D sizeof(PnvMachineState), .instance_init =3D pnv_machine_initfn, .class_init =3D pnv_machine_class_init, .interfaces =3D (InterfaceInfo[]) { - { TYPE_XICS_FABRIC }, { TYPE_INTERRUPT_STATS_PROVIDER }, { }, }, }, { + .name =3D MACHINE_TYPE_NAME("powernv9"), + .parent =3D TYPE_PNV_MACHINE, + .class_init =3D pnv9_machine_class_init, + }, + { + .name =3D MACHINE_TYPE_NAME("powernv8"), + .parent =3D TYPE_PNV_MACHINE, + .class_init =3D pnv8_machine_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_XICS_FABRIC }, + { }, + }, + }, + + /* Power Chip */ + { .name =3D TYPE_PNV_CHIP, .parent =3D TYPE_SYS_BUS_DEVICE, .class_init =3D pnv_chip_class_init, - .instance_init =3D pnv_chip_init, + .instance_init =3D pnv_chip_initfn, .instance_size =3D sizeof(PnvChip), .class_size =3D sizeof(PnvChipClass), .abstract =3D true, }, - DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), - DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), - DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_ini= t), - DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, - pnv_chip_power8nvl_class_init), + + /* + * P9 chips and variants + */ + { + .name =3D TYPE_PNV9_CHIP, + .parent =3D TYPE_PNV_CHIP, + .instance_init =3D pnv_chip_power9_initfn, + .instance_size =3D sizeof(Pnv9Chip), + }, + DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init= ), + + /* + * P8 chips and variants + */ + { + .name =3D TYPE_PNV8_CHIP, + .parent =3D TYPE_PNV_CHIP, + .instance_init =3D pnv_chip_power8_initfn, + .instance_size =3D sizeof(Pnv8Chip), + }, + DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init= ), + DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_in= it), + DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, + pnv_chip_power8nvl_class_init), }; =20 DEFINE_TYPES(types) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 7f13c4bcf52c..265d94c3240d 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -435,7 +435,7 @@ static void pnv_lpc_realize(DeviceState *dev, Error **e= rrp) return; } chip =3D PNV_CHIP(obj); - lpc->psi =3D &chip->psi; + lpc->psi =3D chip->psi; lpc->primary =3D chip->chip_id =3D=3D 0; =20 /* Reg inits */ --=20 2.13.6