Changeset
hw/misc/mos6522.c         | 5 +++--
include/hw/misc/mos6522.h | 1 +
2 files changed, 4 insertions(+), 2 deletions(-)
Git apply log
Switched to a new branch '20180613083015.15749-1-mark.cave-ayland@ilande.co.uk'
Applying: mos6522: only clear the shift register interrupt upon write
Applying: mos6522: remove additional interrupt flag filter from mos6522_update_irq()
Applying: mos6522: expose mos6522_update_irq() through MOS6522DeviceClass
To https://github.com/patchew-project/qemu
 * [new tag]         patchew/20180613083015.15749-1-mark.cave-ayland@ilande.co.uk -> patchew/20180613083015.15749-1-mark.cave-ayland@ilande.co.uk
Test passed: checkpatch

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Test passed: docker-mingw@fedora

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Test passed: s390x

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Test passed: docker-quick@centos7

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[Qemu-devel] [PATCH 0/3] mos6522: allow IRQs from external port pins
Posted by Mark Cave-Ayland, 1 week ago
Whilst testing a conversion of Laurent's q800 patchset over to use mos6522
I discovered some issues which prevented IRQs being generated from inputs to
external port pins.

This is a requirement for the q800 patchset which uses external clocks to
generate periodic interrupts.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


Mark Cave-Ayland (3):
  mos6522: only clear the shift register interrupt upon write
  mos6522: remove additional interrupt flag filter from
    mos6522_update_irq()
  mos6522: expose mos6522_update_irq() through MOS6522DeviceClass

 hw/misc/mos6522.c         | 5 +++--
 include/hw/misc/mos6522.h | 1 +
 2 files changed, 4 insertions(+), 2 deletions(-)

-- 
2.11.0


Re: [Qemu-devel] [PATCH 0/3] mos6522: allow IRQs from external port pins
Posted by David Gibson, 1 week ago
On Wed, Jun 13, 2018 at 09:30:12AM +0100, Mark Cave-Ayland wrote:
> Whilst testing a conversion of Laurent's q800 patchset over to use mos6522
> I discovered some issues which prevented IRQs being generated from inputs to
> external port pins.
> 
> This is a requirement for the q800 patchset which uses external clocks to
> generate periodic interrupts.
> 
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>

Applied, thanks.

> 
> 
> Mark Cave-Ayland (3):
>   mos6522: only clear the shift register interrupt upon write
>   mos6522: remove additional interrupt flag filter from
>     mos6522_update_irq()
>   mos6522: expose mos6522_update_irq() through MOS6522DeviceClass
> 
>  hw/misc/mos6522.c         | 5 +++--
>  include/hw/misc/mos6522.h | 1 +
>  2 files changed, 4 insertions(+), 2 deletions(-)
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson
[Qemu-devel] [PATCH 1/3] mos6522: only clear the shift register interrupt upon write
Posted by Mark Cave-Ayland, 1 week ago
According to the 6522 datasheet the shift register (SR) interrupt flag is
cleared upon write with no mention of any other interrupt flags.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
 hw/misc/mos6522.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 44eb306cf1..ad5041d8c0 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc/mos6522.c
@@ -241,7 +241,7 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
         break;
     case VIA_REG_SR:
         val = s->sr;
-        s->ifr &= ~(SR_INT | CB1_INT | CB2_INT);
+        s->ifr &= ~SR_INT;
         mos6522_update_irq(s);
         break;
     case VIA_REG_ACR:
-- 
2.11.0


[Qemu-devel] [PATCH 2/3] mos6522: remove additional interrupt flag filter from mos6522_update_irq()
Posted by Mark Cave-Ayland, 1 week ago
The datasheet indicates that the interrupt is generated by ANDing the
interrupt flags register (IFR) with the interrupt enable register (IER)
but currently there is an extra filter for the SR and timer interrupts.

Remove this extra filter to allow interrupts to be generated by external
inputs on bits 1 and 2 of ports A and B.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
 hw/misc/mos6522.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index ad5041d8c0..8d5b419825 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc/mos6522.c
@@ -40,7 +40,7 @@ static void mos6522_timer_update(MOS6522State *s, MOS6522Timer *ti,
 
 static void mos6522_update_irq(MOS6522State *s)
 {
-    if (s->ifr & s->ier & (SR_INT | T1_INT | T2_INT)) {
+    if (s->ifr & s->ier) {
         qemu_irq_raise(s->irq);
     } else {
         qemu_irq_lower(s->irq);
-- 
2.11.0


[Qemu-devel] [PATCH 3/3] mos6522: expose mos6522_update_irq() through MOS6522DeviceClass
Posted by Mark Cave-Ayland, 1 week ago
In the case where we have an interrupt generated externally from inputs to
bits 1 and 2 of port A and/or port B, it is necessary to expose
mos6522_update_irq() so it can be called by the interrupt source.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
 hw/misc/mos6522.c         | 1 +
 include/hw/misc/mos6522.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 8d5b419825..14cff26c61 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc/mos6522.c
@@ -463,6 +463,7 @@ static void mos6522_class_init(ObjectClass *oc, void *data)
     mdc->set_sr_int = mos6522_set_sr_int;
     mdc->portB_write = mos6522_portB_write;
     mdc->portA_write = mos6522_portA_write;
+    mdc->update_irq = mos6522_update_irq;
     mdc->get_timer1_counter_value = mos6522_get_counter_value;
     mdc->get_timer2_counter_value = mos6522_get_counter_value;
     mdc->get_timer1_load_time = mos6522_get_load_time;
diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h
index f52b41920b..03d9f0c059 100644
--- a/include/hw/misc/mos6522.h
+++ b/include/hw/misc/mos6522.h
@@ -134,6 +134,7 @@ typedef struct MOS6522DeviceClass {
     void (*set_sr_int)(MOS6522State *dev);
     void (*portB_write)(MOS6522State *dev);
     void (*portA_write)(MOS6522State *dev);
+    void (*update_irq)(MOS6522State *dev);
     /* These are used to influence the CUDA MacOS timebase calibration */
     uint64_t (*get_timer1_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
     uint64_t (*get_timer2_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
-- 
2.11.0