From nobody Fri Apr 19 20:32:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528836494650865.4389832229753; Tue, 12 Jun 2018 13:48:14 -0700 (PDT) Received: from localhost ([::1]:58367 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSqD8-0007Fi-0k for importer@patchew.org; Tue, 12 Jun 2018 16:48:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53620) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSqCB-0006wJ-HT for qemu-devel@nongnu.org; Tue, 12 Jun 2018 16:47:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fSqC6-0004Ub-Lv for qemu-devel@nongnu.org; Tue, 12 Jun 2018 16:47:15 -0400 Received: from smtp57.i.mail.ru ([217.69.128.37]:44492) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fSqC6-0004S0-AR for qemu-devel@nongnu.org; Tue, 12 Jun 2018 16:47:10 -0400 Received: by smtp57.i.mail.ru with esmtpa (envelope-from ) id 1fSqC2-00057o-R9; Tue, 12 Jun 2018 23:47:07 +0300 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=Message-Id:Date:Subject:Cc:To:From; bh=cnt3WxwdFWVlGPwLiCGZhOEyLPpQTfY5ytFhgtd8aXo=; b=HSyWrNCfHgwoVvmksmVmLTgaCPDSlNqbHKEeSS80Sh+GG9y4iDiR5KaYXv6tRkq2YmuVUfyWKbKR1gJAsqPRdKzuHppXKzturJXtlyWvnqZ2MpW521gop9RPf+94eCmGpo/6BAo6Ju68m9DibNKeNCj45xIevBRAc1OJXEvQ/b8=; To: qemu-devel@nongnu.org Date: Tue, 12 Jun 2018 23:46:32 +0300 Message-Id: <20180612204632.28780-1-jusual@mail.ru> X-Mailer: git-send-email 2.17.0 Authentication-Results: smtp57.i.mail.ru; auth=pass smtp.auth=jusual@mail.ru smtp.mailfrom=jusual@mail.ru X-7FA49CB5: 0D63561A33F958A54BD29AE0D4AC26447D36B84733E915AFF8D0CF61512FED170A6AB1C7CE11FEE3EB7D890E3377C531BA3038C0950A5D36B5C8C57E37DE458B4C7702A67D5C33162DBA43225CD8A89FC0F9454058DFE53C1604C2A3C6BF86B5593B4A69AE7113BDC4224003CC836476C0CAF46E325F83A50BF2EBBBDD9D6B0F2EF91E2201DEA5EC574AF45C6390F7469DAA53EE0834AAEE X-Mailru-Sender: 7766D515518070DE138AAC7428EA760DC8897821B4D68D0867FF3D5993CA148575268CCE79D7902D7C4160E8B47E48163DDE9B364B0DF2898CB68AF7A628805D594FB4C9F0DBF412AE208404248635DF X-Mras: OK X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 217.69.128.37 Subject: [Qemu-devel] [PATCH] target/arm: Allow ARMv6-M Thumb2 instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Julia Suvorova via Qemu-devel Reply-To: Julia Suvorova Cc: Peter Maydell , Jim Mussared , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Joel Stanley , Stefan Hajnoczi , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" ARMv6-M supports 6 Thumb2 instructions. This patch checks for these instructions and allows their execution. Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit. This patch is required for future Cortex-M0 support. Signed-off-by: Julia Suvorova Reviewed-by: Stefan Hajnoczi --- target/arm/translate.c | 35 ++++++++++++++++++++++++++++++----- 1 file changed, 30 insertions(+), 5 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0ff5edf2ce..8cae3f5ed0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9965,7 +9965,8 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint= 32_t insn) * end up actually treating this as two 16-bit insns, though, * if it's half of a bl/blx pair that might span a page boundary. */ - if (arm_dc_feature(s, ARM_FEATURE_THUMB2)) { + if (arm_dc_feature(s, ARM_FEATURE_THUMB2) || + arm_dc_feature(s, ARM_FEATURE_M)) { /* Thumb2 cores (including all M profile ones) always treat * 32-bit insns as 32-bit. */ @@ -10075,6 +10076,11 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) { uint32_t imm, shift, offset; uint32_t rd, rn, rm, rs; + uint32_t armv6m_insn[] =3D {0xf3808000 /* msr */, 0xf3b08040 /* dsb */, + 0xf3b08050 /* dmb */, 0xf3b08060 /* isb */, + 0xf3e08000 /* mrs */, 0xf000d000 /* bl */}; + uint32_t armv6m_mask[] =3D {0xffe0d000, 0xfff0d0f0, 0xfff0d0f0, + 0xfff0d0f0, 0xffe0d000, 0xf800d000}; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 tmp3; @@ -10085,10 +10091,25 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) int conds; int logic_cc; =20 - /* The only 32 bit insn that's allowed for Thumb1 is the combined - * BL/BLX prefix and suffix. + /* + * ARMv6-M supports a limited subset of Thumb2 instructions. + * Other Thumb1 architectures allow only 32-bit + * combined BL/BLX prefix and suffix. */ - if ((insn & 0xf800e800) !=3D 0xf000e800) { + if (arm_dc_feature(s, ARM_FEATURE_M) && arm_dc_feature(s, ARM_FEATURE_= V6)) { + int i; + bool found =3D false; + + for (i =3D 0; i < ARRAY_SIZE(armv6m_insn); i++) { + if ((insn & armv6m_mask[i]) =3D=3D armv6m_insn[i]) { + found =3D true; + break; + } + } + if (!found) { + goto illegal_op; + } + } else if ((insn & 0xf800e800) !=3D 0xf000e800) { ARCH(6T2); } =20 @@ -11009,7 +11030,11 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } break; case 3: /* Special control operations. */ - ARCH(7); + if (!arm_dc_feature(s, ARM_FEATURE_V7) && + !(arm_dc_feature(s, ARM_FEATURE_V6) && + arm_dc_feature(s, ARM_FEATURE_M))) { + goto illegal_op; + } op =3D (insn >> 4) & 0xf; switch (op) { case 2: /* clrex */ --=20 2.17.0