From nobody Thu May 2 09:57:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152873806653992.94621199406743; Mon, 11 Jun 2018 10:27:46 -0700 (PDT) Received: from localhost ([::1]:50425 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSQbZ-00017v-NU for importer@patchew.org; Mon, 11 Jun 2018 13:27:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55883) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSQY6-0006mw-Eg for qemu-devel@nongnu.org; Mon, 11 Jun 2018 13:24:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fSQY3-0000SY-3N for qemu-devel@nongnu.org; Mon, 11 Jun 2018 13:24:10 -0400 Received: from mx1.redhat.com ([209.132.183.28]:33836) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fSQY2-0000S3-Qo for qemu-devel@nongnu.org; Mon, 11 Jun 2018 13:24:07 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 681A113AA8; Mon, 11 Jun 2018 17:24:05 +0000 (UTC) Received: from localhost (ovpn-116-19.gru2.redhat.com [10.97.116.19]) by smtp.corp.redhat.com (Postfix) with ESMTP id 7326482E51; Mon, 11 Jun 2018 17:24:02 +0000 (UTC) From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org Date: Mon, 11 Jun 2018 14:23:53 -0300 Message-Id: <20180611172355.12067-2-ehabkost@redhat.com> In-Reply-To: <20180611172355.12067-1-ehabkost@redhat.com> References: <20180611172355.12067-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Mon, 11 Jun 2018 17:24:05 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 1/3] i386: Clean up cache CPUID code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , kvm@vger.kernel.org, "Michael S. Tsirkin" , Marcelo Tosatti , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Always initialize CPUCaches structs with cache information, even if legacy_cache=3Dtrue. Use different CPUCaches struct for CPUID[2], CPUID[4], and the AMD CPUID leaves. This will simplify a lot the logic inside cpu_x86_cpuid(). Signed-off-by: Eduardo Habkost Signed-off-by: Babu Moger Message-Id: <1527176614-26271-2-git-send-email-babu.moger@amd.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.h | 14 ++++-- target/i386/cpu.c | 117 +++++++++++++++++++++++----------------------- 2 files changed, 67 insertions(+), 64 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 664504610e..89c82be8d2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1098,10 +1098,10 @@ typedef struct CPUCacheInfo { =20 =20 typedef struct CPUCaches { - CPUCacheInfo l1d_cache; - CPUCacheInfo l1i_cache; - CPUCacheInfo l2_cache; - CPUCacheInfo l3_cache; + CPUCacheInfo *l1d_cache; + CPUCacheInfo *l1i_cache; + CPUCacheInfo *l2_cache; + CPUCacheInfo *l3_cache; } CPUCaches; =20 typedef struct CPUX86State { @@ -1293,7 +1293,11 @@ typedef struct CPUX86State { /* Features that were explicitly enabled/disabled */ FeatureWordArray user_features; uint32_t cpuid_model[12]; - CPUCaches *cache_info; + /* Cache information for CPUID. When legacy-cache=3Don, the cache data + * on each CPUID leaf will be different, because we keep compatibility + * with old QEMU versions. + */ + CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; =20 /* MTRRs */ uint64_t mtrr_fixed[11]; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 94260412e2..1ea7bf4911 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1112,7 +1112,7 @@ struct X86CPUDefinition { }; =20 static CPUCaches epyc_cache_info =3D { - .l1d_cache =3D { + .l1d_cache =3D &(CPUCacheInfo) { .type =3D DCACHE, .level =3D 1, .size =3D 32 * KiB, @@ -1124,7 +1124,7 @@ static CPUCaches epyc_cache_info =3D { .self_init =3D 1, .no_invd_sharing =3D true, }, - .l1i_cache =3D { + .l1i_cache =3D &(CPUCacheInfo) { .type =3D ICACHE, .level =3D 1, .size =3D 64 * KiB, @@ -1136,7 +1136,7 @@ static CPUCaches epyc_cache_info =3D { .self_init =3D 1, .no_invd_sharing =3D true, }, - .l2_cache =3D { + .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, .level =3D 2, .size =3D 512 * KiB, @@ -1146,7 +1146,7 @@ static CPUCaches epyc_cache_info =3D { .sets =3D 1024, .lines_per_tag =3D 1, }, - .l3_cache =3D { + .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, .level =3D 3, .size =3D 8 * MiB, @@ -3340,9 +3340,8 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefin= ition *def, Error **errp) env->features[w] =3D def->features[w]; } =20 - /* Store Cache information from the X86CPUDefinition if available */ - env->cache_info =3D def->cache_info; - cpu->legacy_cache =3D def->cache_info ? 0 : 1; + /* legacy-cache defaults to 'off' if CPU model provides cache info */ + cpu->legacy_cache =3D !def->cache_info; =20 /* Special cases not set in the X86CPUDefinition structs: */ /* TODO: in-kernel irqchip for hvf */ @@ -3693,21 +3692,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, if (!cpu->enable_l3_cache) { *ecx =3D 0; } else { - if (env->cache_info && !cpu->legacy_cache) { - *ecx =3D cpuid2_cache_descriptor(&env->cache_info->l3_cach= e); - } else { - *ecx =3D cpuid2_cache_descriptor(&legacy_l3_cache); - } - } - if (env->cache_info && !cpu->legacy_cache) { - *edx =3D (cpuid2_cache_descriptor(&env->cache_info->l1d_cache)= << 16) | - (cpuid2_cache_descriptor(&env->cache_info->l1i_cache) <= < 8) | - (cpuid2_cache_descriptor(&env->cache_info->l2_cache)); - } else { - *edx =3D (cpuid2_cache_descriptor(&legacy_l1d_cache) << 16) | - (cpuid2_cache_descriptor(&legacy_l1i_cache) << 8) | - (cpuid2_cache_descriptor(&legacy_l2_cache_cpuid2)); + *ecx =3D cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cac= he); } + *edx =3D (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache= ) << 16) | + (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) = << 8) | + (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); break; case 4: /* cache info: needed for Core compatibility */ @@ -3720,35 +3709,27 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, } } else { *eax =3D 0; - CPUCacheInfo *l1d, *l1i, *l2, *l3; - if (env->cache_info && !cpu->legacy_cache) { - l1d =3D &env->cache_info->l1d_cache; - l1i =3D &env->cache_info->l1i_cache; - l2 =3D &env->cache_info->l2_cache; - l3 =3D &env->cache_info->l3_cache; - } else { - l1d =3D &legacy_l1d_cache; - l1i =3D &legacy_l1i_cache; - l2 =3D &legacy_l2_cache; - l3 =3D &legacy_l3_cache; - } switch (count) { case 0: /* L1 dcache info */ - encode_cache_cpuid4(l1d, 1, cs->nr_cores, + encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, + 1, cs->nr_cores, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ - encode_cache_cpuid4(l1i, 1, cs->nr_cores, + encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, + 1, cs->nr_cores, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ - encode_cache_cpuid4(l2, cs->nr_threads, cs->nr_cores, + encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, + cs->nr_threads, cs->nr_cores, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ pkg_offset =3D apicid_pkg_offset(cs->nr_cores, cs->nr_thre= ads); if (cpu->enable_l3_cache) { - encode_cache_cpuid4(l3, (1 << pkg_offset), cs->nr_core= s, + encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, + (1 << pkg_offset), cs->nr_cores, eax, ebx, ecx, edx); break; } @@ -3961,13 +3942,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); *ebx =3D (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \ (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); - if (env->cache_info && !cpu->legacy_cache) { - *ecx =3D encode_cache_cpuid80000005(&env->cache_info->l1d_cach= e); - *edx =3D encode_cache_cpuid80000005(&env->cache_info->l1i_cach= e); - } else { - *ecx =3D encode_cache_cpuid80000005(&legacy_l1d_cache_amd); - *edx =3D encode_cache_cpuid80000005(&legacy_l1i_cache_amd); - } + *ecx =3D encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); + *edx =3D encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); break; case 0x80000006: /* cache info (L2 cache) */ @@ -3983,17 +3959,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, (L2_DTLB_4K_ENTRIES << 16) | \ (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \ (L2_ITLB_4K_ENTRIES); - if (env->cache_info && !cpu->legacy_cache) { - encode_cache_cpuid80000006(&env->cache_info->l2_cache, - cpu->enable_l3_cache ? - &env->cache_info->l3_cache : NULL, - ecx, edx); - } else { - encode_cache_cpuid80000006(&legacy_l2_cache_amd, - cpu->enable_l3_cache ? - &legacy_l3_cache : NULL, - ecx, edx); - } + encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, + cpu->enable_l3_cache ? + env->cache_info_amd.l3_cache : NULL, + ecx, edx); break; case 0x80000007: *eax =3D 0; @@ -4690,6 +4659,37 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) cpu->phys_bits =3D 32; } } + + /* Cache information initialization */ + if (!cpu->legacy_cache) { + if (!xcc->cpu_def || !xcc->cpu_def->cache_info) { + char *name =3D x86_cpu_class_get_model_name(xcc); + error_setg(errp, + "CPU model '%s' doesn't support legacy-cache=3Doff"= , name); + g_free(name); + return; + } + env->cache_info_cpuid2 =3D env->cache_info_cpuid4 =3D env->cache_i= nfo_amd =3D + *xcc->cpu_def->cache_info; + } else { + /* Build legacy cache information */ + env->cache_info_cpuid2.l1d_cache =3D &legacy_l1d_cache; + env->cache_info_cpuid2.l1i_cache =3D &legacy_l1i_cache; + env->cache_info_cpuid2.l2_cache =3D &legacy_l2_cache_cpuid2; + env->cache_info_cpuid2.l3_cache =3D &legacy_l3_cache; + + env->cache_info_cpuid4.l1d_cache =3D &legacy_l1d_cache; + env->cache_info_cpuid4.l1i_cache =3D &legacy_l1i_cache; + env->cache_info_cpuid4.l2_cache =3D &legacy_l2_cache; + env->cache_info_cpuid4.l3_cache =3D &legacy_l3_cache; + + env->cache_info_amd.l1d_cache =3D &legacy_l1d_cache_amd; + env->cache_info_amd.l1i_cache =3D &legacy_l1i_cache_amd; + env->cache_info_amd.l2_cache =3D &legacy_l2_cache_amd; + env->cache_info_amd.l3_cache =3D &legacy_l3_cache; + } + + cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); @@ -5173,11 +5173,10 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), /* - * lecacy_cache defaults to CPU model being chosen. This is set in - * x86_cpu_load_def based on cache_info which is initialized in - * builtin_x86_defs + * lecacy_cache defaults to true unless the CPU model provides its + * own cache information (see x86_cpu_load_def()). */ - DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, false), + DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), =20 /* * From "Requirements for Implementing the Microsoft --=20 2.18.0.rc1.1.g3f1ff2140 From nobody Thu May 2 09:57:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528738175182339.1288451487005; Mon, 11 Jun 2018 10:29:35 -0700 (PDT) Received: from localhost ([::1]:50440 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSQdK-0002mM-CY for importer@patchew.org; Mon, 11 Jun 2018 13:29:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55947) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSQYA-0006qF-U4 for qemu-devel@nongnu.org; Mon, 11 Jun 2018 13:24:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fSQY9-0000Wk-MN for qemu-devel@nongnu.org; Mon, 11 Jun 2018 13:24:14 -0400 Received: from mx1.redhat.com ([209.132.183.28]:43854) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fSQY9-0000W8-EY for qemu-devel@nongnu.org; Mon, 11 Jun 2018 13:24:13 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7CDAB3082A4F; Mon, 11 Jun 2018 17:24:12 +0000 (UTC) Received: from localhost (ovpn-116-19.gru2.redhat.com [10.97.116.19]) by smtp.corp.redhat.com (Postfix) with ESMTP id C0D4A18B48; Mon, 11 Jun 2018 17:24:06 +0000 (UTC) From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org Date: Mon, 11 Jun 2018 14:23:54 -0300 Message-Id: <20180611172355.12067-3-ehabkost@redhat.com> In-Reply-To: <20180611172355.12067-1-ehabkost@redhat.com> References: <20180611172355.12067-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.45]); Mon, 11 Jun 2018 17:24:12 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 2/3] i386: Populate AMD Processor Cache Information for cpuid 0x8000001D X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , kvm@vger.kernel.org, "Michael S. Tsirkin" , Marcelo Tosatti , Babu Moger , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Babu Moger Add information for cpuid 0x8000001D leaf. Populate cache topology informat= ion for different cache types (Data Cache, Instruction Cache, L2 and L3) suppor= ted by 0x8000001D leaf. Please refer to the Processor Programming Reference (PP= R) for AMD Family 17h Model for more details. Signed-off-by: Babu Moger Message-Id: <1527176614-26271-3-git-send-email-babu.moger@amd.com> Reviewed-by: Eduardo Habkost Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 117 ++++++++++++++++++++++++++++++++++++++++++++++ target/i386/kvm.c | 29 ++++++++++-- 2 files changed, 143 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1ea7bf4911..1e69e68f25 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -334,6 +334,99 @@ static void encode_cache_cpuid80000006(CPUCacheInfo *l= 2, } } =20 +/* + * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E + * Please refer to the AMD64 Architecture Programmer=E2=80=99s Manual Volu= me 3. + * Define the constants to build the cpu topology. Right now, TOPOEXT + * feature is enabled only on EPYC. So, these constants are based on + * EPYC supported configurations. We may need to handle the cases if + * these values change in future. + */ +/* Maximum core complexes in a node */ +#define MAX_CCX 2 +/* Maximum cores in a core complex */ +#define MAX_CORES_IN_CCX 4 +/* Maximum cores in a node */ +#define MAX_CORES_IN_NODE 8 +/* Maximum nodes in a socket */ +#define MAX_NODES_PER_SOCKET 4 + +/* + * Figure out the number of nodes required to build this config. + * Max cores in a node is 8 + */ +static int nodes_in_socket(int nr_cores) +{ + int nodes; + + nodes =3D DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE); + + /* Hardware does not support config with 3 nodes, return 4 in that case= */ + return (nodes =3D=3D 3) ? 4 : nodes; +} + +/* + * Decide the number of cores in a core complex with the given nr_cores us= ing + * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and + * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible + * L3 cache is shared across all cores in a core complex. So, this will al= so + * tell us how many cores are sharing the L3 cache. + */ +static int cores_in_core_complex(int nr_cores) +{ + int nodes; + + /* Check if we can fit all the cores in one core complex */ + if (nr_cores <=3D MAX_CORES_IN_CCX) { + return nr_cores; + } + /* Get the number of nodes required to build this config */ + nodes =3D nodes_in_socket(nr_cores); + + /* + * Divide the cores accros all the core complexes + * Return rounded up value + */ + return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX); +} + +/* Encode cache info for CPUID[8000001D] */ +static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs, + uint32_t *eax, uint32_t *ebx, + uint32_t *ecx, uint32_t *edx) +{ + uint32_t l3_cores; + assert(cache->size =3D=3D cache->line_size * cache->associativity * + cache->partitions * cache->sets); + + *eax =3D CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | + (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); + + /* L3 is shared among multiple cores */ + if (cache->level =3D=3D 3) { + l3_cores =3D cores_in_core_complex(cs->nr_cores); + *eax |=3D ((l3_cores * cs->nr_threads) - 1) << 14; + } else { + *eax |=3D ((cs->nr_threads - 1) << 14); + } + + assert(cache->line_size > 0); + assert(cache->partitions > 0); + assert(cache->associativity > 0); + /* We don't implement fully-associative caches */ + assert(cache->associativity < cache->sets); + *ebx =3D (cache->line_size - 1) | + ((cache->partitions - 1) << 12) | + ((cache->associativity - 1) << 22); + + assert(cache->sets > 0); + *ecx =3D cache->sets - 1; + + *edx =3D (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | + (cache->inclusive ? CACHE_INCLUSIVE : 0) | + (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); +} + /* * Definitions of the hardcoded cache entries we expose: * These are legacy cache values. If there is a need to change any @@ -4003,6 +4096,30 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *edx =3D 0; } break; + case 0x8000001D: + *eax =3D 0; + switch (count) { + case 0: /* L1 dcache info */ + encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs, + eax, ebx, ecx, edx); + break; + case 1: /* L1 icache info */ + encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs, + eax, ebx, ecx, edx); + break; + case 2: /* L2 cache info */ + encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs, + eax, ebx, ecx, edx); + break; + case 3: /* L3 cache info */ + encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs, + eax, ebx, ecx, edx); + break; + default: /* end of info */ + *eax =3D *ebx =3D *ecx =3D *edx =3D 0; + break; + } + break; case 0xC0000000: *eax =3D env->cpuid_xlevel2; *ebx =3D 0; diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 44f70733e7..445e0e0b11 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -979,9 +979,32 @@ int kvm_arch_init_vcpu(CPUState *cs) } c =3D &cpuid_data.entries[cpuid_i++]; =20 - c->function =3D i; - c->flags =3D 0; - cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); + switch (i) { + case 0x8000001d: + /* Query for all AMD cache information leaves */ + for (j =3D 0; ; j++) { + c->function =3D i; + c->flags =3D KVM_CPUID_FLAG_SIGNIFCANT_INDEX; + c->index =3D j; + cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->ed= x); + + if (c->eax =3D=3D 0) { + break; + } + if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { + fprintf(stderr, "cpuid_data is full, no space for " + "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); + abort(); + } + c =3D &cpuid_data.entries[cpuid_i++]; + } + break; + default: + c->function =3D i; + c->flags =3D 0; + cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); + break; + } } =20 /* Call Centaur's CPUID instructions they are supported. */ --=20 2.18.0.rc1.1.g3f1ff2140 From nobody Thu May 2 09:57:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528737954439284.6244832315741; Mon, 11 Jun 2018 10:25:54 -0700 (PDT) Received: from localhost ([::1]:50415 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSQZl-00080y-N7 for importer@patchew.org; Mon, 11 Jun 2018 13:25:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56001) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSQYG-0006uH-WD for qemu-devel@nongnu.org; Mon, 11 Jun 2018 13:24:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fSQYD-0000Zk-Mt for qemu-devel@nongnu.org; Mon, 11 Jun 2018 13:24:20 -0400 Received: from mx1.redhat.com ([209.132.183.28]:41775) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fSQYD-0000Zc-Gr for qemu-devel@nongnu.org; Mon, 11 Jun 2018 13:24:17 -0400 Received: from smtp.corp.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B6B4B30820F3; Mon, 11 Jun 2018 17:24:16 +0000 (UTC) Received: from localhost (ovpn-116-19.gru2.redhat.com [10.97.116.19]) by smtp.corp.redhat.com (Postfix) with ESMTP id DBE68A3FCC; Mon, 11 Jun 2018 17:24:13 +0000 (UTC) From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org Date: Mon, 11 Jun 2018 14:23:55 -0300 Message-Id: <20180611172355.12067-4-ehabkost@redhat.com> In-Reply-To: <20180611172355.12067-1-ehabkost@redhat.com> References: <20180611172355.12067-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.27 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.47]); Mon, 11 Jun 2018 17:24:16 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 3/3] pc: Remove PC_COMPAT_2_12 from 3.0 machine-types X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , kvm@vger.kernel.org, "Michael S. Tsirkin" , Marcelo Tosatti , Xiao Guangrong , Juan Quintela , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" commit f548222c added PC_COMPAT_2_12 to the 3.0 PC machine-types. I believe this happened during manual conflict resolution when applying the patch. Cc: Xiao Guangrong Cc: Juan Quintela Fixes: f548222c24342ca74689de7794f9006b43f86a54 Signed-off-by: Eduardo Habkost Message-Id: <20180608192940.19548-1-ehabkost@redhat.com> Reviewed-by: Marcel Apfelbaum Signed-off-by: Eduardo Habkost --- hw/i386/pc_piix.c | 1 - hw/i386/pc_q35.c | 1 - 2 files changed, 2 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 3d81136065..b4c5b03274 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -430,7 +430,6 @@ static void pc_i440fx_3_0_machine_options(MachineClass = *m) pc_i440fx_machine_options(m); m->alias =3D "pc"; m->is_default =3D 1; - SET_MACHINE_COMPAT(m, PC_COMPAT_2_12); } =20 DEFINE_I440FX_MACHINE(v3_0, "pc-i440fx-3.0", NULL, diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index b60cbb9266..83d6d75efa 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -312,7 +312,6 @@ static void pc_q35_3_0_machine_options(MachineClass *m) { pc_q35_machine_options(m); m->alias =3D "q35"; - SET_MACHINE_COMPAT(m, PC_COMPAT_2_12); } =20 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, --=20 2.18.0.rc1.1.g3f1ff2140