From nobody Mon Apr 29 04:03:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528489183224940.7261205229408; Fri, 8 Jun 2018 13:19:43 -0700 (PDT) Received: from localhost ([::1]:38045 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNrB-0000u7-Lz for importer@patchew.org; Fri, 08 Jun 2018 16:19:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47876) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNex-0007de-0h for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:07:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fRNet-0006l7-6p for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:06:54 -0400 Received: from mout.kundenserver.de ([212.227.126.131]:52991) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fRNei-0006ew-6D; Fri, 08 Jun 2018 16:06:40 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue002 [212.227.15.167]) with ESMTPSA (Nemesis) id 0Ls3eJ-1gPNHj1Str-013tij; Fri, 08 Jun 2018 22:06:09 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 8 Jun 2018 22:05:46 +0200 Message-Id: <20180608200558.386-2-laurent@vivier.eu> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180608200558.386-1-laurent@vivier.eu> References: <20180608200558.386-1-laurent@vivier.eu> X-Provags-ID: V03:K1:hHqHwRIS5GiL8h1Ldh0Kgpn/yXW/p01cA0UZhsrBs5jem1KESq0 twnl1ZUrWTXr6x6XqyKWmjXEL8wMkuO52fUEGeyzzbqpsknDoPKd5YbENwWmaRVWDVm/HkC FmgxNA5JHlLyZwDhgEFL4bKdWHRqvGENHkVxh0F+Hzju8HESkw9rAkui+jece84Ch9BSbDv jW5GxrtzxmeqxJaamrdqg== X-UI-Out-Filterresults: notjunk:1;V01:K0:R5tXzjBOjk8=:DOMU7ZCQd+/0QI12wB5AIY P+b+ShrlP9Fwr5UwCNBUgCq0yZnXUICxeld4w8CU0b+ACjH0Jkmq2RrFp7vPh+236tpSjQo8N RmIz+FfeGmsQuxerx5W7A6l3sUiA30CFTzcy1qa7I3ZuiizrHZAn9mD1ZQsw4TkN+KUJBYSyZ XEjngz0Y8sjHVbbD42eS3JUAXt8IAkDVyPGf/vkyJGfyKpivW+321Zqku37zDXABYuCCUP2fQ tpIXYXfZOEXvHs9fSU7greJUXNlFMHPBCZAGFnwbiFUt9QG6dpKZqalZ7ArKerhC/EPwRqxiK kfKkVTH1cUhfNbOAFQjQBWkE+tSjEGMBiV7pMJuYagasdfth1UoH8tC6EOOMdFjIwh2l4Awko rGrMGRtp/sk7pHkJWJ67aVdS24NqPpuFihW8km0jCtXG7wUwkP8k7w+ZSjD7CEr6LMHppCCxx qbctiLIUa7X5FXLMOkw3XCwcNDOk4X8gTPsUxD6qK3EcCt4PlX2RbFDcL/VowLIjDHl593Cug XLPeUXAqHUPJFSo3Lh2Vz14wfOZHvN/csjw2TFpZMshdLMr9DHpyn6OfBwjpPYUpGViBCMIIB rxvgTx6K3oMZf3HIVrlnTX2+/kLPWuYh9g8hL4UHukraTovwcH3J5D/2nT/b8xPGayyZKVcMx qeQ2Xd1d3W29CbF7otNEC6H1FIfDUV10oAL3iOkuFlCiu99gJGvHUSeQvuoWlCLiUA2k= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.131 Subject: [Qemu-devel] [RFC 01/13] hw/m68k: add via support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Jason Wang , "Dr. David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , Yongbok Kim , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Laurent Vivier --- hw/input/adb.c | 99 ++++- hw/misc/Makefile.objs | 1 + hw/misc/mac_via.c | 940 ++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/input/adb.h | 8 + include/hw/misc/mac_via.h | 45 +++ 5 files changed, 1092 insertions(+), 1 deletion(-) create mode 100644 hw/misc/mac_via.c create mode 100644 include/hw/misc/mac_via.h diff --git a/hw/input/adb.c b/hw/input/adb.c index 23ae6f0d75..2e5460730c 100644 --- a/hw/input/adb.c +++ b/hw/input/adb.c @@ -25,6 +25,17 @@ #include "hw/input/adb.h" #include "adb-internal.h" =20 +#define ADB_POLL_FREQ 50 + +/* Apple Macintosh Family Hardware Refenece + * Table 19-10 ADB transaction states + */ + +#define STATE_NEW 0 +#define STATE_EVEN 1 +#define STATE_ODD 2 +#define STATE_IDLE 3 + /* error codes */ #define ADB_RET_NOTPRESENT (-2) =20 @@ -57,7 +68,6 @@ int adb_request(ADBBusState *s, uint8_t *obuf, const uint= 8_t *buf, int len) return ADB_RET_NOTPRESENT; } =20 -/* XXX: move that to cuda ? */ int adb_poll(ADBBusState *s, uint8_t *obuf, uint16_t poll_mask) { ADBDevice *d; @@ -84,6 +94,93 @@ int adb_poll(ADBBusState *s, uint8_t *obuf, uint16_t pol= l_mask) return olen; } =20 +int adb_send(ADBBusState *adb, int state, uint8_t data) +{ + switch (state) { + case STATE_NEW: + adb->data_out[0] =3D data; + adb->data_out_index =3D 1; + break; + case STATE_EVEN: + if ((adb->data_out_index & 1) =3D=3D 0) { + return 0; + } + adb->data_out[adb->data_out_index++] =3D data; + break; + case STATE_ODD: + if (adb->data_out_index & 1) { + return 0; + } + adb->data_out[adb->data_out_index++] =3D data; + break; + case STATE_IDLE: + return 0; + } + qemu_irq_raise(adb->data_ready); + return 1; +} + +int adb_receive(ADBBusState *adb, int state, uint8_t *data) +{ + switch (state) { + case STATE_NEW: + return 0; + case STATE_EVEN: + if (adb->data_in_size <=3D 0) { + qemu_irq_raise(adb->data_ready); + return 0; + } + if (adb->data_in_index >=3D adb->data_in_size) { + *data =3D 0; + qemu_irq_raise(adb->data_ready); + return 1; + } + if ((adb->data_in_index & 1) =3D=3D 0) { + return 0; + } + *data =3D adb->data_in[adb->data_in_index++]; + break; + case STATE_ODD: + if (adb->data_in_size <=3D 0) { + qemu_irq_raise(adb->data_ready); + return 0; + } + if (adb->data_in_index >=3D adb->data_in_size) { + *data =3D 0; + qemu_irq_raise(adb->data_ready); + return 1; + } + if (adb->data_in_index & 1) { + return 0; + } + *data =3D adb->data_in[adb->data_in_index++]; + break; + case STATE_IDLE: + if (adb->data_out_index =3D=3D 0) { + return 0; + } + adb->data_in_size =3D adb_request(adb, adb->data_in, + adb->data_out, adb->data_out_index= ); + adb->data_out_index =3D 0; + if (adb->data_in_size < 0) { + *data =3D 0xff; + qemu_irq_raise(adb->data_ready); + return -1; + } + if (adb->data_in_size =3D=3D 0) { + return 0; + } + *data =3D adb->data_in[0]; + adb->data_in_index =3D 1; + break; + } + qemu_irq_raise(adb->data_ready); + if (*data =3D=3D 0xff || *data =3D=3D 0) { + return 0; + } + return 1; +} + static const TypeInfo adb_bus_type_info =3D { .name =3D TYPE_ADB_BUS, .parent =3D TYPE_BUS, diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 00e834d0f0..2cd8941faa 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -68,5 +68,6 @@ obj-$(CONFIG_PVPANIC) +=3D pvpanic.o obj-$(CONFIG_HYPERV_TESTDEV) +=3D hyperv_testdev.o obj-$(CONFIG_AUX) +=3D auxbus.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_scu.o aspeed_sdmc.o +obj-$(CONFIG_MAC_VIA) +=3D mac_via.o obj-y +=3D mmio_interface.o obj-$(CONFIG_MSF2) +=3D msf2-sysreg.o diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c new file mode 100644 index 0000000000..a6a11c5b3d --- /dev/null +++ b/hw/misc/mac_via.c @@ -0,0 +1,940 @@ +/* + * QEMU m68k Macintosh VIA device support + * + * Copyright (c) 2011-2018 Laurent Vivier + * + * Some parts from hw/cuda.c + * + * Copyright (c) 2004-2007 Fabrice Bellard + * Copyright (c) 2007 Jocelyn Mayer + * + * some parts from linux-2.6.29, arch/m68k/include/asm/mac_via.h + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "qemu/timer.h" +#include "hw/misc/mac_via.h" +#include "hw/input/adb.h" +#include "sysemu/sysemu.h" +#include "qemu/cutils.h" + +/* debug VIA */ +#undef DEBUG_VIA + +#ifdef DEBUG_VIA +#define VIA_DPRINTF(fmt, ...) \ + do { printf("VIA%d: " fmt , via, ## __VA_ARGS__); } while (0) +#else +#define VIA_DPRINTF(fmt, ...) +#endif + +/* + * VIAs: There are two in every machine, + */ + +#define VIA_SIZE (0x2000) + +/* + * Not all of these are true post MacII I think. + * CSA: probably the ones CHRP marks as 'unused' change purposes + * when the IWM becomes the SWIM. + * http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html + * ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0= .pdf + * + * also, http://developer.apple.com/technotes/hw/hw_09.html claims the + * following changes for IIfx: + * VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP. + * Also, "All of the functionality of VIA2 has been moved to other chips". + */ + +#define VIA1A_vSccWrReq 0x80 /* SCC write. (input) + * [CHRP] SCC WREQ: Reflects the state of t= he + * Wait/Request pins from the SCC. + * [Macintosh Family Hardware] + * as CHRP on SE/30,II,IIx,IIcx,IIci. + * on IIfx, "0 means an active request" + */ +#define VIA1A_vRev8 0x40 /* Revision 8 board ??? + * [CHRP] En WaitReqB: Lets the WaitReq_L + * signal from port B of the SCC appear on + * the PA7 input pin. Output. + * [Macintosh Family] On the SE/30, this + * is the bit to flip screen buffers. + * 0=3Dalternate, 1=3Dmain. + * on II,IIx,IIcx,IIci,IIfx this is a bit + * for Rev ID. 0=3DII,IIx, 1=3DIIcx,IIci,II= fx + */ +#define VIA1A_vHeadSel 0x20 /* Head select for IWM. + * [CHRP] unused. + * [Macintosh Family] "Floppy disk + * state-control line SEL" on all but IIfx + */ +#define VIA1A_vOverlay 0x10 /* [Macintosh Family] On SE/30,II,IIx,IIcx + * this bit enables the "Overlay" address + * map in the address decoders as it is on + * reset for mapping the ROM over the reset + * vector. 1=3Duse overlay map. + * On the IIci,IIfx it is another bit of the + * CPU ID: 0=3Dnormal IIci, 1=3DIIci with p= arity + * feature or IIfx. + * [CHRP] En WaitReqA: Lets the WaitReq_L + * signal from port A of the SCC appear + * on the PA7 input pin (CHRP). Output. + * [MkLinux] "Drive Select" + * (with 0x20 being 'disk head select') + */ +#define VIA1A_vSync 0x08 /* [CHRP] Sync Modem: modem clock select: + * 1: select the external serial clock to + * drive the SCC's /RTxCA pin. + * 0: Select the 3.6864MHz clock to drive + * the SCC cell. + * [Macintosh Family] Correct on all but II= fx + */ + +/* Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control + * on Macs which had the PWM sound hardware. Reserved on newer models. + * On IIci,IIfx, bits 1-2 are the rest of the CPU ID: + * bit 2: 1=3DIIci, 0=3DIIfx + * bit 1: 1 on both IIci and IIfx. + * MkLinux sez bit 0 is 'burnin flag' in this case. + * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as + * inputs, these bits will read 0. + */ +#define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */ +#define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */ +#define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */ +#define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */ +#define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */ + +/* Info on VIA1B is from Macintosh Family Hardware & MkLinux. + * CHRP offers no info. */ +#define VIA1B_vSound 0x80 /* Sound enable (for compatibility with + * PWM hardware) 0=3Denabled. + * Also, on IIci w/parity, shows parity err= or + * 0=3Derror, 1=3DOK. */ +#define VIA1B_vMystery 0x40 /* On IIci, parity enable. 0=3Denabled,1=3D= disabled + * On SE/30, vertical sync interrupt enable. + * 0=3Denabled. This vSync interrupt shows = up + * as a slot $E interrupt. */ +#define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */ +#define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */ +#define VIA1B_vADBInt 0x08 /* ADB interrupt 0=3Dinterrupt (unused on I= Ifx)*/ +#define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=3Denabled. */ +#define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */ +#define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */ + +/* + * VIA2 A register is the interrupt lines raised off the nubus + * slots. + * The below info is from 'Macintosh Family Hardware.' + * MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 = irq.' + * It also notes that the slot $9 IRQ is the 'Ethernet IRQ' and + * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike. + * Perhaps OSS uses vRAM1 and vRAM2 for ADB. + */ + +#define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */ +#define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ= ) */ +#define VIA2A_vIRQE 0x20 /* IRQ from slot $E */ +#define VIA2A_vIRQD 0x10 /* IRQ from slot $D */ +#define VIA2A_vIRQC 0x08 /* IRQ from slot $C */ +#define VIA2A_vIRQB 0x04 /* IRQ from slot $B */ +#define VIA2A_vIRQA 0x02 /* IRQ from slot $A */ +#define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */ + +/* RAM size bits decoded as follows: + * bit1 bit0 size of ICs in bank A + * 0 0 256 kbit + * 0 1 1 Mbit + * 1 0 4 Mbit + * 1 1 16 Mbit + */ + +/* + * Register B has the fun stuff in it + */ + +#define VIA2B_vVBL 0x80 /* VBL output to VIA1 (60.15Hz) driven by + * timer T1. + * on IIci, parity test: 0=3Dtest mode. + * [MkLinux] RBV_PARODD: 1=3Dodd,0=3Deven. */ +#define VIA2B_vSndJck 0x40 /* External sound jack status. + * 0=3Dplug is inserted. On SE/30, always 0= */ +#define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */ +#define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */ +#define VIA2B_vMode32 0x08 /* 24/32bit switch - doubles as cache flush + * on II, AMU/PMMU control. + * if AMU, 0=3D24bit to 32bit translation + * if PMMU, 1=3DPMMU is accessing page tab= le. + * on SE/30 tied low. + * on IIx,IIcx,IIfx, unused. + * on IIci/RBV, cache control. 0=3Dflush cac= he. + */ +#define VIA2B_vPower 0x04 /* Power off, 0=3Dshut off power. + * on SE/30 this signal sent to PDS card. + */ +#define VIA2B_vBusLk 0x02 /* Lock NuBus transactions, 0=3Dlocked. + * on SE/30 sent to PDS card. + */ +#define VIA2B_vCDis 0x01 /* Cache control. On IIci, 1=3Ddisable cache = card + * on others, 0=3Ddisable processor's instruc= tion + * and data caches. + */ + +/* interrupt flags */ + +#define IRQ_SET 0x80 + +/* common */ + +#define VIA_IRQ_TIMER1 0x40 +#define VIA_IRQ_TIMER2 0x20 + +/* Apple sez: http://developer.apple.com/technotes/ov/ov_04.html + * Another example of a valid function that has no ROM support is the use + * of the alternate video page for page-flipping animation. Since there + * is no ROM call to flip pages, it is necessary to go play with the + * right bit in the VIA chip (6522 Versatile Interface Adapter). + * [CSA: don't know which one this is, but it's one of 'em!] + */ + +/* + * 6522 registers - see databook. + * CSA: Assignments for VIA1 confirmed from CHRP spec. + */ + +/* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */ +/* Note: 15 VIA regs, 8 RBV regs */ + +#define vBufB 0x0000 /* [VIA/RBV] Register B */ +#define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE= ! */ +#define vDirB 0x0400 /* [VIA only] Data Direction Register B. */ +#define vDirA 0x0600 /* [VIA only] Data Direction Register A. */ +#define vT1CL 0x0800 /* [VIA only] Timer one counter low. */ +#define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */ +#define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */ +#define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */ +#define vT2CL 0x1000 /* [VIA only] Timer two counter low. */ +#define vT2CH 0x1200 /* [VIA only] Timer two counter high. */ +#define vSR 0x1400 /* [VIA only] Shift register. */ +#define vACR 0x1600 /* [VIA only] Auxilary control register. */ +#define vPCR 0x1800 /* [VIA only] Peripheral control register. */ + /* CHRP sez never ever to *write* this. + * Mac family says never to *change* t= his. + * In fact we need to initialize it once at start. + */ +#define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */ +#define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */ +#define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */ + +/* from linux 2.6 drivers/macintosh/via-macii.c */ + +/* Bits in ACR */ + +#define VIA1ACR_vShiftCtrl 0x1c /* Shift register control b= its */ +#define VIA1ACR_vShiftExtClk 0x0c /* Shift on external clock = */ +#define VIA1ACR_vShiftOut 0x10 /* Shift out if 1 */ + +/* Apple Macintosh Family Hardware Refenece + * Table 19-10 ADB transaction states + */ + +#define VIA1B_vADB_StateMask (VIA1B_vADBS1 | VIA1B_vADBS2) +#define VIA1B_vADB_StateShift 4 + +typedef struct VIATimer { + int index; + uint16_t counter; /* Timer counter */ + uint16_t latch; /* Timer latch */ + int64_t next_irq_time; + QEMUTimer *timer; +} VIATimer; + +typedef struct VIAState { + /* VIA registers */ + uint8_t a; /* data register A */ + uint8_t b; /* data register B */ + uint8_t dira; /* data direction register A (1 =3D output) */ + uint8_t dirb; /* data direction register B (1 =3D output) */ + uint8_t pcr; /* peripheral control register */ + uint8_t acr; /* auxiliary control register */ + uint8_t ifr; /* interrupt flag register */ + uint8_t ier; /* interrupt enable register */ + uint8_t sr; /* shift register */ + + uint8_t last_b; + + /* Timers */ + + VIATimer timers[2]; + + /* IRQs */ + + qemu_irq out_irq; + +} VIAState; + +typedef struct MacVIAState { + SysBusDevice busdev; + + /* MMIO */ + + MemoryRegion mmio; + + /* VIAs */ + + VIAState via[2]; + + /* RTC */ + + uint32_t tick_offset; + + uint8_t data_out; + int data_out_cnt; + uint8_t data_in; + uint8_t data_in_cnt; + uint8_t cmd; + int wprotect; + int alt; + + /* ADB */ + + ADBBusState adb_bus; + + /* external timers */ + + QEMUTimer *one_second_timer; + QEMUTimer *VBL_timer; + +} MacVIAState; + +#define VIA_TIMER_FREQ (783360) + +static int64_t get_next_irq_time(VIATimer *s, int64_t current_time) +{ + int64_t d, next_time; + + /* current counter value */ + d =3D muldiv64(current_time, VIA_TIMER_FREQ, NANOSECONDS_PER_SECOND); + next_time =3D d + s->counter; + next_time =3D muldiv64(next_time, NANOSECONDS_PER_SECOND, VIA_TIMER_FR= EQ); + if (next_time <=3D current_time) { + next_time =3D current_time + 1; + } + return next_time; +} + +#define T1MODE 0xc0 +#define T1MODE_CONT 0x40 + +static void via_arm_timer(VIATimer *ti, int64_t current_time) +{ + if (!ti->timer) { + return; + } + ti->next_irq_time =3D get_next_irq_time(ti, current_time); + timer_mod(ti->timer, ti->next_irq_time); +} + +static void via_timer_update(VIAState *s, VIATimer *ti, + int64_t current_time) +{ + if (!ti->timer) { + return; + } + if (!(s->ier & VIA_IRQ_TIMER1) && + (s->acr & T1MODE) !=3D T1MODE_CONT) { + timer_del(ti->timer); + } else { + ti->counter =3D ti->latch; + via_arm_timer(ti, current_time); + } +} + +static void via_update_irq(VIAState *s) +{ + if (s->ifr & s->ier) { + qemu_irq_raise(s->out_irq); + } else { + qemu_irq_lower(s->out_irq); + } +} + +static void via_timer1(void *opaque) +{ + VIAState *s =3D opaque; + VIATimer *ti =3D &s->timers[0]; + + via_timer_update(s, ti, ti->next_irq_time); + s->ifr |=3D VIA_IRQ_TIMER1; + via_update_irq(s); +} + +static void via1_VBL_update(MacVIAState *m) +{ + if (m->via[0].ifr & m->via[0].ier & VIA1_IRQ_VBLANK) { /* 60 Hz irq */ + timer_mod(m->VBL_timer, (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 1= 6630) + / 16630 * 16630); + } else { + timer_del(m->VBL_timer); + } +} + +static void via1_VBL(void *opaque) +{ + MacVIAState *m =3D opaque; + via1_VBL_update(m); + m->via[0].ifr |=3D VIA1_IRQ_VBLANK; + via_update_irq(&m->via[0]); +} + +static void via1_irq_request(VIAState *s, int irq, int level) +{ + if (level) { + s->ifr |=3D 1 << irq; + } else { + s->ifr &=3D ~(1 << irq); + } + via_update_irq(s); +} + +static void via2_irq_request(VIAState *s, int irq, int level) +{ + if (level) { + s->ifr |=3D 1 << irq; + } else { + s->ifr &=3D ~(1 << irq); + } + via_update_irq(s); +} + +static void via_irq_request(void *opaque, int irq, int level) +{ + MacVIAState *s =3D opaque; + if (irq < VIA1_IRQ_NB) { + via1_irq_request(&s->via[0], irq, level); + return; + } + irq -=3D VIA1_IRQ_NB; + if (irq < VIA2_IRQ_NB) { + via2_irq_request(&s->via[1], irq, level); + return; + } +} + +static void via1_one_second_update(MacVIAState *m) +{ + if (m->via[0].ifr & m->via[0].ier & VIA1_IRQ_ONE_SECOND) { + timer_mod(m->one_second_timer, (qemu_clock_get_ms(QEMU_CLOCK_VIRTU= AL) + + 1000) / 1000 * 1000); + } else { + timer_del(m->one_second_timer); + } +} + +static void via1_one_second(void *opaque) +{ + MacVIAState *m =3D opaque; + via1_one_second_update(m); + m->via[0].ifr |=3D VIA1_IRQ_ONE_SECOND; + via_update_irq(&m->via[0]); +} + +static void via_irq_update(MacVIAState *m, int via) +{ + switch (via) { + case 0: + via1_one_second_update(m); + via1_VBL(m); + break; + case 1: + break; + } +} + +#define RTC_OFFSET 2082844800 +static uint8_t PRAM[256]; + +static void via1_rtc_update(MacVIAState *m) +{ + VIAState *s =3D &m->via[0]; + + if (s->b & VIA1B_vRTCEnb) { + return; + } + + if (s->dirb & VIA1B_vRTCData) { + /* send bits to the RTC */ + if (!(s->last_b & VIA1B_vRTCClk) && (s->b & VIA1B_vRTCClk)) { + m->data_out <<=3D 1; + m->data_out |=3D s->b & VIA1B_vRTCData; + m->data_out_cnt++; + } + } else { + /* receive bits from the RTC */ + if ((s->last_b & VIA1B_vRTCClk) && + !(s->b & VIA1B_vRTCClk) && + m->data_in_cnt) { + s->b =3D (s->b & ~VIA1B_vRTCData) | + ((m->data_in >> 7) & VIA1B_vRTCData); + m->data_in <<=3D 1; + m->data_in_cnt--; + } + } + + if (m->data_out_cnt =3D=3D 8) { + m->data_out_cnt =3D 0; + + if (m->cmd =3D=3D 0) { + if (m->data_out & 0x80) { + /* this is a read command */ + uint32_t time =3D m->tick_offset + + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / + NANOSECONDS_PER_SECOND); + if (m->data_out =3D=3D 0x81) { /* seconds register = 0 */ + m->data_in =3D time & 0xff; + m->data_in_cnt =3D 8; + } else if (m->data_out =3D=3D 0x85) { /* seconds register = 1 */ + m->data_in =3D (time >> 8) & 0xff; + m->data_in_cnt =3D 8; + } else if (m->data_out =3D=3D 0x89) { /* seconds register = 2 */ + m->data_in =3D (time >> 16) & 0xff; + m->data_in_cnt =3D 8; + } else if (m->data_out =3D=3D 0x8d) { /* seconds register = 3 */ + m->data_in =3D (time >> 24) & 0xff; + m->data_in_cnt =3D 8; + } else if ((m->data_out & 0xf3) =3D=3D 0xa1) { + /* PRAM address 0x10 -> 0x13 */ + int addr =3D (m->data_out >> 2) & 0x03; + m->data_in =3D PRAM[addr]; + m->data_in_cnt =3D 8; + } else if ((m->data_out & 0xf3) =3D=3D 0xa1) { + /* PRAM address 0x00 -> 0x0f */ + int addr =3D (m->data_out >> 2) & 0x0f; + m->data_in =3D PRAM[addr]; + m->data_in_cnt =3D 8; + } else if ((m->data_out & 0xf8) =3D=3D 0xb8) { + /* extended memory designator and sector number */ + m->cmd =3D m->data_out; + } + } else { + /* this is a write command */ + m->cmd =3D m->data_out; + } + } else { + if (m->cmd & 0x80) { + if ((m->cmd & 0xf8) =3D=3D 0xb8) { + /* extended memory designator and sector number */ + int sector =3D m->cmd & 0x07; + int addr =3D (m->data_out >> 2) & 0x1f; + + m->data_in =3D PRAM[sector * 8 + addr]; + m->data_in_cnt =3D 8; + } + } else if (!m->wprotect) { + /* this is a write command */ + if (m->alt !=3D 0) { + /* extended memory designator and sector number */ + int sector =3D m->cmd & 0x07; + int addr =3D (m->alt >> 2) & 0x1f; + + PRAM[sector * 8 + addr] =3D m->data_out; + + m->alt =3D 0; + } else if (m->cmd =3D=3D 0x01) { /* seconds register 0 */ + /* FIXME */ + } else if (m->cmd =3D=3D 0x05) { /* seconds register 1 */ + /* FIXME */ + } else if (m->cmd =3D=3D 0x09) { /* seconds register 2 */ + /* FIXME */ + } else if (m->cmd =3D=3D 0x0d) { /* seconds register 3 */ + /* FIXME */ + } else if (m->cmd =3D=3D 0x31) { + /* Test Register */ + } else if (m->cmd =3D=3D 0x35) { + /* Write Protect register */ + m->wprotect =3D m->data_out & 1; + } else if ((m->cmd & 0xf3) =3D=3D 0xa1) { + /* PRAM address 0x10 -> 0x13 */ + int addr =3D (m->cmd >> 2) & 0x03; + PRAM[addr] =3D m->data_out; + } else if ((m->cmd & 0xf3) =3D=3D 0xa1) { + /* PRAM address 0x00 -> 0x0f */ + int addr =3D (m->cmd >> 2) & 0x0f; + PRAM[addr] =3D m->data_out; + } else if ((m->cmd & 0xf8) =3D=3D 0xb8) { + /* extended memory designator and sector number */ + m->alt =3D m->cmd; + } + } + } + m->data_out =3D 0; + } +} + +static void via1_adb_update(MacVIAState *m) +{ + VIAState *s =3D &m->via[0]; + int state; + int ret; + + state =3D (s->b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; + + if (s->acr & VIA1ACR_vShiftOut) { + /* output mode */ + ret =3D adb_send(&m->adb_bus, state, s->sr); + if (ret > 0) { + s->b &=3D ~VIA1B_vADBInt; + } else { + s->b |=3D VIA1B_vADBInt; + } + } else { + /* input mode */ + ret =3D adb_receive(&m->adb_bus, state, &s->sr); + if (ret > 0) { + s->b &=3D ~VIA1B_vADBInt; + } else { + s->b |=3D VIA1B_vADBInt; + } + } +} + +static void via_write(void *opaque, hwaddr addr, + uint64_t val, unsigned int size) +{ + MacVIAState *m =3D opaque; + VIAState *s; + int via; + + via =3D addr / VIA_SIZE; + addr &=3D VIA_SIZE - 1; + + s =3D &m->via[via]; + + switch (addr) { + case vBufA: /* Buffer A */ + VIA_DPRINTF("writeb: vBufA =3D %02"PRIx64"\n", val); + s->a =3D (s->a & ~s->dira) | (val & s->dira); + break; + case vBufB: /* Register B */ + VIA_DPRINTF("writeb: vBufB =3D %02"PRIx64"\n", val); + s->b =3D (s->b & ~s->dirb) | (val & s->dirb); + switch (via) { + case 0: + via1_rtc_update(m); + via1_adb_update(m); + s->last_b =3D s->b; + break; + case 1: + if (s->dirb & VIA2B_vPower && + (val & VIA2B_vPower) =3D=3D 0) { + /* shutdown */ + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN= ); + } + break; + } + break; + case vDirA: /* Data Direction Register A. */ + VIA_DPRINTF("writeb: vDirA =3D %02"PRIx64"\n", val); + s->dira =3D val; + break; + case vDirB: /* Data Direction Register B. */ + VIA_DPRINTF("writeb: vDirB =3D %02"PRIx64"\n", val); + s->dirb =3D val; + break; + case vT1CL: /* Timer one counter low. */ + VIA_DPRINTF("writeb: vT1CL =3D %02"PRIx64"\n", val); + s->timers[0].counter =3D (s->timers[0].counter & 0xff00) | val; + break; + case vT1CH: /* Timer one counter high. */ + VIA_DPRINTF("writeb: vT1CH =3D %02"PRIx64"\n", val); + s->timers[0].counter =3D (s->timers[0].counter & 0x00ff) | (val <<= 8); + via_arm_timer(&s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)= ); + break; + case vT1LL: /* Timer one latches low. */ + VIA_DPRINTF("writeb: vT1LL =3D %02"PRIx64"\n", val); + s->timers[0].latch =3D (s->timers[0].latch & 0xff00) | val; + break; + case vT1LH: /* Timer one latches high. */ + VIA_DPRINTF("writeb: vT1LH =3D %02"PRIx64"\n", val); + s->timers[0].latch =3D (s->timers[0].latch & 0x00ff) | (val << 8); + via_arm_timer(&s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)= ); + break; + case vT2CL: /* Timer two counter low. */ + VIA_DPRINTF("writeb: vT2CL =3D %02"PRIx64"\n", val); + s->timers[1].counter =3D (s->timers[1].counter & 0xff00) | val; + break; + case vT2CH: /* Timer two counter high. */ + VIA_DPRINTF("writeb: vT2CH =3D %02"PRIx64"\n", val); + s->timers[1].counter =3D (s->timers[1].counter & 0x00ff) | (val <<= 8); + via_arm_timer(&s->timers[1], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)= ); + break; + case vSR: /* Shift register. */ + VIA_DPRINTF("writeb: vSR =3D %02"PRIx64"\n", val); + s->sr =3D val; + break; + case vACR: /* Auxilary control register. */ + VIA_DPRINTF("writeb: vACR =3D %02"PRIx64"\n", val); + s->acr =3D val; + via_timer_update(s, &s->timers[0], + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + break; + case vPCR: /* Peripheral control register. */ + VIA_DPRINTF("writeb: vPCR =3D %02"PRIx64"\n", val); + s->pcr =3D val; + break; + case vIFR: /* Interrupt flag register. */ + VIA_DPRINTF("writeb: vIFR =3D %02"PRIx64"\n", val); + if (val & IRQ_SET) { + /* set bits */ + s->ifr |=3D val & 0x7f; + } else { + /* clear bits */ + s->ifr &=3D ~val; + } + VIA_DPRINTF(" -> %02x\n", s->ifr); + via_timer_update(s, &s->timers[0], + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + via_irq_update(m, via); + break; + case vIER: /* Interrupt enable register. */ + VIA_DPRINTF("writeb: vIER =3D %02"PRIx64"\n", val); + if (val & IRQ_SET) { + /* set bits */ + s->ier |=3D val & 0x7f; + } else { + /* clear bits */ + s->ier &=3D ~val; + } + VIA_DPRINTF(" -> %02x\n", s->ier); + via_timer_update(s, &s->timers[0], + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + via_irq_update(m, via); + break; + default: + VIA_DPRINTF("writeb: addr 0x%08lx val %02"PRIx64"\n", (long)addr, = val); + break; + } +} + +static uint64_t via_read(void *opaque, hwaddr addr, + unsigned int size) +{ + MacVIAState *m =3D opaque; + VIAState *s; + uint32_t val; + int via; + + via =3D addr / VIA_SIZE; + addr &=3D VIA_SIZE - 1; + + s =3D &m->via[via]; + + switch (addr) { + case vBufA: /* Buffer A */ + val =3D s->a; + VIA_DPRINTF("readb: vBufA =3D %02x\n", val); + break; + case vBufB: /* Register B */ + val =3D s->b; + VIA_DPRINTF("readb: vBufB =3D %02x\n", val); + break; + case vDirA: /* Data Direction Register A. */ + val =3D s->dira; + VIA_DPRINTF("readb: vDirA =3D %02x\n", val); + break; + case vDirB: /* Data Direction Register B. */ + val =3D s->dirb; + VIA_DPRINTF("readb: vDirB =3D %02x\n", val); + break; + case vT1CL: /* Timer one counter low. */ + val =3D s->timers[0].counter & 0x00ff; + VIA_DPRINTF("readb: vT1CL =3D %02x\n", val); + break; + case vT1CH: /* Timer one counter high. */ + val =3D (s->timers[0].counter >> 8) & 0x00ff; + VIA_DPRINTF("readb: vT1CH =3D %02x\n", val); + break; + case vT1LL: /* Timer one latches low. */ + val =3D s->timers[0].latch & 0x00ff; + VIA_DPRINTF("readb: vT1LL =3D %02x\n", val); + break; + case vT1LH: /* Timer one latches high. */ + val =3D (s->timers[0].latch >> 8) & 0x00ff; + VIA_DPRINTF("readb: vT1LH =3D %02x\n", val); + break; + case vT2CL: /* Timer two counter low. */ + val =3D s->timers[1].counter & 0x00ff; + VIA_DPRINTF("readb: vT2CL =3D %02x\n", val); + break; + case vT2CH: /* Timer two counter high. */ + val =3D (s->timers[1].counter >> 8) & 0x00ff; + VIA_DPRINTF("readb: vT2CH =3D %02x\n", val); + break; + case vSR: /* Shift register. */ + val =3D s->sr; + VIA_DPRINTF("readb: vSR =3D %02x\n", val); + break; + case vACR: /* Auxilary control register. */ + val =3D s->acr; + VIA_DPRINTF("readb: vACR =3D %02x\n", val); + break; + case vPCR: /* Peripheral control register. */ + val =3D s->pcr; + VIA_DPRINTF("readb: vPCR =3D %02x\n", val); + break; + case vIFR: /* Interrupt flag register. */ + val =3D s->ifr | ((s->ifr & 0x7f) ? IRQ_SET : 0); + VIA_DPRINTF("readb: vIFR =3D %02x\n", val); + break; + case vIER: /* Interrupt enable register. */ + val =3D s->ier | IRQ_SET; + VIA_DPRINTF("readb: vIER =3D %02x\n", val); + break; + default: + val =3D 0; + VIA_DPRINTF("readb: addr 0x%08lx val ??\n", (long)addr); + break; + } + return val; +} + +static const MemoryRegionOps via_ops =3D { + .read =3D via_read, + .write =3D via_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static void mac_via_reset(DeviceState *dev) +{ + MacVIAState *m =3D MAC_VIA(dev); + + m->via[0].a =3D 0; + /* 1 =3D disabled */ + m->via[0].b =3D VIA1B_vADB_StateMask | VIA1B_vADBInt | VIA1B_vRTCEnb; + m->via[0].dira =3D 0; + m->via[0].dirb =3D 0; + m->via[0].pcr =3D 0; + m->via[0].acr =3D 0; + m->via[0].ifr =3D 0; + m->via[0].ier =3D 0; + m->via[0].sr =3D 0; + m->via[0].last_b =3D 0; + + m->via[0].timers[0].counter =3D 0; + m->via[0].timers[0].latch =3D 0; + m->via[0].timers[1].counter =3D 0; + m->via[0].timers[1].latch =3D 0; + + m->via[1].a =3D 0; + m->via[1].b =3D 0; + m->via[1].dira =3D 0; + m->via[1].dirb =3D 0; + m->via[1].pcr =3D 0; + m->via[1].acr =3D 0; + m->via[1].ifr =3D 0; + m->via[1].ier =3D 0; + m->via[1].sr =3D 0; + m->via[1].last_b =3D 0; + + m->via[1].timers[0].counter =3D 0; + m->via[1].timers[0].latch =3D 0; + m->via[1].timers[1].counter =3D 0; + m->via[1].timers[1].latch =3D 0; + + m->data_out =3D 0; + m->data_out_cnt =3D 0; + m->data_in =3D 0; + m->data_in_cnt =3D 0; + m->cmd =3D 0; + m->wprotect =3D 0; + m->alt =3D 0; +} + +static void mac_via_realizefn(DeviceState *dev, Error **errp) +{ + MacVIAState *m =3D MAC_VIA(dev); + struct tm tm; + + /* VIA 1 */ + + m->one_second_timer =3D timer_new_ms(QEMU_CLOCK_VIRTUAL, via1_one_seco= nd, m); + m->VBL_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, via1_VBL, m); + + qemu_get_timedate(&tm, 0); + m->tick_offset =3D (uint32_t)mktimegm(&tm) + RTC_OFFSET; + + /* ouput IRQs */ + + m->via[0].timers[0].index =3D 0; + m->via[0].timers[0].timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + via_timer1, &m->via[0]); + m->via[0].timers[1].index =3D 1; + + /* VIA 2 */ + + /* output IRQs */ + + m->via[1].timers[0].index =3D 0; + m->via[1].timers[0].timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + via_timer1, &m->via[1]); + m->via[1].timers[1].index =3D 1; +} + +static void mac_via_initfn(Object *obj) +{ + SysBusDevice *d =3D SYS_BUS_DEVICE(obj); + MacVIAState *m =3D MAC_VIA(obj); + + memory_region_init_io(&m->mmio, NULL, &via_ops, m, "via", 2 * VIA_SIZE= ); + sysbus_init_mmio(d, &m->mmio); + + /* input IRQs */ + + qdev_init_gpio_in(DEVICE(d), via_irq_request, VIA1_IRQ_NB + VIA2_IRQ_N= B); + + /* ouput IRQs */ + + sysbus_init_irq(d, &m->via[0].out_irq); + sysbus_init_irq(d, &m->via[1].out_irq); + + /* ABD */ + + qbus_create_inplace((BusState *)&m->adb_bus, sizeof(m->adb_bus), + TYPE_ADB_BUS, DEVICE(obj), "adb.0"); + + m->adb_bus.data_ready =3D qdev_get_gpio_in(DEVICE(d), + VIA1_IRQ_ADB_READY_BIT); +} + +static void mac_via_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D mac_via_realizefn; + dc->reset =3D mac_via_reset; +} + +static TypeInfo mac_via_info =3D { + .name =3D TYPE_MAC_VIA, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MacVIAState), + .instance_init =3D mac_via_initfn, + .class_init =3D mac_via_class_init, +}; + +static void mac_via_register_types(void) +{ + type_register_static(&mac_via_info); +} + +type_init(mac_via_register_types); diff --git a/include/hw/input/adb.h b/include/hw/input/adb.h index 3ae8445e95..ce393004eb 100644 --- a/include/hw/input/adb.h +++ b/include/hw/input/adb.h @@ -75,6 +75,12 @@ struct ADBBusState { ADBDevice *devices[MAX_ADB_DEVICES]; int nb_devices; int poll_index; + qemu_irq data_ready; + int data_in_size; + int data_in_index; + int data_out_index; + uint8_t data_in[128]; + uint8_t data_out[16]; }; =20 int adb_request(ADBBusState *s, uint8_t *buf_out, @@ -84,4 +90,6 @@ int adb_poll(ADBBusState *s, uint8_t *buf_out, uint16_t p= oll_mask); #define TYPE_ADB_KEYBOARD "adb-keyboard" #define TYPE_ADB_MOUSE "adb-mouse" =20 +int adb_send(ADBBusState *adb, int state, uint8_t data); +int adb_receive(ADBBusState *adb, int state, uint8_t *data); #endif /* ADB_H */ diff --git a/include/hw/misc/mac_via.h b/include/hw/misc/mac_via.h new file mode 100644 index 0000000000..e106133c2a --- /dev/null +++ b/include/hw/misc/mac_via.h @@ -0,0 +1,45 @@ +/* + * + * Copyright (c) 2011-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef HW_MISC_MAC_VIA_H +#define HW_MISC_MAC_VIA_H +#define TYPE_MAC_VIA "mac_via" +#define MAC_VIA(obj) OBJECT_CHECK(MacVIAState, (obj), TYPE_MAC_VIA) + +/* VIA1 */ + +#define VIA1_IRQ_ONE_SECOND_BIT 0 +#define VIA1_IRQ_VBLANK_BIT 1 +#define VIA1_IRQ_ADB_READY_BIT 2 +#define VIA1_IRQ_ADB_DATA_BIT 3 +#define VIA1_IRQ_ADB_CLOCK_BIT 4 + +#define VIA1_IRQ_NB 8 + +#define VIA1_IRQ_ONE_SECOND (1 << VIA1_IRQ_ONE_SECOND_BIT) +#define VIA1_IRQ_VBLANK (1 << VIA1_IRQ_VBLANK_BIT) +#define VIA1_IRQ_ADB_READY (1 << VIA1_IRQ_ADB_READY_BIT) +#define VIA1_IRQ_ADB_DATA (1 << VIA1_IRQ_ADB_DATA_BIT) +#define VIA1_IRQ_ADB_CLOCK (1 << VIA1_IRQ_ADB_CLOCK_BIT) + +/* VIA2 */ + +#define VIA2_IRQ_SCSI_DATA_BIT (VIA1_IRQ_NB + 0) +#define VIA2_IRQ_SLOT_BIT (VIA1_IRQ_NB + 1) +#define VIA2_IRQ_UNUSED_BIT (VIA1_IRQ_NB + 2) +#define VIA2_IRQ_SCSI_BIT (VIA1_IRQ_NB + 3) +#define VIA2_IRQ_ASC_BIT (VIA1_IRQ_NB + 4) + +#define VIA2_IRQ_NB 8 + +#define VIA2_IRQ_SCSI_DATA (1 << VIA2_IRQ_SCSI_DATA_BIT) +#define VIA2_IRQ_SLOT (1 << VIA2_IRQ_SLOT_BIT) +#define VIA2_IRQ_UNUSED (1 << VIA2_IRQ_SCSI_BIT) +#define VIA2_IRQ_SCSI (1 << VIA2_IRQ_UNUSED_BIT) +#define VIA2_IRQ_ASC (1 << VIA2_IRQ_ASC_BIT) +#endif --=20 2.14.4 From nobody Mon Apr 29 04:03:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528488681025578.9818055998475; Fri, 8 Jun 2018 13:11:21 -0700 (PDT) Received: from localhost ([::1]:37988 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNjE-0002fD-4h for importer@patchew.org; Fri, 08 Jun 2018 16:11:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47695) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNej-0007TH-4c for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:06:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fRNeg-0006eh-02 for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:06:41 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:52463) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fRNef-0006eW-MM; Fri, 08 Jun 2018 16:06:37 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue002 [212.227.15.167]) with ESMTPSA (Nemesis) id 0LmiRI-1fuyEg46uK-00h7wA; Fri, 08 Jun 2018 22:06:11 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 8 Jun 2018 22:05:47 +0200 Message-Id: <20180608200558.386-3-laurent@vivier.eu> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180608200558.386-1-laurent@vivier.eu> References: <20180608200558.386-1-laurent@vivier.eu> X-Provags-ID: V03:K1:OOAeqONhbm45/oL9dp4aL2l+14h00SeXPzSdo2XixMxGEWtWaBQ 3rydXsOMQVb4ytK/InYhoXZ40AqTiiWW9mD0/NfzcqGT/XPb4R/mdUpsRaGquIA1R26xhHw RHavLbPTBfnZXKNYycqSkm2ASsFrxwRZ454edsNNbgw98BA9zGiinPli7pDT8lOIDhme2pN uBIFWdBF6ishwoV6SMu2w== X-UI-Out-Filterresults: notjunk:1;V01:K0:7BsHJOLEHLc=:J3sPf8abeQeOHfGh96Q3KB PJLvZC5oE56ALS5sfLtJxTzoaK65msr3h9aer51XCb1G3Hy3ow4O4pGUz4y8fgao4tLLSMpcX jAJxfaKLyJTVnUGSrR7MjG+2+gGH6Ghw49F4EyLZGbaHrQZmJojc/7J4n512g8hFimWfmkEcD 6SlFoxTiTIHwUbfyHJVYkG3qHwC3jYoMJh4EaNq4qCBG0zIemllGLnewtPVas8ZdtB+i+jS4I 0VG5L9qdAdRrIyaK3KlCKsitiBNQp4mRBFLWF6fV7p2o6xyM8JU4miuX6tJYo39BzukwTiZws 5TMAUI9Ai+rVDJw/EwNYwNkORcY2HcYL5DmkOXFSZ8c8/AVhrmvkddHPtz4/+1/9tVg9kv1gh 82VNhAj+P3bNQs8fl+M4puYXVuKQ7KC1Ta1oi7IfKKI8bYqMcXtqYPnsLD7J0EMel+orThDlo 6olf7v8OZUfWl3JjL5nygjOlzqcXFKaGLf1QsQuPmBrpMhADo4EnmgUl+i7oBadbXooffQyJg NIMfgu7C63QP1ebaJvrjjujHuVdneN9dytdil+Wixe+8wWBtF3eudYLFhnia0YNqmjsqfDm5k EN7OPVR9r8BRXX1a7VVDhonDRw0LpHxuPFj0EvnHZQ+NfcMZTO2XwhhKC1NlmT7LwgVEuKmjg AwGvi0WvDZrnSjan8t1L0uaz13OC1h8lsvojgT7CyAu0ZkA1WtFngxXZ7n28aD9UZh0o= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [RFC 02/13] ADB: VIA probes ADB bus when it is idle X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Jason Wang , "Dr. David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , Yongbok Kim , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Laurent Vivier --- hw/input/adb-kbd.c | 4 ++++ hw/input/adb-mouse.c | 4 ++++ hw/input/adb.c | 33 +++++++++++++++++++++++++-------- hw/misc/mac_via.c | 27 ++++++++++++++++++++++++++- include/hw/input/adb.h | 1 + 5 files changed, 60 insertions(+), 9 deletions(-) diff --git a/hw/input/adb-kbd.c b/hw/input/adb-kbd.c index 50b62712c8..7de92935b8 100644 --- a/hw/input/adb-kbd.c +++ b/hw/input/adb-kbd.c @@ -195,6 +195,10 @@ static int adb_kbd_poll(ADBDevice *d, uint8_t *obuf) int keycode; int olen; =20 + if (obuf =3D=3D NULL) { + return s->count; + } + olen =3D 0; if (s->count =3D=3D 0) { return 0; diff --git a/hw/input/adb-mouse.c b/hw/input/adb-mouse.c index 3ba6027d33..a3f0b74dd1 100644 --- a/hw/input/adb-mouse.c +++ b/hw/input/adb-mouse.c @@ -73,6 +73,10 @@ static int adb_mouse_poll(ADBDevice *d, uint8_t *obuf) return 0; } =20 + if (obuf =3D=3D NULL) { + return 2; + } + dx =3D s->dx; if (dx < -63) { dx =3D -63; diff --git a/hw/input/adb.c b/hw/input/adb.c index 2e5460730c..756122ac09 100644 --- a/hw/input/adb.c +++ b/hw/input/adb.c @@ -94,28 +94,47 @@ int adb_poll(ADBBusState *s, uint8_t *obuf, uint16_t po= ll_mask) return olen; } =20 +int adb_via_poll(ADBBusState *adb, int state, uint8_t *data) +{ + if (state !=3D STATE_IDLE) { + return 0; + } + if (adb->data_in_size < adb->data_in_index) { + return 0; + } + if (adb->data_out_index !=3D 0) { + return 0; + } + adb->data_in_index =3D 0; + adb->data_out_index =3D 0; + adb->data_in_size =3D adb_poll(adb, adb->data_in, 0xffff); + if (adb->data_in_size) { + *data =3D adb->data_in[adb->data_in_index++]; + qemu_irq_raise(adb->data_ready); + } + return adb->data_in_size; +} + int adb_send(ADBBusState *adb, int state, uint8_t data) { switch (state) { case STATE_NEW: - adb->data_out[0] =3D data; - adb->data_out_index =3D 1; + adb->data_out_index =3D 0; break; case STATE_EVEN: if ((adb->data_out_index & 1) =3D=3D 0) { return 0; } - adb->data_out[adb->data_out_index++] =3D data; break; case STATE_ODD: if (adb->data_out_index & 1) { return 0; } - adb->data_out[adb->data_out_index++] =3D data; break; case STATE_IDLE: return 0; } + adb->data_out[adb->data_out_index++] =3D data; qemu_irq_raise(adb->data_ready); return 1; } @@ -138,7 +157,6 @@ int adb_receive(ADBBusState *adb, int state, uint8_t *d= ata) if ((adb->data_in_index & 1) =3D=3D 0) { return 0; } - *data =3D adb->data_in[adb->data_in_index++]; break; case STATE_ODD: if (adb->data_in_size <=3D 0) { @@ -153,7 +171,6 @@ int adb_receive(ADBBusState *adb, int state, uint8_t *d= ata) if (adb->data_in_index & 1) { return 0; } - *data =3D adb->data_in[adb->data_in_index++]; break; case STATE_IDLE: if (adb->data_out_index =3D=3D 0) { @@ -162,6 +179,7 @@ int adb_receive(ADBBusState *adb, int state, uint8_t *d= ata) adb->data_in_size =3D adb_request(adb, adb->data_in, adb->data_out, adb->data_out_index= ); adb->data_out_index =3D 0; + adb->data_in_index =3D 0; if (adb->data_in_size < 0) { *data =3D 0xff; qemu_irq_raise(adb->data_ready); @@ -170,10 +188,9 @@ int adb_receive(ADBBusState *adb, int state, uint8_t *= data) if (adb->data_in_size =3D=3D 0) { return 0; } - *data =3D adb->data_in[0]; - adb->data_in_index =3D 1; break; } + *data =3D adb->data_in[adb->data_in_index++]; qemu_irq_raise(adb->data_ready); if (*data =3D=3D 0xff || *data =3D=3D 0) { return 0; diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index a6a11c5b3d..055091535f 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -247,6 +247,8 @@ #define VIA1B_vADB_StateMask (VIA1B_vADBS1 | VIA1B_vADBS2) #define VIA1B_vADB_StateShift 4 =20 +#define VIA_ADB_POLL_FREQ 50 /* XXX: not real */ + typedef struct VIATimer { int index; uint16_t counter; /* Timer counter */ @@ -305,6 +307,7 @@ typedef struct MacVIAState { /* ADB */ =20 ADBBusState adb_bus; + QEMUTimer *adb_poll_timer; =20 /* external timers */ =20 @@ -596,7 +599,7 @@ static void via1_adb_update(MacVIAState *m) } else { /* input mode */ ret =3D adb_receive(&m->adb_bus, state, &s->sr); - if (ret > 0) { + if (ret > 0 && s->sr !=3D 0xff) { s->b &=3D ~VIA1B_vADBInt; } else { s->b |=3D VIA1B_vADBInt; @@ -604,6 +607,23 @@ static void via1_adb_update(MacVIAState *m) } } =20 +static void via_adb_poll(void *opaque) +{ + MacVIAState *m =3D opaque; + VIAState *s =3D &m->via[0]; + int state; + + if (s->b & VIA1B_vADBInt) { + state =3D (s->b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; + if (adb_via_poll(&m->adb_bus, state, &s->sr)) { + s->b &=3D ~VIA1B_vADBInt; + } + } + timer_mod(m->adb_poll_timer, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + (NANOSECONDS_PER_SECOND / VIA_ADB_POLL_FREQ)); +} + static void via_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size) { @@ -858,6 +878,10 @@ static void mac_via_reset(DeviceState *dev) m->cmd =3D 0; m->wprotect =3D 0; m->alt =3D 0; + + timer_mod(m->adb_poll_timer, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + (NANOSECONDS_PER_SECOND / VIA_ADB_POLL_FREQ)); } =20 static void mac_via_realizefn(DeviceState *dev, Error **errp) @@ -872,6 +896,7 @@ static void mac_via_realizefn(DeviceState *dev, Error *= *errp) =20 qemu_get_timedate(&tm, 0); m->tick_offset =3D (uint32_t)mktimegm(&tm) + RTC_OFFSET; + m->adb_poll_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, via_adb_poll, m= ); =20 /* ouput IRQs */ =20 diff --git a/include/hw/input/adb.h b/include/hw/input/adb.h index ce393004eb..9ef7fa2f0e 100644 --- a/include/hw/input/adb.h +++ b/include/hw/input/adb.h @@ -90,6 +90,7 @@ int adb_poll(ADBBusState *s, uint8_t *buf_out, uint16_t p= oll_mask); #define TYPE_ADB_KEYBOARD "adb-keyboard" #define TYPE_ADB_MOUSE "adb-mouse" =20 +int adb_via_poll(ADBBusState *s, int state, uint8_t *data); int adb_send(ADBBusState *adb, int state, uint8_t data); int adb_receive(ADBBusState *adb, int state, uint8_t *data); #endif /* ADB_H */ --=20 2.14.4 From nobody Mon Apr 29 04:03:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528488538230397.7035349405256; Fri, 8 Jun 2018 13:08:58 -0700 (PDT) Received: from localhost ([::1]:37971 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNgo-0000KU-Tr for importer@patchew.org; Fri, 08 Jun 2018 16:08:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47724) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNel-0007Uf-BK for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:06:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fRNei-0006fD-4z for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:06:43 -0400 Received: from mout.kundenserver.de ([212.227.126.134]:48911) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fRNeh-0006et-RN; Fri, 08 Jun 2018 16:06:40 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue002 [212.227.15.167]) with ESMTPSA (Nemesis) id 0M007w-1gGsq90xWW-00uEw6; Fri, 08 Jun 2018 22:06:13 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 8 Jun 2018 22:05:48 +0200 Message-Id: <20180608200558.386-4-laurent@vivier.eu> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180608200558.386-1-laurent@vivier.eu> References: <20180608200558.386-1-laurent@vivier.eu> X-Provags-ID: V03:K1:SybWzqYDg6CGKxpBK4XldUT/BNmIKqH3jmOCIT5sSu+It/a3+qY XwHfQAbMt8vbZjjBrhP2Fd0Geqc3Rb0m/79AEoB7/icuKGr8u3YlzhCJ6VFdEGH1UVoVUIT A+BNdpX4EcL+kS8uBOExUAOyz1X+/2XyYlDNFYjEZjWpkItiKSq7+cBeKBuQhe5h0TDUFGH X5OudsF2E+1yGrX77zKsw== X-UI-Out-Filterresults: notjunk:1;V01:K0:OpOfwnymJMA=:nxIbKTKH49plORJp6mFJpO cN1PdNBOLYkQCLyw/RH4MWl2LzfJGcnrF2lrJ9gPWFfbK2EHRY99rozKhVUZXFv2Lxv9kF18r iG+rP/cJhEsJ7a812AZp4leGFvf//5hA2KfUHSBJo9ZzQwu6ww4CreefbSQW3bEnFu2MxXyt8 HmvwV3/qSL4LigCFispas5w45ZYCdvxhN8ciAQswiVaR5JYPqwxtbsok0PtfEBC7vym6CA4ho UL1/sY4PK4iAcfNJw+EXhjp+YslGZagKc/Thze1dhQ79WooeQsbxG7XXSORtH8CmHhkrQ3X/c p5YyZAeU6iVa7hz3Z3mrk4ohT0hAFZLoxctK9NtsUazdZkLtzYt0MTOnT3/luhx+vCmNQl4TK +hDqy4fZSYeYvLTjLN23ojQ67OSQ7mOkhueFq5yVDEVSFSaD3rV7yI0TSgttZ4Wo38LrBGuCi 73dsDlVKMEpZU/H82JXeUUDVtfuAYe2a0MLPzEje4LHjNO6uQEt3Pk8/iw96T3lArsTmtcvwl xxMnOFUwjtDkof5cWNEaGUns9TQ6cFvVp8/55k/su68VKp63UrGmwxvIGQZmhHYnMmUcXXvEr DEcINxGlUnYuemWAnNrJX0a10lNIOkJBE0U6Vr4Ece9Dymd3zIP2Qhkwp7zpwuzRDvF3mlG8e BveQFTQ2XvSygL60o0r/r573WINN8/4oQ65gKIDKyQzKEUqT4vG9k/PtHvSe4ACDK5Kw= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.134 Subject: [Qemu-devel] [RFC 03/13] escc: introduce a selector for the register bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Jason Wang , "Dr. David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , Yongbok Kim , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Laurent Vivier On Sparc and PowerMac, the bit 0 of the address selects the register type (control or data) and bit 1 selects the channel (B or A). On m68k Macintosh, the bit 0 selects the channel and bit 1 the register type. This patch introduces a new parameter (bit_swap) to the device interface to indicate bits usage must be swapped between registers and channels. For the moment all the machines use the bit 0, but this change will be needed to emulate Quadra 800. Signed-off-by: Laurent Vivier --- hw/char/escc.c | 30 ++++++++++++++++++++++++------ include/hw/char/escc.h | 1 + 2 files changed, 25 insertions(+), 6 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 628f5f81f7..cec75b06f9 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -42,14 +42,21 @@ * mouse and keyboard ports don't implement all functions and they are * only asynchronous. There is no DMA. * - * Z85C30 is also used on PowerMacs. There are some small differences - * between Sparc version (sunzilog) and PowerMac (pmac): + * Z85C30 is also used on PowerMacs and m68k Macs. + * + * There are some small differences between Sparc version (sunzilog) + * and PowerMac (pmac): * Offset between control and data registers * There is some kind of lockup bug, but we can ignore it * CTS is inverted * DMA on pmac using DBDMA chip * pmac can do IRDA and faster rates, sunzilog can only do 38400 * pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz + * + * Linux driver for m68k Macs is the same as for PowerMac (pmac_zilog), + * but registers are grouped by type and not by channel: + * channel is selected by bit 0 of the address (instead of bit 1) + * and register is selected by bit 1 of the address (instead of bit 0). */ =20 /* @@ -169,6 +176,16 @@ static void handle_kbd_command(ESCCChannelState *s, in= t val); static int serial_can_receive(void *opaque); static void serial_receive_byte(ESCCChannelState *s, int ch); =20 +static int reg_shift(ESCCState *s) +{ + return s->bit_swap ? s->it_shift + 1 : s->it_shift; +} + +static int chn_shift(ESCCState *s) +{ + return s->bit_swap ? s->it_shift : s->it_shift + 1; +} + static void clear_queue(void *opaque) { ESCCChannelState *s =3D opaque; @@ -433,8 +450,8 @@ static void escc_mem_write(void *opaque, hwaddr addr, int newreg, channel; =20 val &=3D 0xff; - saddr =3D (addr >> serial->it_shift) & 1; - channel =3D (addr >> (serial->it_shift + 1)) & 1; + saddr =3D (addr >> reg_shift(serial)) & 1; + channel =3D (addr >> chn_shift(serial)) & 1; s =3D &serial->chn[channel]; switch (saddr) { case SERIAL_CTRL: @@ -537,8 +554,8 @@ static uint64_t escc_mem_read(void *opaque, hwaddr addr, uint32_t ret; int channel; =20 - saddr =3D (addr >> serial->it_shift) & 1; - channel =3D (addr >> (serial->it_shift + 1)) & 1; + saddr =3D (addr >> reg_shift(serial)) & 1; + channel =3D (addr >> chn_shift(serial)) & 1; s =3D &serial->chn[channel]; switch (saddr) { case SERIAL_CTRL: @@ -822,6 +839,7 @@ static void escc_realize(DeviceState *dev, Error **errp) static Property escc_properties[] =3D { DEFINE_PROP_UINT32("frequency", ESCCState, frequency, 0), DEFINE_PROP_UINT32("it_shift", ESCCState, it_shift, 0), + DEFINE_PROP_BOOL("bit_swap", ESCCState, bit_swap, false), DEFINE_PROP_UINT32("disabled", ESCCState, disabled, 0), DEFINE_PROP_UINT32("chnBtype", ESCCState, chn[0].type, 0), DEFINE_PROP_UINT32("chnAtype", ESCCState, chn[1].type, 0), diff --git a/include/hw/char/escc.h b/include/hw/char/escc.h index 42aca83611..8762f61c14 100644 --- a/include/hw/char/escc.h +++ b/include/hw/char/escc.h @@ -50,6 +50,7 @@ typedef struct ESCCState { =20 struct ESCCChannelState chn[2]; uint32_t it_shift; + bool bit_swap; MemoryRegion mmio; uint32_t disabled; uint32_t frequency; --=20 2.14.4 From nobody Mon Apr 29 04:03:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528489025411621.5693274941134; Fri, 8 Jun 2018 13:17:05 -0700 (PDT) Received: from localhost ([::1]:38036 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNom-0007g0-GC for importer@patchew.org; Fri, 08 Jun 2018 16:17:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47872) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNew-0007dM-NT for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:06:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fRNeu-0006mK-Bv for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:06:54 -0400 Received: from mout.kundenserver.de ([212.227.126.134]:50651) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fRNen-0006hC-Av; Fri, 08 Jun 2018 16:06:45 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue002 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MgTYM-1ff5JB2oly-00Ng4e; Fri, 08 Jun 2018 22:06:16 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 8 Jun 2018 22:05:49 +0200 Message-Id: <20180608200558.386-5-laurent@vivier.eu> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180608200558.386-1-laurent@vivier.eu> References: <20180608200558.386-1-laurent@vivier.eu> X-Provags-ID: V03:K1:Q9OjtTAyWfr7sUFPJeOwWaEkEvTgd3oJeVMu6KngUnxQVnek088 vmbK8oi4dCaUCsoOg5yQGYoEFXjREe6lCLVGUy+crgZuSCo6JAwwagrujRZK0UztjYyrSue 81YkinOMVU52DBYDrnswQ95oZBOkirZiw/DOaZi3c2wOQSnmdt9l2OMd5/QAIGfKNjKPo9c vJOmxZ6sqZ4Q8Chv9Vq8g== X-UI-Out-Filterresults: notjunk:1;V01:K0:H+CCkaOh/9Q=:i0e49VShjM/5EX4uDriTzD 6zNx7JNqKnbnQV3zbLXObiSjfXX4F1mpMq9YEWsSpxGbrg1qP3HPCfV3DcHyymeqoC1vBp76I iY8YKlZU5tfjAZthHuzjv0BzoMOscc8whkJRCyPwTMVCVVCkw6iXlUzT5ou/k+WW2oeU5LF6F DONxdCw4qsK9MtbTvpEY7NkPdU2Omi2LoL83eLLIN+NfCv08mRKbrUfgpMCr0b2wET+/g70Mr d1lJur5HOYGP6oCj4BUsScFqRXCFdkiKWzy7rfQFlLYkoaOs1FezG6U+kJhkBc+ejqxEwWMRj kUz93b3MjN7WSG6gatvzRQmDbUmoZK5x6HqVOJGJ9BAUkKP4IEmAPd1eXKNBiqrdQBsgJ6gwZ rlfL6szmmvuT+N/twCKsOF59cbiDIibugIuisKQ1yCUkZX6LDndG27dogW+TkDhpli3BzadU+ l9f0Gfb+sHUTJreljTX+GaNZ7mALWG+ZtC3U6Bv8lHksxgUe7athaxT7MVpx5l4GjoBYxzjRh /wMytEQGQ4vn/KBT6983+WZcWj8thkc4fYpgyroDsQVf3NzbHSgN7a/MXrBH/fCqbEFFEOdi8 o8qXAMEmiCtDIyLv0E3SRMD/t2TrHBsv2iCNg3PzJXe/c3wdhO+x2nxnSavr2TQkp6bW7bpcK JNuiSF5xleDsMyt/bm1Ghh98Vp8LAEq3lp9qDYdq3uD3ToTMWwik77Q2XGe1lC8WBvIg= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.134 Subject: [Qemu-devel] [RFC 04/13] hw/m68k: add video card X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Jason Wang , "Dr. David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , Yongbok Kim , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Laurent Vivier Signed-off-by: Laurent Vivier --- arch_init.c | 4 + hw/display/Makefile.objs | 1 + hw/display/macfb-template.h | 158 +++++++++++++++++++++++++ hw/display/macfb.c | 283 ++++++++++++++++++++++++++++++++++++++++= ++++ qemu-options.hx | 2 +- vl.c | 3 +- 6 files changed, 449 insertions(+), 2 deletions(-) create mode 100644 hw/display/macfb-template.h create mode 100644 hw/display/macfb.c diff --git a/arch_init.c b/arch_init.c index f4f3f610c8..5a71b48dc5 100644 --- a/arch_init.c +++ b/arch_init.c @@ -39,6 +39,10 @@ int graphic_width =3D 1024; int graphic_height =3D 768; int graphic_depth =3D 8; +#elif defined(TARGET_M68K) +int graphic_width =3D 800; +int graphic_height =3D 600; +int graphic_depth =3D 8; #else int graphic_width =3D 800; int graphic_height =3D 600; diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs index b5d97ab26d..925d5b848f 100644 --- a/hw/display/Makefile.objs +++ b/hw/display/Makefile.objs @@ -19,6 +19,7 @@ common-obj-$(CONFIG_EXYNOS4) +=3D exynos4210_fimd.o common-obj-$(CONFIG_FRAMEBUFFER) +=3D framebuffer.o common-obj-$(CONFIG_MILKYMIST) +=3D milkymist-vgafb.o common-obj-$(CONFIG_ZAURUS) +=3D tc6393xb.o +common-obj-$(CONFIG_MACFB) +=3D macfb.o =20 common-obj-$(CONFIG_MILKYMIST_TMU2) +=3D milkymist-tmu2.o milkymist-tmu2.o-cflags :=3D $(X11_CFLAGS) diff --git a/hw/display/macfb-template.h b/hw/display/macfb-template.h new file mode 100644 index 0000000000..b6ae5d728f --- /dev/null +++ b/hw/display/macfb-template.h @@ -0,0 +1,158 @@ +#if defined(READ_BITS) +#define PALETTE(i, r, g, b) \ + do { \ + r =3D s->color_palette[i * 3]; \ + g =3D s->color_palette[i * 3 + 1]; \ + b =3D s->color_palette[i * 3 + 2]; \ + } while (0) + +#if READ_BITS =3D=3D 1 +#define READ_PIXEL(from, x, r, g, b) \ + do { \ + int bit =3D x & 7; \ + int idx =3D (*from >> (7 - bit)) & 1; \ + r =3D g =3D b =3D ((1 - idx) << 7); \ + from +=3D (bit =3D=3D 7); \ + } while (0) +#elif READ_BITS =3D=3D 2 +#define READ_PIXEL(from, x, r, g, b) \ + do { \ + int bit =3D (x & 3); \ + int idx =3D (*from >> ((3 - bit) << 1)) & 3; \ + PALETTE(idx, r, g, b); \ + from +=3D (bit =3D=3D 3); \ + } while (0) +#elif READ_BITS =3D=3D 4 +#define READ_PIXEL(from, x, r, g, b) \ + do { \ + int bit =3D x & 1; \ + int idx =3D (*from >> ((1 - bit) << 2)) & 15; \ + PALETTE(idx, r, g, b); \ + from +=3D (bit =3D=3D 1); \ + } while (0) +#elif READ_BITS =3D=3D 8 +#define READ_PIXEL(from, x, r, g, b) \ + do { \ + PALETTE(*from, r, g, b); \ + from++; \ + } while (0) +#elif READ_BITS =3D=3D 16 +#define READ_PIXEL(from, x, r, g, b) \ + do { \ + uint16_t pixel; \ + pixel =3D (from[0] << 8) | from[1]; \ + r =3D ((pixel >> 10) & 0x1f) << 3; \ + g =3D ((pixel >> 5) & 0x1f) << 3; \ + b =3D (pixel & 0x1f) << 3; \ + from +=3D 2; \ + } while (0) +#elif READ_BITS =3D=3D 24 +#define READ_PIXEL(from, x, r, g, b) \ + do { \ + r =3D *from++; \ + g =3D *from++; \ + b =3D *from++; \ + } while (0) +#else +#error unknown bit depth +#endif + +#if WRITE_BITS =3D=3D 8 +#define WRITE_PIXEL(to, r, g, b) \ + do { \ + *to =3D rgb_to_pixel8(r, g, b); \ + to +=3D 1; \ + } while (0) +#elif WRITE_BITS =3D=3D 15 +#define WRITE_PIXEL(to, r, g, b) \ + do { \ + *(uint16_t *)to =3D rgb_to_pixel15(r, g, b); \ + to +=3D 2; \ + } while (0) +#elif WRITE_BITS =3D=3D 16 +#define WRITE_PIXEL(to, r, g, b) \ + do { \ + *(uint16_t *)to =3D rgb_to_pixel16(r, g, b); \ + to +=3D 2; \ + } while (0) +#elif WRITE_BITS =3D=3D 24 +#define WRITE_PIXEL(to, r, g, b) \ + do { \ + uint32_t tmp =3D rgb_to_pixel24(r, g, b); \ + *(to++) =3D tmp & 0xff; \ + *(to++) =3D (tmp >> 8) & 0xff; \ + *(to++) =3D (tmp >> 16) & 0xff; \ + } while (0) +#elif WRITE_BITS =3D=3D 32 +#define WRITE_PIXEL(to, r, g, b) \ + do { \ + *(uint32_t *)to =3D rgb_to_pixel32(r, g, b); \ + to +=3D 4; \ + } while (0) +#else +#error unknown bit depth +#endif + +static void glue(glue(glue(draw_line, READ_BITS), _), WRITE_BITS) + (MacfbState *s, uint8_t *to, uint8_t *from, int = width) +{ + uint8_t r, g, b; + int x; + for (x =3D 0; x < width; x++) { + READ_PIXEL(from, x, r, g, b); + WRITE_PIXEL(to, r, g, b); + } +} +#undef READ_BITS +#undef READ_PIXEL +#undef WRITE_PIXEL + +#elif defined(WRITE_BITS) + +#undef MACFB_RECLEVEL +#define MACFB_RECLEVEL 2 +#define READ_BITS 1 +#include "macfb-template.h" +#define READ_BITS 2 +#include "macfb-template.h" +#define READ_BITS 4 +#include "macfb-template.h" +#define READ_BITS 8 +#include "macfb-template.h" +#define READ_BITS 16 +#include "macfb-template.h" +#define READ_BITS 24 +#include "macfb-template.h" +#undef WRITE_BITS + +#else + +#define WRITE_BITS 8 +#include "macfb-template.h" + +#define WRITE_BITS 16 +#include "macfb-template.h" + +#define WRITE_BITS 24 +#include "macfb-template.h" + +#define WRITE_BITS 32 +#include "macfb-template.h" + +typedef void (*macfb_draw_line_func_t)(MacfbState *, uint8_t *, uint8_t *,= int); + +static macfb_draw_line_func_t macfb_draw_line[24][32] =3D { + [0] =3D { [7] =3D draw_line1_8, [15] =3D draw_line1_16, + [23] =3D draw_line1_24, [31] =3D draw_line1_32 }, + [1] =3D { [7] =3D draw_line2_8, [15] =3D draw_line2_16, + [23] =3D draw_line2_24, [31] =3D draw_line2_32 }, + [3] =3D { [7] =3D draw_line4_8, [15] =3D draw_line4_16, + [23] =3D draw_line4_24, [31] =3D draw_line4_32 }, + [7] =3D { [7] =3D draw_line8_8, [15] =3D draw_line8_16, + [23] =3D draw_line8_24, [31] =3D draw_line8_32 }, + [15] =3D { [7] =3D draw_line16_8, [15] =3D draw_line16_16, + [23] =3D draw_line16_24, [31] =3D draw_line16_32 }, + [23] =3D { [7] =3D draw_line24_8, [15] =3D draw_line24_16, + [23] =3D draw_line24_24, [31] =3D draw_line24_32 }, +}; +#endif diff --git a/hw/display/macfb.c b/hw/display/macfb.c new file mode 100644 index 0000000000..b2dd300a80 --- /dev/null +++ b/hw/display/macfb.c @@ -0,0 +1,283 @@ +/* + * QEMU Motorola 680x0 Macintosh Video Card Emulation + * Copyright (c) 2012-2018 Laurent Vivier + * + * some parts from QEMU G364 framebuffer Emulator. + * Copyright (c) 2007-2011 Herve Poussineau + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "ui/console.h" +#include "ui/pixel_ops.h" + +struct MacfbState { + SysBusDevice busdev; + MemoryRegion mem_vram; + MemoryRegion mem_ctrl; + QemuConsole *con; + + uint8_t *vram; + uint32_t palette_current; + uint8_t color_palette[256 * 3]; + uint32_t width, height; /* in pixels */ + uint8_t depth; +}; +typedef struct MacfbState MacfbState; + +#define TYPE_MACFB "sysbus-macfb" +#define MACFB(obj) \ + OBJECT_CHECK(MacfbSysBusState, (obj), TYPE_MACFB) + +#define MACFB_PAGE_SIZE 4096 +#define MACFB_VRAM_SIZE (4 * 1024 * 1024) + +#define DAFB_RESET 0x200 +#define DAFB_LUT 0x213 + +#include "macfb-template.h" + +static inline void reset_dirty(MacfbState *s, + ram_addr_t page_min, ram_addr_t page_max) +{ + memory_region_reset_dirty(&s->mem_vram, + page_min, + page_max + MACFB_PAGE_SIZE - page_min - 1, + DIRTY_MEMORY_VGA); +} + +static void macfb_draw_graphic(MacfbState *s) +{ + DisplaySurface *surface =3D qemu_console_surface(s->con); + ram_addr_t page, page_min, page_max; + int y, ymin; + int macfb_stride =3D (s->depth * s->width + 7) / 8; + macfb_draw_line_func_t draw_line; + + if (s->depth > 24) { + hw_error("macfb: unknown guest depth %d", s->depth); + return; + } + if (surface_bits_per_pixel(surface) > 32) { + hw_error("macfb: unknown host depth %d", + surface_bits_per_pixel(surface)); + return; + } + draw_line =3D macfb_draw_line[s->depth - 1][surface_bits_per_pixel(sur= face) + - 1]; + + if (draw_line =3D=3D NULL) { + hw_error("macfb: unknown guest/host depth combination %d/%d", s->d= epth, + surface_bits_per_pixel(surface)); + return; + } + + page_min =3D (ram_addr_t)-1; + page_max =3D 0; + ymin =3D -1; + page =3D 0; + for (y =3D 0; y < s->height; y++) { + int update; + + update =3D memory_region_get_dirty(&s->mem_vram, page, macfb_strid= e, + DIRTY_MEMORY_VGA); + + if (update) { + uint8_t *data_display; + + data_display =3D surface_data(surface) + y * surface_stride(su= rface); + draw_line(s, data_display, s->vram + page, s->width); + + if (ymin < 0) { + ymin =3D y; + } + if (page_min =3D=3D (ram_addr_t)-1) { + page_min =3D page; + } + page_max =3D page + macfb_stride - 1; + } else { + if (ymin >=3D 0) { + dpy_gfx_update(s->con, 0, ymin, s->width, y - ymin); + ymin =3D -1; + } + } + page +=3D macfb_stride; + } + if (ymin >=3D 0) { + dpy_gfx_update(s->con, 0, ymin, s->width, y - ymin); + } + if (page_min !=3D (ram_addr_t)-1) { + reset_dirty(s, page_min, page_max); + } +} + +static void macfb_invalidate_display(void *opaque) +{ + MacfbState *s =3D opaque; + + memory_region_set_dirty(&s->mem_vram, 0, MACFB_VRAM_SIZE); +} + +static void macfb_update_display(void *opaque) +{ + MacfbState *s =3D opaque; + DisplaySurface *surface =3D qemu_console_surface(s->con); + + qemu_flush_coalesced_mmio_buffer(); + + if (s->width =3D=3D 0 || s->height =3D=3D 0) { + return; + } + + if (s->width !=3D surface_width(surface) || + s->height !=3D surface_height(surface)) { + qemu_console_resize(s->con, s->width, s->height); + } + + macfb_draw_graphic(s); +} + +static void macfb_reset(MacfbState *s) +{ + int i; + + s->palette_current =3D 0; + for (i =3D 0; i < 256; i++) { + s->color_palette[i * 3] =3D 255 - i; + s->color_palette[i * 3 + 1] =3D 255 - i; + s->color_palette[i * 3 + 2] =3D 255 - i; + } + memset(s->vram, 0, MACFB_VRAM_SIZE); + macfb_invalidate_display(s); +} + +static uint64_t macfb_ctrl_read(void *opaque, + hwaddr addr, + unsigned int size) +{ + return 0; +} + +static void macfb_ctrl_write(void *opaque, + hwaddr addr, + uint64_t val, + unsigned int size) +{ + MacfbState *s =3D opaque; + switch (addr) { + case DAFB_RESET: + s->palette_current =3D 0; + break; + case DAFB_LUT: + s->color_palette[s->palette_current++] =3D val; + if (s->palette_current % 3) { + macfb_invalidate_display(s); + } + break; + } +} + +static const MemoryRegionOps macfb_ctrl_ops =3D { + .read =3D macfb_ctrl_read, + .write =3D macfb_ctrl_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .impl.min_access_size =3D 1, + .impl.max_access_size =3D 4, +}; + +static int macfb_post_load(void *opaque, int version_id) +{ + macfb_invalidate_display(opaque); + return 0; +} + +static const VMStateDescription vmstate_macfb =3D { + .name =3D "macfb", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .post_load =3D macfb_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_BUFFER_UNSAFE(color_palette, MacfbState, 0, 256 * 3), + VMSTATE_UINT32(palette_current, MacfbState), + VMSTATE_END_OF_LIST() + } +}; + +static const GraphicHwOps macfb_ops =3D { + .invalidate =3D macfb_invalidate_display, + .gfx_update =3D macfb_update_display, +}; + +static void macfb_init(DeviceState *dev, MacfbState *s) +{ + s->vram =3D g_malloc0(MACFB_VRAM_SIZE); + + s->con =3D graphic_console_init(dev, 0, &macfb_ops, s); + + memory_region_init_io(&s->mem_ctrl, NULL, &macfb_ctrl_ops, s, "ctrl", + 0x1000); + memory_region_init_ram_ptr(&s->mem_vram, NULL, "vram", MACFB_VRAM_SIZE, + s->vram); + vmstate_register_ram(&s->mem_vram, dev); + memory_region_set_coalescing(&s->mem_vram); +} + +typedef struct { + SysBusDevice busdev; + MacfbState macfb; +} MacfbSysBusState; + +static int macfb_sysbus_init(SysBusDevice *dev) +{ + MacfbState *s =3D &MACFB(dev)->macfb; + + macfb_init(DEVICE(dev), s); + sysbus_init_mmio(dev, &s->mem_ctrl); + sysbus_init_mmio(dev, &s->mem_vram); + + return 0; +} + +static void macfb_sysbus_reset(DeviceState *d) +{ + MacfbSysBusState *s =3D MACFB(d); + macfb_reset(&s->macfb); +} + +static Property macfb_sysbus_properties[] =3D { + DEFINE_PROP_UINT32("width", MacfbSysBusState, macfb.width, 640), + DEFINE_PROP_UINT32("height", MacfbSysBusState, macfb.height, 480), + DEFINE_PROP_UINT8("depth", MacfbSysBusState, macfb.depth, 8), + DEFINE_PROP_END_OF_LIST(), +}; + +static void macfb_sysbus_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); + + k->init =3D macfb_sysbus_init; + dc->desc =3D "Macintosh framebuffer"; + dc->reset =3D macfb_sysbus_reset; + dc->vmsd =3D &vmstate_macfb; + dc->props =3D macfb_sysbus_properties; +} + +static TypeInfo macfb_sysbus_info =3D { + .name =3D TYPE_MACFB, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MacfbSysBusState), + .class_init =3D macfb_sysbus_class_init, +}; + +static void macfb_register_types(void) +{ + type_register_static(&macfb_sysbus_info); +} + +type_init(macfb_register_types) diff --git a/qemu-options.hx b/qemu-options.hx index c0d3951e9f..c1181561e1 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -1551,7 +1551,7 @@ ETEXI =20 DEF("g", 1, QEMU_OPTION_g , "-g WxH[xDEPTH] Set the initial graphical resolution and depth\n", - QEMU_ARCH_PPC | QEMU_ARCH_SPARC) + QEMU_ARCH_PPC | QEMU_ARCH_SPARC | QEMU_ARCH_M68K) STEXI @item -g @var{width}x@var{height}[x@var{depth}] @findex -g diff --git a/vl.c b/vl.c index 06031715ac..ac8e50ee92 100644 --- a/vl.c +++ b/vl.c @@ -3308,7 +3308,8 @@ int main(int argc, char **argv, char **envp) if (*p =3D=3D 'x') { p++; depth =3D strtol(p, (char **)&p, 10); - if (depth !=3D 8 && depth !=3D 15 && depth !=3D 16= && + if (depth !=3D 1 && depth !=3D 2 && depth !=3D 4 && + depth !=3D 8 && depth !=3D 15 && depth !=3D 16= && depth !=3D 24 && depth !=3D 32) goto graphic_error; } else if (*p =3D=3D '\0') { --=20 2.14.4 From nobody Mon Apr 29 04:03:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528488695366741.7328308172476; Fri, 8 Jun 2018 13:11:35 -0700 (PDT) Received: from localhost ([::1]:37989 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNjQ-0002px-Hq for importer@patchew.org; Fri, 08 Jun 2018 16:11:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47771) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNen-0007Wm-Qb for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:06:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fRNel-0006gf-J7 for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:06:45 -0400 Received: from mout.kundenserver.de ([212.227.126.134]:55083) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fRNel-0006g0-5S; Fri, 08 Jun 2018 16:06:43 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue002 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MVEDt-1fmTp616tR-00YQn5; Fri, 08 Jun 2018 22:06:17 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 8 Jun 2018 22:05:50 +0200 Message-Id: <20180608200558.386-6-laurent@vivier.eu> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180608200558.386-1-laurent@vivier.eu> References: <20180608200558.386-1-laurent@vivier.eu> X-Provags-ID: V03:K1:297Gry1o3/AJvqCI90hpmEZMra2hr6hgUqRNagikeAEJJwCOPQk WaXBdFC3izidEDQteUxGDQ77tOHyQBXsNunT71E7ZnpOKBQofUkM1u7BXcsKbH+XDcgywOV 0+QIPi/UB8XJLxD6fVbOh6l6RUU9vNa9cG1qAqbipfw7obQ5AJiecFcgyUExGmbWMvOAc9J 97Jv+RWeai6ViNv38UeYw== X-UI-Out-Filterresults: notjunk:1;V01:K0:Jl1EZa530fM=:RGYz1Rg3ZsMLJpSfSwv6vL QE8pdwOu2WqNw2sSNagsORRHeoGyqGLOUyINkqiBJh1sZwHBTgWdgwLlNv/6HYBIt4zzET5IL 1YVmx0fVl10IUZ9bFUcwViZ1qQ54FXnSh/CZaCxM/mg/JpeBGtZysZ8zSHl55k/F6pQjjsqtk q14QOqrarNDENwL6xG/U1V4YN1vDmnuHhQO5Nl5JqDlmIwWgL681g5370eCaTHNzUglCpET+5 rJlJhhkF6G1IkmTZCWSsmuHAEor06OtovosKoUtNU1sXnLr8O6M4nLiwRSkQs9ZMl4a2OMOoQ nlm15SipVFTZ3pxJ+pvK1m2OwPxzdqpkDY+SpOJUOH8zy+31AZJ1NYQT+BemKV9TOHEurtn2v jxUqC5DeWgYywHncA8su9bQv9rZNZiaguGgvvURCk+UaV5LMNRfwx1gFwM/s+I1SndcJaU5PC sGvxne2Y0T4PDbJjlsLyqrCI5qv8D9Tll/wuElceHwddMY3HHkdV9oTbtFkjmhG1n+jlFCGxr UJljgMTfvJ5WWgcOpO00EvdlGO3AmAbRkhUuOflBI8Iam1Uk366ngH6uCNF2syzta1vLVwOJd hTTEtDva0P8VIBJVeQkvNrHTW/CE++9XoEFYwdRu5sjnj/AcfziUXsM9W2PQPOKivr5883VGz /jcbkxvDi41I4GPqnqZz/SJIywi92/7GdaUSxe5uFVhmFXTffPgCxdJ++x1n7Qgehnr0= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.134 Subject: [Qemu-devel] [RFC 05/13] hw/m68k: Apple Sound Chip (ASC) emulation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Jason Wang , "Dr. David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , Yongbok Kim , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Laurent Vivier This is broken as the linux driver seems broken too... Signed-off-by: Laurent Vivier --- hw/audio/Makefile.objs | 1 + hw/audio/asc.c | 492 +++++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/audio/asc.h | 21 +++ 3 files changed, 514 insertions(+) create mode 100644 hw/audio/asc.c create mode 100644 include/hw/audio/asc.h diff --git a/hw/audio/Makefile.objs b/hw/audio/Makefile.objs index 63db383709..44d1ada7b0 100644 --- a/hw/audio/Makefile.objs +++ b/hw/audio/Makefile.objs @@ -16,3 +16,4 @@ common-obj-$(CONFIG_MARVELL_88W8618) +=3D marvell_88w8618= .o common-obj-$(CONFIG_MILKYMIST) +=3D milkymist-ac97.o =20 common-obj-y +=3D soundhw.o +common-obj-$(CONFIG_ASC) +=3D asc.o diff --git a/hw/audio/asc.c b/hw/audio/asc.c new file mode 100644 index 0000000000..3c07d4fa91 --- /dev/null +++ b/hw/audio/asc.c @@ -0,0 +1,492 @@ +/* + * QEMU Apple Sound Chip emulation + * + * Apple Sound Chip (ASC) 344S0063 + * Enhanced Apple Sound Chip (EASC) 343S1063 + * + * Copyright (c) 2012-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "audio/audio.h" +#include "hw/audio/asc.h" + +/* + * Linux doesn't provide information about ASC, see arch/m68k/mac/macboing= .c + * and arch/m68k/include/asm/mac_asc.h + * + * best information is coming from MAME: + * http://mamedev.org/source/src/emu/sound/asc.h.html + * http://mamedev.org/source/src/emu/sound/asc.c.html + * Emulation by R. Belmont + * + * 0x800: VERSION + * 0x801: MODE + * 1=3DFIFO mode, + * 2=3Dwavetable mode + * 0x802: CONTROL + * bit 0=3Danalog or PWM output, + * 1=3Dstereo/mono, + * 7=3Dprocessing time exceeded + * 0x803: FIFO MODE + * bit 7=3Dclear FIFO, + * bit 1=3D"non-ROM companding", + * bit 0=3D"ROM companding") + * 0x804: FIFO IRQ STATUS + * bit 0=3Dch A 1/2 full, + * 1=3Dch A full, + * 2=3Dch B 1/2 full, + * 3=3Dch B full) + * 0x805: WAVETABLE CONTROL + * bits 0-3 wavetables 0-3 start + * 0x806: VOLUME + * bits 2-4 =3D 3 bit internal ASC volume, + * bits 5-7 =3D volume control sent to Sony sound chip + * 0x807: CLOCK RATE + * 0 =3D Mac 22257 Hz, + * 1 =3D undefined, + * 2 =3D 22050 Hz, + * 3 =3D 44100 Hz + * 0x80a: PLAY REC A + * 0x80f: TEST + * bits 6-7 =3D digital test, + * bits 4-5 =3D analog test + * 0x810: WAVETABLE 0 PHASE + * big-endian 9.15 fixed-point, only 24 bits valid + * 0x814: WAVETABLE 0 INCREMENT + * big-endian 9.15 fixed-point, only 24 bits valid + * 0x818: WAVETABLE 1 PHASE + * 0x81C: WAVETABLE 1 INCREMENT + * 0x820: WAVETABLE 2 PHASE + * 0x824: WAVETABLE 2 INCREMENT + * 0x828: WAVETABLE 3 PHASE + * 0x82C: WAVETABLE 3 INCREMENT + */ + +#define ASC_LENGTH 0x2000 +#define ASC_BUF_SIZE 0x0800 + +#define ASC_REG_BASE 0x0800 +enum { + ASC_VERSION =3D 0x00, + ASC_MODE =3D 0x01, + ASC_CONTROL =3D 0x02, + ASC_FIFOMODE =3D 0x03, + ASC_FIFOIRQ =3D 0x04, + ASC_WAVECTRL =3D 0x05, + ASC_VOLUME =3D 0x06, + ASC_CLOCK =3D 0x07, + ASC_PLAYRECA =3D 0x0a, + ASC_TEST =3D 0x0f, + ASC_WAVETABLE =3D 0x10 +}; + +struct ASCState { + SysBusDevice busdev; + MemoryRegion mem_regs; + + QEMUSoundCard card; + SWVoiceOut *channel; + + qemu_irq irq; + + uint8_t type; + int a_wptr, a_rptr, a_cnt; + int b_wptr, b_rptr, b_cnt; + + uint8_t *fifo; + + uint8_t regs[48]; +}; +typedef struct ASCState ASCState; + +#define TYPE_ASC "apple-sound-chip" +#define ASC(obj) OBJECT_CHECK(ASCSysBusState, (obj), TYPE_ASC) + +static inline uint32_t get_phase(ASCState *s, int channel) +{ + return be32_to_cpu(*(uint32_t *)(s->regs + ASC_WAVETABLE + channel * 8= )); +} + +static inline void set_phase(ASCState *s, int channel, uint32_t phase) +{ + *(uint32_t *)(s->regs + ASC_WAVETABLE + channel * 8) =3D cpu_to_be32(p= hase); +} + +static inline uint32_t get_incr(ASCState *s, int channel) +{ + return be32_to_cpu(*(uint32_t *)(s->regs + ASC_WAVETABLE + 4 + + channel * 8)); +} + +static inline uint32_t incr_phase(ASCState *s, int channel) +{ + uint32_t incr =3D get_incr(s, channel); + uint32_t phase =3D get_phase(s, channel); + + set_phase(s, channel, phase + incr); + + return get_phase(s, channel); +} + +static void generate_fifo(ASCState *s, int free_b) +{ + int8_t buf[2048]; + int i; + int to_copy; + + do { + to_copy =3D audio_MIN(sizeof(buf), free_b); + for (i =3D 0; i < (to_copy >> 1); to_copy++) { + int8_t left, right; + + left =3D s->fifo[s->a_rptr] ^ 0x80; + right =3D s->fifo[s->b_rptr + 0x400] ^ 0x80; + + if (s->a_cnt) { + s->a_rptr++; + s->a_rptr &=3D 0x3ff; + s->a_cnt--; + } + + if (s->b_cnt) { + s->b_rptr++; + s->b_rptr &=3D 0x3ff; + s->b_cnt--; + } + + if (s->type =3D=3D ASC_TYPE_SONORA) { + if (s->a_cnt < 0x200) { + s->regs[ASC_FIFOIRQ] |=3D 4; /* FIFO A less than half = full */ + qemu_irq_raise(s->irq); + } + if (s->b_cnt < 0x200) { + s->regs[ASC_FIFOIRQ] |=3D 8; /* FIFO B less than half = full */ + qemu_irq_raise(s->irq); + } + } else { + if (s->a_cnt =3D=3D 0x1ff) { + s->regs[ASC_FIFOIRQ] |=3D 1; /* FIFO A half empty */ + qemu_irq_raise(s->irq); + } else if (s->a_cnt =3D=3D 0x001) { + s->regs[ASC_FIFOIRQ] |=3D 2; /* FIFO A half empty */ + qemu_irq_raise(s->irq); + } + if (s->b_cnt =3D=3D 0x1ff) { + s->regs[ASC_FIFOIRQ] |=3D 4; /* FIFO A half empty */ + qemu_irq_raise(s->irq); + } else if (s->b_cnt =3D=3D 0x001) { + s->regs[ASC_FIFOIRQ] |=3D 8; /* FIFO A half empty */ + qemu_irq_raise(s->irq); + } + } + buf[i * 2] =3D left; + buf[i * 2 + 1] =3D right; + } + AUD_write(s->channel, buf, to_copy); + free_b -=3D to_copy; + } while (free_b); +} + +static void generate_wavetable(ASCState *s, int free_b) +{ + int8_t buf[2048]; + int i; + int channel; + int to_copy; + int control =3D s->regs[ASC_WAVECTRL]; + + do { + to_copy =3D audio_MIN(sizeof(buf), free_b); + for (i =3D 0; i < (to_copy >> 1); i++) { + int32_t left, right; + int8_t sample; + + left =3D 0; + right =3D 0; + + if (control) { /* FIXME: how to use it ? */ + for (channel =3D 0; channel < 4; channel++) { + uint32_t phase =3D incr_phase(s, channel); + + phase =3D (phase >> 15) & 0x1ff; + sample =3D s->fifo[0x200 * channel + phase] ^ 0x80; + + left +=3D sample; + right +=3D sample; + } + buf[i * 2] =3D left >> 2; + buf[i * 2 + 1] =3D right >> 2; + } else { + /* FIXME: only works with linux macboing.c */ + uint32_t phase =3D incr_phase(s, 0); + phase =3D (phase >> 15) & 0x7ff; + sample =3D s->fifo[phase]; + buf[i * 2] =3D sample; + buf[i * 2 + 1] =3D sample; + } + } + AUD_write(s->channel, buf, to_copy); + free_b -=3D to_copy; + } while (free_b); +} + +static void asc_out_cb(void *opaque, int free_b) +{ + ASCState *s =3D opaque; + + switch (s->regs[ASC_MODE] & 3) { + case 0: /* Off */ + break; + case 1: /* FIFO mode */ + generate_fifo(s, free_b); + break; + case 2: /* Wave table mode */ + generate_wavetable(s, free_b); + break; + } +} + +static uint64_t asc_read(void *opaque, hwaddr addr, + unsigned size) +{ + ASCState *s =3D opaque; + uint64_t prev; + + if (addr < 0x800) { + return s->fifo[addr]; + } + + addr -=3D 0x800; + + if (addr >=3D 0x030) { + return 0; + } + + switch (addr) { + case ASC_VERSION: + switch (s->type) { + case ASC_TYPE_ASC: + return 0; + case ASC_TYPE_V8: + case ASC_TYPE_EAGLE: + case ASC_TYPE_SPICE: + case ASC_TYPE_VASP: + return 0xe8; + case ASC_TYPE_SONORA: + return 0xbc; + default: + break; + } + break; + case ASC_MODE: + switch (s->type) { + case ASC_TYPE_V8: + case ASC_TYPE_EAGLE: + case ASC_TYPE_SPICE: + case ASC_TYPE_VASP: + return 1; + default: + break; + } + break; + case ASC_CONTROL: + switch (s->type) { + case ASC_TYPE_V8: + case ASC_TYPE_EAGLE: + case ASC_TYPE_SPICE: + case ASC_TYPE_VASP: + return 1; + default: + break; + } + break; + case ASC_FIFOIRQ: + if (s->type =3D=3D ASC_TYPE_V8) { + prev =3D 3; + } else { + prev =3D s->regs[ASC_FIFOIRQ]; + } + s->regs[ASC_FIFOIRQ] =3D 0; + qemu_irq_lower(s->irq); + return prev; + default: + break; + } + + return s->regs[addr]; +} + +static void asc_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + ASCState *s =3D opaque; + + if (addr < 0x800) { + if (s->regs[ASC_MODE] =3D=3D 1) { + if (addr < 0x400) { + /* FIFO A */ + s->fifo[s->a_wptr++] =3D value; + s->a_cnt++; + if (s->a_cnt =3D=3D 0x3ff) { + s->regs[ASC_FIFOIRQ] |=3D 2; /* FIFO A Full */ + } + s->a_wptr &=3D 0x3ff; + } else { + /* FIFO B */ + s->fifo[s->b_wptr++ + 0x400] =3D value; + s->b_cnt++; + if (s->b_cnt =3D=3D 0x3ff) { + s->regs[ASC_FIFOIRQ] |=3D 8; /* FIFO B Full */ + } + s->b_wptr &=3D 0x3ff; + } + } else { + s->fifo[addr] =3D value; + } + return; + } + + addr -=3D 0x800; + if (addr >=3D 0x30) { + return; + } + switch (addr) { + case ASC_MODE: + value &=3D 3; + if (value !=3D s->regs[ASC_MODE]) { + s->a_rptr =3D 0; + s->a_wptr =3D 0; + s->a_cnt =3D 0; + s->b_rptr =3D 0; + s->b_wptr =3D 0; + s->b_cnt =3D 0; + if (value !=3D 0) { + AUD_set_active_out(s->channel, 1); + } else { + AUD_set_active_out(s->channel, 0); + } + } + break; + case ASC_FIFOMODE: + if (value & 0x80) { + s->a_rptr =3D 0; + s->a_wptr =3D 0; + s->a_cnt =3D 0; + s->b_rptr =3D 0; + s->b_wptr =3D 0; + s->b_cnt =3D 0; + } + break; + case ASC_WAVECTRL: + break; + } + s->regs[addr] =3D value; +} + +static const MemoryRegionOps asc_mmio_ops =3D { + .read =3D asc_read, + .write =3D asc_write, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + +static int asc_post_load(void *opaque, int version_id) +{ + return 0; +} + +static const VMStateDescription vmstate_asc =3D { + .name =3D "apple-sound-chip", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .post_load =3D asc_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_END_OF_LIST() + } +}; + +typedef struct { + SysBusDevice busdev; + ASCState asc; +} ASCSysBusState; + +static int asc_sysbus_init(SysBusDevice *dev) +{ + ASCState *s =3D &ASC(dev)->asc; + struct audsettings as; + + s->fifo =3D g_malloc0(ASC_BUF_SIZE); + + sysbus_init_irq(dev, &s->irq); + + AUD_register_card("Apple Sound Chip", &s->card); + + as.freq =3D 22257; + as.nchannels =3D 2; + as.fmt =3D AUD_FMT_S8; + as.endianness =3D 0; + + s->channel =3D AUD_open_out(&s->card, s->channel, "asc.out", + s, asc_out_cb, &as); + + memory_region_init_io(&s->mem_regs, NULL, &asc_mmio_ops, s, "asc", + ASC_LENGTH); + sysbus_init_mmio(dev, &s->mem_regs); + + return 0; +} + +static void asc_sysbus_reset(DeviceState *d) +{ + ASCSysBusState *s =3D ASC(d); + + AUD_set_active_out(s->asc.channel, 0); + + memset(s->asc.regs, 0, sizeof(s->asc.regs)); + s->asc.a_wptr =3D 0; + s->asc.a_rptr =3D 0; + s->asc.a_cnt =3D 0; + s->asc.b_wptr =3D 0; + s->asc.b_rptr =3D 0; + s->asc.b_cnt =3D 0; +} + +static Property asc_sysbus_properties[] =3D { + DEFINE_PROP_UINT8("asctype", ASCSysBusState, asc.type, ASC_TYPE_ASC), + DEFINE_PROP_END_OF_LIST(), +}; + +static void asc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); + + k->init =3D asc_sysbus_init; + dc->reset =3D asc_sysbus_reset; + dc->vmsd =3D &vmstate_asc; + dc->props =3D asc_sysbus_properties; +} + +static TypeInfo asc_sysbus_info =3D { + .name =3D TYPE_ASC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(ASCSysBusState), + .class_init =3D asc_class_init, +}; + +static void asc_register_types(void) +{ + type_register_static(&asc_sysbus_info); +} + +type_init(asc_register_types) diff --git a/include/hw/audio/asc.h b/include/hw/audio/asc.h new file mode 100644 index 0000000000..f2a292bbb0 --- /dev/null +++ b/include/hw/audio/asc.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2012-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef HW_AUDIO_ASC_H +#define HW_AUDIO_ASC_H +enum { + ASC_TYPE_ASC =3D 0, /* original discrete Apple Sound Chip */ + ASC_TYPE_EASC =3D 1, /* discrete Enhanced Apple Sound Chip */ + ASC_TYPE_V8 =3D 2, /* ASC included in the V8 ASIC (LC/LCII) */ + ASC_TYPE_EAGLE =3D 3, /* ASC included in the Eagle ASIC (Classic II)= */ + ASC_TYPE_SPICE =3D 4, /* ASC included in the Spice ASIC (Color Class= ic) */ + ASC_TYPE_SONORA =3D 5, /* ASC included in the Sonora ASIC (LCIII) */ + ASC_TYPE_VASP =3D 6, /* ASC included in the VASP ASIC (IIvx/IIvi) = */ + ASC_TYPE_ARDBEG =3D 7 /* ASC included in the Ardbeg ASIC (LC520) */ +}; +#endif --=20 2.14.4 From nobody Mon Apr 29 04:03:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528488638678125.76328007603558; Fri, 8 Jun 2018 13:10:38 -0700 (PDT) Received: from localhost ([::1]:37982 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNiX-00020J-RQ for importer@patchew.org; Fri, 08 Jun 2018 16:10:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47929) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNez-0007fv-Ad for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:07:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fRNew-0006oW-6U for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:06:57 -0400 Received: from mout.kundenserver.de ([212.227.126.130]:53281) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fRNeq-0006iV-5O; Fri, 08 Jun 2018 16:06:48 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue002 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MYXbd-1fnZDm0ZvN-00V8T9; Fri, 08 Jun 2018 22:06:19 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 8 Jun 2018 22:05:51 +0200 Message-Id: <20180608200558.386-7-laurent@vivier.eu> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180608200558.386-1-laurent@vivier.eu> References: <20180608200558.386-1-laurent@vivier.eu> X-Provags-ID: V03:K1:1jn5XJ/9ow/c2VVGe2GCKhSftjfYUYD8+iBHlM3kJVNWe+Np+6h sLUFJLAsdIK6u375oOBEHulDi4iYDgEh/PSaiQ51A2iBJjMNHf51xUoiM3VHm1+ke+1zfZN vkV0CsR0Kb0Hn8ss851bm24rTk9Ts5/fn6r0LQWaDgsiBn/WNN7lfnozaqMd5HTNxuf5qwE Yp72NZfxHaLyMvlR/MB4Q== X-UI-Out-Filterresults: notjunk:1;V01:K0:3jgxV0t/qNY=:kn6aS57YWixljW6I5VM3lV cQlUQhQgxecf7bB5/a0D1jqVcaJ6RxIRuPJaC4OrR2ecRvNIAKBnHcmsE1IfKsyCsI3xzgmzO mHgW45GPotpihCOw7DJgzVa/QR3QJQak0zJHJ+SQy7DHwx1AlbpsqtPDfEcMMVcZGXdle6WVU ebIB6swJNgp2aG2a56F9d6ojXOlmTwLS9dt7WOiahhfLwFEZjasp4GIJR6ZdfXKE80XoXrHPR u3/bYXBy0hJeBEmbMCrxq5tN20cgiTTfkfc4yCGZyYMfaf7nK6iX2O2nc7SiQOfKKqD1qjqmP HPDTCcaNy0NwKQM73f9zlQxKIZv3UpASUY3bQhojHAFa9AiYA/Xn02AewOoV9GO4K+kcktiHi okIN7wDFRB0VKXAI6WvFe/G/D7jU5PWQ+KHCLEJKghW81qicnU4q3c6DqUtvIZVL7hTl5KT4/ oGoXwk6ym5gyMQw41OXe9Tdf6JkBkiU6AqSRV7f5ikgIHQ/KKHRPuwFX/J2Fv7W1yV2DBgNNH 6x1X+6zd0fqfcfWYPX9UavwEF4wYImop+RlbBtlF7TGCoQc4jzbxzGF1CtQyT/nCxj4+I5SqC TiUGee1dbtx90AgE96mEH3vF70Qm+HfUr0D5WgS+EGM3JJofjgMMmPxu9XS0QoXqWMVsf82hP jLrOS7kduE7l7ro7AFU5l96JPTxgZ209I6Ciy+xHOhxgn9U3LPVHysye0EkXFr+Quulc= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.130 Subject: [Qemu-devel] [RFC 06/13] ESP: add pseudo-DMA as used by Macintosh X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Jason Wang , "Dr. David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , Yongbok Kim , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Laurent Vivier Signed-off-by: Laurent Vivier Tested-by: Herv=C3=A9 Poussineau --- hw/mips/mips_jazz.c | 2 +- hw/scsi/esp.c | 330 +++++++++++++++++++++++++++++++++++++++++++++-= ---- include/hw/scsi/esp.h | 15 ++- 3 files changed, 313 insertions(+), 34 deletions(-) diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index 90cb306f53..87118f2d03 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -282,7 +282,7 @@ static void mips_jazz_init(MachineState *machine, =20 /* SCSI adapter */ esp =3D esp_init(0x80002000, 0, rc4030_dma_read, rc4030_dma_write, dma= s[0], - qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable); + qdev_get_gpio_in(rc4030, 5), NULL, &esp_reset, &dma_ena= ble); scsi_bus_legacy_handle_cmdline(&esp->bus); =20 /* Floppy */ diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 9ed9727744..4d7fa71309 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -37,6 +37,8 @@ * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9= X.txt */ =20 +/* on Macintosh Quadra it is a NCR53C96 */ + static void esp_raise_irq(ESPState *s) { if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { @@ -55,6 +57,16 @@ static void esp_lower_irq(ESPState *s) } } =20 +static void esp_raise_drq(ESPState *s) +{ + qemu_irq_raise(s->irq_data); +} + +static void esp_lower_drq(ESPState *s) +{ + qemu_irq_lower(s->irq_data); +} + void esp_dma_enable(ESPState *s, int irq, int level) { if (level) { @@ -81,29 +93,11 @@ void esp_request_cancelled(SCSIRequest *req) } } =20 -static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen) +static int get_cmd_cb(ESPState *s) { - uint32_t dmalen; int target; =20 target =3D s->wregs[ESP_WBUSID] & BUSID_DID; - if (s->dma) { - dmalen =3D s->rregs[ESP_TCLO]; - dmalen |=3D s->rregs[ESP_TCMID] << 8; - dmalen |=3D s->rregs[ESP_TCHI] << 16; - if (dmalen > buflen) { - return 0; - } - s->dma_memory_read(s->dma_opaque, buf, dmalen); - } else { - dmalen =3D s->ti_size; - if (dmalen > TI_BUFSZ) { - return 0; - } - memcpy(buf, s->ti_buf, dmalen); - buf[0] =3D buf[2] >> 5; - } - trace_esp_get_cmd(dmalen, target); =20 s->ti_size =3D 0; s->ti_rptr =3D 0; @@ -122,8 +116,48 @@ static uint32_t get_cmd(ESPState *s, uint8_t *buf, uin= t8_t buflen) s->rregs[ESP_RINTR] =3D INTR_DC; s->rregs[ESP_RSEQ] =3D SEQ_0; esp_raise_irq(s); + return -1; + } + return 0; +} + +static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen) +{ + int target; + uint32_t dmalen; + + target =3D s->wregs[ESP_WBUSID] & BUSID_DID; + if (s->dma) { + dmalen =3D s->rregs[ESP_TCLO]; + dmalen |=3D s->rregs[ESP_TCMID] << 8; + dmalen |=3D s->rregs[ESP_TCHI] << 16; + if (dmalen > buflen) { + return 0; + } + if (s->dma_memory_read) { + s->dma_memory_read(s->dma_opaque, buf, dmalen); + } else { + memcpy(s->pdma_buf, buf, dmalen); + s->pdma_len =3D dmalen; + s->pdma_start =3D s->pdma_buf; + s->pdma_cur =3D s->pdma_buf; + esp_raise_drq(s); + return 0; + } + } else { + dmalen =3D s->ti_size; + if (dmalen > TI_BUFSZ) { + return 0; + } + memcpy(buf, s->ti_buf, dmalen); + buf[0] =3D buf[2] >> 5; + } + trace_esp_get_cmd(dmalen, target); + + if (get_cmd_cb(s) < 0) { return 0; } + return dmalen; } =20 @@ -162,6 +196,15 @@ static void do_cmd(ESPState *s, uint8_t *buf) do_busid_cmd(s, &buf[1], busid); } =20 +static void satn_pdma_cb(ESPState *s) +{ + if (get_cmd_cb(s) < 0) { + return; + } + if (s->pdma_cur !=3D s->pdma_start) + do_cmd(s, s->pdma_start); +} + static void handle_satn(ESPState *s) { uint8_t buf[32]; @@ -171,11 +214,21 @@ static void handle_satn(ESPState *s) s->dma_cb =3D handle_satn; return; } + s->pdma_cb =3D satn_pdma_cb; len =3D get_cmd(s, buf, sizeof(buf)); if (len) do_cmd(s, buf); } =20 +static void s_without_satn_pdma_cb(ESPState *s) +{ + if (get_cmd_cb(s) < 0) { + return; + } + if (s->pdma_cur !=3D s->pdma_start) + do_busid_cmd(s, s->pdma_start, 0); +} + static void handle_s_without_atn(ESPState *s) { uint8_t buf[32]; @@ -185,18 +238,36 @@ static void handle_s_without_atn(ESPState *s) s->dma_cb =3D handle_s_without_atn; return; } + s->pdma_cb =3D s_without_satn_pdma_cb; len =3D get_cmd(s, buf, sizeof(buf)); if (len) { do_busid_cmd(s, buf, 0); } } =20 +static void satn_stop_pdma_cb(ESPState *s) +{ + if (get_cmd_cb(s) < 0) { + return; + } + s->cmdlen =3D s->pdma_cur - s->pdma_start; + if (s->cmdlen) { + trace_esp_handle_satn_stop(s->cmdlen); + s->do_cmd =3D 1; + s->rregs[ESP_RSTAT] =3D STAT_TC | STAT_CD; + s->rregs[ESP_RINTR] =3D INTR_BS | INTR_FC; + s->rregs[ESP_RSEQ] =3D SEQ_CD; + esp_raise_irq(s); + } +} + static void handle_satn_stop(ESPState *s) { if (s->dma && !s->dma_enabled) { s->dma_cb =3D handle_satn_stop; return; } + s->pdma_cb =3D satn_stop_pdma_cb;; s->cmdlen =3D get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf)); if (s->cmdlen) { trace_esp_handle_satn_stop(s->cmdlen); @@ -208,16 +279,33 @@ static void handle_satn_stop(ESPState *s) } } =20 +static void write_response_pdma_cb(ESPState *s) +{ + s->rregs[ESP_RSTAT] =3D STAT_TC | STAT_ST; + s->rregs[ESP_RINTR] =3D INTR_BS | INTR_FC; + s->rregs[ESP_RSEQ] =3D SEQ_CD; + esp_raise_irq(s); +} + static void write_response(ESPState *s) { trace_esp_write_response(s->status); s->ti_buf[0] =3D s->status; s->ti_buf[1] =3D 0; if (s->dma) { - s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); - s->rregs[ESP_RSTAT] =3D STAT_TC | STAT_ST; - s->rregs[ESP_RINTR] =3D INTR_BS | INTR_FC; - s->rregs[ESP_RSEQ] =3D SEQ_CD; + if (s->dma_memory_write) { + s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); + s->rregs[ESP_RSTAT] =3D STAT_TC | STAT_ST; + s->rregs[ESP_RINTR] =3D INTR_BS | INTR_FC; + s->rregs[ESP_RSEQ] =3D SEQ_CD; + } else { + s->pdma_len =3D 2; + s->pdma_start =3D s->ti_buf; + s->pdma_cur =3D s->ti_buf; + s->pdma_cb =3D write_response_pdma_cb; + esp_raise_drq(s); + return; + } } else { s->ti_size =3D 2; s->ti_rptr =3D 0; @@ -239,6 +327,39 @@ static void esp_dma_done(ESPState *s) esp_raise_irq(s); } =20 +static void do_dma_pdma_cb(ESPState *s) +{ + int to_device =3D (s->ti_size < 0); + int len =3D s->pdma_cur - s->pdma_start; + if (s->do_cmd) { + s->ti_size =3D 0; + s->cmdlen =3D 0; + s->do_cmd =3D 0; + do_cmd(s, s->cmdbuf); + return; + } + s->dma_left -=3D len; + s->async_buf +=3D len; + s->async_len -=3D len; + if (to_device) { + s->ti_size +=3D len; + } else { + s->ti_size -=3D len; + } + if (s->async_len =3D=3D 0) { + scsi_req_continue(s->current_req); + /* If there is still data to be read from the device then + complete the DMA operation immediately. Otherwise defer + until the scsi layer has completed. */ + if (to_device || s->dma_left !=3D 0 || s->ti_size =3D=3D 0) { + return; + } + } + + /* Partially filled a scsi buffer. Complete immediately. */ + esp_dma_done(s); +} + static void esp_do_dma(ESPState *s) { uint32_t len; @@ -249,10 +370,26 @@ static void esp_do_dma(ESPState *s) trace_esp_do_dma(s->cmdlen, len); assert (s->cmdlen <=3D sizeof(s->cmdbuf) && len <=3D sizeof(s->cmdbuf) - s->cmdlen); - s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); + if (s->dma_memory_read) { + s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); + } else { + s->pdma_len =3D len; + s->pdma_start =3D &s->cmdbuf[s->cmdlen]; + s->pdma_cur =3D &s->cmdbuf[s->cmdlen]; + s->pdma_cb =3D do_dma_pdma_cb; + esp_raise_drq(s); + return; + } + s->ti_size =3D 0; + s->cmdlen =3D 0; + s->do_cmd =3D 0; + do_cmd(s, s->cmdbuf); return; } if (s->async_len =3D=3D 0) { + if (s->dma_left =3D=3D 0) { + esp_dma_done(s); + } /* Defer until data is available. */ return; } @@ -261,9 +398,27 @@ static void esp_do_dma(ESPState *s) } to_device =3D (s->ti_size < 0); if (to_device) { - s->dma_memory_read(s->dma_opaque, s->async_buf, len); + if (s->dma_memory_read) { + s->dma_memory_read(s->dma_opaque, s->async_buf, len); + } else { + s->pdma_len =3D len; + s->pdma_start =3D s->async_buf; + s->pdma_cur =3D s->async_buf; + s->pdma_cb =3D do_dma_pdma_cb; + esp_raise_drq(s); + return; + } } else { - s->dma_memory_write(s->dma_opaque, s->async_buf, len); + if (s->dma_memory_write) { + s->dma_memory_write(s->dma_opaque, s->async_buf, len); + } else { + s->pdma_len =3D len; + s->pdma_start =3D s->async_buf; + s->pdma_cur =3D s->async_buf; + s->pdma_cb =3D do_dma_pdma_cb; + esp_raise_drq(s); + return; + } } s->dma_left -=3D len; s->async_buf +=3D len; @@ -356,8 +511,7 @@ static void handle_ti(ESPState *s) s->dma_left =3D minlen; s->rregs[ESP_RSTAT] &=3D ~STAT_TC; esp_do_dma(s); - } - if (s->do_cmd) { + } else if (s->do_cmd) { trace_esp_handle_ti_cmd(s->cmdlen); s->ti_size =3D 0; s->cmdlen =3D 0; @@ -384,6 +538,7 @@ void esp_hard_reset(ESPState *s) static void esp_soft_reset(ESPState *s) { qemu_irq_lower(s->irq); + qemu_irq_lower(s->irq_data); esp_hard_reset(s); } =20 @@ -409,6 +564,7 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr) s->ti_size--; s->rregs[ESP_FIFO] =3D s->ti_buf[s->ti_rptr++]; } + esp_raise_irq(s); if (s->ti_rptr =3D=3D s->ti_wptr) { s->ti_rptr =3D 0; s->ti_wptr =3D 0; @@ -619,11 +775,85 @@ static const MemoryRegionOps sysbus_esp_mem_ops =3D { .valid.accepts =3D esp_mem_accepts, }; =20 +static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, + uint64_t val, unsigned int size) +{ + SysBusESPState *sysbus =3D opaque; + ESPState *s =3D &sysbus->esp; + uint32_t dmalen; + + dmalen =3D s->rregs[ESP_TCLO]; + dmalen |=3D s->rregs[ESP_TCMID] << 8; + dmalen |=3D s->rregs[ESP_TCHI] << 16; + if (dmalen =3D=3D 0 || s->pdma_len =3D=3D 0) { + return; + } + switch (size) { + case 1: + *s->pdma_cur++ =3D val; + s->pdma_len--; + dmalen--; + break; + case 2: + *s->pdma_cur++ =3D val >> 8; + *s->pdma_cur++ =3D val; + s->pdma_len -=3D 2; + dmalen -=3D 2; + break; + } + s->rregs[ESP_TCLO] =3D dmalen & 0xff; + s->rregs[ESP_TCMID] =3D dmalen >> 8; + s->rregs[ESP_TCHI] =3D dmalen >> 16; + if (s->pdma_len =3D=3D 0 && s->pdma_cb) { + esp_lower_drq(s); + s->pdma_cb(s); + s->pdma_cb =3D NULL; + } +} + +static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, + unsigned int size) +{ + SysBusESPState *sysbus =3D opaque; + ESPState *s =3D &sysbus->esp; + uint64_t val =3D 0; + + if (s->pdma_len =3D=3D 0) { + return 0; + } + switch (size) { + case 1: + val =3D *s->pdma_cur++; + s->pdma_len--; + break; + case 2: + val =3D *s->pdma_cur++; + val =3D (val << 8) | *s->pdma_cur++; + s->pdma_len -=3D 2; + break; + } + + if (s->pdma_len =3D=3D 0 && s->pdma_cb) { + esp_lower_drq(s); + s->pdma_cb(s); + s->pdma_cb =3D NULL; + } + return val; +} + +static const MemoryRegionOps sysbus_esp_pdma_ops =3D { + .read =3D sysbus_esp_pdma_read, + .write =3D sysbus_esp_pdma_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 2, +}; + ESPState *esp_init(hwaddr espaddr, int it_shift, ESPDMAMemoryReadWriteFunc dma_memory_read, ESPDMAMemoryReadWriteFunc dma_memory_write, - void *dma_opaque, qemu_irq irq, qemu_irq *reset, - qemu_irq *dma_enable) + void *dma_opaque, qemu_irq irq, qemu_irq irq_data, + qemu_irq *reset, qemu_irq *dma_enable) { DeviceState *dev; SysBusDevice *s; @@ -642,10 +872,44 @@ ESPState *esp_init(hwaddr espaddr, int it_shift, qdev_init_nofail(dev); s =3D SYS_BUS_DEVICE(dev); sysbus_connect_irq(s, 0, irq); + sysbus_connect_irq(s, 1, irq_data); + sysbus_mmio_map(s, 0, espaddr); + *reset =3D qdev_get_gpio_in(dev, 0); + *dma_enable =3D qdev_get_gpio_in(dev, 1); + + return esp; +} + +ESPState *esp_init_pdma(hwaddr espaddr, int it_shift, + hwaddr pdmaaddr, + qemu_irq irq, qemu_irq irq_data, + qemu_irq *reset, qemu_irq *dma_enable) +{ + DeviceState *dev; + SysBusDevice *s; + SysBusESPState *sysbus; + ESPState *esp; + + dev =3D qdev_create(NULL, "esp"); + sysbus =3D ESP_STATE(dev); + esp =3D &sysbus->esp; + esp->dma_memory_read =3D NULL; + esp->dma_memory_write =3D NULL; + esp->dma_opaque =3D NULL; + sysbus->it_shift =3D it_shift; + /* XXX for now until rc4030 has been changed to use DMA enable signal = */ + esp->dma_enabled =3D 1; + qdev_init_nofail(dev); + s =3D SYS_BUS_DEVICE(dev); + sysbus_connect_irq(s, 0, irq); + sysbus_connect_irq(s, 1, irq_data); sysbus_mmio_map(s, 0, espaddr); + sysbus_mmio_map(s, 1, pdmaaddr); *reset =3D qdev_get_gpio_in(dev, 0); *dma_enable =3D qdev_get_gpio_in(dev, 1); =20 + scsi_bus_legacy_handle_cmdline(&esp->bus); + return esp; } =20 @@ -681,12 +945,16 @@ static void sysbus_esp_realize(DeviceState *dev, Erro= r **errp) ESPState *s =3D &sysbus->esp; =20 sysbus_init_irq(sbd, &s->irq); + sysbus_init_irq(sbd, &s->irq_data); assert(sysbus->it_shift !=3D -1); =20 s->chip_id =3D TCHI_FAS100A; memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_= ops, - sysbus, "esp", ESP_REGS << sysbus->it_shift); + sysbus, "esp-regs", ESP_REGS << sysbus->it_shift= ); sysbus_init_mmio(sbd, &sysbus->iomem); + memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_= ops, + sysbus, "esp-pdma", 2); + sysbus_init_mmio(sbd, &sysbus->pdma); =20 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); =20 diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index 93fdaced67..de6c490acd 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -18,6 +18,7 @@ struct ESPState { uint8_t rregs[ESP_REGS]; uint8_t wregs[ESP_REGS]; qemu_irq irq; + qemu_irq irq_data; uint8_t chip_id; bool tchi_written; int32_t ti_size; @@ -46,6 +47,11 @@ struct ESPState { ESPDMAMemoryReadWriteFunc dma_memory_write; void *dma_opaque; void (*dma_cb)(ESPState *s); + uint8_t pdma_buf[32]; + uint32_t pdma_len; + uint8_t *pdma_start; + uint8_t *pdma_cur; + void (*pdma_cb)(ESPState *s); }; =20 #define TYPE_ESP "esp" @@ -57,6 +63,7 @@ typedef struct { /*< public >*/ =20 MemoryRegion iomem; + MemoryRegion pdma; uint32_t it_shift; ESPState esp; } SysBusESPState; @@ -134,8 +141,12 @@ typedef struct { ESPState *esp_init(hwaddr espaddr, int it_shift, ESPDMAMemoryReadWriteFunc dma_memory_read, ESPDMAMemoryReadWriteFunc dma_memory_write, - void *dma_opaque, qemu_irq irq, qemu_irq *reset, - qemu_irq *dma_enable); + void *dma_opaque, qemu_irq irq, qemu_irq irq_data, + qemu_irq *reset, qemu_irq *dma_enable); +ESPState *esp_init_pdma(hwaddr espaddr, int it_shift, + hwaddr pdmaaddr, + qemu_irq irq, qemu_irq irq_data, + qemu_irq *reset, qemu_irq *dma_enable); void esp_dma_enable(ESPState *s, int irq, int level); void esp_request_cancelled(SCSIRequest *req); void esp_command_complete(SCSIRequest *req, uint32_t status, size_t resid); --=20 2.14.4 From nobody Mon Apr 29 04:03:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528488905370949.4875641415113; Fri, 8 Jun 2018 13:15:05 -0700 (PDT) Received: from localhost ([::1]:38011 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNmq-0005sX-Gw for importer@patchew.org; Fri, 08 Jun 2018 16:15:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48052) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNf5-0007mz-GE for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:07:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fRNf2-0006vg-9s for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:07:03 -0400 Received: from mout.kundenserver.de ([212.227.126.134]:59859) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fRNes-0006ks-Vj; Fri, 08 Jun 2018 16:06:51 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue002 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MdTH9-1fidYM2FP9-00IQsP; Fri, 08 Jun 2018 22:06:22 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 8 Jun 2018 22:05:52 +0200 Message-Id: <20180608200558.386-8-laurent@vivier.eu> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180608200558.386-1-laurent@vivier.eu> References: <20180608200558.386-1-laurent@vivier.eu> X-Provags-ID: V03:K1:hSre1M1Xgi1hbM9oEjCJKfVqPFzTCWPaVDSVJ5TzSvFjPS9Rs6H niZ4fNbSrQuxRT2xNMUhID8S/CU55O8JvvMIPBiYlnYDg86Mh1NxUKWxhG2NEuiLels51Fv 55PEJqP5rk7JTYLD4EsHoiCqpiw7rfn7O1q06nZy2lHTsMtZaUjTE/i59l89oC7Mnf77z4v vxWiq6wv8BgvgddUnTgQQ== X-UI-Out-Filterresults: notjunk:1;V01:K0:6ucAirR+EC8=:JKmaDjrYMf/mljD6robX9d JLkq+PWQcERogk5xM9W1CpQMKmpVrSg3ZijMaiC6nYdCHKSKvYobcYuaC3WePQMBvWunoDEQs Cm26hVRhGwD2C1hz/ehOYLIwqfc7WQSDoH1sv7JskA4uV37LO+6p0hFbB64co+wipHnSFajqi 1m3GwvJvgSLMXAA5haF8CPQiMaotTTO0fFJ+7kKl3a4CHFYXOIPIyfTs7dLS6+Sp46qJBJdCn F4v3T1S3wJDIvYtnYwaA6EqEk32S9YOwODimU4pjimmJgstwAj6QMN67+L+yJOGoa14bXzhmQ 0fUkGVLyeXy1ys+cKuWw4WJDCiPSCXWgD5sm8P3PN04yJnc9973dT+ujNKndvh/LYaq/2jJGn qljoZDFb5XimYXSP+Fpc2wT9e0kod/w0gZ9BjiIPGh1Pgmw+OZBj5IVTbZuUjnXN5qyKHXL9V yH4CMCdstnLpAsLsKKfMXwMMeSWInMHw/qJunqAZ46Lm1r4XmXsbNxyTZYR5TGBho7bI8YftR g9hqSfEWvAnKPB2WVOdsEz1c+9iGp6t7eMlE2VmpXJwQOnCQ4DKE2Qw7jXpgW1dBea0O9nfXs 2uJyYlkeVNFCREqPLw71LNXo1n9FyUgvJBlwyQ/HPOmueeJNMOxJFPI2fw1kCnPSfmWEvpzXo uFwfXHE5A8S9Ha0lu+VtIfriin3OFG3hhPdseobznZwyRaCzdtea9iTPW96j5dWNZLqA= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.134 Subject: [Qemu-devel] [RFC 07/13] hw/m68k: add Nubus support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Jason Wang , "Dr. David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , Yongbok Kim , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Laurent Vivier --- hw/Makefile.objs | 1 + hw/display/macfb.c | 67 +++++++++++- hw/nubus/Makefile.objs | 4 + hw/nubus/mac.c | 112 +++++++++++++++++++ hw/nubus/nubus-bridge.c | 34 ++++++ hw/nubus/nubus-bus.c | 60 +++++++++++ hw/nubus/nubus-device.c | 275 +++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/nubus/mac.h | 24 +++++ include/hw/nubus/nubus.h | 89 +++++++++++++++ include/qemu/typedefs.h | 2 + 10 files changed, 663 insertions(+), 5 deletions(-) create mode 100644 hw/nubus/Makefile.objs create mode 100644 hw/nubus/mac.c create mode 100644 hw/nubus/nubus-bridge.c create mode 100644 hw/nubus/nubus-bus.c create mode 100644 hw/nubus/nubus-device.c create mode 100644 include/hw/nubus/mac.h create mode 100644 include/hw/nubus/nubus.h diff --git a/hw/Makefile.objs b/hw/Makefile.objs index a19c1417ed..8c97b4b97b 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -35,6 +35,7 @@ devices-dirs-$(CONFIG_SOFTMMU) +=3D watchdog/ devices-dirs-$(CONFIG_SOFTMMU) +=3D xen/ devices-dirs-$(CONFIG_MEM_HOTPLUG) +=3D mem/ devices-dirs-$(CONFIG_SOFTMMU) +=3D smbios/ +devices-dirs-$(CONFIG_NUBUS) +=3D nubus/ devices-dirs-y +=3D core/ common-obj-y +=3D $(devices-dirs-y) obj-y +=3D $(devices-dirs-y) diff --git a/hw/display/macfb.c b/hw/display/macfb.c index b2dd300a80..295fd0fc8a 100644 --- a/hw/display/macfb.c +++ b/hw/display/macfb.c @@ -14,9 +14,12 @@ #include "hw/sysbus.h" #include "ui/console.h" #include "ui/pixel_ops.h" +#include "hw/nubus/nubus.h" + +#define VIDEO_BASE 0x00001000 +#define DAFB_BASE 0x00800000 =20 struct MacfbState { - SysBusDevice busdev; MemoryRegion mem_vram; MemoryRegion mem_ctrl; QemuConsole *con; @@ -219,10 +222,10 @@ static void macfb_init(DeviceState *dev, MacfbState *= s) =20 s->con =3D graphic_console_init(dev, 0, &macfb_ops, s); =20 - memory_region_init_io(&s->mem_ctrl, NULL, &macfb_ctrl_ops, s, "ctrl", + memory_region_init_io(&s->mem_ctrl, NULL, &macfb_ctrl_ops, s, "macfb-c= trl", 0x1000); - memory_region_init_ram_ptr(&s->mem_vram, NULL, "vram", MACFB_VRAM_SIZE, - s->vram); + memory_region_init_ram_ptr(&s->mem_vram, NULL, "macfb-vram", + MACFB_VRAM_SIZE, s->vram); vmstate_register_ram(&s->mem_vram, dev); memory_region_set_coalescing(&s->mem_vram); } @@ -232,6 +235,11 @@ typedef struct { MacfbState macfb; } MacfbSysBusState; =20 +typedef struct { + NubusDevice busdev; + MacfbState macfb; +} MacfbNubusState; + static int macfb_sysbus_init(SysBusDevice *dev) { MacfbState *s =3D &MACFB(dev)->macfb; @@ -243,12 +251,34 @@ static int macfb_sysbus_init(SysBusDevice *dev) return 0; } =20 +const uint8_t macfb_rom[] =3D { + 255, 0, 0, 0, +}; + +static int macfb_nubus_init(NubusDevice *dev) +{ + MacfbState *s =3D &DO_UPCAST(MacfbNubusState, busdev, dev)->macfb; + + macfb_init(DEVICE(dev), s); + nubus_add_slot_mmio(dev, DAFB_BASE, &s->mem_ctrl); + nubus_add_slot_mmio(dev, VIDEO_BASE, &s->mem_vram); + nubus_register_rom(dev, macfb_rom, sizeof(macfb_rom), 1, 9, 0xf); + + return 0; +} + static void macfb_sysbus_reset(DeviceState *d) { MacfbSysBusState *s =3D MACFB(d); macfb_reset(&s->macfb); } =20 +static void macfb_nubus_reset(DeviceState *d) +{ + MacfbNubusState *s =3D DO_UPCAST(MacfbNubusState, busdev.qdev, d); + macfb_reset(&s->macfb); +} + static Property macfb_sysbus_properties[] =3D { DEFINE_PROP_UINT32("width", MacfbSysBusState, macfb.width, 640), DEFINE_PROP_UINT32("height", MacfbSysBusState, macfb.height, 480), @@ -256,18 +286,37 @@ static Property macfb_sysbus_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static Property macfb_nubus_properties[] =3D { + DEFINE_PROP_UINT32("width", MacfbNubusState, macfb.width, 640), + DEFINE_PROP_UINT32("height", MacfbNubusState, macfb.height, 480), + DEFINE_PROP_UINT8("depth", MacfbNubusState, macfb.depth, 8), + DEFINE_PROP_END_OF_LIST(), +}; + static void macfb_sysbus_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); =20 k->init =3D macfb_sysbus_init; - dc->desc =3D "Macintosh framebuffer"; + dc->desc =3D "SysBus Macintosh framebuffer"; dc->reset =3D macfb_sysbus_reset; dc->vmsd =3D &vmstate_macfb; dc->props =3D macfb_sysbus_properties; } =20 +static void macfb_nubus_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + NubusDeviceClass *k =3D NUBUS_DEVICE_CLASS(klass); + + k->init =3D macfb_nubus_init; + dc->desc =3D "Nubus Macintosh framebuffer"; + dc->reset =3D macfb_nubus_reset; + dc->vmsd =3D &vmstate_macfb; + dc->props =3D macfb_nubus_properties; +} + static TypeInfo macfb_sysbus_info =3D { .name =3D TYPE_MACFB, .parent =3D TYPE_SYS_BUS_DEVICE, @@ -275,9 +324,17 @@ static TypeInfo macfb_sysbus_info =3D { .class_init =3D macfb_sysbus_class_init, }; =20 +static TypeInfo macfb_nubus_info =3D { + .name =3D "nubus-macfb", + .parent =3D TYPE_NUBUS_DEVICE, + .instance_size =3D sizeof(MacfbNubusState), + .class_init =3D macfb_nubus_class_init, +}; + static void macfb_register_types(void) { type_register_static(&macfb_sysbus_info); + type_register_static(&macfb_nubus_info); } =20 type_init(macfb_register_types) diff --git a/hw/nubus/Makefile.objs b/hw/nubus/Makefile.objs new file mode 100644 index 0000000000..812c8ea92f --- /dev/null +++ b/hw/nubus/Makefile.objs @@ -0,0 +1,4 @@ +common-obj-y +=3D nubus-device.o +common-obj-y +=3D nubus-bus.o +common-obj-y +=3D nubus-bridge.o +common-obj-$(CONFIG_MAC) +=3D mac.o diff --git a/hw/nubus/mac.c b/hw/nubus/mac.c new file mode 100644 index 0000000000..ba366d3705 --- /dev/null +++ b/hw/nubus/mac.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2013-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/nubus/mac.h" + +static void mac_nubus_slot_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) +{ +} + + +static uint64_t mac_nubus_slot_read(void *opaque, hwaddr addr, + unsigned int size) +{ + return 0; +} + +static const MemoryRegionOps mac_nubus_slot_ops =3D { + .read =3D mac_nubus_slot_read, + .write =3D mac_nubus_slot_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static void mac_nubus_super_slot_write(void *opaque, hwaddr addr, uint64_t= val, + unsigned int size) +{ +} + +static uint64_t mac_nubus_super_slot_read(void *opaque, hwaddr addr, + unsigned int size) +{ + return 0; +} + +static const MemoryRegionOps mac_nubus_super_slot_ops =3D { + .read =3D mac_nubus_super_slot_read, + .write =3D mac_nubus_super_slot_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static int mac_nubus_initfn(SysBusDevice *dev) +{ + MacNubusState *s =3D DO_UPCAST(MacNubusState, sysbus_dev, dev); + MemoryRegion *super_slot_io =3D g_malloc(sizeof(MemoryRegion));; + MemoryRegion *slot_io =3D g_malloc(sizeof(MemoryRegion)); + + memory_region_init_io(super_slot_io, NULL, &mac_nubus_super_slot_ops, + s, "nubus-super-slots", + NUBUS_SUPER_SLOT_NB * NUBUS_SUPER_SLOT_SIZE); + + memory_region_init_io(slot_io, NULL, &mac_nubus_slot_ops, + s, "nubus-slots", + NUBUS_SLOT_NB * NUBUS_SLOT_SIZE); + + sysbus_init_mmio(dev, super_slot_io); + sysbus_init_mmio(dev, slot_io); + + s->bus =3D nubus_bus_new(DEVICE(s), super_slot_io, slot_io); + + return 0; +} + +static void mac_nubus_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); + + k->init =3D mac_nubus_initfn; + dc->desc =3D "Nubus bridge"; +} + +static const TypeInfo mac_nubus_type_info =3D { + .name =3D TYPE_MAC_NUBUS_BRIDGE, + .parent =3D TYPE_NUBUS_BRIDGE, + .instance_size =3D sizeof(MacNubusState), + .class_init =3D mac_nubus_class_init, +}; + + +NubusBus *nubus_mac_new(hwaddr super_slot_base, hwaddr slot_base) +{ + DeviceState *dev; + + dev =3D qdev_create(NULL, TYPE_MAC_NUBUS_BRIDGE); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, super_slot_base); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, slot_base); + + return MAC_NUBUS_BRIDGE(dev)->bus; +} + +static void mac_nubus_register_types(void) +{ + type_register_static(&mac_nubus_type_info); +} + +type_init(mac_nubus_register_types) diff --git a/hw/nubus/nubus-bridge.c b/hw/nubus/nubus-bridge.c new file mode 100644 index 0000000000..cd8c6a91eb --- /dev/null +++ b/hw/nubus/nubus-bridge.c @@ -0,0 +1,34 @@ +/* + * QEMU Macintosh Nubus + * + * Copyright (c) 2013-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/nubus/nubus.h" + +static void nubus_bridge_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->fw_name =3D "nubus"; +} + +static const TypeInfo nubus_bridge_info =3D { + .name =3D TYPE_NUBUS_BRIDGE, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(SysBusDevice), + .class_init =3D nubus_bridge_class_init, +}; + +static void nubus_register_types(void) +{ + type_register_static(&nubus_bridge_info); +} + +type_init(nubus_register_types) diff --git a/hw/nubus/nubus-bus.c b/hw/nubus/nubus-bus.c new file mode 100644 index 0000000000..fd1344e554 --- /dev/null +++ b/hw/nubus/nubus-bus.c @@ -0,0 +1,60 @@ +/* + * QEMU Macintosh Nubus + * + * Copyright (c) 2013-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/nubus/nubus.h" + +static NubusBus *nubus; + +static void nubus_bus_initfn(Object *obj) +{ + NubusBus *bus =3D NUBUS_BUS(obj);; + bus->current_slot =3D NUBUS_FIRST_SLOT; +} + +static void nubus_bus_class_init(ObjectClass *klass, void *data) +{ +} + +static const TypeInfo nubus_bus_info =3D { + .name =3D TYPE_NUBUS_BUS, + .parent =3D TYPE_BUS, + .instance_size =3D sizeof(NubusBus), + .instance_init =3D nubus_bus_initfn, + .class_init =3D nubus_bus_class_init, +}; + +NubusBus *nubus_bus_new(DeviceState *dev, MemoryRegion *super_slot_io, + MemoryRegion *slot_io) +{ + if (nubus) { + fprintf(stderr, "Can't create a second Nubus bus\n"); + return NULL; + } + + if (NULL =3D=3D dev) { + dev =3D qdev_create(NULL, "nubus-bridge"); + qdev_init_nofail(dev); + } + + nubus =3D NUBUS_BUS(qbus_create(TYPE_NUBUS_BUS, dev, NULL)); + + nubus->super_slot_io =3D super_slot_io; + nubus->slot_io =3D slot_io; + + return nubus; +} + +static void nubus_register_types(void) +{ + type_register_static(&nubus_bus_info); +} + +type_init(nubus_register_types) diff --git a/hw/nubus/nubus-device.c b/hw/nubus/nubus-device.c new file mode 100644 index 0000000000..0c8023d46a --- /dev/null +++ b/hw/nubus/nubus-device.c @@ -0,0 +1,275 @@ +/* + * QEMU Macintosh Nubus + * + * Copyright (c) 2013-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/nubus/nubus.h" + +/* The Format Block Structure */ + +#define FBLOCK_DIRECTORY_OFFSET 0 +#define FBLOCK_LENGTH 4 +#define FBLOCK_CRC 8 +#define FBLOCK_REVISION_LEVEL 12 +#define FBLOCK_FORMAT 13 +#define FBLOCK_TEST_PATTERN 14 +#define FBLOCK_RESERVED 18 +#define FBLOCK_BYTE_LANES 19 + +#define FBLOCK_SIZE 20 + +# define FBLOCK_PATTERN_VAL 0x5a932bc7 + +static uint64_t nubus_fblock_read(void *opaque, hwaddr addr, unsigned int = size) +{ + NubusDevice *dev =3D opaque; + uint64_t val; + +#define BYTE(v, b) (((v) >> (24 - 8 * (b))) & 0xff) + switch (addr) { + case FBLOCK_BYTE_LANES: + val =3D dev->byte_lanes; + val |=3D (val ^ 0xf) << 4; + break; + case FBLOCK_RESERVED: + val =3D 0x00; + break; + case FBLOCK_TEST_PATTERN...FBLOCK_TEST_PATTERN + 3: + val =3D BYTE(FBLOCK_PATTERN_VAL, addr - FBLOCK_TEST_PATTERN); + break; + case FBLOCK_FORMAT: + val =3D dev->rom_format; + break; + case FBLOCK_REVISION_LEVEL: + val =3D dev->rom_rev; + break; + case FBLOCK_CRC...FBLOCK_CRC + 3: + val =3D BYTE(dev->rom_crc, addr - FBLOCK_CRC); + break; + case FBLOCK_LENGTH...FBLOCK_LENGTH + 3: + val =3D BYTE(dev->rom_length, addr - FBLOCK_LENGTH); + break; + case FBLOCK_DIRECTORY_OFFSET...FBLOCK_DIRECTORY_OFFSET + 3: + val =3D BYTE(dev->directory_offset, addr - FBLOCK_DIRECTORY_OFFSET= ); + break; + default: + val =3D 0; + break; + } + return val; +} + +static void nubus_fblock_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) +{ + /* READ-ONLY */ +} + +static const MemoryRegionOps nubus_format_block_ops =3D { + .read =3D nubus_fblock_read, + .write =3D nubus_fblock_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + } +}; + +static void nubus_register_format_block(NubusDevice *dev) +{ + char fblock_name[27]; + NubusBus *bus =3D nubus_bus_from_device(dev); + + sprintf(fblock_name, "nubus-slot-%d-format-block", dev->slot_nb); + + hwaddr fblock_offset =3D (dev->slot_nb + 1) * NUBUS_SLOT_SIZE - FBLOCK= _SIZE; + memory_region_init_io(&dev->fblock_io, NULL, &nubus_format_block_ops, + dev, fblock_name, FBLOCK_SIZE); + memory_region_add_subregion(bus->slot_io, fblock_offset, + &dev->fblock_io); +} + +NubusDevice *nubus_create(NubusBus *bus, const char *name) +{ + DeviceState *dev; + NubusDevice *d; + + if (!bus) { + hw_error("Tried to create nubus device %s with no nubus bus presen= t.", + name); + } + + if (bus->current_slot < NUBUS_FIRST_SLOT || + bus->current_slot > NUBUS_LAST_SLOT) { + fprintf(stderr, "Cannot register nubus card '%s', not enough slot\= n", + name); + return NULL; + } + + dev =3D qdev_create(&bus->qbus, name); + + d =3D NUBUS_DEVICE(dev); + d->slot_nb =3D bus->current_slot++; + nubus_register_format_block(d); + + return d; +} + +NubusDevice *nubus_try_create(NubusBus *bus, const char *name) +{ + DeviceState *dev; + NubusDevice *d; + + if (!bus) { + hw_error("Tried to create nubus device %s with no nubus bus presen= t.", + name); + } + + if (bus->current_slot < NUBUS_FIRST_SLOT || + bus->current_slot > NUBUS_LAST_SLOT) { + fprintf(stderr, "Cannot register nubus card '%s', not enough slot\= n", + name); + return NULL; + } + + dev =3D qdev_try_create(&bus->qbus, name); + if (!dev) { + return NULL; + } + + d =3D NUBUS_DEVICE(dev); + d->slot_nb =3D bus->current_slot++; + nubus_register_format_block(d); + + return d; +} + +NubusDevice *nubus_create_simple(NubusBus *bus, const char *name) +{ + NubusDevice *dev; + + dev =3D nubus_create(bus, name); + qdev_init_nofail(&dev->qdev); + + return dev; +} + +void nubus_add_slot_mmio(NubusDevice *dev, + hwaddr offset, + MemoryRegion *subregion) +{ + NubusBus *bus =3D nubus_bus_from_device(dev); + hwaddr slot_offset =3D dev->slot_nb * NUBUS_SLOT_SIZE + offset; + memory_region_add_subregion(bus->slot_io, slot_offset, subregion); +} + +void nubus_add_super_slot_mmio(NubusDevice *dev, + hwaddr offset, + MemoryRegion *subregion) +{ + NubusBus *bus =3D nubus_bus_from_device(dev); + hwaddr slot_offset =3D (dev->slot_nb - 6) * NUBUS_SUPER_SLOT_SIZE + of= fset; + memory_region_add_subregion(bus->super_slot_io, slot_offset, subregion= ); +} + +static void mac_nubus_rom_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) +{ +} + +static uint64_t mac_nubus_rom_read(void *opaque, hwaddr addr, + unsigned int size) +{ + NubusDevice *dev =3D opaque; + + return dev->rom[addr]; +} + +static const MemoryRegionOps mac_nubus_rom_ops =3D { + .read =3D mac_nubus_rom_read, + .write =3D mac_nubus_rom_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + + +void nubus_register_rom(NubusDevice *dev, const uint8_t *rom, uint32_t siz= e, + int revision, int format, uint8_t byte_lanes) +{ + NubusBus *bus =3D nubus_bus_from_device(dev); + hwaddr rom_offset; + char rom_name[18]; + + /* FIXME : really compute CRC */ + dev->rom_length =3D 0; + dev->rom_crc =3D 0; + + dev->rom_rev =3D revision; + dev->rom_format =3D format; + + dev->byte_lanes =3D byte_lanes; + dev->directory_offset =3D -size; + + /* ROM */ + + dev->rom =3D rom; + sprintf(rom_name, "nubus-slot-%d-rom", dev->slot_nb); + memory_region_init_io(&dev->rom_io, NULL, &mac_nubus_rom_ops, + dev, rom_name, size); + memory_region_set_readonly(&dev->rom_io, true); + + rom_offset =3D (dev->slot_nb + 1) * NUBUS_SLOT_SIZE - FBLOCK_SIZE + + dev->directory_offset; + memory_region_add_subregion(bus->slot_io, rom_offset, &dev->rom_io); + +} + + +static void nubus_device_init(Object *obj) +{ +} + +static int nubus_qdev_init(DeviceState *qdev) +{ + NubusDevice *dev =3D NUBUS_DEVICE(qdev); + NubusDeviceClass *klass =3D NUBUS_DEVICE_GET_CLASS(dev); + + if (klass->init) { + return klass->init(dev); + } + + return 0; +} + +static void nubus_device_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *k =3D DEVICE_CLASS(klass); + k->init =3D nubus_qdev_init; + k->bus_type =3D TYPE_NUBUS_BUS; +} + +static const TypeInfo nubus_device_type_info =3D { + .name =3D TYPE_NUBUS_DEVICE, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(NubusDevice), + .instance_init =3D nubus_device_init, + .abstract =3D true, + .class_size =3D sizeof(NubusDeviceClass), + .class_init =3D nubus_device_class_init, +}; + +static void nubus_register_types(void) +{ + type_register_static(&nubus_device_type_info); +} + +type_init(nubus_register_types) diff --git a/include/hw/nubus/mac.h b/include/hw/nubus/mac.h new file mode 100644 index 0000000000..502d35ba9d --- /dev/null +++ b/include/hw/nubus/mac.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2013-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef HW_NUBUS_MAC_H +#define HW_NUBUS_MAC_H + +#include "hw/nubus/nubus.h" + +#define TYPE_MAC_NUBUS_BRIDGE "mac-nubus-bridge" +#define MAC_NUBUS_BRIDGE(obj) OBJECT_CHECK(MacNubusState, (obj), \ + TYPE_MAC_NUBUS_BRIDGE) + +typedef struct MacNubusState { + SysBusDevice sysbus_dev; + NubusBus *bus; +} MacNubusState; + +NubusBus *nubus_mac_new(hwaddr super_slot_base, hwaddr slot_base); +#endif diff --git a/include/hw/nubus/nubus.h b/include/hw/nubus/nubus.h new file mode 100644 index 0000000000..c0cbbfea33 --- /dev/null +++ b/include/hw/nubus/nubus.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2013-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef HW_NUBUS_NUBUS_H +#define HW_NUBUS_NUBUS_H + +#include "hw/qdev.h" +#include "exec/address-spaces.h" + +#define NUBUS_SUPER_SLOT_SIZE 0x10000000U +#define NUBUS_SUPER_SLOT_NB 0x9 + +#define NUBUS_SLOT_SIZE 0x01000000 +#define NUBUS_SLOT_NB 0xF + +#define NUBUS_FIRST_SLOT 0x9 +#define NUBUS_LAST_SLOT 0xF + +#define TYPE_NUBUS_DEVICE "nubus-device" +#define NUBUS_DEVICE(obj) \ + OBJECT_CHECK(NubusDevice, (obj), TYPE_NUBUS_DEVICE) +#define NUBUS_DEVICE_CLASS(klass) \ + OBJECT_CLASS_CHECK(NubusDeviceClass, (klass), TYPE_NUBUS_DEVICE) +#define NUBUS_DEVICE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(NubusDeviceClass, (obj), TYPE_NUBUS_DEVICE) + +#define TYPE_NUBUS_BUS "nubus-bus" +#define NUBUS_BUS(obj) OBJECT_CHECK(NubusBus, (obj), TYPE_NUBUS_BUS) + +#define TYPE_NUBUS_BRIDGE "nubus-bridge" +#define NUBUS_BRIDGE(obj) OBJECT_CHECK(NubusBridge, (obj), TYPE_NUBUS_BRID= GE) + +typedef struct NubusDeviceClass { + DeviceClass parent_class; + int (*init)(NubusDevice *dev); +} NubusDeviceClass; + +struct NubusBus { + BusState qbus; + int current_slot; + MemoryRegion *super_slot_io; + MemoryRegion *slot_io; + qemu_irq *irqs; +}; + +struct NubusDevice { + DeviceState qdev; + + int slot_nb; + + /* Format Block */ + + MemoryRegion fblock_io; + + uint32_t rom_length; + uint32_t rom_crc; + uint8_t rom_rev; + uint8_t rom_format; + uint8_t byte_lanes; + int32_t directory_offset; + + /* ROM */ + + MemoryRegion rom_io; + const uint8_t *rom; +}; + +NubusBus *nubus_bus_new(DeviceState *dev, MemoryRegion *super_slot_io, + MemoryRegion *slot_io); +NubusDevice *nubus_try_create(NubusBus *bus, const char *name); +NubusDevice *nubus_create_simple(NubusBus *bus, const char *name); +NubusDevice *nubus_create(NubusBus *bus, const char *name); +void nubus_add_slot_mmio(NubusDevice *dev, hwaddr offset, + MemoryRegion *subregion); +void nubus_add_super_slot_mmio(NubusDevice *dev, hwaddr offset, + MemoryRegion *subregion); +void nubus_register_rom(NubusDevice *dev, const uint8_t *rom, uint32_t siz= e, + int revision, int format, uint8_t byte_lanes); + +static inline NubusBus *nubus_bus_from_device(NubusDevice *d) +{ + return NUBUS_BUS(qdev_get_parent_bus(DEVICE(d))); +} +#endif diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 325c72de33..91a50fe954 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -43,6 +43,8 @@ typedef struct I2SCodec I2SCodec; typedef struct ISABus ISABus; typedef struct ISADevice ISADevice; typedef struct IsaDma IsaDma; +typedef struct NubusBus NubusBus; +typedef struct NubusDevice NubusDevice; typedef struct MACAddr MACAddr; typedef struct MachineClass MachineClass; typedef struct MachineState MachineState; --=20 2.14.4 From nobody Mon Apr 29 04:03:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 15284888598971013.1305876496398; Fri, 8 Jun 2018 13:14:19 -0700 (PDT) Received: from localhost ([::1]:38007 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNly-00058G-He for importer@patchew.org; Fri, 08 Jun 2018 16:14:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47822) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNet-0007a1-OA for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:06:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fRNeq-0006kM-H9 for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:06:51 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:53137) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fRNeq-0006iX-6M; Fri, 08 Jun 2018 16:06:48 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue002 [212.227.15.167]) with ESMTPSA (Nemesis) id 0Lg9w4-1g5vXw3Xsq-00nlmU; Fri, 08 Jun 2018 22:06:25 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 8 Jun 2018 22:05:53 +0200 Message-Id: <20180608200558.386-9-laurent@vivier.eu> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180608200558.386-1-laurent@vivier.eu> References: <20180608200558.386-1-laurent@vivier.eu> X-Provags-ID: V03:K1:CBlbKs8E0s1Ckap8gRgogQgCx+l0AoR5eACk7/c3VIwZ7SvC3AL 1LZ35FzbxpMEHoDR4GdJ2AfpoLkKS7Og/eDGNDt74A4XEXJyvPigsEx4aXm+c83txzMHurD unONKHB0Y0k1y2gM1EJFZpVYjiC8qIUntBS/gX5gLhKniERfNsZs8GsJRiMQQv71IvZ+DAr vGaS/3tT/lQUZuqQCqPrA== X-UI-Out-Filterresults: notjunk:1;V01:K0:R05x2W+91Ek=:1hC4Elv1nbHGZLswQDldpx sbeyWDDNs1S8YMbwCDoq8EJdN/HnLDeXr28GTrmpwBO8pbtn63+I2FljTndSPs//7sAqtLu49 wrvDz2lKobhKpH/LpdhQaCzyhPYTeGfFEa12JOgUR35bBse/49xkZS5+8QNnCNKvvLn5FpHNz gTnIxUqpjqsNPengmjEULhM023yeRsnFxj7NWyFq8ORxj9v+q/B1bFUMFVZLnanx6Y8/rTa7L 9u5XBcnZru/knQZCcB8895tBLHCV3empwAHDWCR3XtSavHO1VryIdDOJrv2IcaVBhNX00xh0B WvX+OTH0Cqv7d1ooIwx/9Z+CPd991ZMjrvA9bSbZvQ/76WMRTQmwRpzlsxcDo0Nqa7B0Ry06m EGYqfD5nHr9L8/aq71BVyupfCJsvoO4vo1kOepQO1xANsgQIyBM1Cy4hu5iYlINdA0croqqsr 8aaUKb1kgAAa8YeWngi55qo/U4CsfKat5/oEUa6rjWaIgGwh4ptFwYBhcTqBf70BVDj/3r6S0 sCM1FhufC6hv7Gpxn2OuRVV6QAKBKWH0dhfh27gGZh9tXaB/63e8M7yDxCeZozsxcQtRBnt22 t5uio3ZhSbgAzJbKpV5VdleJPXl5GNhQghcEwHefUBtVRz0Gg0zNqBGj6JzpdnqMR+rvxz0dz nZDGj8crCWLDvsnvUA91r5jKrc7wHP+rILD1b8Xov/ILh4WBz1YiQaMAYPCFMtkTap9E= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [RFC 08/13] hw/m68k: add a dummy SWIM floppy controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Jason Wang , "Dr. David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , Yongbok Kim , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Laurent Vivier --- hw/block/Makefile.objs | 1 + hw/block/swim.c | 325 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 326 insertions(+) create mode 100644 hw/block/swim.c diff --git a/hw/block/Makefile.objs b/hw/block/Makefile.objs index 53ce5751ae..068de3f0c9 100644 --- a/hw/block/Makefile.objs +++ b/hw/block/Makefile.objs @@ -8,6 +8,7 @@ common-obj-$(CONFIG_XEN) +=3D xen_disk.o common-obj-$(CONFIG_ECC) +=3D ecc.o common-obj-$(CONFIG_ONENAND) +=3D onenand.o common-obj-$(CONFIG_NVME_PCI) +=3D nvme.o +common-obj-$(CONFIG_SWIM) +=3D swim.o =20 obj-$(CONFIG_SH4) +=3D tc58128.o =20 diff --git a/hw/block/swim.c b/hw/block/swim.c new file mode 100644 index 0000000000..33424ca76f --- /dev/null +++ b/hw/block/swim.c @@ -0,0 +1,325 @@ +/* + * QEMU Macintosh floppy disk controller emulator (SWIM) + * + * Copyright (c) 2014-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" + +/* IWM registers */ + +#define IWM_PH0L 0 +#define IWM_PH0H 1 +#define IWM_PH1L 2 +#define IWM_PH1H 3 +#define IWM_PH2L 4 +#define IWM_PH2H 5 +#define IWM_PH3L 6 +#define IWM_PH3H 7 +#define IWM_MTROFF 8 +#define IWM_MTRON 9 +#define IWM_INTDRIVE 10 +#define IWM_EXTDRIVE 11 +#define IWM_Q6L 12 +#define IWM_Q6H 13 +#define IWM_Q7L 14 +#define IWM_Q7H 15 + +/* SWIM registers */ + +#define SWIM_WRITE_DATA 0 +#define SWIM_WRITE_MARK 1 +#define SWIM_WRITE_CRC 2 +#define SWIM_WRITE_PARAMETER 3 +#define SWIM_WRITE_PHASE 4 +#define SWIM_WRITE_SETUP 5 +#define SWIM_WRITE_MODE0 6 +#define SWIM_WRITE_MODE1 7 + +#define SWIM_READ_DATA 8 +#define SWIM_READ_MARK 9 +#define SWIM_READ_ERROR 10 +#define SWIM_READ_PARAMETER 11 +#define SWIM_READ_PHASE 12 +#define SWIM_READ_SETUP 13 +#define SWIM_READ_STATUS 14 +#define SWIM_READ_HANDSHAKE 15 + +#define REG_SHIFT 9 + +#define MAX_FD 2 + +typedef struct SWIMCtrl SWIMCtrl; + +typedef struct FDrive { + SWIMCtrl *swimctrl; + BlockBackend *blk; +} FDrive; + +#define SWIM_MODE_IWM 0 +#define SWIM_MODE_SWIM 1 + +/* bits in phase register */ + +#define SWIM_SEEK_NEGATIVE 0x074 +#define SWIM_STEP 0x071 +#define SWIM_MOTOR_ON 0x072 +#define SWIM_MOTOR_OFF 0x076 +#define SWIM_INDEX 0x073 +#define SWIM_EJECT 0x077 +#define SWIM_SETMFM 0x171 +#define SWIM_SETGCR 0x175 +#define SWIM_RELAX 0x033 +#define SWIM_LSTRB 0x008 +#define SWIM_CA_MASK 0x077 + +/* Select values for swim_select and swim_readbit */ + +#define SWIM_READ_DATA_0 0x074 +#define SWIM_TWOMEG_DRIVE 0x075 +#define SWIM_SINGLE_SIDED 0x076 +#define SWIM_DRIVE_PRESENT 0x077 +#define SWIM_DISK_IN 0x170 +#define SWIM_WRITE_PROT 0x171 +#define SWIM_TRACK_ZERO 0x172 +#define SWIM_TACHO 0x173 +#define SWIM_READ_DATA_1 0x174 +#define SWIM_MFM_MODE 0x175 +#define SWIM_SEEK_COMPLETE 0x176 +#define SWIM_ONEMEG_MEDIA 0x177 + +/* Bits in handshake register */ + +#define SWIM_MARK_BYTE 0x01 +#define SWIM_CRC_ZERO 0x02 +#define SWIM_RDDATA 0x04 +#define SWIM_SENSE 0x08 +#define SWIM_MOTEN 0x10 +#define SWIM_ERROR 0x20 +#define SWIM_DAT2BYTE 0x40 +#define SWIM_DAT1BYTE 0x80 + +/* bits in setup register */ + +#define SWIM_S_INV_WDATA 0x01 +#define SWIM_S_3_5_SELECT 0x02 +#define SWIM_S_GCR 0x04 +#define SWIM_S_FCLK_DIV2 0x08 +#define SWIM_S_ERROR_CORR 0x10 +#define SWIM_S_IBM_DRIVE 0x20 +#define SWIM_S_GCR_WRITE 0x40 +#define SWIM_S_TIMEOUT 0x80 + +/* bits in mode register */ + +#define SWIM_CLFIFO 0x01 +#define SWIM_ENBL1 0x02 +#define SWIM_ENBL2 0x04 +#define SWIM_ACTION 0x08 +#define SWIM_WRITE_MODE 0x10 +#define SWIM_HEDSEL 0x20 +#define SWIM_MOTON 0x80 + +struct SWIMCtrl { + MemoryRegion iomem; + FDrive drives[MAX_FD]; + int mode; + /* IWM mode */ + int iwm_switch; + int regs[8]; +#define IWM_PH0 0 +#define IWM_PH1 1 +#define IWM_PH2 2 +#define IWM_PH3 3 +#define IWM_MTR 4 +#define IWM_DRIVE 5 +#define IWM_Q6 6 +#define IWM_Q7 7 + uint8_t iwm_data; + uint8_t iwm_mode; + /* SWIM mode */ + uint8_t swim_phase; + uint8_t swim_mode; +}; + +#define TYPE_SYSBUS_SWIM "sysbus-swim" +#define SYSBUS_SWIM(obj) OBJECT_CHECK(SWIMCtrlSysBus, (obj), TYPE_SYSBUS_S= WIM) + +typedef struct SWIMCtrlSysBus { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + struct SWIMCtrl state; +} SWIMCtrlSysBus; + +static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value, + unsigned size) +{ + SWIMCtrl *swimctrl =3D opaque; + + reg >>=3D REG_SHIFT; + + swimctrl->regs[reg >> 1] =3D reg & 1; + + if (swimctrl->regs[IWM_Q6] && + swimctrl->regs[IWM_Q7]) { + if (swimctrl->regs[IWM_MTR]) { + /* data register */ + swimctrl->iwm_data =3D value; + } else { + /* mode register */ + swimctrl->iwm_mode =3D value; + /* detect sequence to switch from IWM mode to SWIM mode */ + switch (swimctrl->iwm_switch) { + case 0: + if (value =3D=3D 0x57) { + swimctrl->iwm_switch++; + } + break; + case 1: + if (value =3D=3D 0x17) { + swimctrl->iwm_switch++; + } + break; + case 2: + if (value =3D=3D 0x57) { + swimctrl->iwm_switch++; + } + break; + case 3: + if (value =3D=3D 0x57) { + swimctrl->mode =3D SWIM_MODE_SWIM; + swimctrl->iwm_switch =3D 0; + } + break; + } + } + } +} + +static uint64_t iwmctrl_read(void *opaque, hwaddr reg, unsigned size) +{ + SWIMCtrl *swimctrl =3D opaque; + + reg >>=3D REG_SHIFT; + + swimctrl->regs[reg >> 1] =3D reg & 1; + + return 0; +} + +static void swimctrl_write(void *opaque, hwaddr reg, uint64_t value, + unsigned size) +{ + SWIMCtrl *swimctrl =3D opaque; + + if (swimctrl->mode =3D=3D SWIM_MODE_IWM) { + iwmctrl_write(opaque, reg, value, size); + return; + } + + reg >>=3D REG_SHIFT; + + switch (reg) { + case SWIM_WRITE_PHASE: + swimctrl->swim_phase =3D value; + break; + case SWIM_WRITE_MODE0: + swimctrl->swim_mode &=3D ~value; + break; + case SWIM_WRITE_MODE1: + swimctrl->swim_mode |=3D value; + break; + case SWIM_WRITE_DATA: + case SWIM_WRITE_MARK: + case SWIM_WRITE_CRC: + case SWIM_WRITE_PARAMETER: + case SWIM_WRITE_SETUP: + break; + } +} + +static uint64_t swimctrl_read(void *opaque, hwaddr reg, unsigned size) +{ + SWIMCtrl *swimctrl =3D opaque; + uint32_t value =3D 0; + + if (swimctrl->mode =3D=3D SWIM_MODE_IWM) { + return iwmctrl_read(opaque, reg, size); + } + + reg >>=3D REG_SHIFT; + + switch (reg) { + case SWIM_READ_PHASE: + value =3D swimctrl->swim_phase; + break; + case SWIM_READ_HANDSHAKE: + if (swimctrl->swim_phase =3D=3D SWIM_DRIVE_PRESENT) { + /* always answer "no drive present" */ + value =3D SWIM_SENSE; + } + break; + case SWIM_READ_DATA: + case SWIM_READ_MARK: + case SWIM_READ_ERROR: + case SWIM_READ_PARAMETER: + case SWIM_READ_SETUP: + case SWIM_READ_STATUS: + break; + } + + return value; +} + +static const MemoryRegionOps swimctrl_mem_ops =3D { + .write =3D swimctrl_write, + .read =3D swimctrl_read, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static void sysbus_swim_initfn(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + SWIMCtrlSysBus *sys =3D SYSBUS_SWIM(obj); + SWIMCtrl *swimctrl =3D &sys->state; + + memory_region_init_io(&swimctrl->iomem, obj, &swimctrl_mem_ops, swimct= rl, + "swim", 0x2000); + sysbus_init_mmio(sbd, &swimctrl->iomem); +} + +static Property sysbus_swim_properties[] =3D { + DEFINE_PROP_DRIVE("driveA", SWIMCtrlSysBus, state.drives[0].blk), + DEFINE_PROP_DRIVE("driveB", SWIMCtrlSysBus, state.drives[1].blk), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sysbus_swim_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->props =3D sysbus_swim_properties; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); +} + +static const TypeInfo sysbus_swim_info =3D { + .name =3D TYPE_SYSBUS_SWIM, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(SWIMCtrlSysBus), + .instance_init =3D sysbus_swim_initfn, + .class_init =3D sysbus_swim_class_init, +}; + +static void swim_register_types(void) +{ + type_register_static(&sysbus_swim_info); +} + +type_init(swim_register_types) --=20 2.14.4 From nobody Mon Apr 29 04:03:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528488864586843.7701549624394; Fri, 8 Jun 2018 13:14:24 -0700 (PDT) Received: from localhost ([::1]:38008 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNm3-0005Bc-Bl for importer@patchew.org; Fri, 08 Jun 2018 16:14:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47940) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNez-0007gZ-Or for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:07:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fRNew-0006oO-3P for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:06:57 -0400 Received: from mout.kundenserver.de ([212.227.126.131]:55933) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fRNev-0006mn-Kk; Fri, 08 Jun 2018 16:06:54 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue002 [212.227.15.167]) with ESMTPSA (Nemesis) id 0LiKia-1fzLxe1DI4-00ci5K; Fri, 08 Jun 2018 22:06:27 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 8 Jun 2018 22:05:54 +0200 Message-Id: <20180608200558.386-10-laurent@vivier.eu> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180608200558.386-1-laurent@vivier.eu> References: <20180608200558.386-1-laurent@vivier.eu> X-Provags-ID: V03:K1:lQg5t1IHhsOyhv6iHV4Jw4WT5nELi2/c3QXuRhg1s3UNN7YRRiB snKrKNVWuHMjfapuBc+SEtE03wu7saUEU6+zxB6P12XKO8zvFcuMNuJbMuD2YCX2Rnc9Acp e4fitiXqX9hN4XAI4s4429gZN/lThZ6moOHQzusmTbqvqigFboeZrU6g19qVUbbknRTTDYw Z5zpcMF8sxnZepcJSqBow== X-UI-Out-Filterresults: notjunk:1;V01:K0:9a/LjXycE2Q=:4lWZAbCEyJVFiIDA+mz1+o W8wFC9Uc4lJR6v9cROqij4R5xumYpzq1Wcc28SA6oWt+FkQRvC+IgbRzv90IzLU/UVnAXhYIT BWEDU9AyKCGROWIlfcncA4/UoIK+oNOBfOr5z1zt9XcaHKCMRXh41d5lsb8y4vG1Q7AlYccd6 tmZanIe7wyQQYrqb0aiRTnncNFKBQKKZ3HL2qJm6cPFqmglqZJpvvpn17IH+z5lG1a5qJPI40 sx96r17q8ABgqcs2tov7xncHRVr2OceaEtguREYcSK6megpxZn8CbWjtHsmt3L8ygBir70NU8 cNlwBQd1Cwq/tFhbFPcwamk37EWQNFkDi3+t9wRHFbnOsSaZ5mzvVvLIMdpIcC0kRHyGTIpL3 xpNwLy8CtjvYAQaSi1Wrr5QNOOObV4HOTW6G+G27zCtfqoVu7GB+JIKeExeUHt4vlOvRi9t2w 6YmNmyAfXUP2OkIEaZVFH7GdOW/p2nApCANIpsw6UgeY/j9OVgiXAfz1PlQ2FSkv50yr5SAk2 VJZsbW0FNjxZl+RWv7CFK83xnW2jKT8wpJ9wh+EmrJkT2x8LKs6czcmAFiHgZUN6c8pHYhxg0 JDcWbmW1x9SGkgYcYrb52+COR1ycSEqDwD97UqcLsWShGADvenRLhmMKHx0buyKMgwKuC55jV XzdTYzML38HTKsb5ntOUJ4ujT8KBcERtjLE0NsT7c9nHAlWsn6BLdfwnOQnNUoIO2TJA= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.131 Subject: [Qemu-devel] [RFC 09/13] hw/m68k: define Macintosh Quadra 800 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Jason Wang , "Dr. David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , Yongbok Kim , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Laurent Vivier Signed-off-by: Laurent Vivier --- default-configs/m68k-softmmu.mak | 12 ++ hw/display/macfb.c | 31 ++-- hw/m68k/Makefile.objs | 6 +- hw/m68k/bootinfo.h | 99 ++++++++++ hw/m68k/mac.c | 384 +++++++++++++++++++++++++++++++++++= ++++ hw/nubus/nubus-device.c | 13 -- tests/qom-test.c | 5 + tests/test-hmp.c | 3 +- 8 files changed, 519 insertions(+), 34 deletions(-) create mode 100644 hw/m68k/bootinfo.h create mode 100644 hw/m68k/mac.c diff --git a/default-configs/m68k-softmmu.mak b/default-configs/m68k-softmm= u.mak index 60f7cdfbf2..1b568be166 100644 --- a/default-configs/m68k-softmmu.mak +++ b/default-configs/m68k-softmmu.mak @@ -2,3 +2,15 @@ =20 CONFIG_COLDFIRE=3Dy CONFIG_PTIMER=3Dy +CONFIG_ESCC=3Dy +CONFIG_FRAMEBUFFER=3Dy +CONFIG_ADB=3Dy +CONFIG_MAC_VIA=3Dy +CONFIG_MAC=3Dy +CONFIG_SCSI=3Dy +CONFIG_ESP=3Dy +CONFIG_ASC=3Dy +CONFIG_MACFB=3Dy +CONFIG_NUBUS=3Dy +CONFIG_DP8393X=3Dy +CONFIG_SWIM=3Dy diff --git a/hw/display/macfb.c b/hw/display/macfb.c index 295fd0fc8a..a3204ab150 100644 --- a/hw/display/macfb.c +++ b/hw/display/macfb.c @@ -240,31 +240,28 @@ typedef struct { MacfbState macfb; } MacfbNubusState; =20 -static int macfb_sysbus_init(SysBusDevice *dev) +static void macfb_sysbus_realize(DeviceState *dev, Error **errp) { MacfbState *s =3D &MACFB(dev)->macfb; =20 - macfb_init(DEVICE(dev), s); - sysbus_init_mmio(dev, &s->mem_ctrl); - sysbus_init_mmio(dev, &s->mem_vram); - - return 0; + macfb_init(dev, s); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mem_ctrl); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mem_vram); } =20 const uint8_t macfb_rom[] =3D { 255, 0, 0, 0, }; =20 -static int macfb_nubus_init(NubusDevice *dev) +static void macfb_nubus_realize(DeviceState *dev, Error **errp) { - MacfbState *s =3D &DO_UPCAST(MacfbNubusState, busdev, dev)->macfb; + NubusDevice *nubus =3D NUBUS_DEVICE(dev); + MacfbState *s =3D &DO_UPCAST(MacfbNubusState, busdev, nubus)->macfb; =20 - macfb_init(DEVICE(dev), s); - nubus_add_slot_mmio(dev, DAFB_BASE, &s->mem_ctrl); - nubus_add_slot_mmio(dev, VIDEO_BASE, &s->mem_vram); - nubus_register_rom(dev, macfb_rom, sizeof(macfb_rom), 1, 9, 0xf); - - return 0; + macfb_init(dev, s); + nubus_add_slot_mmio(nubus, DAFB_BASE, &s->mem_ctrl); + nubus_add_slot_mmio(nubus, VIDEO_BASE, &s->mem_vram); + nubus_register_rom(nubus, macfb_rom, sizeof(macfb_rom), 1, 9, 0xf); } =20 static void macfb_sysbus_reset(DeviceState *d) @@ -296,9 +293,8 @@ static Property macfb_nubus_properties[] =3D { static void macfb_sysbus_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); =20 - k->init =3D macfb_sysbus_init; + dc->realize =3D macfb_sysbus_realize; dc->desc =3D "SysBus Macintosh framebuffer"; dc->reset =3D macfb_sysbus_reset; dc->vmsd =3D &vmstate_macfb; @@ -308,9 +304,8 @@ static void macfb_sysbus_class_init(ObjectClass *klass,= void *data) static void macfb_nubus_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); - NubusDeviceClass *k =3D NUBUS_DEVICE_CLASS(klass); =20 - k->init =3D macfb_nubus_init; + dc->realize =3D macfb_nubus_realize; dc->desc =3D "Nubus Macintosh framebuffer"; dc->reset =3D macfb_nubus_reset; dc->vmsd =3D &vmstate_macfb; diff --git a/hw/m68k/Makefile.objs b/hw/m68k/Makefile.objs index d1f089c08a..ff739617b2 100644 --- a/hw/m68k/Makefile.objs +++ b/hw/m68k/Makefile.objs @@ -1,2 +1,4 @@ -obj-y +=3D an5206.o mcf5208.o -obj-y +=3D mcf5206.o mcf_intc.o +obj-$(CONFIG_COLDFIRE) +=3D an5206.o mcf5208.o +obj-$(CONFIG_MAC) +=3D mac.o + +obj-$(CONFIG_COLDFIRE) +=3D mcf5206.o mcf_intc.o diff --git a/hw/m68k/bootinfo.h b/hw/m68k/bootinfo.h new file mode 100644 index 0000000000..b04153ce1e --- /dev/null +++ b/hw/m68k/bootinfo.h @@ -0,0 +1,99 @@ +struct bi_record { + uint16_t tag; /* tag ID */ + uint16_t size; /* size of record */ + uint32_t data[0]; /* data */ +}; + +/* machine independent tags */ + +#define BI_LAST 0x0000 /* last record */ +#define BI_MACHTYPE 0x0001 /* machine type (u_long) */ +#define BI_CPUTYPE 0x0002 /* cpu type (u_long) */ +#define BI_FPUTYPE 0x0003 /* fpu type (u_long) */ +#define BI_MMUTYPE 0x0004 /* mmu type (u_long) */ +#define BI_MEMCHUNK 0x0005 /* memory chunk address and size */ + /* (struct mem_info) */ +#define BI_RAMDISK 0x0006 /* ramdisk address and size */ + /* (struct mem_info) */ +#define BI_COMMAND_LINE 0x0007 /* kernel command line parameters */ + /* (string) */ + +/* Macintosh-specific tags (all u_long) */ + +#define BI_MAC_MODEL 0x8000 /* Mac Gestalt ID (model type) */ +#define BI_MAC_VADDR 0x8001 /* Mac video base address */ +#define BI_MAC_VDEPTH 0x8002 /* Mac video depth */ +#define BI_MAC_VROW 0x8003 /* Mac video rowbytes */ +#define BI_MAC_VDIM 0x8004 /* Mac video dimensions */ +#define BI_MAC_VLOGICAL 0x8005 /* Mac video logical base */ +#define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */ +#define BI_MAC_BTIME 0x8007 /* Mac boot time */ +#define BI_MAC_GMTBIAS 0x8008 /* Mac GMT timezone offset */ +#define BI_MAC_MEMSIZE 0x8009 /* Mac RAM size (sanity check) */ +#define BI_MAC_CPUID 0x800a /* Mac CPU type (sanity check) */ +#define BI_MAC_ROMBASE 0x800b /* Mac system ROM base address */ + +/* Macintosh hardware profile data */ + +#define BI_MAC_VIA1BASE 0x8010 /* Mac VIA1 base address (always present) = */ +#define BI_MAC_VIA2BASE 0x8011 /* Mac VIA2 base address (type varies) */ +#define BI_MAC_VIA2TYPE 0x8012 /* Mac VIA2 type (VIA, RBV, OSS) */ +#define BI_MAC_ADBTYPE 0x8013 /* Mac ADB interface type */ +#define BI_MAC_ASCBASE 0x8014 /* Mac Apple Sound Chip base address */ +#define BI_MAC_SCSI5380 0x8015 /* Mac NCR 5380 SCSI (base address, multi)= */ +#define BI_MAC_SCSIDMA 0x8016 /* Mac SCSI DMA (base address) */ +#define BI_MAC_SCSI5396 0x8017 /* Mac NCR 53C96 SCSI (base address, multi= ) */ +#define BI_MAC_IDETYPE 0x8018 /* Mac IDE interface type */ +#define BI_MAC_IDEBASE 0x8019 /* Mac IDE interface base address */ +#define BI_MAC_NUBUS 0x801a /* Mac Nubus type (none, regular, pseudo) = */ +#define BI_MAC_SLOTMASK 0x801b /* Mac Nubus slots present */ +#define BI_MAC_SCCTYPE 0x801c /* Mac SCC serial type (normal, IOP) */ +#define BI_MAC_ETHTYPE 0x801d /* Mac builtin ethernet type (Sonic, MACE = */ +#define BI_MAC_ETHBASE 0x801e /* Mac builtin ethernet base address */ +#define BI_MAC_PMU 0x801f /* Mac power management / poweroff hardwar= e */ +#define BI_MAC_IOP_SWIM 0x8020 /* Mac SWIM floppy IOP */ +#define BI_MAC_IOP_ADB 0x8021 /* Mac ADB IOP */ + +#define BOOTINFO0(as, base, id) \ + do { \ + stw_phys(as, base, id); \ + base +=3D 2; \ + stw_phys(as, base, sizeof(struct bi_record)); \ + base +=3D 2; \ + } while (0) + +#define BOOTINFO1(as, base, id, value) \ + do { \ + stw_phys(as, base, id); \ + base +=3D 2; \ + stw_phys(as, base, sizeof(struct bi_record) + 4); \ + base +=3D 2; \ + stl_phys(as, base, value); \ + base +=3D 4; \ + } while (0) + +#define BOOTINFO2(as, base, id, value1, value2) \ + do { \ + stw_phys(as, base, id); \ + base +=3D 2; \ + stw_phys(as, base, sizeof(struct bi_record) + 8); \ + base +=3D 2; \ + stl_phys(as, base, value1); \ + base +=3D 4; \ + stl_phys(as, base, value2); \ + base +=3D 4; \ + } while (0) + +#define BOOTINFOSTR(as, base, id, string) \ + do { \ + int i; \ + stw_phys(as, base, id); \ + base +=3D 2; \ + stw_phys(as, base, (sizeof(struct bi_record) + strlen(string) + 2)= & ~1); \ + base +=3D 2; \ + for (i =3D 0; string[i]; i++) { \ + stb_phys(as, base++, string[i]); \ + } \ + stb_phys(as, base++, 0); \ + base =3D (parameters_base + 1) & ~1; \ + } while (0) diff --git a/hw/m68k/mac.c b/hw/m68k/mac.c new file mode 100644 index 0000000000..d573339e66 --- /dev/null +++ b/hw/m68k/mac.c @@ -0,0 +1,384 @@ +/* + * QEMU Motorla 680x0 Macintosh hardware System Emulator + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "sysemu/sysemu.h" +#include "cpu.h" +#include "hw/hw.h" +#include "hw/boards.h" +#include "elf.h" +#include "hw/loader.h" +#include "hw/display/framebuffer.h" +#include "ui/console.h" +#include "exec/address-spaces.h" +#include "hw/char/escc.h" +#include "hw/sysbus.h" +#include "hw/scsi/esp.h" +#include "bootinfo.h" +#include "hw/misc/mac_via.h" +#include "hw/input/adb.h" +#include "hw/audio/asc.h" +#include "hw/nubus/mac.h" +#include "net/net.h" +#include "qapi/error.h" + +#define MACROM_ADDR 0x40000000 +#define MACROM_SIZE 0x00100000 + +/* + * .ident =3D MAC_MODEL_Q800, + * .name =3D "Quadra 800", + * .adb_type =3D MAC_ADB_II, + * .via_type =3D MAC_VIA_QUADRA, + * .scsi_type =3D MAC_SCSI_QUADRA, + * .scc_type =3D MAC_SCC_QUADRA, + * .ether_type =3D MAC_ETHER_SONIC, + * .nubus_type =3D MAC_NUBUS + */ + +#define MACROM_FILENAME "MacROM.bin" + +#define Q800_MACHINE_ID 35 +#define Q800_CPU_ID (1 << 2) +#define Q800_FPU_ID (1 << 2) +#define Q800_MMU_ID (1 << 2) + +#define MACH_MAC 3 +#define Q800_MAC_CPU_ID 2 + +#define VIA_BASE 0x50f00000 +#define SONIC_PROM_BASE 0x50f08000 +#define SONIC_BASE 0x50f0a000 +#define SCC_BASE 0x50f0c020 +#define ESP_BASE 0x50f10000 +#define ESP_PDMA 0x50f10100 +#define ASC_BASE 0x50F14000 +#define SWIM_BASE 0x50F1E000 +#define NUBUS_SUPER_SLOT_BASE 0x60000000 +#define NUBUS_SLOT_BASE 0xf0000000 + +/* the video base, whereas it a Nubus address, + * is needed by the kernel to have early display and + * thus provided by the bootloader + */ +#define VIDEO_BASE 0xf9001000 + +#define MAC_CLOCK 3686418 + +typedef struct { + M68kCPU *cpu; + uint8_t ipr; +} q800_glue_state_t; + +static void q800_glue_set_irq(void *opaque, int irq, int level) +{ + int i; + + q800_glue_state_t *s =3D opaque; + + if (level) { + s->ipr |=3D 1 << irq; + } else { + s->ipr &=3D ~(1 << irq); + } + + for (i =3D 7; i >=3D 0; i--) { + if ((s->ipr >> i) & 1) { + m68k_set_irq_level(s->cpu, i + 1, i + 25); + return; + } + } + m68k_set_irq_level(s->cpu, 0, 0); +} + +static void main_cpu_reset(void *opaque) +{ + M68kCPU *cpu =3D opaque; + CPUState *cs =3D CPU(cpu); + + cpu_reset(cs); + cpu->env.aregs[7] =3D ldl_phys(cs->as, 0); + cpu->env.pc =3D ldl_phys(cs->as, 4); +} + +static void q800_init(MachineState *machine) +{ + M68kCPU *cpu =3D NULL; + int linux_boot; + int32_t kernel_size; + uint64_t elf_entry; + char *filename; + int bios_size; + ram_addr_t initrd_base; + int32_t initrd_size; + MemoryRegion *rom; + MemoryRegion *ram; + ram_addr_t ram_size =3D machine->ram_size; + const char *kernel_filename =3D machine->kernel_filename; + const char *initrd_filename =3D machine->initrd_filename; + const char *kernel_cmdline =3D machine->kernel_cmdline; + q800_glue_state_t *s; + qemu_irq *pic; + hwaddr parameters_base; + CPUState *cs; + DeviceState *dev; + DeviceState *via_dev; + SysBusDevice *sysbus; + BusState *adb_bus; + qemu_irq esp_reset_irq, esp_dma_enable; + NubusBus *nubus; + NubusDevice *nubus_dev; + DriveInfo *fds[2]; + + linux_boot =3D (kernel_filename !=3D NULL); + + /* init CPUs */ + cpu =3D M68K_CPU(cpu_create(machine->cpu_type)); + if (!cpu) { + hw_error("qemu: unable to find m68k CPU definition\n"); + exit(1); + } + qemu_register_reset(main_cpu_reset, cpu); + + ram =3D g_malloc(sizeof(*ram)); + memory_region_init_ram(ram, NULL, "m68k_mac.ram", ram_size, &error_abo= rt); + memory_region_add_subregion(get_system_memory(), 0, ram); + + /* Glue */ + + s =3D (q800_glue_state_t *)g_malloc0(sizeof(q800_glue_state_t)); + s->cpu =3D cpu; + pic =3D qemu_allocate_irqs(q800_glue_set_irq, s, 6); + + /* VIA */ + + via_dev =3D qdev_create(NULL, TYPE_MAC_VIA); + qdev_init_nofail(via_dev); + sysbus =3D SYS_BUS_DEVICE(via_dev); + sysbus_mmio_map(sysbus, 0, VIA_BASE); + sysbus_connect_irq(sysbus, 0, pic[0]); + sysbus_connect_irq(sysbus, 1, pic[1]); + + adb_bus =3D qdev_get_child_bus(via_dev, "adb.0"); + dev =3D qdev_create(adb_bus, TYPE_ADB_KEYBOARD); + qdev_init_nofail(dev); + dev =3D qdev_create(adb_bus, TYPE_ADB_MOUSE); + qdev_init_nofail(dev); + + /* MACSONIC */ + + if (nb_nics !=3D 1) { + hw_error("Q800 needs a dp83932 ethernet interfaces"); + } + if (!nd_table[0].model) { + nd_table[0].model =3D g_strdup("dp83932"); + } + if (strcmp(nd_table[0].model, "dp83932") !=3D 0) { + hw_error("Q800 needs a dp83932 ethernet interfaces"); + } else { + /* MacSonic driver needs an Apple MAC address + * Valid prefix are: + * 00:05:02 Apple + * 00:80:19 Dayna Communications, Inc. + * 00:A0:40 Apple + * 08:00:07 Apple + * (Q800 use the last one) + */ + nd_table[0].macaddr.a[0] =3D 0x08; + nd_table[0].macaddr.a[1] =3D 0x00; + nd_table[0].macaddr.a[2] =3D 0x07; + } + qemu_check_nic_model(&nd_table[0], "dp83932"); + dev =3D qdev_create(NULL, "dp8393x"); + qdev_set_nic_properties(dev, &nd_table[0]); + qdev_prop_set_uint8(dev, "it_shift", 2); + qdev_prop_set_bit(dev, "big_endian", true); + qdev_prop_set_ptr(dev, "dma_mr", get_system_memory()); + qdev_init_nofail(dev); + sysbus =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(sysbus, 0, SONIC_BASE); + sysbus_mmio_map(sysbus, 1, SONIC_PROM_BASE); + sysbus_connect_irq(sysbus, 0, pic[2]); + + /* SCC */ + + dev =3D qdev_create(NULL, "escc"); + qdev_prop_set_uint32(dev, "disabled", 0); + qdev_prop_set_uint32(dev, "frequency", MAC_CLOCK); + qdev_prop_set_uint32(dev, "it_shift", 1); + qdev_prop_set_bit(dev, "bit_swap", true); + qdev_prop_set_chr(dev, "chrA", serial_hd(0)); + qdev_prop_set_chr(dev, "chrB", serial_hd(1)); + qdev_prop_set_uint32(dev, "chnBtype", 0); + qdev_prop_set_uint32(dev, "chnAtype", 0); + qdev_init_nofail(dev); + sysbus =3D SYS_BUS_DEVICE(dev); + sysbus_connect_irq(sysbus, 0, pic[3]); + sysbus_connect_irq(sysbus, 1, pic[3]); + sysbus_mmio_map(sysbus, 0, SCC_BASE); + + /* SCSI */ + + esp_init_pdma(ESP_BASE, 4, ESP_PDMA, + qdev_get_gpio_in(via_dev, VIA2_IRQ_SCSI_BIT), + qdev_get_gpio_in(via_dev, VIA2_IRQ_SCSI_DATA_BIT), + &esp_reset_irq, &esp_dma_enable); + + /* Apple Sound Chip */ + + dev =3D qdev_create(NULL, "apple-sound-chip"); + qdev_prop_set_uint8(dev, "asctype", ASC_TYPE_ASC); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ASC_BASE); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, + qdev_get_gpio_in(via_dev, VIA2_IRQ_ASC_BIT)); + + /* SWIM floppy controller */ + + if (drive_get_max_bus(IF_FLOPPY) >=3D 2) { + fprintf(stderr, "qemu: too many floppy drives\n"); + exit(1); + } + fds[0] =3D drive_get(IF_FLOPPY, 0, 0); + fds[1] =3D drive_get(IF_FLOPPY, 0, 1); + + dev =3D qdev_create(NULL, "sysbus-swim"); + if (fds[0]) { + qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]), + &error_fatal); + } + if (fds[1]) { + qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]), + &error_fatal); + } + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SWIM_BASE); + + /* NuBus */ + + nubus =3D nubus_mac_new(NUBUS_SUPER_SLOT_BASE, NUBUS_SLOT_BASE); + + /* framebuffer in nubus slot #9 */ + + nubus_dev =3D nubus_create(nubus, "nubus-macfb"); + qdev_prop_set_uint32(&nubus_dev->qdev, "width", graphic_width); + qdev_prop_set_uint32(&nubus_dev->qdev, "height", graphic_height); + qdev_prop_set_uint8(&nubus_dev->qdev, "depth", graphic_depth); + qdev_init_nofail(&nubus_dev->qdev); + + cs =3D CPU(cpu); + if (linux_boot) { + uint64_t high; + kernel_size =3D load_elf(kernel_filename, NULL, NULL, + &elf_entry, NULL, &high, 1, + EM_68K, 0, 0); + if (kernel_size < 0) { + hw_error("qemu: could not load kernel '%s'\n", + kernel_filename); + exit(1); + } + stl_phys(cs->as, 4, elf_entry); /* reset initial PC */ + parameters_base =3D (high + 1) & ~1; + + BOOTINFO1(cs->as, parameters_base, BI_MACHTYPE, MACH_MAC); + BOOTINFO1(cs->as, parameters_base, BI_FPUTYPE, Q800_FPU_ID); + BOOTINFO1(cs->as, parameters_base, BI_MMUTYPE, Q800_MMU_ID); + BOOTINFO1(cs->as, parameters_base, BI_CPUTYPE, Q800_CPU_ID); + BOOTINFO1(cs->as, parameters_base, BI_MAC_CPUID, Q800_MAC_CPU_ID); + BOOTINFO1(cs->as, parameters_base, BI_MAC_MODEL, Q800_MACHINE_ID); + BOOTINFO1(cs->as, parameters_base, + BI_MAC_MEMSIZE, ram_size >> 20); /* in MB */ + BOOTINFO2(cs->as, parameters_base, BI_MEMCHUNK, 0, ram_size); + BOOTINFO1(cs->as, parameters_base, BI_MAC_VADDR, VIDEO_BASE); + BOOTINFO1(cs->as, parameters_base, BI_MAC_VDEPTH, graphic_depth); + BOOTINFO1(cs->as, parameters_base, BI_MAC_VDIM, + (graphic_height << 16) | graphic_width); + BOOTINFO1(cs->as, parameters_base, BI_MAC_VROW, + (graphic_width * graphic_depth + 7) / 8); + BOOTINFO1(cs->as, parameters_base, BI_MAC_SCCBASE, SCC_BASE); + + if (kernel_cmdline) { + BOOTINFOSTR(cs->as, parameters_base, BI_COMMAND_LINE, + kernel_cmdline); + } + + /* load initrd */ + if (initrd_filename) { + initrd_size =3D get_image_size(initrd_filename); + if (initrd_size < 0) { + hw_error("qemu: could not load initial ram disk '%s'\n", + initrd_filename); + exit(1); + } + + initrd_base =3D (ram_size - initrd_size) & TARGET_PAGE_MASK; + load_image_targphys(initrd_filename, initrd_base, + ram_size - initrd_base); + BOOTINFO2(cs->as, parameters_base, BI_RAMDISK, initrd_base, + initrd_size); + } else { + initrd_base =3D 0; + initrd_size =3D 0; + } + BOOTINFO0(cs->as, parameters_base, BI_LAST); + } else { + uint8_t *ptr; + /* allocate and load BIOS */ + rom =3D g_malloc(sizeof(*rom)); + memory_region_init_ram(rom, NULL, "m68k_mac.rom", MACROM_SIZE, + &error_abort); + if (bios_name =3D=3D NULL) { + bios_name =3D MACROM_FILENAME; + } + filename =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + memory_region_set_readonly(rom, true); + memory_region_add_subregion(get_system_memory(), MACROM_ADDR, rom); + + /* Load MacROM binary */ + if (filename) { + bios_size =3D load_image_targphys(filename, MACROM_ADDR, MACRO= M_SIZE); + g_free(filename); + } else { + bios_size =3D -1; + } + if (bios_size < 0 || bios_size > MACROM_SIZE) { + hw_error("qemu: could not load MacROM '%s'\n", bios_name); + exit(1); + } + ptr =3D rom_ptr(MACROM_ADDR); + stl_phys(cs->as, 0, ldl_p(ptr)); /* reset initial SP */ + stl_phys(cs->as, 4, + MACROM_ADDR + ldl_p(ptr + 4)); /* reset initial PC */ + } +} + +static void q800_machine_init(MachineClass *mc) +{ + mc->desc =3D "Macintosh Quadra 800"; + mc->init =3D q800_init; + mc->default_cpu_type =3D M68K_CPU_TYPE_NAME("m68040"); + mc->max_cpus =3D 1; + mc->is_default =3D 0; + mc->block_default_type =3D IF_SCSI; +} + +DEFINE_MACHINE("q800", q800_machine_init) diff --git a/hw/nubus/nubus-device.c b/hw/nubus/nubus-device.c index 0c8023d46a..7fd1e03909 100644 --- a/hw/nubus/nubus-device.c +++ b/hw/nubus/nubus-device.c @@ -238,22 +238,9 @@ static void nubus_device_init(Object *obj) { } =20 -static int nubus_qdev_init(DeviceState *qdev) -{ - NubusDevice *dev =3D NUBUS_DEVICE(qdev); - NubusDeviceClass *klass =3D NUBUS_DEVICE_GET_CLASS(dev); - - if (klass->init) { - return klass->init(dev); - } - - return 0; -} - static void nubus_device_class_init(ObjectClass *klass, void *data) { DeviceClass *k =3D DEVICE_CLASS(klass); - k->init =3D nubus_qdev_init; k->bus_type =3D TYPE_NUBUS_BUS; } =20 diff --git a/tests/qom-test.c b/tests/qom-test.c index e6f712cbd3..373699fda4 100644 --- a/tests/qom-test.c +++ b/tests/qom-test.c @@ -19,12 +19,17 @@ static const char *blacklist_x86[] =3D { "xenfv", "xenpv", NULL }; =20 +static const char *blacklist_m68k[] =3D { + "q800", NULL +}; + static const struct { const char *arch; const char **machine; } blacklists[] =3D { { "i386", blacklist_x86 }, { "x86_64", blacklist_x86 }, + { "m68k", blacklist_m68k }, }; =20 static bool is_blacklisted(const char *arch, const char *mach) diff --git a/tests/test-hmp.c b/tests/test-hmp.c index 5352c9c088..f3b79d5bdf 100644 --- a/tests/test-hmp.c +++ b/tests/test-hmp.c @@ -139,7 +139,8 @@ static void add_machine_test_case(const char *mname) char *path; =20 /* Ignore blacklisted machines that have known problems */ - if (!strcmp("xenfv", mname) || !strcmp("xenpv", mname)) { + if (!strcmp("xenfv", mname) || !strcmp("xenpv", mname) || + !strcmp("q800", mname)) { return; } =20 --=20 2.14.4 From nobody Mon Apr 29 04:03:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152848855879549.80009611267644; Fri, 8 Jun 2018 13:09:18 -0700 (PDT) Received: from localhost ([::1]:37975 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNhF-0000iy-Ti for importer@patchew.org; Fri, 08 Jun 2018 16:09:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47953) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNf0-0007gj-Cg for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:07:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fRNez-0006sc-ES for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:06:58 -0400 Received: from mout.kundenserver.de ([212.227.126.133]:35181) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fRNet-0006ky-SV; Fri, 08 Jun 2018 16:06:52 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue002 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MHQA7-1fVUOm409b-00E9a9; Fri, 08 Jun 2018 22:06:28 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 8 Jun 2018 22:05:55 +0200 Message-Id: <20180608200558.386-11-laurent@vivier.eu> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180608200558.386-1-laurent@vivier.eu> References: <20180608200558.386-1-laurent@vivier.eu> X-Provags-ID: V03:K1:186I45Z5Jbinba6ey0ll6pm6fpqE3mPTJi8c6rS8M07MGUKI6Fh KJUMLGaZUynYNm+wNyVtd/Pj4R0sng5dm9t4/2L+nqJr8Ibdle6hWKVD1sytUe4pl9/kx7O UXEF4y7mWCuM8ErS8h4UViGG2dKzwZgkskBlMNehIhAMfvWRFCFWvBNZR39Qruv7rdhuj7m 9FYyF2zUYo3Bbs0a1Ow8w== X-UI-Out-Filterresults: notjunk:1;V01:K0:0dCWD/fZGtc=:wD6TP5NzJ6QelK6zvOEWTk mrKXXkuRxZNE9PLtfcBfoYZEFgNdAiyLcj0IlT+MsIHgVLtzLB7DzmivR/8qRlcdQEbQau281 NOOKHsVW8AaoPAE/7cGrQv7cOkTtu3E9kHQ6D0aa5YuPzE96irqtzJK0ZFTyEV1LQSXBIvhHc Qzv83LZTrT46QaR4AHvK8IwuJJ7D2WgwVxZBNJxkCRnFPKbcoUB5FDp6FNtUsIl+9HGGP0Z7e QFVil1gYgcieZ3pUPVHy7LG2bRYOnaQfYPokNrxCv+voIha95uGLsSkp5XgGghl9LBo1qJPdW wRu+L3Fb34+MbV1IYSve3NlOhl9g62TUVzGpUDgXNcqohk3RN3KF+OfhXX0gNycGF6HHyXLol BgGx+vG6NfBK0AM/7maaB0dRKu11UZ+Z4gAHOgyng0Ug4KrVy8+ZIbn63lC4pT7RL0Upcs7r9 vcQFV7vsxe5vOjfmiKzziAPKIuE002Xje1Bu9FP4xfab6gNnmNkMKZhkVJB+HKRUYp4FIR4BV yFJeZq0gaHgV3mDe4j+EuEkndHRjZz5T6bbDqx+kRW716SMU4M+2jjg+x1rholFNX2N4m6QN7 yZEPfsY9B+T3Qfo5S9NUQ727tx0GtynmP8W0BCY1S0G+v4/puZcaHKuivCuV9xpgDLtycnlFr K9DTnHBO1r95ezgEK51FSNp9xO96m471bwKgwZMbYeujLy85gUlIHxNGy8Y7jL2XtWS0= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.133 Subject: [Qemu-devel] [RFC 10/13] dp8393x: fix dp8393x_receive X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Jason Wang , "Dr. David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , Yongbok Kim , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" address_space_rw() access size must be multiplied by width. dp8393x_receive() must return the number of bytes read, not the length of the last memory access. Signed-off-by: Laurent Vivier --- hw/net/dp8393x.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index f2d2ce344c..ef5f1eb94f 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -808,9 +808,11 @@ static ssize_t dp8393x_receive(NetClientState *nc, con= st uint8_t * buf, /* EOL detected */ s->regs[SONIC_ISR] |=3D SONIC_ISR_RDE; } else { + size =3D sizeof(uint16_t) * width; data[0 * width] =3D 0; /* in_use */ - address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 6 * = width, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, sizeof(uint16_t), 1); + address_space_rw(&s->as, + dp8393x_crda(s) + sizeof(uint16_t) * 6 * width, + MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1); s->regs[SONIC_CRDA] =3D s->regs[SONIC_LLFA]; s->regs[SONIC_ISR] |=3D SONIC_ISR_PKTRX; s->regs[SONIC_RSC] =3D (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[= SONIC_RSC] & 0x00ff) + 1) & 0x00ff); @@ -824,7 +826,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, cons= t uint8_t * buf, /* Done */ dp8393x_update_irq(s); =20 - return size; + return rx_len; } =20 static void dp8393x_reset(DeviceState *dev) --=20 2.14.4 From nobody Mon Apr 29 04:03:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528489305820799.1340600518181; Fri, 8 Jun 2018 13:21:45 -0700 (PDT) Received: from localhost ([::1]:38060 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNtI-0002TK-Vu for importer@patchew.org; Fri, 08 Jun 2018 16:21:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47922) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNez-0007fk-4e for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:07:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fRNet-0006lQ-Eg for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:06:57 -0400 Received: from mout.kundenserver.de ([212.227.126.130]:51413) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fRNet-0006ku-5A; Fri, 08 Jun 2018 16:06:51 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue002 [212.227.15.167]) with ESMTPSA (Nemesis) id 0Lcsfw-1g9CnV1F1k-00iFT4; Fri, 08 Jun 2018 22:06:29 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 8 Jun 2018 22:05:56 +0200 Message-Id: <20180608200558.386-12-laurent@vivier.eu> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180608200558.386-1-laurent@vivier.eu> References: <20180608200558.386-1-laurent@vivier.eu> X-Provags-ID: V03:K1:pA7vUGbOlaor8O4X7v5LKfnNjG7+oy73Ydc55DGmq5MuQhNaMID jU5gOu4ETFwuPZFFcDzKZ9eq3q0uc5BDVWK9boxNKgJOT4hnYovc7bbmkO13EwNcRGu1SdF 3UVXHYykcSwPEwFP1omfyzy3b9xoO+yidgZH9nou7AfRYsnrnQKlZohhjFXhq2+pFAx33ej pQlspyV43EPfunEKaigTw== X-UI-Out-Filterresults: notjunk:1;V01:K0:pe9tuxG2zRA=:9CXKo5vmTqPMadMUINNF0q C3KOsauR6WWdyN6YdxXAS9lBNZgBGFKQTroccACZuqca7iPlZr27296vd89H/Yr8uZWQABPF4 Jqmg09Dx3O6nuAYtYzxH5XPB3RpYfOfSeOIqMShS83yJR4BII1z0Z/j9585SXtywHBhYjZmfo 2tmMYgh2oudKe7Dngw66Qw3YB+CXIr7QB7gFVlrjiS2mmdhLfy4eMpk0h8+nDDy4E60udGt0l BPQ+vhRFylmtUJncOYXsN7CsmpnqU2LHTNDKQU2MjEpN1DjVKx2tE0abOtvwR2InEJDZVTnEu z17frSnjeChAj98n4aIFXD91EqDrHiU+cMtJihcWkAEYO1mdm6dh1bdJHHvOl0gFfTmmuyxlO sY12xSwEJhn7hiNAT9YPN1g/oFj55j3vc94A7RoVy+c1JzI1Sx9vf0ii1G/eClVaRqMjuIgU8 0TP/I6ZoeDAodo5/wVdjCg6UWiGgF3aMKjVvM1LQwadtQZnduBYK52mkFax85RgN4HT7BDuxO BmERsBiadpiFxWAdl0LQKrMWka0PFfYfqS8+lTOqfx/qtigb4n+1wzIteG0msrBkHK5uRofB8 Ttqi2dH+qySRsGJGv//uSxnNQGhbjAFiQsXM9RJw1+7AFPmutnqk0gfIIwNAGv9PsKUSAbdzV UAGLuif7vFQ4RID7uf+WYPZDYOjGdVh3/4Y0w6zUMrqHmGo/KTWnMuWleAs3Nf9Y53t0= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.130 Subject: [Qemu-devel] [RFC 11/13] dp8393x: manage big endian bus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Jason Wang , "Dr. David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , Yongbok Kim , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is needed by Quadra 800, this card can run on little-endian or big-endian bus. Signed-off-by: Laurent Vivier Tested-by: Herv=C3=A9 Poussineau --- hw/net/dp8393x.c | 101 ++++++++++++++++++++++++++++++++++++++-------------= ---- 1 file changed, 70 insertions(+), 31 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index ef5f1eb94f..5061474e6b 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -150,6 +150,7 @@ typedef struct dp8393xState { =20 /* Hardware */ uint8_t it_shift; + bool big_endian; qemu_irq irq; #ifdef DEBUG_SONIC int irq_level; @@ -174,6 +175,12 @@ typedef struct dp8393xState { AddressSpace as; } dp8393xState; =20 +#ifdef HOST_WORDS_BIGENDIAN +static const bool host_big_endian =3D true; +#else +static const bool host_big_endian =3D false; +#endif + /* Accessor functions for values which are formed by * concatenating two 16 bit device registers. By putting these * in their own functions with a uint32_t return type we avoid the @@ -220,6 +227,36 @@ static uint32_t dp8393x_wt(dp8393xState *s) return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; } =20 +static uint16_t dp8393x_get(dp8393xState *s, int width, uint16_t *base, + int offset) +{ + uint16_t val; + + if (s->big_endian) { + val =3D base[offset * width + width - 1]; + } else { + val =3D base[offset * width]; + } + if (s->big_endian !=3D host_big_endian) { + val =3D bswap16(val); + } + return val; +} + +static void dp8393x_put(dp8393xState *s, int width, uint16_t *base, int of= fset, + uint16_t val) +{ + if (s->big_endian !=3D host_big_endian) { + val =3D bswap16(val); + } + + if (s->big_endian) { + base[offset * width + width - 1] =3D val; + } else { + base[offset * width] =3D val; + } +} + static void dp8393x_update_irq(dp8393xState *s) { int level =3D (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0; @@ -251,12 +288,12 @@ static void dp8393x_do_load_cam(dp8393xState *s) /* Fill current entry */ address_space_rw(&s->as, dp8393x_cdp(s), MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->cam[index][0] =3D data[1 * width] & 0xff; - s->cam[index][1] =3D data[1 * width] >> 8; - s->cam[index][2] =3D data[2 * width] & 0xff; - s->cam[index][3] =3D data[2 * width] >> 8; - s->cam[index][4] =3D data[3 * width] & 0xff; - s->cam[index][5] =3D data[3 * width] >> 8; + s->cam[index][0] =3D dp8393x_get(s, width, data, 1) & 0xff; + s->cam[index][1] =3D dp8393x_get(s, width, data, 1) >> 8; + s->cam[index][2] =3D dp8393x_get(s, width, data, 2) & 0xff; + s->cam[index][3] =3D dp8393x_get(s, width, data, 2) >> 8; + s->cam[index][4] =3D dp8393x_get(s, width, data, 3) & 0xff; + s->cam[index][5] =3D dp8393x_get(s, width, data, 3) >> 8; DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index, s->cam[index][0], s->cam[index][1], s->cam[index][2], s->cam[index][3], s->cam[index][4], s->cam[index][5]); @@ -269,7 +306,7 @@ static void dp8393x_do_load_cam(dp8393xState *s) /* Read CAM enable */ address_space_rw(&s->as, dp8393x_cdp(s), MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->regs[SONIC_CE] =3D data[0 * width]; + s->regs[SONIC_CE] =3D dp8393x_get(s, width, data, 0); DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); =20 /* Done */ @@ -290,10 +327,10 @@ static void dp8393x_do_read_rra(dp8393xState *s) MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); =20 /* Update SONIC registers */ - s->regs[SONIC_CRBA0] =3D data[0 * width]; - s->regs[SONIC_CRBA1] =3D data[1 * width]; - s->regs[SONIC_RBWC0] =3D data[2 * width]; - s->regs[SONIC_RBWC1] =3D data[3 * width]; + s->regs[SONIC_CRBA0] =3D dp8393x_get(s, width, data, 0); + s->regs[SONIC_CRBA1] =3D dp8393x_get(s, width, data, 1); + s->regs[SONIC_RBWC0] =3D dp8393x_get(s, width, data, 2); + s->regs[SONIC_RBWC1] =3D dp8393x_get(s, width, data, 3); DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n", s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); @@ -408,12 +445,12 @@ static void dp8393x_do_transmit_packets(dp8393xState = *s) tx_len =3D 0; =20 /* Update registers */ - s->regs[SONIC_TCR] =3D data[0 * width] & 0xf000; - s->regs[SONIC_TPS] =3D data[1 * width]; - s->regs[SONIC_TFC] =3D data[2 * width]; - s->regs[SONIC_TSA0] =3D data[3 * width]; - s->regs[SONIC_TSA1] =3D data[4 * width]; - s->regs[SONIC_TFS] =3D data[5 * width]; + s->regs[SONIC_TCR] =3D dp8393x_get(s, width, data, 0) & 0xf000; + s->regs[SONIC_TPS] =3D dp8393x_get(s, width, data, 1); + s->regs[SONIC_TFC] =3D dp8393x_get(s, width, data, 2); + s->regs[SONIC_TSA0] =3D dp8393x_get(s, width, data, 3); + s->regs[SONIC_TSA1] =3D dp8393x_get(s, width, data, 4); + s->regs[SONIC_TFS] =3D dp8393x_get(s, width, data, 5); =20 /* Handle programmable interrupt */ if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) { @@ -439,9 +476,9 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) address_space_rw(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * wid= th, MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->regs[SONIC_TSA0] =3D data[0 * width]; - s->regs[SONIC_TSA1] =3D data[1 * width]; - s->regs[SONIC_TFS] =3D data[2 * width]; + s->regs[SONIC_TSA0] =3D dp8393x_get(s, width, data, 0); + s->regs[SONIC_TSA1] =3D dp8393x_get(s, width, data, 1); + s->regs[SONIC_TFS] =3D dp8393x_get(s, width, data, 2); } } =20 @@ -468,7 +505,8 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) s->regs[SONIC_TCR] |=3D SONIC_TCR_PTX; =20 /* Write status */ - data[0 * width] =3D s->regs[SONIC_TCR] & 0x0fff; /* status */ + dp8393x_put(s, width, data, 0, + s->regs[SONIC_TCR] & 0x0fff); /* status */ size =3D sizeof(uint16_t) * width; address_space_rw(&s->as, dp8393x_ttda(s), @@ -482,8 +520,8 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) sizeof(uint16_t) * (4 + 3 * s->regs[SONIC_TFC]) * width, MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->regs[SONIC_CTDA] =3D data[0 * width] & ~0x1; - if (data[0 * width] & 0x1) { + s->regs[SONIC_CTDA] =3D dp8393x_get(s, width, data, 0) & ~0x1; + if (dp8393x_get(s, width, data, 0) & 0x1) { /* EOL detected */ break; } @@ -746,7 +784,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, cons= t uint8_t * buf, address =3D dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - if (data[0 * width] & 0x1) { + if (dp8393x_get(s, width, data, 0) & 0x1) { /* Still EOL ; stop reception */ return -1; } else { @@ -790,11 +828,11 @@ static ssize_t dp8393x_receive(NetClientState *nc, co= nst uint8_t * buf, =20 /* Write status to memory */ DPRINTF("Write status at %08x\n", dp8393x_crda(s)); - data[0 * width] =3D s->regs[SONIC_RCR]; /* status */ - data[1 * width] =3D rx_len; /* byte count */ - data[2 * width] =3D s->regs[SONIC_TRBA0]; /* pkt_ptr0 */ - data[3 * width] =3D s->regs[SONIC_TRBA1]; /* pkt_ptr1 */ - data[4 * width] =3D s->regs[SONIC_RSC]; /* seq_no */ + dp8393x_put(s, width, data, 0, s->regs[SONIC_RCR]); /* status */ + dp8393x_put(s, width, data, 1, rx_len); /* byte count */ + dp8393x_put(s, width, data, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */ + dp8393x_put(s, width, data, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */ + dp8393x_put(s, width, data, 4, s->regs[SONIC_RSC]); /* seq_no */ size =3D sizeof(uint16_t) * 5 * width; address_space_rw(&s->as, dp8393x_crda(s), MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1); @@ -803,13 +841,13 @@ static ssize_t dp8393x_receive(NetClientState *nc, co= nst uint8_t * buf, size =3D sizeof(uint16_t) * width; address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * widt= h, MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->regs[SONIC_LLFA] =3D data[0 * width]; + s->regs[SONIC_LLFA] =3D dp8393x_get(s, width, data, 0); if (s->regs[SONIC_LLFA] & 0x1) { /* EOL detected */ s->regs[SONIC_ISR] |=3D SONIC_ISR_RDE; } else { size =3D sizeof(uint16_t) * width; - data[0 * width] =3D 0; /* in_use */ + dp8393x_put(s, width, data, 0, 0); /* in_use */ address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 6 * width, MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1); @@ -923,6 +961,7 @@ static Property dp8393x_properties[] =3D { DEFINE_NIC_PROPERTIES(dp8393xState, conf), DEFINE_PROP_PTR("dma_mr", dp8393xState, dma_mr), DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0), + DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.14.4 From nobody Mon Apr 29 04:03:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528488867628782.3105102579799; Fri, 8 Jun 2018 13:14:27 -0700 (PDT) Received: from localhost ([::1]:38009 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNmA-0005Id-Bb for importer@patchew.org; Fri, 08 Jun 2018 16:14:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48031) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNf4-0007lb-Mg for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:07:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fRNf2-0006w8-QK for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:07:02 -0400 Received: from mout.kundenserver.de ([212.227.126.130]:36341) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fRNev-0006nE-WF; Fri, 08 Jun 2018 16:06:54 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue002 [212.227.15.167]) with ESMTPSA (Nemesis) id 0McvJJ-1fjBUF34sr-00Hsud; Fri, 08 Jun 2018 22:06:31 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 8 Jun 2018 22:05:57 +0200 Message-Id: <20180608200558.386-13-laurent@vivier.eu> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180608200558.386-1-laurent@vivier.eu> References: <20180608200558.386-1-laurent@vivier.eu> X-Provags-ID: V03:K1:+yHlMMJompKVyujJut8Yzs+xbs1LwW0sqIbwqMYoUp0zIRVFkmU LSbJI+scKaFxUOT1OS3Xjeyw4Y/crFvl/051driKsapZjbN9VJ3u9/ZaqFJNySja3W/ljKS NPyls50ZQ6Vol20+pZp7xo0uUMEa/OPa4RAfcUamzp95nIaWSa42gxKe0rab4UVF2pR3Uhv XTAldFtW3CzTqPEYQj16Q== X-UI-Out-Filterresults: notjunk:1;V01:K0:OEzOODHj3N0=:AVXNVzf41HkXIezLw04ALw 8kdJCiyHVIgwR3IkgPJU4oiEBMYTEouSmfenxgDRUu3B2Tgp2VqPeFB0ukA7YC0TxB/j88uBr 2iIajHmKawRbBNVAwyGtYMJYJqyCfEyHHV5NErIcJhl/wO/8mRuvoLioJqrAXeXu+PjQa1EeV YWdFxqwJDczX64qgF7Izumnr9OZgknslGCILh08MyrNFW/p7sG6WIDgAM1qtSe05nc+v0TmEp OsA/sRMU7Ste3qdl1u14c6zC3TDfUp9No7EikdBISL44stMslCfAYX232Ww7jPBGU9zJwe4Ru tUv0ZtaBbGvBcYA1Rt0Km2kHwzeCI/N0s/L8MNqk69npsWiCT05L+V9GMrjoJ7Y29YR4tEw8r X4HwdXM5ZnTu4oBeKYgUE2W8tD0dy+mn3uP3BLr6GG42pp2eXreoDAINIP5cWXizbTlZ2aSK7 3bHtOeK28jqvLoLDkOFmx9HuyAoamilNeDLhFva7CMq2UIllOwEhnp/9KR0QGeaNvyZQ/Gqde 4382WKD2BgmwMr0iiNUEcdC0A1QnDBO7C0AKdLQROnmLnIp26y/PBJ1CuDDeVyxsMxsi/Bvvy ZIKRXMKKRJpsGQKRkhQ8DRRd+aVfVsBp1PsX2Y0e9qdzkC7ijMu2KdqoouSCCxrLKx1fq7/Sa 8I8awm5XbfSFoIDaQro2nlvAMLumxId7gBCRabb5tS2B6e8ucm1OpVXwb9oApnDpAMhA= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.130 Subject: [Qemu-devel] [RFC 12/13] dp8393x: put DMA temp buffer in the state, not in the stack X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Jason Wang , "Dr. David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , Yongbok Kim , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" It's only 32 bytes, and this simplifies the dp8393x_get()/ dp8393x_put() interface. Signed-off-by: Laurent Vivier Tested-by: Herv=C3=A9 Poussineau --- hw/net/dp8393x.c | 107 ++++++++++++++++++++++++++-------------------------= ---- 1 file changed, 51 insertions(+), 56 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index 5061474e6b..40e5f8257b 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -168,6 +168,7 @@ typedef struct dp8393xState { =20 /* Temporaries */ uint8_t tx_buffer[0x10000]; + uint16_t data[16]; int loopback_packet; =20 /* Memory access */ @@ -227,15 +228,14 @@ static uint32_t dp8393x_wt(dp8393xState *s) return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; } =20 -static uint16_t dp8393x_get(dp8393xState *s, int width, uint16_t *base, - int offset) +static uint16_t dp8393x_get(dp8393xState *s, int width, int offset) { uint16_t val; =20 if (s->big_endian) { - val =3D base[offset * width + width - 1]; + val =3D s->data[offset * width + width - 1]; } else { - val =3D base[offset * width]; + val =3D s->data[offset * width]; } if (s->big_endian !=3D host_big_endian) { val =3D bswap16(val); @@ -243,7 +243,7 @@ static uint16_t dp8393x_get(dp8393xState *s, int width,= uint16_t *base, return val; } =20 -static void dp8393x_put(dp8393xState *s, int width, uint16_t *base, int of= fset, +static void dp8393x_put(dp8393xState *s, int width, int offset, uint16_t val) { if (s->big_endian !=3D host_big_endian) { @@ -251,9 +251,9 @@ static void dp8393x_put(dp8393xState *s, int width, uin= t16_t *base, int offset, } =20 if (s->big_endian) { - base[offset * width + width - 1] =3D val; + s->data[offset * width + width - 1] =3D val; } else { - base[offset * width] =3D val; + s->data[offset * width] =3D val; } } =20 @@ -277,7 +277,6 @@ static void dp8393x_update_irq(dp8393xState *s) =20 static void dp8393x_do_load_cam(dp8393xState *s) { - uint16_t data[8]; int width, size; uint16_t index =3D 0; =20 @@ -287,13 +286,13 @@ static void dp8393x_do_load_cam(dp8393xState *s) while (s->regs[SONIC_CDC] & 0x1f) { /* Fill current entry */ address_space_rw(&s->as, dp8393x_cdp(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->cam[index][0] =3D dp8393x_get(s, width, data, 1) & 0xff; - s->cam[index][1] =3D dp8393x_get(s, width, data, 1) >> 8; - s->cam[index][2] =3D dp8393x_get(s, width, data, 2) & 0xff; - s->cam[index][3] =3D dp8393x_get(s, width, data, 2) >> 8; - s->cam[index][4] =3D dp8393x_get(s, width, data, 3) & 0xff; - s->cam[index][5] =3D dp8393x_get(s, width, data, 3) >> 8; + MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + s->cam[index][0] =3D dp8393x_get(s, width, 1) & 0xff; + s->cam[index][1] =3D dp8393x_get(s, width, 1) >> 8; + s->cam[index][2] =3D dp8393x_get(s, width, 2) & 0xff; + s->cam[index][3] =3D dp8393x_get(s, width, 2) >> 8; + s->cam[index][4] =3D dp8393x_get(s, width, 3) & 0xff; + s->cam[index][5] =3D dp8393x_get(s, width, 3) >> 8; DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index, s->cam[index][0], s->cam[index][1], s->cam[index][2], s->cam[index][3], s->cam[index][4], s->cam[index][5]); @@ -305,8 +304,8 @@ static void dp8393x_do_load_cam(dp8393xState *s) =20 /* Read CAM enable */ address_space_rw(&s->as, dp8393x_cdp(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->regs[SONIC_CE] =3D dp8393x_get(s, width, data, 0); + MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + s->regs[SONIC_CE] =3D dp8393x_get(s, width, 0); DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); =20 /* Done */ @@ -317,20 +316,19 @@ static void dp8393x_do_load_cam(dp8393xState *s) =20 static void dp8393x_do_read_rra(dp8393xState *s) { - uint16_t data[8]; int width, size; =20 /* Read memory */ width =3D (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; size =3D sizeof(uint16_t) * 4 * width; address_space_rw(&s->as, dp8393x_rrp(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); + MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); =20 /* Update SONIC registers */ - s->regs[SONIC_CRBA0] =3D dp8393x_get(s, width, data, 0); - s->regs[SONIC_CRBA1] =3D dp8393x_get(s, width, data, 1); - s->regs[SONIC_RBWC0] =3D dp8393x_get(s, width, data, 2); - s->regs[SONIC_RBWC1] =3D dp8393x_get(s, width, data, 3); + s->regs[SONIC_CRBA0] =3D dp8393x_get(s, width, 0); + s->regs[SONIC_CRBA1] =3D dp8393x_get(s, width, 1); + s->regs[SONIC_RBWC0] =3D dp8393x_get(s, width, 2); + s->regs[SONIC_RBWC1] =3D dp8393x_get(s, width, 3); DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n", s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); @@ -427,7 +425,6 @@ static void dp8393x_do_receiver_disable(dp8393xState *s) static void dp8393x_do_transmit_packets(dp8393xState *s) { NetClientState *nc =3D qemu_get_queue(s->nic); - uint16_t data[12]; int width, size; int tx_len, len; uint16_t i; @@ -436,21 +433,20 @@ static void dp8393x_do_transmit_packets(dp8393xState = *s) =20 while (1) { /* Read memory */ - size =3D sizeof(uint16_t) * 6 * width; + size =3D sizeof(uint16_t) * 7 * width; s->regs[SONIC_TTDA] =3D s->regs[SONIC_CTDA]; DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s)); - address_space_rw(&s->as, - dp8393x_ttda(s) + sizeof(uint16_t) * width, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); + address_space_rw(&s->as, dp8393x_ttda(s), + MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); tx_len =3D 0; =20 /* Update registers */ - s->regs[SONIC_TCR] =3D dp8393x_get(s, width, data, 0) & 0xf000; - s->regs[SONIC_TPS] =3D dp8393x_get(s, width, data, 1); - s->regs[SONIC_TFC] =3D dp8393x_get(s, width, data, 2); - s->regs[SONIC_TSA0] =3D dp8393x_get(s, width, data, 3); - s->regs[SONIC_TSA1] =3D dp8393x_get(s, width, data, 4); - s->regs[SONIC_TFS] =3D dp8393x_get(s, width, data, 5); + s->regs[SONIC_TCR] =3D dp8393x_get(s, width, 1) & 0xf000; + s->regs[SONIC_TPS] =3D dp8393x_get(s, width, 2); + s->regs[SONIC_TFC] =3D dp8393x_get(s, width, 3); + s->regs[SONIC_TSA0] =3D dp8393x_get(s, width, 4); + s->regs[SONIC_TSA1] =3D dp8393x_get(s, width, 5); + s->regs[SONIC_TFS] =3D dp8393x_get(s, width, 6); =20 /* Handle programmable interrupt */ if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) { @@ -475,10 +471,10 @@ static void dp8393x_do_transmit_packets(dp8393xState = *s) size =3D sizeof(uint16_t) * 3 * width; address_space_rw(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * wid= th, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->regs[SONIC_TSA0] =3D dp8393x_get(s, width, data, 0); - s->regs[SONIC_TSA1] =3D dp8393x_get(s, width, data, 1); - s->regs[SONIC_TFS] =3D dp8393x_get(s, width, data, 2); + MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + s->regs[SONIC_TSA0] =3D dp8393x_get(s, width, 0); + s->regs[SONIC_TSA1] =3D dp8393x_get(s, width, 1); + s->regs[SONIC_TFS] =3D dp8393x_get(s, width, 2); } } =20 @@ -505,12 +501,12 @@ static void dp8393x_do_transmit_packets(dp8393xState = *s) s->regs[SONIC_TCR] |=3D SONIC_TCR_PTX; =20 /* Write status */ - dp8393x_put(s, width, data, 0, + dp8393x_put(s, width, 0, s->regs[SONIC_TCR] & 0x0fff); /* status */ size =3D sizeof(uint16_t) * width; address_space_rw(&s->as, dp8393x_ttda(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1); + MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1); =20 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { /* Read footer of packet */ @@ -519,9 +515,9 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * s->regs[SONIC_TFC]) * width, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->regs[SONIC_CTDA] =3D dp8393x_get(s, width, data, 0) & ~0x1; - if (dp8393x_get(s, width, data, 0) & 0x1) { + MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + s->regs[SONIC_CTDA] =3D dp8393x_get(s, width, 0) & ~0x1; + if (dp8393x_get(s, width, 0) & 0x1) { /* EOL detected */ break; } @@ -758,7 +754,6 @@ static ssize_t dp8393x_receive(NetClientState *nc, cons= t uint8_t * buf, size_t size) { dp8393xState *s =3D qemu_get_nic_opaque(nc); - uint16_t data[10]; int packet_type; uint32_t available, address; int width, rx_len =3D size; @@ -783,8 +778,8 @@ static ssize_t dp8393x_receive(NetClientState *nc, cons= t uint8_t * buf, size =3D sizeof(uint16_t) * 1 * width; address =3D dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, - (uint8_t *)data, size, 0); - if (dp8393x_get(s, width, data, 0) & 0x1) { + (uint8_t *)s->data, size, 0); + if (dp8393x_get(s, width, 0) & 0x1) { /* Still EOL ; stop reception */ return -1; } else { @@ -828,29 +823,29 @@ static ssize_t dp8393x_receive(NetClientState *nc, co= nst uint8_t * buf, =20 /* Write status to memory */ DPRINTF("Write status at %08x\n", dp8393x_crda(s)); - dp8393x_put(s, width, data, 0, s->regs[SONIC_RCR]); /* status */ - dp8393x_put(s, width, data, 1, rx_len); /* byte count */ - dp8393x_put(s, width, data, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */ - dp8393x_put(s, width, data, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */ - dp8393x_put(s, width, data, 4, s->regs[SONIC_RSC]); /* seq_no */ + dp8393x_put(s, width, 0, s->regs[SONIC_RCR]); /* status */ + dp8393x_put(s, width, 1, rx_len); /* byte count */ + dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */ + dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */ + dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */ size =3D sizeof(uint16_t) * 5 * width; address_space_rw(&s->as, dp8393x_crda(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1); + MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1); =20 /* Move to next descriptor */ size =3D sizeof(uint16_t) * width; address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * widt= h, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->regs[SONIC_LLFA] =3D dp8393x_get(s, width, data, 0); + MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + s->regs[SONIC_LLFA] =3D dp8393x_get(s, width, 0); if (s->regs[SONIC_LLFA] & 0x1) { /* EOL detected */ s->regs[SONIC_ISR] |=3D SONIC_ISR_RDE; } else { size =3D sizeof(uint16_t) * width; - dp8393x_put(s, width, data, 0, 0); /* in_use */ + dp8393x_put(s, width, 0, 0); /* in_use */ address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 6 * width, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1); + MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1); s->regs[SONIC_CRDA] =3D s->regs[SONIC_LLFA]; s->regs[SONIC_ISR] |=3D SONIC_ISR_PKTRX; s->regs[SONIC_RSC] =3D (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[= SONIC_RSC] & 0x00ff) + 1) & 0x00ff); --=20 2.14.4 From nobody Mon Apr 29 04:03:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528488718029810.307242547434; Fri, 8 Jun 2018 13:11:58 -0700 (PDT) Received: from localhost ([::1]:37991 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNjp-0003E7-9c for importer@patchew.org; Fri, 08 Jun 2018 16:11:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47925) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRNez-0007fr-94 for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:07:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fRNew-0006pZ-Rj for qemu-devel@nongnu.org; Fri, 08 Jun 2018 16:06:57 -0400 Received: from mout.kundenserver.de ([212.227.126.130]:51051) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fRNew-0006nu-HC; Fri, 08 Jun 2018 16:06:54 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue002 [212.227.15.167]) with ESMTPSA (Nemesis) id 0Mf66r-1fcbuj2baT-00OUcp; Fri, 08 Jun 2018 22:06:32 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 8 Jun 2018 22:05:58 +0200 Message-Id: <20180608200558.386-14-laurent@vivier.eu> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180608200558.386-1-laurent@vivier.eu> References: <20180608200558.386-1-laurent@vivier.eu> X-Provags-ID: V03:K1:wEvUxou2nbTVyLP1tPnudaQu8M89qNMmIxn2nVkH9wK7WabXPLR WVPaEJbWTp8SCJNj4wyNjSc+IlhHjzK/CISuH8gEhiVVBa2zXmv2Fa7OEfIWg0ptKbHcg/Q JR8YSiuYWCVoWtaXnTT02XcivVScPiq87KR7Lk8frE6bBvnq8/JvedM0aaClWUOfMJ2Yoz7 YH/ZLs1DjhU0cTYhytlAg== X-UI-Out-Filterresults: notjunk:1;V01:K0:0zmjVcHWmMA=:23ilJtj7yKn8slxHBIMnmq 7uG9v1BMTVpOltd/ZiuthchxhlcIPfRRU6WzkDPN+HooCFwJdUTfkfyeYEO90zKvwhVQTeiRL KU49Vv57G19b1NOXPb0sQ8klRRqrj12tJEw4EKqiBxvfvzzXMnm+dQ6OEgb9OO43b5na3xKzn oKgIqnZC1QgGDKhf6wubc1S9/5jfXnK3e2mVJ7LRGBIo60nnttIsZguhbf9f/XDNJl+lo6Lv1 YMjlSpYXz7I9VlYNxatKkAZktxf69sOKpUeh6ieetp/KNBra22dKNJ0uUgTAqPR0GyQrdqM1h d7N4sDxVFRxG/lJrJjEgNJKD8eNmP0iWjhbob980RZ2cKnHADksnwFSfl2mBTHvbQTmZn6r4E Bkx+nxvb13gaolVukat68qx0srY+ZS0Oadavvd5Cu1ES15roQu2TEQQYM1Ru+FkABmMFsI1Wv rjsavuymhb01X9z8IGUP5oXXdfB5wrvvC8AcItimt5PT025gOwtr9aQRiXe/Dv7zEfgghWcz/ G/9TIeDAK56YIOu/ZiozFZhQ8h0SzOFif5ZsQJ0mdn1HsrY6M+lH5fKo5dFbtI+UVIpPBGJgT 1/b2ajMVcw80GyMo2ny3k8eHSLZagG4DRBwg4bs33229h1SBv2nKW5wsFoopIPRN7vQ4WvJzo gLQVbL/fdMXlYzvnun59qc4K9hmdDGBM3efom+ZOeFzKRYuxq8tuEI4ETHBLouJOeJ5I= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.130 Subject: [Qemu-devel] [RFC 13/13] dp8393x: fix receiving buffer exhaustion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Jason Wang , "Dr. David Alan Gilbert" , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , Yongbok Kim , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The card is not able to exit from exhaustion state, because while the drive consumes the buffers, the RRP is incremented (when the driver clears the ISR RBE bit), so it stays equal to RWP, and while RRP =3D=3D RWP, the card thinks it is always in exhaustion state. So the driver consumes all the buffers, but the card cannot receive new ones. This patch fixes the problem by not incrementing RRP when the driver clears the ISR RBE bit. Signed-off-by: Laurent Vivier Tested-by: Herv=C3=A9 Poussineau --- hw/net/dp8393x.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index 40e5f8257b..fd0f6cf2a0 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -314,7 +314,7 @@ static void dp8393x_do_load_cam(dp8393xState *s) dp8393x_update_irq(s); } =20 -static void dp8393x_do_read_rra(dp8393xState *s) +static void dp8393x_do_read_rra(dp8393xState *s, int next) { int width, size; =20 @@ -333,19 +333,20 @@ static void dp8393x_do_read_rra(dp8393xState *s) s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); =20 - /* Go to next entry */ - s->regs[SONIC_RRP] +=3D size; + if (next) { + /* Go to next entry */ + s->regs[SONIC_RRP] +=3D size; =20 - /* Handle wrap */ - if (s->regs[SONIC_RRP] =3D=3D s->regs[SONIC_REA]) { - s->regs[SONIC_RRP] =3D s->regs[SONIC_RSA]; - } + /* Handle wrap */ + if (s->regs[SONIC_RRP] =3D=3D s->regs[SONIC_REA]) { + s->regs[SONIC_RRP] =3D s->regs[SONIC_RSA]; + } =20 - /* Check resource exhaustion */ - if (s->regs[SONIC_RRP] =3D=3D s->regs[SONIC_RWP]) - { - s->regs[SONIC_ISR] |=3D SONIC_ISR_RBE; - dp8393x_update_irq(s); + /* Check resource exhaustion */ + if (s->regs[SONIC_RRP] =3D=3D s->regs[SONIC_RWP]) { + s->regs[SONIC_ISR] |=3D SONIC_ISR_RBE; + dp8393x_update_irq(s); + } } =20 /* Done */ @@ -559,7 +560,7 @@ static void dp8393x_do_command(dp8393xState *s, uint16_= t command) if (command & SONIC_CR_RST) dp8393x_do_software_reset(s); if (command & SONIC_CR_RRRA) - dp8393x_do_read_rra(s); + dp8393x_do_read_rra(s, 1); if (command & SONIC_CR_LCAM) dp8393x_do_load_cam(s); } @@ -650,7 +651,7 @@ static void dp8393x_write(void *opaque, hwaddr addr, ui= nt64_t data, data &=3D s->regs[reg]; s->regs[reg] &=3D ~data; if (data & SONIC_ISR_RBE) { - dp8393x_do_read_rra(s); + dp8393x_do_read_rra(s, 0); } dp8393x_update_irq(s); if (dp8393x_can_receive(s->nic->ncs)) { @@ -852,7 +853,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, cons= t uint8_t * buf, =20 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) { /* Read next RRA */ - dp8393x_do_read_rra(s); + dp8393x_do_read_rra(s, 1); } } =20 --=20 2.14.4