From nobody Fri May 3 03:43:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 15276316047801004.70116391787; Tue, 29 May 2018 15:06:44 -0700 (PDT) Received: from localhost ([::1]:35236 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNmlJ-0008Mq-U7 for importer@patchew.org; Tue, 29 May 2018 18:06:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41858) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNmjD-0007GL-NM for qemu-devel@nongnu.org; Tue, 29 May 2018 18:04:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNmjC-0007qT-RL for qemu-devel@nongnu.org; Tue, 29 May 2018 18:04:27 -0400 Received: from smtp18.mail.ru ([94.100.176.155]:44936) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fNmjC-0007ps-Jj for qemu-devel@nongnu.org; Tue, 29 May 2018 18:04:26 -0400 Received: by smtp18.mail.ru with esmtpa (envelope-from ) id 1fNmjA-00076p-QT; Wed, 30 May 2018 01:04:25 +0300 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=6KXYqeYe69V0T6M3KqL8LrPPehYktuPCaBrjiIvYFqw=; b=oEr3oSbc5Uh+QTvypNf5EiGTLScaH8cBkjietLujuUrwTkvvpUkS6tOY5l1xFId4zHOL9UY9BHLyUH2pwUsQfjqSoM7as46Ke2Sqmv1k7eCmb8hz2spAa2KCeO+yQ2cpNEYIH29f+DRje+5766+kqxnpUfNIgVBEz4TUddcsxYI=; To: qemu-devel Date: Wed, 30 May 2018 01:03:36 +0300 Message-Id: <20180529220338.10879-2-jusual@mail.ru> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180529220338.10879-1-jusual@mail.ru> References: <20180529220338.10879-1-jusual@mail.ru> Authentication-Results: smtp18.mail.ru; auth=pass smtp.auth=jusual@mail.ru smtp.mailfrom=jusual@mail.ru X-7FA49CB5: 0D63561A33F958A50A986AC80C43E4006F0765A1669F95CCB164F540FB2E6CA1725E5C173C3A84C3A2CE164612F1211F25C01993F489E81A9EF166FBCB559E95C4224003CC836476C0CAF46E325F83A50BF2EBBBDD9D6B0FECB2555BB02FD5A93B503F486389A921A5CC5B56E945C8DA X-Mailru-Sender: 7766D515518070DE138AAC7428EA760D7C1C1BBCE7BE7AE3C98D1DDFCB1AABACC655969879B08F797C4160E8B47E48163DDE9B364B0DF2898CB68AF7A628805D594FB4C9F0DBF412AE208404248635DF X-Mras: OK X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 94.100.176.155 Subject: [Qemu-devel] [RFC 1/3] hw/arm/nrf51_soc: Fix compilation and memory regions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Julia Suvorova via Qemu-devel Reply-To: Julia Suvorova Cc: Peter Maydell , Jim Mussared , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Stefan Hajnoczi , Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" nRF51 SoC implementation is intended for the BBC Micro:bit board, which has 256 KB flash and 16 KB RAM. Added FICR defines. Signed-off-by: Julia Suvorova --- hw/arm/nrf51_soc.c | 12 +++++++----- include/hw/arm/nrf51_soc.h | 1 + 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index e59ba7079f..6fe06dcfd2 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -26,15 +26,17 @@ #define IOMEM_SIZE 0x20000000 =20 #define FLASH_BASE 0x00000000 -#define FLASH_SIZE (144 * 1024) +#define FLASH_SIZE (256 * 1024) + +#define FICR_BASE 0x10000000 +#define FICR_SIZE 0x100 =20 #define SRAM_BASE 0x20000000 -#define SRAM_SIZE (6 * 1024) +#define SRAM_SIZE (16 * 1024) =20 static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) { NRF51State *s =3D NRF51_SOC(dev_soc); - DeviceState *nvic; Error *err =3D NULL; =20 /* IO space */ @@ -69,8 +71,8 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error= **errp) memory_region_add_subregion(system_memory, SRAM_BASE, sram); =20 /* TODO: implement a cortex m0 and update this */ - nvic =3D armv7m_init(get_system_memory(), FLASH_SIZE, 96, - s->kernel_filename, ARM_CPU_TYPE_NAME("cortex-m3")); + s->nvic =3D armv7m_init(get_system_memory(), FLASH_SIZE, 96, + s->kernel_filename, ARM_CPU_TYPE_NAME("cortex-m3")); } =20 static Property nrf51_soc_properties[] =3D { diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index 5431d200f8..a6bbe9f108 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -23,6 +23,7 @@ typedef struct NRF51State { =20 /*< public >*/ char *kernel_filename; + DeviceState *nvic; =20 MemoryRegion iomem; } NRF51State; --=20 2.17.0 From nobody Fri May 3 03:43:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1527631619200695.9060363787067; Tue, 29 May 2018 15:06:59 -0700 (PDT) Received: from localhost ([::1]:35237 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNmlZ-000063-56 for importer@patchew.org; Tue, 29 May 2018 18:06:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41897) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNmjM-0007Ld-0f for qemu-devel@nongnu.org; Tue, 29 May 2018 18:04:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNmjI-0007xz-PB for qemu-devel@nongnu.org; Tue, 29 May 2018 18:04:36 -0400 Received: from smtp18.mail.ru ([94.100.176.155]:45132) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fNmjI-0007vu-DZ for qemu-devel@nongnu.org; Tue, 29 May 2018 18:04:32 -0400 Received: by smtp18.mail.ru with esmtpa (envelope-from ) id 1fNmjG-00076p-GM; Wed, 30 May 2018 01:04:30 +0300 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=gBtOfa/jiSzDDq0hy/Uou7sqPguA3R+cagsg/hFIAUU=; b=h+iSCdaFIPGB3JBwxxX8dDjOPs+rWYzTG7s8fxEFpRGlER8bYF1e532TJYfGC+ypUkvxJb7kGzlJ6N/gh+X/xrhwuQRdRoEYWKFueFkBK6+jgeqwSCToJGxqiU2qFm5dHqRxbRh4ClqysT/pDkc7vAKXjdjpUtZajy8Ew4jZznE=; To: qemu-devel Date: Wed, 30 May 2018 01:03:37 +0300 Message-Id: <20180529220338.10879-3-jusual@mail.ru> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180529220338.10879-1-jusual@mail.ru> References: <20180529220338.10879-1-jusual@mail.ru> Authentication-Results: smtp18.mail.ru; auth=pass smtp.auth=jusual@mail.ru smtp.mailfrom=jusual@mail.ru X-7FA49CB5: 0D63561A33F958A59A76BBC3AD2215976F0765A1669F95CCBF62296B5FDE3213725E5C173C3A84C325A81A29FB5043FDF9F6675564C6C9EB1CE60B8040019C36C4224003CC836476C0CAF46E325F83A50BF2EBBBDD9D6B0F9A3D58A9A349F5073B503F486389A921A5CC5B56E945C8DA X-Mailru-Sender: 7766D515518070DE138AAC7428EA760DECECE4A2404640203D74FF77091D58B1348E23661E11A3517C4160E8B47E48163DDE9B364B0DF2898CB68AF7A628805D594FB4C9F0DBF412AE208404248635DF X-Mras: OK X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 94.100.176.155 Subject: [Qemu-devel] [RFC 2/3] hw/char/nrf51_uart: Implement nRF51 SoC UART X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Julia Suvorova via Qemu-devel Reply-To: Julia Suvorova Cc: Peter Maydell , Jim Mussared , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Stefan Hajnoczi , Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Basic implementation of nRF51 SoC UART. Description could be found here: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf The following features are not yet implemented: Control with SUSPEND/START*/STOP* CTS/NCTS flow control Mapping registers to pins Signed-off-by: Julia Suvorova --- hw/arm/nrf51_soc.c | 7 ++ hw/char/Makefile.objs | 1 + hw/char/nrf51_uart.c | 232 +++++++++++++++++++++++++++++++++++ include/hw/arm/nrf51_soc.h | 1 + include/hw/char/nrf51_uart.h | 54 ++++++++ 5 files changed, 295 insertions(+) create mode 100644 hw/char/nrf51_uart.c create mode 100644 include/hw/char/nrf51_uart.h diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 6fe06dcfd2..a2ee6f3f3b 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -21,6 +21,7 @@ #include "cpu.h" =20 #include "hw/arm/nrf51_soc.h" +#include "hw/char/nrf51_uart.h" =20 #define IOMEM_BASE 0x40000000 #define IOMEM_SIZE 0x20000000 @@ -34,6 +35,9 @@ #define SRAM_BASE 0x20000000 #define SRAM_SIZE (16 * 1024) =20 +#define UART_BASE 0x40002000 +#define UART_SIZE 0x1000 + static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) { NRF51State *s =3D NRF51_SOC(dev_soc); @@ -73,6 +77,9 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error= **errp) /* TODO: implement a cortex m0 and update this */ s->nvic =3D armv7m_init(get_system_memory(), FLASH_SIZE, 96, s->kernel_filename, ARM_CPU_TYPE_NAME("cortex-m3")); + + s->uart =3D nrf51_uart_create(UART_BASE, qdev_get_gpio_in(s->nvic, 2), + serial_hd(0)); } =20 static Property nrf51_soc_properties[] =3D { diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs index 1b979100b7..1060c62a54 100644 --- a/hw/char/Makefile.objs +++ b/hw/char/Makefile.objs @@ -1,5 +1,6 @@ common-obj-$(CONFIG_IPACK) +=3D ipoctal232.o common-obj-$(CONFIG_ESCC) +=3D escc.o +common-obj-$(CONFIG_NRF51_SOC) +=3D nrf51_uart.o common-obj-$(CONFIG_PARALLEL) +=3D parallel.o common-obj-$(CONFIG_PARALLEL) +=3D parallel-isa.o common-obj-$(CONFIG_PL011) +=3D pl011.o diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c new file mode 100644 index 0000000000..2da97aa0c4 --- /dev/null +++ b/hw/char/nrf51_uart.c @@ -0,0 +1,232 @@ +/* + * nRF51 SoC UART emulation + * + * Copyright (c) 2018 Julia Suvorova + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/registerfields.h" +#include "hw/char/nrf51_uart.h" + +REG32(STARTRX, 0x000) +REG32(STOPRX, 0x004) +REG32(STARTTX, 0x008) +REG32(STOPTX, 0x00C) +REG32(SUSPEND, 0x01C) + +REG32(CTS, 0x100) +REG32(NCTS, 0x104) +REG32(RXDRDY, 0x108) +REG32(TXDRDY, 0x11C) +REG32(ERROR, 0x124) +REG32(RXTO, 0x144) + +REG32(INTEN, 0x300) + FIELD(INTEN, CTS, 0, 1) + FIELD(INTEN, NCTS, 1, 1) + FIELD(INTEN, RXDRDY, 2, 1) + FIELD(INTEN, TXDRDY, 7, 1) + FIELD(INTEN, ERROR, 9, 1) + FIELD(INTEN, RXTO, 17, 1) +REG32(INTENSET, 0x304) +REG32(INTENCLR, 0x308) +REG32(ERRORSRC, 0x480) +REG32(ENABLE, 0x500) +REG32(PSELRTS, 0x508) +REG32(PSELTXD, 0x50C) +REG32(PSELCTS, 0x510) +REG32(PSELRXD, 0x514) +REG32(RXD, 0x518) +REG32(TXD, 0x51C) +REG32(BAUDRATE, 0x524) +REG32(CONFIG, 0x56C) + +static void nrf51_uart_update_irq(Nrf51UART *s) +{ + unsigned int irq =3D 0; + + irq =3D irq || (s->reg[A_RXDRDY] && (s->reg[A_INTEN] & R_INTEN_RXDRDY_= MASK)); + irq =3D irq || (s->reg[A_TXDRDY] && (s->reg[A_INTEN] & R_INTEN_TXDRDY_= MASK)); + irq =3D irq || (s->reg[A_ERROR] && (s->reg[A_INTEN] & R_INTEN_ERROR_M= ASK)); + irq =3D irq || (s->reg[A_RXTO] && (s->reg[A_INTEN] & R_INTEN_RXTO_MA= SK)); + + qemu_set_irq(s->irq, !!irq); +} + +static uint64_t uart_read(void *opaque, hwaddr addr, unsigned int size) +{ + Nrf51UART *s =3D NRF51_UART(opaque); + uint64_t r; + + switch (addr) { + case A_RXD: + r =3D s->rx_fifo[s->rx_fifo_pos]; + if (s->rx_fifo_len > 0) { + s->rx_fifo_pos =3D (s->rx_fifo_pos + 1) % UART_FIFO_LENGTH; + s->rx_fifo_len--; + qemu_chr_fe_accept_input(&s->chr); + } + break; + + case A_INTENSET: + case A_INTENCLR: + case A_INTEN: + r =3D s->reg[A_INTEN]; + break; + default: + r =3D s->reg[addr]; + break; + } + + return r; +} + +static gboolean uart_transmit(GIOChannel *chan, GIOCondition cond, void *o= paque) +{ + Nrf51UART *s =3D NRF51_UART(opaque); + int r; + + s->watch_tag =3D 0; + + r =3D qemu_chr_fe_write(&s->chr, (uint8_t *) &s->reg[A_TXD], 1); + if (r <=3D 0) { + s->watch_tag =3D qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HU= P, + uart_transmit, s); + if (!s->watch_tag) { + goto buffer_drained; + } + return FALSE; + } + +buffer_drained: + s->reg[A_TXDRDY] =3D 1; + nrf51_uart_update_irq(s); + return FALSE; +} + +static void uart_cancel_transmit(Nrf51UART *s) +{ + if (s->watch_tag) { + g_source_remove(s->watch_tag); + s->watch_tag =3D 0; + } +} + +static void uart_write(void *opaque, hwaddr addr, + uint64_t value, unsigned int size) +{ + Nrf51UART *s =3D NRF51_UART(opaque); + + switch (addr) { + case A_TXD: + s->reg[A_TXD] =3D value; + uart_transmit(NULL, G_IO_OUT, s); + break; + case A_INTENSET: + s->reg[A_INTEN] |=3D value; + break; + case A_INTENCLR: + s->reg[A_INTEN] &=3D ~value; + break; + case A_CTS ... A_RXTO: + s->reg[addr] =3D value; + nrf51_uart_update_irq(s); + default: + s->reg[addr] =3D value; + break; + } +} + +static const MemoryRegionOps uart_ops =3D { + .read =3D uart_read, + .write =3D uart_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void nrf51_uart_reset(DeviceState *dev) +{ + Nrf51UART *s =3D NRF51_UART(dev); + + uart_cancel_transmit(s); + + memset(s->reg, 0, sizeof(s->reg)); + + s->rx_fifo_len =3D 0; + s->rx_fifo_pos =3D 0; +} + +static void uart_receive(void *opaque, const uint8_t *buf, int size) +{ + + Nrf51UART *s =3D NRF51_UART(opaque); + + if (s->rx_fifo_len >=3D UART_FIFO_LENGTH) { + return; + } + + s->rx_fifo[(s->rx_fifo_pos + s->rx_fifo_len) % UART_FIFO_LENGTH] =3D *= buf; + s->rx_fifo_len++; + + s->reg[A_RXDRDY] =3D 1; + nrf51_uart_update_irq(s); +} + +static int uart_can_receive(void *opaque) +{ + Nrf51UART *s =3D NRF51_UART(opaque); + + return (s->rx_fifo_len < sizeof(s->rx_fifo)); +} + +static void nrf51_uart_realize(DeviceState *dev, Error **errp) +{ + Nrf51UART *s =3D NRF51_UART(dev); + + qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive, + NULL, NULL, s, NULL, true); +} + +static void nrf51_uart_init(Object *obj) +{ + Nrf51UART *s =3D NRF51_UART(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->mmio, obj, &uart_ops, s, + "nrf51_soc.uart", 0x1000); + sysbus_init_mmio(sbd, &s->mmio); + sysbus_init_irq(sbd, &s->irq); +} + +static Property nrf51_uart_properties[] =3D { + DEFINE_PROP_CHR("chardev", Nrf51UART, chr), + DEFINE_PROP_END_OF_LIST(), +}; + +static void nrf51_uart_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D nrf51_uart_reset; + dc->realize =3D nrf51_uart_realize; + dc->props =3D nrf51_uart_properties; +} + +static const TypeInfo nrf51_uart_info =3D { + .name =3D TYPE_NRF51_UART, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Nrf51UART), + .instance_init =3D nrf51_uart_init, + .class_init =3D nrf51_uart_class_init +}; + +static void nrf51_uart_register_types(void) +{ + type_register_static(&nrf51_uart_info); +} + +type_init(nrf51_uart_register_types) diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index a6bbe9f108..a38b984675 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -24,6 +24,7 @@ typedef struct NRF51State { /*< public >*/ char *kernel_filename; DeviceState *nvic; + DeviceState *uart; =20 MemoryRegion iomem; } NRF51State; diff --git a/include/hw/char/nrf51_uart.h b/include/hw/char/nrf51_uart.h new file mode 100644 index 0000000000..758203f1c3 --- /dev/null +++ b/include/hw/char/nrf51_uart.h @@ -0,0 +1,54 @@ +/* + * nRF51 SoC UART emulation + * + * Copyright (c) 2018 Julia Suvorova + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#ifndef NRF51_UART_H +#define NRF51_UART_H + +#include "hw/sysbus.h" +#include "chardev/char-fe.h" + +#define UART_FIFO_LENGTH 6 + +#define TYPE_NRF51_UART "nrf51_soc.uart" +#define NRF51_UART(obj) OBJECT_CHECK(Nrf51UART, (obj), TYPE_NRF51_UART) + +typedef struct Nrf51UART { + SysBusDevice parent_obj; + + MemoryRegion mmio; + CharBackend chr; + qemu_irq irq; + guint watch_tag; + + uint8_t rx_fifo[UART_FIFO_LENGTH]; + unsigned int rx_fifo_pos; + unsigned int rx_fifo_len; + + uint32_t reg[0x1000]; +} Nrf51UART; + +static inline DeviceState *nrf51_uart_create(hwaddr addr, + qemu_irq irq, + Chardev *chr) +{ + DeviceState *dev; + SysBusDevice *s; + + dev =3D qdev_create(NULL, "nrf51_soc.uart"); + s =3D SYS_BUS_DEVICE(dev); + qdev_prop_set_chr(dev, "chardev", chr); + qdev_init_nofail(dev); + sysbus_mmio_map(s, 0, addr); + sysbus_connect_irq(s, 0, irq); + + return dev; +} + +#endif --=20 2.17.0 From nobody Fri May 3 03:43:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1527631617846735.2453151705545; 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s=mail2; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=Z6VSYZbQmyTocBJ5FAX3J+yhqSg/yhk78aBGSyN8KIA=; b=rhdkVlYuqt9XfwAwsYpUWtZDv39tHIeB+fWvsmGbzpZrBBcJBW/YePpZdpWo+RIwLns2PtXawKhAU+u3Vj193bc8fBTkDbPJ2cxIzpZmqYhFyxIRYNixSn1OwHqBpywFYLNY56ZnbKB3rnlkccwfNb0M9gyVawN/47jDGTwaYB8=; To: qemu-devel Date: Wed, 30 May 2018 01:03:38 +0300 Message-Id: <20180529220338.10879-4-jusual@mail.ru> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180529220338.10879-1-jusual@mail.ru> References: <20180529220338.10879-1-jusual@mail.ru> Authentication-Results: smtp18.mail.ru; auth=pass smtp.auth=jusual@mail.ru smtp.mailfrom=jusual@mail.ru X-7FA49CB5: 0D63561A33F958A5CCE673736A218D5F6F0765A1669F95CC28A6D463EDFD0DBB725E5C173C3A84C35D1D84EF68E022EA1AF6857BB18E05C60555CCFDA08FA3FAC4224003CC836476C0CAF46E325F83A50BF2EBBBDD9D6B0F2EF91E2201DEA5EC574AF45C6390F7469DAA53EE0834AAEE X-Mailru-Sender: 7766D515518070DE138AAC7428EA760D1EE0CD12089E7727A37AF845B72DA822E11A6E312C87D21D7C4160E8B47E48163DDE9B364B0DF2898CB68AF7A628805D594FB4C9F0DBF412AE208404248635DF X-Mras: OK X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 94.100.176.155 Subject: [Qemu-devel] [RFC 3/3] tests/boot-serial-test: Add support for the microbit board X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Julia Suvorova via Qemu-devel Reply-To: Julia Suvorova Cc: Peter Maydell , Jim Mussared , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Stefan Hajnoczi , Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" New mini-kernel test for nRF51 SoC UART. Signed-off-by: Julia Suvorova --- tests/boot-serial-test.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c index 4d6815c3e0..e6dbc8a293 100644 --- a/tests/boot-serial-test.c +++ b/tests/boot-serial-test.c @@ -62,6 +62,16 @@ static const uint8_t kernel_aarch64[] =3D { 0xfd, 0xff, 0xff, 0x17, /* b -12 (loop) */ }; =20 +static const uint8_t kernel_nrf51[] =3D { + 0x00, 0x00, 0x00, 0x00, /* Stack top address */ + 0x09, 0x00, 0x00, 0x00, /* Reset handler address */ + 0x01, 0x4b, /* ldr r3,[pc,#4] Get bas= e */ + 0x54, 0x22, /* mov r2,#'T' */ + 0x1a, 0x70, /* strb r2,[r3] */ + 0x01, 0xe0, /* b loop */ + 0x1c, 0x25, 0x00, 0x40, /* 0x40002000 =3D UART0 base a= ddr */ +}; + typedef struct testdef { const char *arch; /* Target architecture */ const char *machine; /* Name of the machine */ @@ -107,6 +117,7 @@ static testdef_t tests[] =3D { { "hppa", "hppa", "", "SeaBIOS wants SYSTEM HALT" }, { "aarch64", "virt", "-cpu cortex-a57", "TT", sizeof(kernel_aarch64), kernel_aarch64 }, + { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 }, =20 { NULL } }; --=20 2.17.0