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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.25.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:25:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jDhX1u7/y5BhcUMp6xkxadIqpIgioPiIemVTRTRzYQI=; b=hKaVPx1HpkY0Y/5tB0EEu7vt5+5kjjq4/nyJzddp8RByudPI0hyjrHhY5+69cIILCX tXLzAx/GM9lk3/pG4JPjLRiqDUjVZRxa1Yd2WkRUzgCiHo+fXN/bK/rkpKh0zlqYAqJH pyxoP5Bw9llCivxLM+7nBswbaAKuHCrqZIqTM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jDhX1u7/y5BhcUMp6xkxadIqpIgioPiIemVTRTRzYQI=; b=C13BubWOtt3hJvMVxfEvF/T7rTqMsewJzZS7W/Y6tWH8S58TGz3fPhZUQCSU5eHp5+ jW6K6y/Af8UVapMIyhICMHUwgjjaY4GvbbHn+5wjwpt1jBkAl6rbF2KE7ClUHYqhs3Og 9Ugz7yK0FUkvAtt/GNZdWKRVZvkIe0WFssLowALXOYN/uIlMrrpiKwO5225A3vhxWCzU v32A/sLG1vrSPwMC8fsZl1y5n9u+7/uT2QCNDG6Y7ROqtu43vsipZ2JfQ+5gherLHCg0 57CEDr6Be28jkbC13WaRP55rZ4VgBr9XQuzRBoV/f041JbYW5Dml6GUAV4yHbhaN66E/ qU1w== X-Gm-Message-State: ALKqPwegH8vPTKBElx95Hw90x5ILjd8Zfl71G1EqSSsIDDpuytphMCyS oNg2aHW+hGtzGzBnupaOj/k6EkpixjE= X-Google-Smtp-Source: AB8JxZrS5Ygc5G36SZMytzXqNsWdyjSV+V74Tveo9zXmm1Wp0uZV6LTB7xuxeJ9QTk8JaPk/xFM91w== X-Received: by 2002:a65:6489:: with SMTP id e9-v6mr13787783pgv.44.1526423145784; Tue, 15 May 2018 15:25:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:13 -0700 Message-Id: <20180515222540.9988-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v6 01/28] fpu/softfloat: Fix conversion from uint64 to float128 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org, Petr Tesarik Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Petr Tesarik The significand is passed to normalizeRoundAndPackFloat128() as high first, low second. The current code passes the integer first, so the result is incorrectly shifted left by 64 bits. This bug affects the emulation of s390x instruction CXLGBR (convert from logical 64-bit binary-integer operand to extended BFP result). Cc: qemu-stable@nongnu.org Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Petr Tesarik Message-Id: <20180511071052.1443-1-ptesarik@suse.com> Signed-off-by: Richard Henderson --- fpu/softfloat.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index bc0f52fa54..d07419324a 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3147,7 +3147,7 @@ float128 uint64_to_float128(uint64_t a, float_status = *status) if (a =3D=3D 0) { return float128_zero; } - return normalizeRoundAndPackFloat128(0, 0x406E, a, 0, status); + return normalizeRoundAndPackFloat128(0, 0x406E, 0, a, status); } =20 =20 --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526423327831397.3491561256865; Tue, 15 May 2018 15:28:47 -0700 (PDT) Received: from localhost ([::1]:36316 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiR4-00052h-UR for importer@patchew.org; Tue, 15 May 2018 18:28:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39468) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOF-0003Gi-Hp for qemu-devel@nongnu.org; Tue, 15 May 2018 18:25:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOC-0003aC-Q2 for qemu-devel@nongnu.org; Tue, 15 May 2018 18:25:51 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:44810) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOC-0003T0-Hu for qemu-devel@nongnu.org; Tue, 15 May 2018 18:25:48 -0400 Received: by mail-pf0-x242.google.com with SMTP id q22-v6so730737pff.11 for ; Tue, 15 May 2018 15:25:48 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.25.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:25:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vUbiquEpPpv1Jwk4MPNGVRk9CWrHz238T8o7L7traPo=; b=NIz/LgFT7knSfTby3Tsen28kEx7JKi4wW03SCcOzVjmMnWpA48ZyENdNK/czVc8UQb R+bbG/yTQM73oFmaQe8hUMigcbwo6h0rwcO5ssZCkSM06s1Ij7qa+bgPpMrU7MDQf3yj wA59tKmP4/cNmh4sGpJcbh0GnThMa5gbEszeg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vUbiquEpPpv1Jwk4MPNGVRk9CWrHz238T8o7L7traPo=; b=V1qvWbaGymI7OAHxFKxzWjc0c0sU9rN87bYKQy2ZLG0RtVwHzvX/JowKuLTMqNdOYO jNDo3RFmkmwgwrxiIkZDxzTrk64QtqkPGP6REOQLueGPaihrXDdiiAnwrQ+IU1U/6j6i mybEfpFiR9UcXc7845HZL5HCkc5ZSG6lPzq05Cy4s1m/xlWJyEQRMh0K/f0AjCIdTYjh SWz8m4BfCF0jNO1hu4HOVF6yufbA3+4Edj7fQ3TjIfJI7DjDWKAk4l73jSEfL0Om+9bm SPeMj2l2bY8kaT5tNpGXSJlg9GCPvw+SxkxR2vf6NbeOMRQn9wrQ/i1CfRAT0sSXNujw DPuQ== X-Gm-Message-State: ALKqPwfzwhQr8HYpJ33Xhm/7Caj1bCmY9IQvabgvAQyVvjHwmTAGnNgH kqQZuJSvDFi5HfZ9TY3wGONAN/dsZ/o= X-Google-Smtp-Source: AB8JxZqOAaC7osFVs37shTCjGjZoeOYaJgcwnIv8KcERxHclOjk6L9vwrlbjAohkcdoeJmyo5BEXww== X-Received: by 2002:a63:65c4:: with SMTP id z187-v6mr13429856pgb.180.1526423147178; Tue, 15 May 2018 15:25:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:14 -0700 Message-Id: <20180515222540.9988-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v6 02/28] fpu/softfloat: Merge NO_SIGNALING_NANS definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Move the ifdef inside the relevant functions instead of duplicating the function declarations. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 100 +++++++++++++++---------------------- 1 file changed, 40 insertions(+), 60 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 27834af0de..58b05718c8 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -233,17 +233,6 @@ typedef struct { uint64_t high, low; } commonNaNT; =20 -#ifdef NO_SIGNALING_NANS -int float16_is_quiet_nan(float16 a_, float_status *status) -{ - return float16_is_any_nan(a_); -} - -int float16_is_signaling_nan(float16 a_, float_status *status) -{ - return 0; -} -#else /*------------------------------------------------------------------------= ---- | Returns 1 if the half-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -251,12 +240,16 @@ int float16_is_signaling_nan(float16 a_, float_status= *status) =20 int float16_is_quiet_nan(float16 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float16_is_any_nan(a_); +#else uint16_t a =3D float16_val(a_); if (status->snan_bit_is_one) { return (((a >> 9) & 0x3F) =3D=3D 0x3E) && (a & 0x1FF); } else { return ((a & ~0x8000) >=3D 0x7C80); } +#endif } =20 /*------------------------------------------------------------------------= ---- @@ -266,14 +259,17 @@ int float16_is_quiet_nan(float16 a_, float_status *st= atus) =20 int float16_is_signaling_nan(float16 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else uint16_t a =3D float16_val(a_); if (status->snan_bit_is_one) { return ((a & ~0x8000) >=3D 0x7C80); } else { return (((a >> 9) & 0x3F) =3D=3D 0x3E) && (a & 0x1FF); } -} #endif +} =20 /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the half-precision floating point value `a' is a @@ -333,17 +329,6 @@ static float16 commonNaNToFloat16(commonNaNT a, float_= status *status) } } =20 -#ifdef NO_SIGNALING_NANS -int float32_is_quiet_nan(float32 a_, float_status *status) -{ - return float32_is_any_nan(a_); -} - -int float32_is_signaling_nan(float32 a_, float_status *status) -{ - return 0; -} -#else /*------------------------------------------------------------------------= ---- | Returns 1 if the single-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -351,12 +336,16 @@ int float32_is_signaling_nan(float32 a_, float_status= *status) =20 int float32_is_quiet_nan(float32 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float32_is_any_nan(a_); +#else uint32_t a =3D float32_val(a_); if (status->snan_bit_is_one) { return (((a >> 22) & 0x1FF) =3D=3D 0x1FE) && (a & 0x003FFFFF); } else { return ((uint32_t)(a << 1) >=3D 0xFF800000); } +#endif } =20 /*------------------------------------------------------------------------= ---- @@ -366,14 +355,17 @@ int float32_is_quiet_nan(float32 a_, float_status *st= atus) =20 int float32_is_signaling_nan(float32 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else uint32_t a =3D float32_val(a_); if (status->snan_bit_is_one) { return ((uint32_t)(a << 1) >=3D 0xFF800000); } else { return (((a >> 22) & 0x1FF) =3D=3D 0x1FE) && (a & 0x003FFFFF); } -} #endif +} =20 /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the single-precision floating point value `a' is a @@ -744,17 +736,6 @@ static float32 propagateFloat32NaN(float32 a, float32 = b, float_status *status) } } =20 -#ifdef NO_SIGNALING_NANS -int float64_is_quiet_nan(float64 a_, float_status *status) -{ - return float64_is_any_nan(a_); -} - -int float64_is_signaling_nan(float64 a_, float_status *status) -{ - return 0; -} -#else /*------------------------------------------------------------------------= ---- | Returns 1 if the double-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -762,6 +743,9 @@ int float64_is_signaling_nan(float64 a_, float_status *= status) =20 int float64_is_quiet_nan(float64 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float64_is_any_nan(a_); +#else uint64_t a =3D float64_val(a_); if (status->snan_bit_is_one) { return (((a >> 51) & 0xFFF) =3D=3D 0xFFE) @@ -769,6 +753,7 @@ int float64_is_quiet_nan(float64 a_, float_status *stat= us) } else { return ((a << 1) >=3D 0xFFF0000000000000ULL); } +#endif } =20 /*------------------------------------------------------------------------= ---- @@ -778,6 +763,9 @@ int float64_is_quiet_nan(float64 a_, float_status *stat= us) =20 int float64_is_signaling_nan(float64 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else uint64_t a =3D float64_val(a_); if (status->snan_bit_is_one) { return ((a << 1) >=3D 0xFFF0000000000000ULL); @@ -785,8 +773,8 @@ int float64_is_signaling_nan(float64 a_, float_status *= status) return (((a >> 51) & 0xFFF) =3D=3D 0xFFE) && (a & LIT64(0x0007FFFFFFFFFFFF)); } -} #endif +} =20 /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the double-precision floating point value `a' is a @@ -899,17 +887,6 @@ static float64 propagateFloat64NaN(float64 a, float64 = b, float_status *status) } } =20 -#ifdef NO_SIGNALING_NANS -int floatx80_is_quiet_nan(floatx80 a_, float_status *status) -{ - return floatx80_is_any_nan(a_); -} - -int floatx80_is_signaling_nan(floatx80 a_, float_status *status) -{ - return 0; -} -#else /*------------------------------------------------------------------------= ---- | Returns 1 if the extended double-precision floating-point value `a' is a | quiet NaN; otherwise returns 0. This slightly differs from the same @@ -918,6 +895,9 @@ int floatx80_is_signaling_nan(floatx80 a_, float_status= *status) =20 int floatx80_is_quiet_nan(floatx80 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return floatx80_is_any_nan(a); +#else if (status->snan_bit_is_one) { uint64_t aLow; =20 @@ -929,6 +909,7 @@ int floatx80_is_quiet_nan(floatx80 a, float_status *sta= tus) return ((a.high & 0x7FFF) =3D=3D 0x7FFF) && (LIT64(0x8000000000000000) <=3D ((uint64_t)(a.low << 1))); } +#endif } =20 /*------------------------------------------------------------------------= ---- @@ -939,6 +920,9 @@ int floatx80_is_quiet_nan(floatx80 a, float_status *sta= tus) =20 int floatx80_is_signaling_nan(floatx80 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else if (status->snan_bit_is_one) { return ((a.high & 0x7FFF) =3D=3D 0x7FFF) && ((a.low << 1) >=3D 0x8000000000000000ULL); @@ -950,8 +934,8 @@ int floatx80_is_signaling_nan(floatx80 a, float_status = *status) && (uint64_t)(aLow << 1) && (a.low =3D=3D aLow); } -} #endif +} =20 /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the extended double-precision floating point value @@ -1060,17 +1044,6 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b= , float_status *status) } } =20 -#ifdef NO_SIGNALING_NANS -int float128_is_quiet_nan(float128 a_, float_status *status) -{ - return float128_is_any_nan(a_); -} - -int float128_is_signaling_nan(float128 a_, float_status *status) -{ - return 0; -} -#else /*------------------------------------------------------------------------= ---- | Returns 1 if the quadruple-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -1078,6 +1051,9 @@ int float128_is_signaling_nan(float128 a_, float_stat= us *status) =20 int float128_is_quiet_nan(float128 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float128_is_any_nan(a); +#else if (status->snan_bit_is_one) { return (((a.high >> 47) & 0xFFFF) =3D=3D 0xFFFE) && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); @@ -1085,6 +1061,7 @@ int float128_is_quiet_nan(float128 a, float_status *s= tatus) return ((a.high << 1) >=3D 0xFFFF000000000000ULL) && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); } +#endif } =20 /*------------------------------------------------------------------------= ---- @@ -1094,6 +1071,9 @@ int float128_is_quiet_nan(float128 a, float_status *s= tatus) =20 int float128_is_signaling_nan(float128 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else if (status->snan_bit_is_one) { return ((a.high << 1) >=3D 0xFFFF000000000000ULL) && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); @@ -1101,8 +1081,8 @@ int float128_is_signaling_nan(float128 a, float_statu= s *status) return (((a.high >> 47) & 0xFFFF) =3D=3D 0xFFFE) && (a.low || (a.high & LIT64(0x00007FFFFFFFFFFF))); } -} #endif +} =20 /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the quadruple-precision floating point value `a' = is --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152642406908111.86770056444027; Tue, 15 May 2018 15:41:09 -0700 (PDT) Received: from localhost ([::1]:36388 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIid2-00062f-6Y for importer@patchew.org; Tue, 15 May 2018 18:41:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39493) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOH-0003IJ-Et for qemu-devel@nongnu.org; Tue, 15 May 2018 18:25:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOE-0003pY-O5 for qemu-devel@nongnu.org; Tue, 15 May 2018 18:25:53 -0400 Received: from mail-pf0-x232.google.com ([2607:f8b0:400e:c00::232]:43860) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOE-0003ic-8V for qemu-devel@nongnu.org; Tue, 15 May 2018 18:25:50 -0400 Received: by mail-pf0-x232.google.com with SMTP id j20-v6so732607pff.10 for ; Tue, 15 May 2018 15:25:50 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.25.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:25:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aWGAG4VepTBKKjzXJ8krtoY3A2cSRVVZvpCgb6Q0Vj8=; b=fmF/lZZN0ugNj7NLGUL0BqsGVEgI0nJBe7wiTr9EUi8nZtngkK7OAoeKO02VyR5rwH 8V+z7Vt9usRIfzY6PpYiBFhakjTtiWbfqPk+7Z/8VvZscC1O5Eb91btGS8PNux3B7lZ3 fapIyxuL+uje3jTiIsmv2KX3rPDxGavgVC5bU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aWGAG4VepTBKKjzXJ8krtoY3A2cSRVVZvpCgb6Q0Vj8=; b=Fa2tJVfQaY68ZW4z1dl7CjrDtU25wa2C5+c5t5YMADMJSSDBLp3iY9IwVyNEOkRCgB 5mnz38NOf2ihdWWjFz56iN1DL+txeWAZXE7EyOIgIQyhzTAKOz8bMB3yF5RjqGRBY6wV Nni7LEHX2Ho7F9T7/GZ6SmXKBC3yEXDRo+Pjh2vI7qF0SKxbfFAgWMbkvrIxVanJl81a PJ74fVO3gCf2nluY0rCu5RJit/CSjdvXkhNtDtdf/4/xtKnVwdgkGaVk1ZH/X8UGNZt0 s5Aw1DrvExnckxInw8g3RNMmcHNdca+eOphCVHVNRyybQqM3VWTsaZH0+pCFiI5uzbG3 jzlw== X-Gm-Message-State: ALKqPweXA3tKGvequC82EkRRiIVj/TJOrPnmYUuY0oOj4qHAAr1dsi6Q QLcHxyt9/f8zH9QKHw7gHOmxGHFl4tk= X-Google-Smtp-Source: AB8JxZrEWVxvZofM0qPheJfZy9Xjh8wp3Ca42Na3DGpoAPI4HcTsTmHV3kEOittw5SBN64PZ9SNcZQ== X-Received: by 2002:a63:3286:: with SMTP id y128-v6mr14005084pgy.419.1526423148482; Tue, 15 May 2018 15:25:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:15 -0700 Message-Id: <20180515222540.9988-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::232 Subject: [Qemu-devel] [PATCH v6 03/28] fpu/softfloat: Split floatXX_silence_nan from floatXX_maybe_silence_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 The new function assumes that the input is an SNaN and does not double-check. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 174 +++++++++++++++++++++++++------------ include/fpu/softfloat.h | 5 ++ 2 files changed, 123 insertions(+), 56 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 58b05718c8..4fc9ea4ac0 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -271,22 +271,35 @@ int float16_is_signaling_nan(float16 a_, float_status= *status) #endif } =20 +/*------------------------------------------------------------------------= ---- +| Returns a quiet NaN from a signalling NaN for the half-precision +| floating point value `a'. +*-------------------------------------------------------------------------= ---*/ + +float16 float16_silence_nan(float16 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { + return float16_default_nan(status); + } else { + return a | (1 << 9); + } +#endif +} + /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the half-precision floating point value `a' is a | signaling NaN; otherwise returns `a'. *-------------------------------------------------------------------------= ---*/ -float16 float16_maybe_silence_nan(float16 a_, float_status *status) + +float16 float16_maybe_silence_nan(float16 a, float_status *status) { - if (float16_is_signaling_nan(a_, status)) { - if (status->snan_bit_is_one) { - return float16_default_nan(status); - } else { - uint16_t a =3D float16_val(a_); - a |=3D (1 << 9); - return make_float16(a); - } + if (float16_is_signaling_nan(a, status)) { + return float16_silence_nan(a, status); } - return a_; + return a; } =20 /*------------------------------------------------------------------------= ---- @@ -367,30 +380,40 @@ int float32_is_signaling_nan(float32 a_, float_status= *status) #endif } =20 +/*------------------------------------------------------------------------= ---- +| Returns a quiet NaN from a signalling NaN for the single-precision +| floating point value `a'. +*-------------------------------------------------------------------------= ---*/ + +float32 float32_silence_nan(float32 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { +# ifdef TARGET_HPPA + a &=3D ~0x00400000; + a |=3D 0x00200000; + return a; +# else + return float32_default_nan(status); +# endif + } else { + return a | (1 << 22); + } +#endif +} /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the single-precision floating point value `a' is a | signaling NaN; otherwise returns `a'. *-------------------------------------------------------------------------= ---*/ =20 -float32 float32_maybe_silence_nan(float32 a_, float_status *status) +float32 float32_maybe_silence_nan(float32 a, float_status *status) { - if (float32_is_signaling_nan(a_, status)) { - if (status->snan_bit_is_one) { -#ifdef TARGET_HPPA - uint32_t a =3D float32_val(a_); - a &=3D ~0x00400000; - a |=3D 0x00200000; - return make_float32(a); -#else - return float32_default_nan(status); -#endif - } else { - uint32_t a =3D float32_val(a_); - a |=3D (1 << 22); - return make_float32(a); - } + if (float32_is_signaling_nan(a, status)) { + return float32_silence_nan(a, status); } - return a_; + return a; } =20 /*------------------------------------------------------------------------= ---- @@ -776,30 +799,41 @@ int float64_is_signaling_nan(float64 a_, float_status= *status) #endif } =20 +/*------------------------------------------------------------------------= ---- +| Returns a quiet NaN from a signalling NaN for the double-precision +| floating point value `a'. +*-------------------------------------------------------------------------= ---*/ + +float64 float64_silence_nan(float64 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { +# ifdef TARGET_HPPA + a &=3D ~0x0008000000000000ULL; + a |=3D 0x0004000000000000ULL; + return a; +# else + return float64_default_nan(status); +# endif + } else { + return a | LIT64(0x0008000000000000); + } +#endif +} + /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the double-precision floating point value `a' is a | signaling NaN; otherwise returns `a'. *-------------------------------------------------------------------------= ---*/ =20 -float64 float64_maybe_silence_nan(float64 a_, float_status *status) +float64 float64_maybe_silence_nan(float64 a, float_status *status) { - if (float64_is_signaling_nan(a_, status)) { - if (status->snan_bit_is_one) { -#ifdef TARGET_HPPA - uint64_t a =3D float64_val(a_); - a &=3D ~0x0008000000000000ULL; - a |=3D 0x0004000000000000ULL; - return make_float64(a); -#else - return float64_default_nan(status); -#endif - } else { - uint64_t a =3D float64_val(a_); - a |=3D LIT64(0x0008000000000000); - return make_float64(a); - } + if (float64_is_signaling_nan(a, status)) { + return float64_silence_nan(a, status); } - return a_; + return a; } =20 /*------------------------------------------------------------------------= ---- @@ -937,6 +971,25 @@ int floatx80_is_signaling_nan(floatx80 a, float_status= *status) #endif } =20 +/*------------------------------------------------------------------------= ---- +| Returns a quiet NaN from a signalling NaN for the extended double-precis= ion +| floating point value `a'. +*-------------------------------------------------------------------------= ---*/ + +floatx80 floatx80_silence_nan(floatx80 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { + return floatx80_default_nan(status); + } else { + a.low |=3D LIT64(0xC000000000000000); + return a; + } +#endif +} + /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the extended double-precision floating point value | `a' is a signaling NaN; otherwise returns `a'. @@ -945,12 +998,7 @@ int floatx80_is_signaling_nan(floatx80 a, float_status= *status) floatx80 floatx80_maybe_silence_nan(floatx80 a, float_status *status) { if (floatx80_is_signaling_nan(a, status)) { - if (status->snan_bit_is_one) { - a =3D floatx80_default_nan(status); - } else { - a.low |=3D LIT64(0xC000000000000000); - return a; - } + return floatx80_silence_nan(a, status); } return a; } @@ -1084,6 +1132,25 @@ int float128_is_signaling_nan(float128 a, float_stat= us *status) #endif } =20 +/*------------------------------------------------------------------------= ---- +| Returns a quiet NaN from a signalling NaN for the quadruple-precision +| floating point value `a'. +*-------------------------------------------------------------------------= ---*/ + +float128 float128_silence_nan(float128 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { + return float128_default_nan(status); + } else { + a.high |=3D LIT64(0x0000800000000000); + return a; + } +#endif +} + /*------------------------------------------------------------------------= ---- | Returns a quiet NaN if the quadruple-precision floating point value `a' = is | a signaling NaN; otherwise returns `a'. @@ -1092,12 +1159,7 @@ int float128_is_signaling_nan(float128 a, float_stat= us *status) float128 float128_maybe_silence_nan(float128 a, float_status *status) { if (float128_is_signaling_nan(a, status)) { - if (status->snan_bit_is_one) { - a =3D float128_default_nan(status); - } else { - a.high |=3D LIT64(0x0000800000000000); - return a; - } + return float128_silence_nan(a, status); } return a; } diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 36626a501b..43962dc3f5 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -257,6 +257,7 @@ int float16_compare_quiet(float16, float16, float_statu= s *status); =20 int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); +float16 float16_silence_nan(float16, float_status *status); float16 float16_maybe_silence_nan(float16, float_status *status); =20 static inline int float16_is_any_nan(float16 a) @@ -368,6 +369,7 @@ float32 float32_minnummag(float32, float32, float_statu= s *status); float32 float32_maxnummag(float32, float32, float_status *status); int float32_is_quiet_nan(float32, float_status *status); int float32_is_signaling_nan(float32, float_status *status); +float32 float32_silence_nan(float32, float_status *status); float32 float32_maybe_silence_nan(float32, float_status *status); float32 float32_scalbn(float32, int, float_status *status); =20 @@ -497,6 +499,7 @@ float64 float64_minnummag(float64, float64, float_statu= s *status); float64 float64_maxnummag(float64, float64, float_status *status); int float64_is_quiet_nan(float64 a, float_status *status); int float64_is_signaling_nan(float64, float_status *status); +float64 float64_silence_nan(float64, float_status *status); float64 float64_maybe_silence_nan(float64, float_status *status); float64 float64_scalbn(float64, int, float_status *status); =20 @@ -600,6 +603,7 @@ int floatx80_compare(floatx80, floatx80, float_status *= status); int floatx80_compare_quiet(floatx80, floatx80, float_status *status); int floatx80_is_quiet_nan(floatx80, float_status *status); int floatx80_is_signaling_nan(floatx80, float_status *status); +floatx80 floatx80_silence_nan(floatx80, float_status *status); floatx80 floatx80_maybe_silence_nan(floatx80, float_status *status); floatx80 floatx80_scalbn(floatx80, int, float_status *status); =20 @@ -811,6 +815,7 @@ int float128_compare(float128, float128, float_status *= status); int float128_compare_quiet(float128, float128, float_status *status); int float128_is_quiet_nan(float128, float_status *status); int float128_is_signaling_nan(float128, float_status *status); +float128 float128_silence_nan(float128, float_status *status); float128 float128_maybe_silence_nan(float128, float_status *status); float128 float128_scalbn(float128, int, float_status *status); =20 --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526423703432335.81723045077376; Tue, 15 May 2018 15:35:03 -0700 (PDT) Received: from localhost ([::1]:36350 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiX8-00013a-KC for importer@patchew.org; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.25.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:25:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X0O0oscg2DXfZxWsZs+cPbi2oDfigSQN1qMljqBQmYE=; b=JZVbqzD1j+/xjAJZ3GgGtZBICHS7b/cpBh1KbaCRpJp0/48hHw6KZW+dFHxEhVTI7A 3NM3MCod3/BMWmAMqvzouzEAla+3I60y8B9RQgN0W/N0xKiEnhaYESYc9RC05lQPnYga fPdu31p4aamyzGq9vKTrj/7+NLncjJV+9W+ss= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X0O0oscg2DXfZxWsZs+cPbi2oDfigSQN1qMljqBQmYE=; b=gz/ODzceMKAtlj190rkhGBuk6o/7GUbJu9gqKTH33GxDDmkcgk7t45V408fykifNo0 hYQiwXo6HRdMwv91Mi3/+FSiqLNijS1K7UEoEGLutrUKi/SAJ6laEqit049iOmfo+fC4 I3ZiRAvSgc4olldHxhaW7Opn5BrxswURyJX4DAo7H/vQPScVLdEiimRKmWeBz+Zdle53 gD3ugD4z1F83g1xpW6ddoA0DIOSi6+FEzspoDlo+SMTpFWOhMKVOLWQ1ohVZ6WazuO68 f2gvTBKV23F6HUaO9Mc++J55tdIH2aH97pp1vqW+2o+YaM7HoWqiR0oa+g+p67LZqsGk GLpg== X-Gm-Message-State: ALKqPwemGJ6hmxiZaJCJ0M0HvcheKyXtF95By6I66L3/qZnu4cdpXdrK l7TaRjFiRSmUkF7OGiKJF45032Vt49g= X-Google-Smtp-Source: AB8JxZoXduF85uDMftsKLxS13Nl0/1eJJazqxJPBosfWnmqNCz7RCBwgIlLgujoqx9tdbpejCxfQZw== X-Received: by 2002:a65:438a:: with SMTP id m10-v6mr11887878pgp.315.1526423149796; Tue, 15 May 2018 15:25:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:16 -0700 Message-Id: <20180515222540.9988-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v6 04/28] fpu/softfloat: Move softfloat-specialize.h below FloatParts definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 We want to be able to specialize on the canonical representation. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index d07419324a..0d17027379 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -95,16 +95,6 @@ this code that are retained. *-------------------------------------------------------------------------= ---*/ #include "fpu/softfloat-macros.h" =20 -/*------------------------------------------------------------------------= ---- -| Functions and definitions to determine: (1) whether tininess for underf= low -| is detected before or after rounding by default, (2) what (if anything) -| happens when exceptions are raised, (3) how signaling NaNs are distingui= shed -| from quiet NaNs, (4) the default generated quiet NaNs, and (5) how NaNs -| are propagated from function inputs to output. These details are target- -| specific. -*-------------------------------------------------------------------------= ---*/ -#include "softfloat-specialize.h" - /*------------------------------------------------------------------------= ---- | Returns the fraction bits of the half-precision floating-point value `a'. *-------------------------------------------------------------------------= ---*/ @@ -322,6 +312,16 @@ static inline float64 float64_pack_raw(FloatParts p) return make_float64(pack_raw(float64_params, p)); } =20 +/*------------------------------------------------------------------------= ---- +| Functions and definitions to determine: (1) whether tininess for underf= low +| is detected before or after rounding by default, (2) what (if anything) +| happens when exceptions are raised, (3) how signaling NaNs are distingui= shed +| from quiet NaNs, (4) the default generated quiet NaNs, and (5) how NaNs +| are propagated from function inputs to output. These details are target- +| specific. +*-------------------------------------------------------------------------= ---*/ +#include "softfloat-specialize.h" + /* Canonicalize EXP and FRAC, setting CLS. */ static FloatParts canonicalize(FloatParts part, const FloatFmt *parm, float_status *status) --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152642388803195.17027267817332; Tue, 15 May 2018 15:38:08 -0700 (PDT) Received: from localhost ([::1]:36370 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIia7-0003WP-84 for importer@patchew.org; Tue, 15 May 2018 18:38:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39511) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOI-0003JZ-Sw for qemu-devel@nongnu.org; Tue, 15 May 2018 18:25:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOG-00044g-Jt for qemu-devel@nongnu.org; Tue, 15 May 2018 18:25:54 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:40241) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOG-0003yh-Ck for qemu-devel@nongnu.org; Tue, 15 May 2018 18:25:52 -0400 Received: by mail-pf0-x241.google.com with SMTP id f189-v6so736075pfa.7 for ; Tue, 15 May 2018 15:25:52 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.25.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:25:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/xl8f2zQlEINP9lneuf7ucQwkBVVFUmq+tNHsXqCle4=; b=KAks+qfNdDptnN3Gu5xQRRh+cEDmQWZ3Tf7fObac4IOVwGW4WgIG35YwO2ao5yXWPm rdOrtu+OrKiinPfCU/zp48QLUUA7wEFG82bZg+fLQRKh7IhdGuuarR49jrfQ5dsu34wP DRuT10BaRIzFSXIkUp5GByi67VI/x/esQGI5I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/xl8f2zQlEINP9lneuf7ucQwkBVVFUmq+tNHsXqCle4=; b=KqgDRmGZZokACbu2p8ZUe0KZam4W+mlpVxY+odOcY9D7CMnlbl2h8kWIY2WMPtPrbx XYM7U2I5M++QA2j1thB/htgWyRK6czV70Ry0U+tHVLHrOCXDH/DrIBJ0rTW5nw6MjLag dCGEiR4+Uq6iGJn4vCyDfIBRNcEDlQMdet7mjDfxShF8ELM/c898XNIFwqsNIHHPDp9P /KWZqzDej5ntOYP1NwDvrPTlJbATHWeRoLE4/pScuqk9twz2gr9csP9SlLgq3Bf5cXBL KePlMSTQGEJeMyOoKrmVGsmMiDYoGhNoEeroemuJqNwnii5edrsbjbDDeY/1mCO7uUgm 1yew== X-Gm-Message-State: ALKqPwfeRqrmI+G1epo6LWsYd2S18NK48y4AxKqLqoInSv4u5rKesX9Z vGrw/H9YSZ/rl4wLHbMywqQkE1er79A= X-Google-Smtp-Source: AB8JxZqbxqFjKeYGGDHryWVZOGrFLuJXe93w34aPAodDwol9jIm/K2VW4JHQjyEPy0j3seJkcdX2wA== X-Received: by 2002:a63:bd49:: with SMTP id d9-v6mr13963324pgp.14.1526423151110; Tue, 15 May 2018 15:25:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:17 -0700 Message-Id: <20180515222540.9988-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v6 05/28] fpu/softfloat: Canonicalize NaN fraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Shift the NaN fraction to a canonical position, much like we do for the fraction of normal numbers. This will facilitate manipulation of NaNs within the shared code paths. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 0d17027379..607c4a78d5 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -330,10 +330,11 @@ static FloatParts canonicalize(FloatParts part, const= FloatFmt *parm, if (part.frac =3D=3D 0) { part.cls =3D float_class_inf; } else { + part.frac <<=3D parm->frac_shift; #ifdef NO_SIGNALING_NANS part.cls =3D float_class_qnan; #else - int64_t msb =3D part.frac << (parm->frac_shift + 2); + int64_t msb =3D part.frac << 2; if ((msb < 0) =3D=3D status->snan_bit_is_one) { part.cls =3D float_class_snan; } else { @@ -480,6 +481,7 @@ static FloatParts round_canonical(FloatParts p, float_s= tatus *s, case float_class_qnan: case float_class_snan: exp =3D exp_max; + frac >>=3D parm->frac_shift; break; =20 default: @@ -503,6 +505,7 @@ static float16 float16_round_pack_canonical(FloatParts = p, float_status *s) case float_class_dnan: return float16_default_nan(s); case float_class_msnan: + p.frac >>=3D float16_params.frac_shift; return float16_maybe_silence_nan(float16_pack_raw(p), s); default: p =3D round_canonical(p, s, &float16_params); @@ -521,6 +524,7 @@ static float32 float32_round_pack_canonical(FloatParts = p, float_status *s) case float_class_dnan: return float32_default_nan(s); case float_class_msnan: + p.frac >>=3D float32_params.frac_shift; return float32_maybe_silence_nan(float32_pack_raw(p), s); default: p =3D round_canonical(p, s, &float32_params); @@ -539,6 +543,7 @@ static float64 float64_round_pack_canonical(FloatParts = p, float_status *s) case float_class_dnan: return float64_default_nan(s); case float_class_msnan: + p.frac >>=3D float64_params.frac_shift; return float64_maybe_silence_nan(float64_pack_raw(p), s); default: p =3D round_canonical(p, s, &float64_params); --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526423295761330.86384923990795; Tue, 15 May 2018 15:28:15 -0700 (PDT) Received: from localhost ([::1]:36315 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiQY-0004eg-TS for importer@patchew.org; Tue, 15 May 2018 18:28:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39526) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOK-0003KU-1E for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOH-0004Cv-Qk for qemu-devel@nongnu.org; Tue, 15 May 2018 18:25:55 -0400 Received: from mail-pl0-x22d.google.com ([2607:f8b0:400e:c01::22d]:32834) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOH-00048Z-Jl for qemu-devel@nongnu.org; Tue, 15 May 2018 18:25:53 -0400 Received: by mail-pl0-x22d.google.com with SMTP id n10-v6so872861plp.0 for ; Tue, 15 May 2018 15:25:53 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c01::22d Subject: [Qemu-devel] [PATCH v6 06/28] fpu/softfloat: Introduce parts_is_snan_frac X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 15 +++++++++++++++ fpu/softfloat.c | 12 ++---------- 2 files changed, 17 insertions(+), 10 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 4fc9ea4ac0..515cb12cfa 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -86,6 +86,21 @@ this code that are retained. #define NO_SIGNALING_NANS 1 #endif =20 +/*------------------------------------------------------------------------= ---- +| For the deconstructed floating-point with fraction FRAC, return true +| if the fraction represents a signalling NaN; otherwise false. +*-------------------------------------------------------------------------= ---*/ + +static bool parts_is_snan_frac(uint64_t frac, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + return false; +#else + flag msb =3D extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); + return msb =3D=3D status->snan_bit_is_one; +#endif +} + /*------------------------------------------------------------------------= ---- | The pattern for a default generated half-precision NaN. *-------------------------------------------------------------------------= ---*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 607c4a78d5..19f40d6932 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -331,16 +331,8 @@ static FloatParts canonicalize(FloatParts part, const = FloatFmt *parm, part.cls =3D float_class_inf; } else { part.frac <<=3D parm->frac_shift; -#ifdef NO_SIGNALING_NANS - part.cls =3D float_class_qnan; -#else - int64_t msb =3D part.frac << 2; - if ((msb < 0) =3D=3D status->snan_bit_is_one) { - part.cls =3D float_class_snan; - } else { - part.cls =3D float_class_qnan; - } -#endif + part.cls =3D (parts_is_snan_frac(part.frac, status) + ? float_class_snan : float_class_qnan); } } else if (part.exp =3D=3D 0) { if (likely(part.frac =3D=3D 0)) { --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152642353455680.77595212379401; Tue, 15 May 2018 15:32:14 -0700 (PDT) Received: from localhost ([::1]:36336 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiUP-0007Wf-Gc for importer@patchew.org; Tue, 15 May 2018 18:32:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39548) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOL-0003KW-VB for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOJ-0004PJ-FN for qemu-devel@nongnu.org; Tue, 15 May 2018 18:25:57 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:36933) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOJ-0004JQ-4g for qemu-devel@nongnu.org; Tue, 15 May 2018 18:25:55 -0400 Received: by mail-pf0-x244.google.com with SMTP id e9-v6so739347pfi.4 for ; Tue, 15 May 2018 15:25:55 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.25.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:25:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lJnCZDN0PRg9xnf5HrS6QJvF08nF0qG9pJRnCl2JME0=; b=Nf9zkxJ5RDlyPIuT9firO8DjwrDeKN2I+yooIJ3EzUe4PGhBE26HlAK2yltIGMmnpE JzGgR6rOww4/bmN1LstDK89zg4pufqkvjwohkXqZyMMZa4Gutexxsw9unqTtxCC8muGc gi3kcq1CRnYUyo79WCq8lM0eCnpdYfG5lep7Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lJnCZDN0PRg9xnf5HrS6QJvF08nF0qG9pJRnCl2JME0=; b=Yi/EvqEI0ro1hizGQJ8dURolDx8QseAc8vmvotKDmeUozS+gLSRG/uE/0Csjl9RYtT q3IpuSRFtMUeAlaXi4AKKEWy+l50qquDUAZQbYsYFfR47B6F5TOfo5DVD9cM9Pnb6Sd3 NGgo2HefxNktQOx5K54UWnhrwByQbLT6csJZlv3+ga0kDJwPyke4ZomDWs1qZY47q3pK QVbmSOZMMZM07H6vW7B5ER/bjuDxAewxP57slLiwLbC5UH9KJXB6x7uMDHkmvIGfRH7L QskbE2BCuudGXHGdQ7CcsbV7thsbZZO1Lps7YYSdDtokwZs+AmBPfjfnQ691DQ/lad5e 2crg== X-Gm-Message-State: ALKqPwcb6GF3xWUoPNNFMRTwfUGgu76HrkWvRzgdZtFKoBCcWG2FLYfp ljPEKG3KffyGgH9xX0nAA+mx4d3suRM= X-Google-Smtp-Source: AB8JxZoYPcNQJdu0QFminFS2S+9y6MGRABbgml48OsK59Qm9MyrBHnFcQxLMTqlU5fBzhQhBvvMHTQ== X-Received: by 2002:a62:4086:: with SMTP id f6-v6mr16766476pfd.194.1526423153827; Tue, 15 May 2018 15:25:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:19 -0700 Message-Id: <20180515222540.9988-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v6 07/28] fpu/softfloat: Replace float_class_dnan with parts_default_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 With a canonical representation of NaNs, we can return the default nan directly rather than delay the expansion until the final format is known. Note one case where we uselessly assigned to a.sign, which was overwritten/ignored later when expanding float_class_dnan. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 37 +++++++++++++++++++++++++++++++++++++ fpu/softfloat.c | 38 +++++++++++--------------------------- 2 files changed, 48 insertions(+), 27 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 515cb12cfa..0d3d81a52b 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -101,6 +101,43 @@ static bool parts_is_snan_frac(uint64_t frac, float_st= atus *status) #endif } =20 +/*------------------------------------------------------------------------= ---- +| The pattern for a default generated deconstructed floating-point NaN. +*-------------------------------------------------------------------------= ---*/ + +static FloatParts parts_default_nan(float_status *status) +{ + bool sign =3D 0; + uint64_t frac; + +#if defined(TARGET_SPARC) || defined(TARGET_M68K) + frac =3D (1ULL << DECOMPOSED_BINARY_POINT) - 1; +#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) = || \ + defined(TARGET_S390X) || defined(TARGET_RISCV) + frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); +#elif defined(TARGET_HPPA) + frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); +#else + if (status->snan_bit_is_one) { + frac =3D (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; + } else { +#if defined(TARGET_MIPS) + frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); +#else + frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); + sign =3D 1; +#endif + } +#endif + + return (FloatParts) { + .cls =3D float_class_qnan, + .sign =3D sign, + .exp =3D INT_MAX, + .frac =3D frac + }; +} + /*------------------------------------------------------------------------= ---- | The pattern for a default generated half-precision NaN. *-------------------------------------------------------------------------= ---*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 19f40d6932..51780b718f 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -188,7 +188,6 @@ typedef enum __attribute__ ((__packed__)) { float_class_inf, float_class_qnan, /* all NaNs from here */ float_class_snan, - float_class_dnan, float_class_msnan, /* maybe silenced */ } FloatClass; =20 @@ -494,8 +493,6 @@ static FloatParts float16_unpack_canonical(float16 f, f= loat_status *s) static float16 float16_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float16_default_nan(s); case float_class_msnan: p.frac >>=3D float16_params.frac_shift; return float16_maybe_silence_nan(float16_pack_raw(p), s); @@ -513,8 +510,6 @@ static FloatParts float32_unpack_canonical(float32 f, f= loat_status *s) static float32 float32_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float32_default_nan(s); case float_class_msnan: p.frac >>=3D float32_params.frac_shift; return float32_maybe_silence_nan(float32_pack_raw(p), s); @@ -532,8 +527,6 @@ static FloatParts float64_unpack_canonical(float64 f, f= loat_status *s) static float64 float64_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float64_default_nan(s); case float_class_msnan: p.frac >>=3D float64_params.frac_shift; return float64_maybe_silence_nan(float64_pack_raw(p), s); @@ -566,7 +559,7 @@ static FloatParts return_nan(FloatParts a, float_status= *s) /* fall through */ case float_class_qnan: if (s->default_nan_mode) { - a.cls =3D float_class_dnan; + return parts_default_nan(s); } break; =20 @@ -583,7 +576,7 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, = float_status *s) } =20 if (s->default_nan_mode) { - a.cls =3D float_class_dnan; + return parts_default_nan(s); } else { if (pickNaN(is_qnan(a.cls), is_snan(a.cls), is_qnan(b.cls), is_snan(b.cls), @@ -614,8 +607,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatPa= rts b, FloatParts c, /* Note that this check is after pickNaNMulAdd so that function * has an opportunity to set the Invalid flag. */ - a.cls =3D float_class_dnan; - return a; + which =3D 3; } =20 switch (which) { @@ -628,8 +620,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatPa= rts b, FloatParts c, a =3D c; break; case 3: - a.cls =3D float_class_dnan; - return a; + return parts_default_nan(s); default: g_assert_not_reached(); } @@ -682,7 +673,7 @@ static FloatParts addsub_floats(FloatParts a, FloatPart= s b, bool subtract, if (a.cls =3D=3D float_class_inf) { if (b.cls =3D=3D float_class_inf) { float_raise(float_flag_invalid, s); - a.cls =3D float_class_dnan; + return parts_default_nan(s); } return a; } @@ -828,9 +819,7 @@ static FloatParts mul_floats(FloatParts a, FloatParts b= , float_status *s) if ((a.cls =3D=3D float_class_inf && b.cls =3D=3D float_class_zero) || (a.cls =3D=3D float_class_zero && b.cls =3D=3D float_class_inf)) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; - a.sign =3D sign; - return a; + return parts_default_nan(s); } /* Multiply by 0 or Inf */ if (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero) { @@ -908,8 +897,7 @@ static FloatParts muladd_floats(FloatParts a, FloatPart= s b, FloatParts c, =20 if (inf_zero) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; - return a; + return parts_default_nan(s); } =20 if (flags & float_muladd_negate_c) { @@ -933,12 +921,12 @@ static FloatParts muladd_floats(FloatParts a, FloatPa= rts b, FloatParts c, if (c.cls =3D=3D float_class_inf) { if (p_class =3D=3D float_class_inf && p_sign !=3D c.sign) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; + return parts_default_nan(s); } else { a.cls =3D float_class_inf; a.sign =3D c.sign ^ sign_flip; + return a; } - return a; } =20 if (p_class =3D=3D float_class_inf) { @@ -1148,8 +1136,7 @@ static FloatParts div_floats(FloatParts a, FloatParts= b, float_status *s) && (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero)) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; - return a; + return parts_default_nan(s); } /* Inf / x or 0 / x */ if (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero) { @@ -1347,7 +1334,6 @@ static int64_t round_to_int_and_pack(FloatParts in, i= nt rmode, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_dnan: case float_class_msnan: s->float_exception_flags =3D orig_flags | float_flag_invalid; return max; @@ -1439,7 +1425,6 @@ static uint64_t round_to_uint_and_pack(FloatParts in,= int rmode, uint64_t max, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_dnan: case float_class_msnan: s->float_exception_flags =3D orig_flags | float_flag_invalid; return max; @@ -1940,8 +1925,7 @@ static FloatParts sqrt_float(FloatParts a, float_stat= us *s, const FloatFmt *p) } if (a.sign) { s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_dnan; - return a; + return parts_default_nan(s); } if (a.cls =3D=3D float_class_inf) { return a; /* sqrt(+inf) =3D +inf */ --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.25.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:25:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=n043IcTuWLeJOrF4bZrWAR222qKx5CvPEizqYpyknu8=; b=kXb+TbX9LYFrKXDXkFtqLe8gChywchnh7qrLtA5k5qjYyk06SJhBTnFhoPr9Bnlf2l pl9+ID2L05fuplqO/KHfmktu/K7/ATjfASOnyrESblx4DOsvBClURQH99XIQ5IJLyhq5 ZodA7CMwLQ+PrwRlcV/WY6NN7ePz8CeGNgUzw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n043IcTuWLeJOrF4bZrWAR222qKx5CvPEizqYpyknu8=; b=ecb05cYiuKNrB9i/nFtNi3WkgmPWtntGyuOc8G4jBblTILDgylO6k1bEmKLpydD0W0 Wsd0XtTDi4J4Y6q4lIFrVnQcwiiR1ps909drO97GrMQOA1iIQ2MoQtsj0+utml3GxKoE e2pLkSYovbgG9LnemvHBCpDS2Zyij/L9tRi2Gcj+JlaxsFX57uvSZyfTh66YCWJHLN38 qPhStIkhKSBzGJy5YsIWsZbh2io3NfQ/9kvkiId90V/pLaHpEP/LLo9/UgFEkRQDb3Q6 IdyaQBCC8PsDsRniXn/CLT+brRhjMPb28x/Q1H33eB3tNeguZgqA7f8xUIjmrJUKfk2G PPCA== X-Gm-Message-State: ALKqPwdUk9qUR6pia//GLNTM+lzzfV33Yi2xW87dNaE8q222E+V0vcNQ HTt81gOD0HZ5xh20HkoUDROEABLNtOk= X-Google-Smtp-Source: AB8JxZpWH93L7eNTcXCpL0a+0/LQoTjCfMHyTw3fwZ+bp0U+hk1LXljWjik8tokyHj1mXmluIZk2rQ== X-Received: by 2002:a17:902:274a:: with SMTP id j10-v6mr16636167plg.393.1526423155284; Tue, 15 May 2018 15:25:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:20 -0700 Message-Id: <20180515222540.9988-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22a Subject: [Qemu-devel] [PATCH v6 08/28] fpu/softfloat: Replace float_class_msnan with parts_silence_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 With a canonical representation of NaNs, we can silence an SNaN immediately rather than delay until the final format is known. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 23 ++++++++++++++++++++++ fpu/softfloat.c | 40 ++++++++++---------------------------- 2 files changed, 33 insertions(+), 30 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 0d3d81a52b..571d1df378 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -138,6 +138,29 @@ static FloatParts parts_default_nan(float_status *stat= us) }; } =20 +/*------------------------------------------------------------------------= ---- +| Returns a quiet NaN from a signalling NaN for the deconstructed +| floating-point parts. +*-------------------------------------------------------------------------= ---*/ + +static FloatParts parts_silence_nan(FloatParts a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#elif defined(TARGET_HPPA) + a.frac &=3D ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); + a.frac |=3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); +#else + if (status->snan_bit_is_one) { + return parts_default_nan(status); + } else { + a.frac |=3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); + } +#endif + a.cls =3D float_class_qnan; + return a; +} + /*------------------------------------------------------------------------= ---- | The pattern for a default generated half-precision NaN. *-------------------------------------------------------------------------= ---*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 51780b718f..41253c6749 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -188,7 +188,6 @@ typedef enum __attribute__ ((__packed__)) { float_class_inf, float_class_qnan, /* all NaNs from here */ float_class_snan, - float_class_msnan, /* maybe silenced */ } FloatClass; =20 /* @@ -492,14 +491,7 @@ static FloatParts float16_unpack_canonical(float16 f, = float_status *s) =20 static float16 float16_round_pack_canonical(FloatParts p, float_status *s) { - switch (p.cls) { - case float_class_msnan: - p.frac >>=3D float16_params.frac_shift; - return float16_maybe_silence_nan(float16_pack_raw(p), s); - default: - p =3D round_canonical(p, s, &float16_params); - return float16_pack_raw(p); - } + return float16_pack_raw(round_canonical(p, s, &float16_params)); } =20 static FloatParts float32_unpack_canonical(float32 f, float_status *s) @@ -509,14 +501,7 @@ static FloatParts float32_unpack_canonical(float32 f, = float_status *s) =20 static float32 float32_round_pack_canonical(FloatParts p, float_status *s) { - switch (p.cls) { - case float_class_msnan: - p.frac >>=3D float32_params.frac_shift; - return float32_maybe_silence_nan(float32_pack_raw(p), s); - default: - p =3D round_canonical(p, s, &float32_params); - return float32_pack_raw(p); - } + return float32_pack_raw(round_canonical(p, s, &float32_params)); } =20 static FloatParts float64_unpack_canonical(float64 f, float_status *s) @@ -526,14 +511,7 @@ static FloatParts float64_unpack_canonical(float64 f, = float_status *s) =20 static float64 float64_round_pack_canonical(FloatParts p, float_status *s) { - switch (p.cls) { - case float_class_msnan: - p.frac >>=3D float64_params.frac_shift; - return float64_maybe_silence_nan(float64_pack_raw(p), s); - default: - p =3D round_canonical(p, s, &float64_params); - return float64_pack_raw(p); - } + return float64_pack_raw(round_canonical(p, s, &float64_params)); } =20 /* Simple helpers for checking if what NaN we have */ @@ -555,7 +533,7 @@ static FloatParts return_nan(FloatParts a, float_status= *s) switch (a.cls) { case float_class_snan: s->float_exception_flags |=3D float_flag_invalid; - a.cls =3D float_class_msnan; + a =3D parts_silence_nan(a, s); /* fall through */ case float_class_qnan: if (s->default_nan_mode) { @@ -584,7 +562,9 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, = float_status *s) (a.frac =3D=3D b.frac && a.sign < b.sign))) { a =3D b; } - a.cls =3D float_class_msnan; + if (is_snan(a.cls)) { + return parts_silence_nan(a, s); + } } return a; } @@ -624,8 +604,10 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatP= arts b, FloatParts c, default: g_assert_not_reached(); } - a.cls =3D float_class_msnan; =20 + if (is_snan(a.cls)) { + return parts_silence_nan(a, s); + } return a; } =20 @@ -1334,7 +1316,6 @@ static int64_t round_to_int_and_pack(FloatParts in, i= nt rmode, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_msnan: s->float_exception_flags =3D orig_flags | float_flag_invalid; return max; case float_class_inf: @@ -1425,7 +1406,6 @@ static uint64_t round_to_uint_and_pack(FloatParts in,= int rmode, uint64_t max, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_msnan: s->float_exception_flags =3D orig_flags | float_flag_invalid; return max; case float_class_inf: --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.25.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:25:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FEc7SxbeBMZBwLGSDicvRkuUEbfKYvzHDzIo35eVQvA=; b=ebhCaakA8O0DRsSQzNSi4JK9PaJEj0enEtqlSmgf3hAv5frR92xB7Vai4Mcjqt3XYr PTZOqPnZEmzxOeL0GLNJSdqAOrbDooJBbeHIVCTv5tvGqHmZ8iyuYayeNkWv+ONSv86n p5BIFuhTzJ8ZdeKYAbFtdtCnJQ8HUa3gp2hbk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FEc7SxbeBMZBwLGSDicvRkuUEbfKYvzHDzIo35eVQvA=; b=R6ivQGZblsv92hRUouBGXqVQsdpAYMPU8n4bIV6pVTR7CBPLk28Eh/y4t/oW+xiUfP ZWS3Pm6v6+5LgjXP0hLPnrsDlHKWjbVaDg5Q++3C1ecCDqU9kIiTSUF5lcn/NdZ6BybT idXPxiHhMZ3IGnVi5z+VDdrmF2rK3LeCpchxKlxwvyW0x6zc0xRGlCNPqIPvKQXcTcQ0 xBV9SvuKvCZSPoI36o71b7rvF+1liy0gsKogbiPOPTSNCdTSRzKRkrh5QPb+utebKkqs Q2VzVDTxdBAHXBan0b5QEMZgRhJTTe6QAemTAZWYhWOVLUBWrNbsQuPc/XKFCSxGtzZL TGMQ== X-Gm-Message-State: ALKqPwdXwnv8m+enzDD4j0oIPIC1hyRIzbQ8JvoAxbRCL9pjRwtMx7Pm Po5wb3dUSfkfM5wo+7hP9GEbjJ9oZlA= X-Google-Smtp-Source: AB8JxZoar/mNP1zstTWRSAsSX1OJJCUfyQnhVB8kuPEXUTMQtPGaB7xQtywv9NsrdYj6GMy4KTB/Mg== X-Received: by 2002:a63:955e:: with SMTP id t30-v6mr13411639pgn.77.1526423156719; Tue, 15 May 2018 15:25:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:21 -0700 Message-Id: <20180515222540.9988-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22b Subject: [Qemu-devel] [PATCH v6 09/28] target/arm: convert conversion helpers to fpst/ahp_flag X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e Instead of passing env and leaving it up to the helper to get the right fpstatus we pass it explicitly. There was already a get_fpstatus helper for neon for the 32 bit code. We also add an get_ahp_flag() for passing the state of the alternative FP16 format flag. This leaves scope for later tracking the AHP state in translation flags. Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- v4 - remove neon_fcvt_*; they are now identical to vfp_fcvt_*. - add flags to vfp_fcvt_* helper decls. - add some missing tcg_temp_free_*. v5 - always use get_fpstatus_ptr(false) for FZ, since FZ16 is supposed to be supressed. v6 - really always use get_fpstatus_ptr(false). --- target/arm/helper.h | 10 +++--- target/arm/translate.h | 12 +++++++ target/arm/helper.c | 56 +++++------------------------ target/arm/translate-a64.c | 37 +++++++++++++++---- target/arm/translate.c | 74 +++++++++++++++++++++++++++++--------- 5 files changed, 112 insertions(+), 77 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index ce89968b2d..047f3bc1ca 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -187,12 +187,10 @@ DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr) DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env) =20 -DEF_HELPER_2(vfp_fcvt_f16_to_f32, f32, i32, env) -DEF_HELPER_2(vfp_fcvt_f32_to_f16, i32, f32, env) -DEF_HELPER_2(neon_fcvt_f16_to_f32, f32, i32, env) -DEF_HELPER_2(neon_fcvt_f32_to_f16, i32, f32, env) -DEF_HELPER_FLAGS_2(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, i32, env) -DEF_HELPER_FLAGS_2(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, i32, f64, env) +DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, ptr, i3= 2) +DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, ptr, i3= 2) +DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, ptr, i3= 2) +DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, ptr, i3= 2) =20 DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, ptr) DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr) diff --git a/target/arm/translate.h b/target/arm/translate.h index 37a1bba056..45f04244be 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -177,4 +177,16 @@ void arm_free_cc(DisasCompare *cmp); void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); void arm_gen_test_cc(int cc, TCGLabel *label); =20 +/* Return state of Alternate Half-precision flag, caller frees result */ +static inline TCGv_i32 get_ahp_flag(void) +{ + TCGv_i32 ret =3D tcg_temp_new_i32(); + + tcg_gen_ld_i32(ret, cpu_env, + offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR])); + tcg_gen_extract_i32(ret, ret, 26, 1); + + return ret; +} + #endif /* TARGET_ARM_TRANSLATE_H */ diff --git a/target/arm/helper.c b/target/arm/helper.c index c6fd7f9479..1762042fc7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11540,64 +11540,24 @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, C= PUARMState *env) } =20 /* Half precision conversions. */ -static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_stat= us *s) +float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_m= ode) { - int ieee =3D (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) =3D=3D 0; - float32 r =3D float16_to_float32(make_float16(a), ieee, s); - if (ieee) { - return float32_maybe_silence_nan(r, s); - } - return r; + return float16_to_float32(a, !ahp_mode, fpstp); } =20 -static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_stat= us *s) +float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_m= ode) { - int ieee =3D (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) =3D=3D 0; - float16 r =3D float32_to_float16(a, ieee, s); - if (ieee) { - r =3D float16_maybe_silence_nan(r, s); - } - return float16_val(r); + return float32_to_float16(a, !ahp_mode, fpstp); } =20 -float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) +float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_m= ode) { - return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status); + return float16_to_float64(a, !ahp_mode, fpstp); } =20 -uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) +float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_m= ode) { - return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status); -} - -float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) -{ - return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status); -} - -uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) -{ - return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); -} - -float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env) -{ - int ieee =3D (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) =3D=3D 0; - float64 r =3D float16_to_float64(make_float16(a), ieee, &env->vfp.fp_s= tatus); - if (ieee) { - return float64_maybe_silence_nan(r, &env->vfp.fp_status); - } - return r; -} - -uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env) -{ - int ieee =3D (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) =3D=3D 0; - float16 r =3D float64_to_float16(a, ieee, &env->vfp.fp_status); - if (ieee) { - r =3D float16_maybe_silence_nan(r, &env->vfp.fp_status); - } - return float16_val(r); + return float64_to_float16(a, !ahp_mode, fpstp); } =20 #define float32_two make_float32(0x40000000) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a0b0c43d12..d8284678f7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5147,10 +5147,15 @@ static void handle_fp_fcvt(DisasContext *s, int opc= ode, } else { /* Single to half */ TCGv_i32 tcg_rd =3D tcg_temp_new_i32(); - gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, cpu_env); + TCGv_i32 ahp =3D get_ahp_flag(); + TCGv_ptr fpst =3D get_fpstatus_ptr(false); + + gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, fpst, ahp); /* write_fp_sreg is OK here because top half of tcg_rd is zero= */ write_fp_sreg(s, rd, tcg_rd); tcg_temp_free_i32(tcg_rd); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); } tcg_temp_free_i32(tcg_rn); break; @@ -5163,9 +5168,13 @@ static void handle_fp_fcvt(DisasContext *s, int opco= de, /* Double to single */ gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env); } else { + TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_i32 ahp =3D get_ahp_flag(); /* Double to half */ - gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, cpu_env); + gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, fpst, ahp); /* write_fp_sreg is OK here because top half of tcg_rd is zero= */ + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(ahp); } write_fp_sreg(s, rd, tcg_rd); tcg_temp_free_i32(tcg_rd); @@ -5175,17 +5184,21 @@ static void handle_fp_fcvt(DisasContext *s, int opc= ode, case 0x3: { TCGv_i32 tcg_rn =3D read_fp_sreg(s, rn); + TCGv_ptr tcg_fpst =3D get_fpstatus_ptr(false); + TCGv_i32 tcg_ahp =3D get_ahp_flag(); tcg_gen_ext16u_i32(tcg_rn, tcg_rn); if (dtype =3D=3D 0) { /* Half to single */ TCGv_i32 tcg_rd =3D tcg_temp_new_i32(); - gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, cpu_env); + gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_a= hp); write_fp_sreg(s, rd, tcg_rd); + tcg_temp_free_ptr(tcg_fpst); + tcg_temp_free_i32(tcg_ahp); tcg_temp_free_i32(tcg_rd); } else { /* Half to double */ TCGv_i64 tcg_rd =3D tcg_temp_new_i64(); - gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, cpu_env); + gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_a= hp); write_fp_dreg(s, rd, tcg_rd); tcg_temp_free_i64(tcg_rd); } @@ -9053,12 +9066,17 @@ static void handle_2misc_narrow(DisasContext *s, bo= ol scalar, } else { TCGv_i32 tcg_lo =3D tcg_temp_new_i32(); TCGv_i32 tcg_hi =3D tcg_temp_new_i32(); + TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_i32 ahp =3D get_ahp_flag(); + tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, tcg_op); - gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, cpu_env); - gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, cpu_env); + gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, fpst, ahp); + gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, fpst, ahp); tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16); tcg_temp_free_i32(tcg_lo); tcg_temp_free_i32(tcg_hi); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(ahp); } break; case 0x56: /* FCVTXN, FCVTXN2 */ @@ -11532,18 +11550,23 @@ static void handle_2misc_widening(DisasContext *s= , int opcode, bool is_q, /* 16 -> 32 bit fp conversion */ int srcelt =3D is_q ? 4 : 0; TCGv_i32 tcg_res[4]; + TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_i32 ahp =3D get_ahp_flag(); =20 for (pass =3D 0; pass < 4; pass++) { tcg_res[pass] =3D tcg_temp_new_i32(); =20 read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_1= 6); gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass], - cpu_env); + fpst, ahp); } for (pass =3D 0; pass < 4; pass++) { write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); tcg_temp_free_i32(tcg_res[pass]); } + + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(ahp); } } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 731cf327a1..613598d090 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3824,38 +3824,56 @@ static int disas_vfp_insn(DisasContext *s, uint32_t= insn) gen_vfp_sqrt(dp); break; case 4: /* vcvtb.f32.f16, vcvtb.f64.f16 */ + { + TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_i32 ahp_mode =3D get_ahp_flag(); tmp =3D gen_vfp_mrs(); tcg_gen_ext16u_i32(tmp, tmp); if (dp) { gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d, tmp, - cpu_env); + fpst, ahp_mode); } else { gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, - cpu_env); + fpst, ahp_mode); } + tcg_temp_free_i32(ahp_mode); + tcg_temp_free_ptr(fpst); tcg_temp_free_i32(tmp); break; + } case 5: /* vcvtt.f32.f16, vcvtt.f64.f16 */ + { + TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_i32 ahp =3D get_ahp_flag(); tmp =3D gen_vfp_mrs(); tcg_gen_shri_i32(tmp, tmp, 16); if (dp) { gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d, tmp, - cpu_env); + fpst, ahp); } else { gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, - cpu_env); + fpst, ahp); } tcg_temp_free_i32(tmp); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); break; + } case 6: /* vcvtb.f16.f32, vcvtb.f16.f64 */ + { + TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_i32 ahp =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); + if (dp) { gen_helper_vfp_fcvt_f64_to_f16(tmp, cpu_F0d, - cpu_env); + fpst, ahp); } else { gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, - cpu_env); + fpst, ahp); } + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); gen_mov_F0_vreg(0, rd); tmp2 =3D gen_vfp_mrs(); tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); @@ -3863,15 +3881,21 @@ static int disas_vfp_insn(DisasContext *s, uint32_t= insn) tcg_temp_free_i32(tmp2); gen_vfp_msr(tmp); break; + } case 7: /* vcvtt.f16.f32, vcvtt.f16.f64 */ + { + TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_i32 ahp =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); if (dp) { gen_helper_vfp_fcvt_f64_to_f16(tmp, cpu_F0d, - cpu_env); + fpst, ahp); } else { gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, - cpu_env); + fpst, ahp); } + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); tcg_gen_shli_i32(tmp, tmp, 16); gen_mov_F0_vreg(0, rd); tmp2 =3D gen_vfp_mrs(); @@ -3880,6 +3904,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) tcg_temp_free_i32(tmp2); gen_vfp_msr(tmp); break; + } case 8: /* cmp */ gen_vfp_cmp(dp); break; @@ -7222,53 +7247,70 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) } break; case NEON_2RM_VCVT_F16_F32: + { + TCGv_ptr fpst; + TCGv_i32 ahp; + if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) || q || (rm & 1)) { return 1; } tmp =3D tcg_temp_new_i32(); tmp2 =3D tcg_temp_new_i32(); + fpst =3D get_fpstatus_ptr(false); + ahp =3D get_ahp_flag(); tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0= )); - gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); + gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, fpst, ahp= ); tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1= )); - gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env= ); + gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, fpst, ah= p); tcg_gen_shli_i32(tmp2, tmp2, 16); tcg_gen_or_i32(tmp2, tmp2, tmp); tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2= )); - gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); + gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, fpst, ahp= ); tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3= )); neon_store_reg(rd, 0, tmp2); tmp2 =3D tcg_temp_new_i32(); - gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env= ); + gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, fpst, ah= p); tcg_gen_shli_i32(tmp2, tmp2, 16); tcg_gen_or_i32(tmp2, tmp2, tmp); neon_store_reg(rd, 1, tmp2); tcg_temp_free_i32(tmp); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); break; + } case NEON_2RM_VCVT_F32_F16: + { + TCGv_ptr fpst; + TCGv_i32 ahp; if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) || q || (rd & 1)) { return 1; } + fpst =3D get_fpstatus_ptr(false); + ahp =3D get_ahp_flag(); tmp3 =3D tcg_temp_new_i32(); tmp =3D neon_load_reg(rm, 0); tmp2 =3D neon_load_reg(rm, 1); tcg_gen_ext16u_i32(tmp3, tmp); - gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env= ); + gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ah= p); tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0= )); tcg_gen_shri_i32(tmp3, tmp, 16); - gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env= ); + gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ah= p); tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1= )); tcg_temp_free_i32(tmp); tcg_gen_ext16u_i32(tmp3, tmp2); - gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env= ); + gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ah= p); tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2= )); tcg_gen_shri_i32(tmp3, tmp2, 16); - gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env= ); + gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ah= p); tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3= )); tcg_temp_free_i32(tmp2); tcg_temp_free_i32(tmp3); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); break; + } case NEON_2RM_AESE: case NEON_2RM_AESMC: if (!arm_dc_feature(s, ARM_FEATURE_V8_AES) || ((rm | rd) & 1)) { --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526423501755447.34436255370997; Tue, 15 May 2018 15:31:41 -0700 (PDT) Received: from localhost ([::1]:36335 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiTs-00079G-Uy for importer@patchew.org; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.25.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:25:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kkdclCQGVBM2KvXTD5izLcmQOYfhQuj8dN6mUZN/37s=; b=koANexULSM5BJWU3oFRtzvo45qGWWnz7iQXmM9aI3Uu32u7/cRqhzMPuclxIkNfoUR 0pedsqtgT0gFtY/mJdTQ1Tzw21z0TjqvXvuzG6cSPXxS5K53Q/7aAUEXqr58VN4Y+iUP Dyai2oUCPS+GCCE6r+K7P6QSeqNY6IhDyTt7I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kkdclCQGVBM2KvXTD5izLcmQOYfhQuj8dN6mUZN/37s=; b=agWg8mMX1/74+B5/FZsOzTCz/VqkYEfq5DRLuDDjMUWNJFHZjMACnv41sUHDm0yn0n h8rhE+IG3uwcO0K4weza7JTEqWsMrUjFWuExfAk7uTgYCwVL470LmR2WH8PQGF8Z+k81 tt2Z8/cYxzwQszgVEc71l0n6Bpsa3Ba4qbSU9/ATG14e/wsEcJ0LQd5+pQ7a/5Pky6rm j1LFyInnGaX6aRxaZKGYPogI566B5Q5ZJHjHm+WybqWUSuL9OGoD9V75+YaNrd0nW7kq gVlWRA8p8A02088GkgfsgLqc/7VtyGNFyGUT9PLyJEFwqGPMAR8FgXZ0Lz66VTzG1AKq 6hvw== X-Gm-Message-State: ALKqPwf5+Ybb/9hoWuYzFu3ZDbZLYr/BNbiXwIfhuR92EWEft2x9YIeM wWv3cufTmfOxD8g3h6J5pyBcfSN2fH4= X-Google-Smtp-Source: AB8JxZonLWTowFPw8vEULhBJNe5ulxdm16QCFNLYrdvRfFp8gqWCKRCwMMva1lW16GfF1ygTj3z+gA== X-Received: by 2002:a65:4b8d:: with SMTP id t13-v6mr12344543pgq.53.1526423158137; Tue, 15 May 2018 15:25:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:22 -0700 Message-Id: <20180515222540.9988-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22e Subject: [Qemu-devel] [PATCH v6 10/28] target/arm: squash FZ16 behaviour for conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e The ARM ARM specifies FZ16 is suppressed for conversions. Rather than pushing this logic into the softfloat code we can simply save the FZ state and temporarily disable it for the softfloat call. Reviewed-by: Peter Maydell Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- v4 - float16_to_floatX squished the wrong softfloat bit for FZ16; need to adjust input denormals in this case. --- target/arm/helper.c | 40 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1762042fc7..238a3ceba8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11542,22 +11542,54 @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, C= PUARMState *env) /* Half precision conversions. */ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_m= ode) { - return float16_to_float32(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing input denormals. + */ + float_status *fpst =3D fpstp; + flag save =3D get_flush_inputs_to_zero(fpst); + set_flush_inputs_to_zero(false, fpst); + float32 r =3D float16_to_float32(a, !ahp_mode, fpst); + set_flush_inputs_to_zero(save, fpst); + return r; } =20 float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_m= ode) { - return float32_to_float16(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing output denormals. + */ + float_status *fpst =3D fpstp; + flag save =3D get_flush_to_zero(fpst); + set_flush_to_zero(false, fpst); + float16 r =3D float32_to_float16(a, !ahp_mode, fpst); + set_flush_to_zero(save, fpst); + return r; } =20 float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_m= ode) { - return float16_to_float64(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing input denormals. + */ + float_status *fpst =3D fpstp; + flag save =3D get_flush_inputs_to_zero(fpst); + set_flush_inputs_to_zero(false, fpst); + float64 r =3D float16_to_float64(a, !ahp_mode, fpst); + set_flush_inputs_to_zero(save, fpst); + return r; } =20 float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_m= ode) { - return float64_to_float16(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing output denormals. + */ + float_status *fpst =3D fpstp; + flag save =3D get_flush_to_zero(fpst); + set_flush_to_zero(false, fpst); + float16 r =3D float64_to_float16(a, !ahp_mode, fpst); + set_flush_to_zero(save, fpst); + return r; } =20 #define float32_two make_float32(0x40000000) --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526424252735730.7149141690198; Tue, 15 May 2018 15:44:12 -0700 (PDT) Received: from localhost ([::1]:36403 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIifw-0008T4-7D for importer@patchew.org; Tue, 15 May 2018 18:44:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39591) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOR-0003S9-2d for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOP-0005Hu-45 for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:03 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:33149) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOO-0005Ah-Py for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:00 -0400 Received: by mail-pf0-x241.google.com with SMTP id a20-v6so745323pfo.0 for ; Tue, 15 May 2018 15:26:00 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.25.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:25:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8WVCgIbaq/jdNQA6d+Wa1CN7e/ZoYkChVYLL1VI8a6s=; b=FvAH2FlJ24p7UqSez5AzYqmFezOP/NiGp+wyN09Wc5YqWK48C3SkajB0qZzetHG4il mRtQI3HlbzViwiCYnwRzU4wUdQLNhnLPePGzAx99XQTumwQihGxy7XgF1bY7VdnFLhP7 L4U0XGI25Qgj7cqswyjn7q+V0YM95RshxUU1A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8WVCgIbaq/jdNQA6d+Wa1CN7e/ZoYkChVYLL1VI8a6s=; b=m1YrxMjj0hDQQTT9kRv1Ak+1RZkcrOIPVq2zhnUB0YGw5SrHH2b82ZqjTaFdt5tyBe YutGC2wimthJRDUzX4zzLSh4tnE11lunVATeD+Bfe68QizmpLVK6Turxfg1P7mIz2zYI C7OERdslg3UQ88v1ENNh0fgPhc4BK3Wd+z3tf0LskvoolTgEz4dLntAfRw4KcnPHloqT b8pY6ssvaX2wZw2SfVzOwXPNSLJa5x2ZbsXXttuDZRK0LIGIAvMxeB3JT3XvIa2NbGsK E1T6nkuuAbVeKAeXyaANeKMowIabDi+olaL+Ce4A0GwFu+6WDLBh8+JJa4eu1frUCvGy /Ebg== X-Gm-Message-State: ALKqPwfjRnEBWh9yKOnCArS/H+Gw1wi/aeDjUbPPlB6IAyoS22wHVOBy cr5hHUgtFqkF0g5N7Nv780VGcK5A+OY= X-Google-Smtp-Source: AB8JxZpMw1Yt7P2nqSyTqpc0PpF/CfrOIFZfdziEH4xVz3et2XAADaFxhG1sHD0BBbynqd0QwOrdxA== X-Received: by 2002:a63:380e:: with SMTP id f14-v6mr6728854pga.242.1526423159515; Tue, 15 May 2018 15:25:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:23 -0700 Message-Id: <20180515222540.9988-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v6 11/28] fpu/softfloat: Partial support for ARM Alternative half-precision X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e For float16 ARM supports an alternative half-precision format which sacrifices the ability to represent NaN/Inf in return for a higher dynamic range. The new FloatFmt flag, arm_althp, is then used to modify the behaviour of canonicalize and round_canonical with respect to representation and exception raising. Usage of this new flag waits until we re-factor float-to-float conversions. Reviewed-by: Peter Maydell Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- v3 - squash NaN to 0 if destination is AHP F16 v4 - handle inf -> ahp max in float_to_float not round_canonical - assert no nan and inf for ahp in round_canonical - check ahp before snan in float_to_float v5 - split out canonicalize and round_canonical changes from the rest --- fpu/softfloat.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 41253c6749..64e1ad4f98 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -220,8 +220,10 @@ typedef struct { * frac_shift: shift to normalise the fraction with DECOMPOSED_BINARY_PO= INT * The following are computed based the size of fraction * frac_lsb: least significant bit of fraction - * fram_lsbm1: the bit bellow the least significant bit (for rounding) + * frac_lsbm1: the bit below the least significant bit (for rounding) * round_mask/roundeven_mask: masks used for rounding + * The following optional modifiers are available: + * arm_althp: handle ARM Alternative Half Precision */ typedef struct { int exp_size; @@ -233,6 +235,7 @@ typedef struct { uint64_t frac_lsbm1; uint64_t round_mask; uint64_t roundeven_mask; + bool arm_althp; } FloatFmt; =20 /* Expand fields based on the size of exponent and fraction */ @@ -324,7 +327,7 @@ static inline float64 float64_pack_raw(FloatParts p) static FloatParts canonicalize(FloatParts part, const FloatFmt *parm, float_status *status) { - if (part.exp =3D=3D parm->exp_max) { + if (part.exp =3D=3D parm->exp_max && !parm->arm_althp) { if (part.frac =3D=3D 0) { part.cls =3D float_class_inf; } else { @@ -413,7 +416,15 @@ static FloatParts round_canonical(FloatParts p, float_= status *s, } frac >>=3D frac_shift; =20 - if (unlikely(exp >=3D exp_max)) { + if (parm->arm_althp) { + /* ARM Alt HP eschews Inf and NaN for a wider exponent. */ + if (unlikely(exp > exp_max)) { + /* Overflow. Return the maximum normal. */ + flags =3D float_flag_invalid; + exp =3D exp_max; + frac =3D -1; + } + } else if (unlikely(exp >=3D exp_max)) { flags |=3D float_flag_overflow | float_flag_inexact; if (overflow_norm) { exp =3D exp_max - 1; @@ -464,12 +475,14 @@ static FloatParts round_canonical(FloatParts p, float= _status *s, =20 case float_class_inf: do_inf: + assert(!parm->arm_althp); exp =3D exp_max; frac =3D 0; break; =20 case float_class_qnan: case float_class_snan: + assert(!parm->arm_althp); exp =3D exp_max; frac >>=3D parm->frac_shift; break; --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526424526449576.1107700483365; Tue, 15 May 2018 15:48:46 -0700 (PDT) Received: from localhost ([::1]:36934 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIikP-0004Mf-H9 for importer@patchew.org; Tue, 15 May 2018 18:48:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39637) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOV-0003Wz-Dr for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOQ-0005Ya-T5 for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:07 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:36273) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOQ-0005QF-Fm for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:02 -0400 Received: by mail-pg0-x242.google.com with SMTP id z70-v6so657621pgz.3 for ; Tue, 15 May 2018 15:26:02 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.25.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:26:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y/TW5tf3KEhdOymukCGMAEV+By3moYUk+jlpzcdfkd4=; b=h0suNwsoiLqHrQwwYO6l8gAEoDCvgf2YxABMGT7AHXN5ea43V5D4KxmBKl3/N62G4/ NYS4l8Ra8hDUFYhMGtM9XtlkvqLOBYOSkYaHSMTl94cg7xnnLGvpLRQsmU29qDPFSM/p yIf8MXEac7u03cVKO6CY1RwdAdP0146D54cmk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y/TW5tf3KEhdOymukCGMAEV+By3moYUk+jlpzcdfkd4=; b=ucO3nmaQnBxnk9BTEG0PV0I+uQ8RUUGrL5XfobCnBFeB5L9lolkFjqRTeS9sm/4qZ7 7PSTWui9c149i3Snk7qM0dVNz9sNZKRzUCYE6Lndu7miuOxdezcCJL0EQBGdDpQe90vD BJapPcto+0znq+mIhPfuquqiNuYMtxXvSRW+LOCUS8YRGxSRQHD/SIlmfMagn+cDoQlj g7yPi+5NOhPMsInMRUrI2nJqspRVY3Vj478W7JSEVuPeWaopiDxv2gBzPPpxx4dMsqjI qSGEEEaHSzNlJ+QL9nGvpqYXWNti9vVLAaqqcifxFNpWKW2XAeA7Jt5HZXFsmf2jjohG o2Dg== X-Gm-Message-State: ALKqPwcLkUrTwZJ1liSuyZJ/tUHKZ34NkMGoLYhxV5H0wcMi1DdV1qtA vHSLSTE4iSVa+k3lJETySwTYGV/XI84= X-Google-Smtp-Source: AB8JxZpS7kJWU8YdOTWvQLTbhyeN9nlDqdiXqQZ2znl7v1FzSj2FbZ/3UvUnhaDOP9VbfMIpdv15aw== X-Received: by 2002:a63:77c9:: with SMTP id s192-v6mr13876374pgc.364.1526423160816; Tue, 15 May 2018 15:26:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:24 -0700 Message-Id: <20180515222540.9988-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v6 12/28] fpu/softfloat: re-factor float to float conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e This allows us to delete a lot of additional boilerplate code which is no longer needed. Reviewed-by: Peter Maydell Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- v2 - pass FloatFmt to float_to_float instead of sizes - split AHP handling to another patch - use rth's suggested re-packing (+ setting .exp) v3 - also rm extractFloat16Sign v4 - update for canonical nan handling v5 - merge arm alt fp16 support into this patch --- fpu/softfloat-specialize.h | 40 --- include/fpu/softfloat.h | 8 +- fpu/softfloat.c | 488 +++++++++---------------------------- 3 files changed, 122 insertions(+), 414 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 571d1df378..995a0132c6 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -377,46 +377,6 @@ float16 float16_maybe_silence_nan(float16 a, float_sta= tus *status) return a; } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the half-precision floating-point NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*-------------------------------------------------------------------------= ---*/ - -static commonNaNT float16ToCommonNaN(float16 a, float_status *status) -{ - commonNaNT z; - - if (float16_is_signaling_nan(a, status)) { - float_raise(float_flag_invalid, status); - } - z.sign =3D float16_val(a) >> 15; - z.low =3D 0; - z.high =3D ((uint64_t) float16_val(a)) << 54; - return z; -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the canonical NaN `a' to the half- -| precision floating-point format. -*-------------------------------------------------------------------------= ---*/ - -static float16 commonNaNToFloat16(commonNaNT a, float_status *status) -{ - uint16_t mantissa =3D a.high >> 54; - - if (status->default_nan_mode) { - return float16_default_nan(status); - } - - if (mantissa) { - return make_float16(((((uint16_t) a.sign) << 15) - | (0x1F << 10) | mantissa)); - } else { - return float16_default_nan(status); - } -} - /*------------------------------------------------------------------------= ---- | Returns 1 if the single-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 43962dc3f5..a6860e858d 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -211,10 +211,10 @@ float128 uint64_to_float128(uint64_t, float_status *s= tatus); /*------------------------------------------------------------------------= ---- | Software half-precision conversion routines. *-------------------------------------------------------------------------= ---*/ -float16 float32_to_float16(float32, flag, float_status *status); -float32 float16_to_float32(float16, flag, float_status *status); -float16 float64_to_float16(float64 a, flag ieee, float_status *status); -float64 float16_to_float64(float16 a, flag ieee, float_status *status); +float16 float32_to_float16(float32, bool ieee, float_status *status); +float32 float16_to_float32(float16, bool ieee, float_status *status); +float16 float64_to_float16(float64 a, bool ieee, float_status *status); +float64 float16_to_float64(float16 a, bool ieee, float_status *status); int16_t float16_to_int16(float16, float_status *status); uint16_t float16_to_uint16(float16 a, float_status *status); int16_t float16_to_int16_round_to_zero(float16, float_status *status); diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 64e1ad4f98..55e6701f26 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -113,15 +113,6 @@ static inline int extractFloat16Exp(float16 a) return (float16_val(a) >> 10) & 0x1f; } =20 -/*------------------------------------------------------------------------= ---- -| Returns the sign bit of the single-precision floating-point value `a'. -*-------------------------------------------------------------------------= ---*/ - -static inline flag extractFloat16Sign(float16 a) -{ - return float16_val(a)>>15; -} - /*------------------------------------------------------------------------= ---- | Returns the fraction bits of the single-precision floating-point value `= a'. *-------------------------------------------------------------------------= ---*/ @@ -254,6 +245,11 @@ static const FloatFmt float16_params =3D { FLOAT_PARAMS(5, 10) }; =20 +static const FloatFmt float16_params_ahp =3D { + FLOAT_PARAMS(5, 10), + .arm_althp =3D true +}; + static const FloatFmt float32_params =3D { FLOAT_PARAMS(8, 23) }; @@ -497,14 +493,27 @@ static FloatParts round_canonical(FloatParts p, float= _status *s, return p; } =20 +/* Explicit FloatFmt version */ +static FloatParts float16a_unpack_canonical(float16 f, float_status *s, + const FloatFmt *params) +{ + return canonicalize(float16_unpack_raw(f), params, s); +} + static FloatParts float16_unpack_canonical(float16 f, float_status *s) { - return canonicalize(float16_unpack_raw(f), &float16_params, s); + return float16a_unpack_canonical(f, s, &float16_params); +} + +static float16 float16a_round_pack_canonical(FloatParts p, float_status *s, + const FloatFmt *params) +{ + return float16_pack_raw(round_canonical(p, s, params)); } =20 static float16 float16_round_pack_canonical(FloatParts p, float_status *s) { - return float16_pack_raw(round_canonical(p, s, &float16_params)); + return float16a_round_pack_canonical(p, s, &float16_params); } =20 static FloatParts float32_unpack_canonical(float32 f, float_status *s) @@ -1181,6 +1190,104 @@ float64 float64_div(float64 a, float64 b, float_sta= tus *status) return float64_round_pack_canonical(pr, status); } =20 +/* + * Float to Float conversions + * + * Returns the result of converting one float format to another. The + * conversion is performed according to the IEC/IEEE Standard for + * Binary Floating-Point Arithmetic. + * + * The float_to_float helper only needs to take care of raising + * invalid exceptions and handling the conversion on NaNs. + */ + +static FloatParts float_to_float(FloatParts a, const FloatFmt *dstf, + float_status *s) +{ + if (dstf->arm_althp) { + switch (a.cls) { + case float_class_qnan: + case float_class_snan: + /* There is no NaN in the destination format. Raise Invalid + * and return a zero with the sign of the input NaN. + */ + s->float_exception_flags |=3D float_flag_invalid; + a.cls =3D float_class_zero; + a.frac =3D 0; + a.exp =3D 0; + break; + + case float_class_inf: + /* There is no Inf in the destination format. Raise Invalid + * and return the maximum normal with the correct sign. + */ + s->float_exception_flags |=3D float_flag_invalid; + a.cls =3D float_class_normal; + a.exp =3D dstf->exp_max; + a.frac =3D ((1ull << dstf->frac_size) - 1) << dstf->frac_shift; + break; + + default: + break; + } + } else if (is_nan(a.cls)) { + if (is_snan(a.cls)) { + s->float_exception_flags |=3D float_flag_invalid; + a =3D parts_silence_nan(a, s); + } + if (s->default_nan_mode) { + return parts_default_nan(s); + } + } + return a; +} + +float32 float16_to_float32(float16 a, bool ieee, float_status *s) +{ + const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; + FloatParts p =3D float16a_unpack_canonical(a, s, fmt16); + FloatParts pr =3D float_to_float(p, &float32_params, s); + return float32_round_pack_canonical(pr, s); +} + +float64 float16_to_float64(float16 a, bool ieee, float_status *s) +{ + const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; + FloatParts p =3D float16a_unpack_canonical(a, s, fmt16); + FloatParts pr =3D float_to_float(p, &float64_params, s); + return float64_round_pack_canonical(pr, s); +} + +float16 float32_to_float16(float32 a, bool ieee, float_status *s) +{ + const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; + FloatParts p =3D float32_unpack_canonical(a, s); + FloatParts pr =3D float_to_float(p, fmt16, s); + return float16a_round_pack_canonical(pr, s, fmt16); +} + +float64 float32_to_float64(float32 a, float_status *s) +{ + FloatParts p =3D float32_unpack_canonical(a, s); + FloatParts pr =3D float_to_float(p, &float64_params, s); + return float64_round_pack_canonical(pr, s); +} + +float16 float64_to_float16(float64 a, bool ieee, float_status *s) +{ + const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; + FloatParts p =3D float64_unpack_canonical(a, s); + FloatParts pr =3D float_to_float(p, fmt16, s); + return float16a_round_pack_canonical(pr, s, fmt16); +} + +float32 float64_to_float32(float64 a, float_status *s) +{ + FloatParts p =3D float64_unpack_canonical(a, s); + FloatParts pr =3D float_to_float(p, &float32_params, s); + return float32_round_pack_canonical(pr, s); +} + /* * Rounds the floating-point value `a' to an integer, and returns the * result as a floating-point value. The operation is performed @@ -3124,41 +3231,6 @@ float128 uint64_to_float128(uint64_t a, float_status= *status) return normalizeRoundAndPackFloat128(0, 0x406E, 0, a, status); } =20 - - - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the single-precision floating-point val= ue -| `a' to the double-precision floating-point format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float64 float32_to_float64(float32 a, float_status *status) -{ - flag aSign; - int aExp; - uint32_t aSig; - a =3D float32_squash_input_denormal(a, status); - - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - if ( aExp =3D=3D 0xFF ) { - if (aSig) { - return commonNaNToFloat64(float32ToCommonNaN(a, status), statu= s); - } - return packFloat64( aSign, 0x7FF, 0 ); - } - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return packFloat64( aSign, 0, 0 ); - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - --aExp; - } - return packFloat64( aSign, aExp + 0x380, ( (uint64_t) aSig )<<29 ); - -} - /*------------------------------------------------------------------------= ---- | Returns the result of converting the single-precision floating-point val= ue | `a' to the extended double-precision floating-point format. The convers= ion @@ -3677,173 +3749,6 @@ int float32_unordered_quiet(float32 a, float32 b, f= loat_status *status) return 0; } =20 - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the double-precision floating-point val= ue -| `a' to the single-precision floating-point format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float32 float64_to_float32(float64 a, float_status *status) -{ - flag aSign; - int aExp; - uint64_t aSig; - uint32_t zSig; - a =3D float64_squash_input_denormal(a, status); - - aSig =3D extractFloat64Frac( a ); - aExp =3D extractFloat64Exp( a ); - aSign =3D extractFloat64Sign( a ); - if ( aExp =3D=3D 0x7FF ) { - if (aSig) { - return commonNaNToFloat32(float64ToCommonNaN(a, status), statu= s); - } - return packFloat32( aSign, 0xFF, 0 ); - } - shift64RightJamming( aSig, 22, &aSig ); - zSig =3D aSig; - if ( aExp || zSig ) { - zSig |=3D 0x40000000; - aExp -=3D 0x381; - } - return roundAndPackFloat32(aSign, aExp, zSig, status); - -} - - -/*------------------------------------------------------------------------= ---- -| Packs the sign `zSign', exponent `zExp', and significand `zSig' into a -| half-precision floating-point value, returning the result. After being -| shifted into the proper positions, the three fields are simply added -| together to form the result. This means that any integer portion of `zS= ig' -| will be added into the exponent. Since a properly normalized significand -| will have an integer portion equal to 1, the `zExp' input should be 1 le= ss -| than the desired result exponent whenever `zSig' is a complete, normaliz= ed -| significand. -*-------------------------------------------------------------------------= ---*/ -static float16 packFloat16(flag zSign, int zExp, uint16_t zSig) -{ - return make_float16( - (((uint32_t)zSign) << 15) + (((uint32_t)zExp) << 10) + zSig); -} - -/*------------------------------------------------------------------------= ---- -| Takes an abstract floating-point value having sign `zSign', exponent `zE= xp', -| and significand `zSig', and returns the proper half-precision floating- -| point value corresponding to the abstract input. Ordinarily, the abstra= ct -| value is simply rounded and packed into the half-precision format, with -| the inexact exception raised if the abstract input cannot be represented -| exactly. However, if the abstract value is too large, the overflow and -| inexact exceptions are raised and an infinity or maximal finite value is -| returned. If the abstract value is too small, the input value is rounde= d to -| a subnormal number, and the underflow and inexact exceptions are raised = if -| the abstract input cannot be represented exactly as a subnormal half- -| precision floating-point number. -| The `ieee' flag indicates whether to use IEEE standard half precision, or -| ARM-style "alternative representation", which omits the NaN and Inf -| encodings in order to raise the maximum representable exponent by one. -| The input significand `zSig' has its binary point between bits 22 -| and 23, which is 13 bits to the left of the usual location. This shifted -| significand must be normalized or smaller. If `zSig' is not normalized, -| `zExp' must be 0; in that case, the result returned is a subnormal numbe= r, -| and it must not require rounding. In the usual case that `zSig' is -| normalized, `zExp' must be 1 less than the ``true'' floating-point expon= ent. -| Note the slightly odd position of the binary point in zSig compared with= the -| other roundAndPackFloat functions. This should probably be fixed if we -| need to implement more float16 routines than just conversion. -| The handling of underflow and overflow follows the IEC/IEEE Standard for -| Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -static float16 roundAndPackFloat16(flag zSign, int zExp, - uint32_t zSig, flag ieee, - float_status *status) -{ - int maxexp =3D ieee ? 29 : 30; - uint32_t mask; - uint32_t increment; - bool rounding_bumps_exp; - bool is_tiny =3D false; - - /* Calculate the mask of bits of the mantissa which are not - * representable in half-precision and will be lost. - */ - if (zExp < 1) { - /* Will be denormal in halfprec */ - mask =3D 0x00ffffff; - if (zExp >=3D -11) { - mask >>=3D 11 + zExp; - } - } else { - /* Normal number in halfprec */ - mask =3D 0x00001fff; - } - - switch (status->float_rounding_mode) { - case float_round_nearest_even: - increment =3D (mask + 1) >> 1; - if ((zSig & mask) =3D=3D increment) { - increment =3D zSig & (increment << 1); - } - break; - case float_round_ties_away: - increment =3D (mask + 1) >> 1; - break; - case float_round_up: - increment =3D zSign ? 0 : mask; - break; - case float_round_down: - increment =3D zSign ? mask : 0; - break; - default: /* round_to_zero */ - increment =3D 0; - break; - } - - rounding_bumps_exp =3D (zSig + increment >=3D 0x01000000); - - if (zExp > maxexp || (zExp =3D=3D maxexp && rounding_bumps_exp)) { - if (ieee) { - float_raise(float_flag_overflow | float_flag_inexact, status); - return packFloat16(zSign, 0x1f, 0); - } else { - float_raise(float_flag_invalid, status); - return packFloat16(zSign, 0x1f, 0x3ff); - } - } - - if (zExp < 0) { - /* Note that flush-to-zero does not affect half-precision results = */ - is_tiny =3D - (status->float_detect_tininess =3D=3D float_tininess_before_ro= unding) - || (zExp < -1) - || (!rounding_bumps_exp); - } - if (zSig & mask) { - float_raise(float_flag_inexact, status); - if (is_tiny) { - float_raise(float_flag_underflow, status); - } - } - - zSig +=3D increment; - if (rounding_bumps_exp) { - zSig >>=3D 1; - zExp++; - } - - if (zExp < -10) { - return packFloat16(zSign, 0, 0); - } - if (zExp < 0) { - zSig >>=3D -zExp; - zExp =3D 0; - } - return packFloat16(zSign, zExp, zSig >> 13); -} - /*------------------------------------------------------------------------= ---- | If `a' is denormal and we are in flush-to-zero mode then set the | input-denormal exception and return zero. Otherwise just return the valu= e. @@ -3859,163 +3764,6 @@ float16 float16_squash_input_denormal(float16 a, fl= oat_status *status) return a; } =20 -static void normalizeFloat16Subnormal(uint32_t aSig, int *zExpPtr, - uint32_t *zSigPtr) -{ - int8_t shiftCount =3D countLeadingZeros32(aSig) - 21; - *zSigPtr =3D aSig << shiftCount; - *zExpPtr =3D 1 - shiftCount; -} - -/* Half precision floats come in two formats: standard IEEE and "ARM" form= at. - The latter gains extra exponent range by omitting the NaN/Inf encodings= . */ - -float32 float16_to_float32(float16 a, flag ieee, float_status *status) -{ - flag aSign; - int aExp; - uint32_t aSig; - - aSign =3D extractFloat16Sign(a); - aExp =3D extractFloat16Exp(a); - aSig =3D extractFloat16Frac(a); - - if (aExp =3D=3D 0x1f && ieee) { - if (aSig) { - return commonNaNToFloat32(float16ToCommonNaN(a, status), statu= s); - } - return packFloat32(aSign, 0xff, 0); - } - if (aExp =3D=3D 0) { - if (aSig =3D=3D 0) { - return packFloat32(aSign, 0, 0); - } - - normalizeFloat16Subnormal(aSig, &aExp, &aSig); - aExp--; - } - return packFloat32( aSign, aExp + 0x70, aSig << 13); -} - -float16 float32_to_float16(float32 a, flag ieee, float_status *status) -{ - flag aSign; - int aExp; - uint32_t aSig; - - a =3D float32_squash_input_denormal(a, status); - - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - if ( aExp =3D=3D 0xFF ) { - if (aSig) { - /* Input is a NaN */ - if (!ieee) { - float_raise(float_flag_invalid, status); - return packFloat16(aSign, 0, 0); - } - return commonNaNToFloat16( - float32ToCommonNaN(a, status), status); - } - /* Infinity */ - if (!ieee) { - float_raise(float_flag_invalid, status); - return packFloat16(aSign, 0x1f, 0x3ff); - } - return packFloat16(aSign, 0x1f, 0); - } - if (aExp =3D=3D 0 && aSig =3D=3D 0) { - return packFloat16(aSign, 0, 0); - } - /* Decimal point between bits 22 and 23. Note that we add the 1 bit - * even if the input is denormal; however this is harmless because - * the largest possible single-precision denormal is still smaller - * than the smallest representable half-precision denormal, and so we - * will end up ignoring aSig and returning via the "always return zero" - * codepath. - */ - aSig |=3D 0x00800000; - aExp -=3D 0x71; - - return roundAndPackFloat16(aSign, aExp, aSig, ieee, status); -} - -float64 float16_to_float64(float16 a, flag ieee, float_status *status) -{ - flag aSign; - int aExp; - uint32_t aSig; - - aSign =3D extractFloat16Sign(a); - aExp =3D extractFloat16Exp(a); - aSig =3D extractFloat16Frac(a); - - if (aExp =3D=3D 0x1f && ieee) { - if (aSig) { - return commonNaNToFloat64( - float16ToCommonNaN(a, status), status); - } - return packFloat64(aSign, 0x7ff, 0); - } - if (aExp =3D=3D 0) { - if (aSig =3D=3D 0) { - return packFloat64(aSign, 0, 0); - } - - normalizeFloat16Subnormal(aSig, &aExp, &aSig); - aExp--; - } - return packFloat64(aSign, aExp + 0x3f0, ((uint64_t)aSig) << 42); -} - -float16 float64_to_float16(float64 a, flag ieee, float_status *status) -{ - flag aSign; - int aExp; - uint64_t aSig; - uint32_t zSig; - - a =3D float64_squash_input_denormal(a, status); - - aSig =3D extractFloat64Frac(a); - aExp =3D extractFloat64Exp(a); - aSign =3D extractFloat64Sign(a); - if (aExp =3D=3D 0x7FF) { - if (aSig) { - /* Input is a NaN */ - if (!ieee) { - float_raise(float_flag_invalid, status); - return packFloat16(aSign, 0, 0); - } - return commonNaNToFloat16( - float64ToCommonNaN(a, status), status); - } - /* Infinity */ - if (!ieee) { - float_raise(float_flag_invalid, status); - return packFloat16(aSign, 0x1f, 0x3ff); - } - return packFloat16(aSign, 0x1f, 0); - } - shift64RightJamming(aSig, 29, &aSig); - zSig =3D aSig; - if (aExp =3D=3D 0 && zSig =3D=3D 0) { - return packFloat16(aSign, 0, 0); - } - /* Decimal point between bits 22 and 23. Note that we add the 1 bit - * even if the input is denormal; however this is harmless because - * the largest possible single-precision denormal is still smaller - * than the smallest representable half-precision denormal, and so we - * will end up ignoring aSig and returning via the "always return zero" - * codepath. - */ - zSig |=3D 0x00800000; - aExp -=3D 0x3F1; - - return roundAndPackFloat16(aSign, aExp, zSig, ieee, status); -} - /*------------------------------------------------------------------------= ---- | Returns the result of converting the double-precision floating-point val= ue | `a' to the extended double-precision floating-point format. The convers= ion --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526424422179593.3763833375206; Tue, 15 May 2018 15:47:02 -0700 (PDT) Received: from localhost ([::1]:36884 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiic-000320-9P for importer@patchew.org; Tue, 15 May 2018 18:46:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39616) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOT-0003VP-Ug for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOR-0005ia-Vr for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:05 -0400 Received: from mail-pf0-x234.google.com ([2607:f8b0:400e:c00::234]:32906) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOR-0005bE-NA for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:03 -0400 Received: by mail-pf0-x234.google.com with SMTP id a20-v6so745363pfo.0 for ; Tue, 15 May 2018 15:26:03 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.26.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:26:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HCzhOWHu2+7g6xUjsUPmKAtx3rgdm8J3LWpkOAk/KmQ=; b=QP+L9prztRd2v4+sJV69G/QRe1teCX/lPYEYqLtKmycvQwtjj/Y1F1JbU6zdmG7iH2 GMazBj29iul9C1eVHkTC45dtUJrOg7joRuD5viV6Og0+s1yQUfLPh4mxbLKgS5laCryO 7/iTb0cqJBg0hPfFT94HAMLoFhB6yeXNZkx0I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HCzhOWHu2+7g6xUjsUPmKAtx3rgdm8J3LWpkOAk/KmQ=; b=J1HwOk4PTX4zya+5Nh88w69kvt3E8tu5zJIf4A8ROtHLWKtHWPreM5N+hjTEb2UepI NYz0fDkWQPbHNQFB6Hqzss5g6ZseJ6aOZGuHhHL7AbdAKeFvPCcM2iDC7K629AIkHsGE 8W8qRv7i1PNY27m4b90WatnO/ShJXBJPSQOoJ0EvDFm86PVUP9bopqEi6sm1TSB3Kstw Lpg910tpG5dpvYT6I2RzLvIHyLvhgCRjalVUo162yXMZ349A/30J4QLh+Xi2GgOFbWqb 2upsMXEqk4mqQNIyyAsYcwwfMgrdCA6tggI2xPnhGQ4ttzTfZQ3xpkBV9OtEvBts71TP m4fg== X-Gm-Message-State: ALKqPweZAB+/p8sV/bIGENCygJ+Ng2ZYJnBV5R4A9NfhsGpmAHYXyvJl /bPj03O1HTammNNKlFH85jazWZAl1uE= X-Google-Smtp-Source: AB8JxZpw0PNuCbADu/KvdX0gYVDiw3yhv83TMKmAm2vPwvPfYYcsxN8a3PseMCIIYwL6TBfIrIwmZg== X-Received: by 2002:a63:7315:: with SMTP id o21-v6mr13605077pgc.360.1526423162363; Tue, 15 May 2018 15:26:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:25 -0700 Message-Id: <20180515222540.9988-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::234 Subject: [Qemu-devel] [PATCH v6 13/28] target/arm: Use floatX_silence_nan when we have already checked for SNaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 6 +++--- target/arm/helper.c | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 4f8034c513..6f0eb83661 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -376,7 +376,7 @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp) float16 nan =3D a; if (float16_is_signaling_nan(a, fpst)) { float_raise(float_flag_invalid, fpst); - nan =3D float16_maybe_silence_nan(a, fpst); + nan =3D float16_silence_nan(a, fpst); } if (fpst->default_nan_mode) { nan =3D float16_default_nan(fpst); @@ -405,7 +405,7 @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp) float32 nan =3D a; if (float32_is_signaling_nan(a, fpst)) { float_raise(float_flag_invalid, fpst); - nan =3D float32_maybe_silence_nan(a, fpst); + nan =3D float32_silence_nan(a, fpst); } if (fpst->default_nan_mode) { nan =3D float32_default_nan(fpst); @@ -434,7 +434,7 @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp) float64 nan =3D a; if (float64_is_signaling_nan(a, fpst)) { float_raise(float_flag_invalid, fpst); - nan =3D float64_maybe_silence_nan(a, fpst); + nan =3D float64_silence_nan(a, fpst); } if (fpst->default_nan_mode) { nan =3D float64_default_nan(fpst); diff --git a/target/arm/helper.c b/target/arm/helper.c index 238a3ceba8..e05c7230d4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11731,7 +11731,7 @@ float16 HELPER(recpe_f16)(float16 input, void *fpst= p) float16 nan =3D f16; if (float16_is_signaling_nan(f16, fpst)) { float_raise(float_flag_invalid, fpst); - nan =3D float16_maybe_silence_nan(f16, fpst); + nan =3D float16_silence_nan(f16, fpst); } if (fpst->default_nan_mode) { nan =3D float16_default_nan(fpst); @@ -11779,7 +11779,7 @@ float32 HELPER(recpe_f32)(float32 input, void *fpst= p) float32 nan =3D f32; if (float32_is_signaling_nan(f32, fpst)) { float_raise(float_flag_invalid, fpst); - nan =3D float32_maybe_silence_nan(f32, fpst); + nan =3D float32_silence_nan(f32, fpst); } if (fpst->default_nan_mode) { nan =3D float32_default_nan(fpst); @@ -11827,7 +11827,7 @@ float64 HELPER(recpe_f64)(float64 input, void *fpst= p) float64 nan =3D f64; if (float64_is_signaling_nan(f64, fpst)) { float_raise(float_flag_invalid, fpst); - nan =3D float64_maybe_silence_nan(f64, fpst); + nan =3D float64_silence_nan(f64, fpst); } if (fpst->default_nan_mode) { nan =3D float64_default_nan(fpst); @@ -11926,7 +11926,7 @@ float16 HELPER(rsqrte_f16)(float16 input, void *fps= tp) float16 nan =3D f16; if (float16_is_signaling_nan(f16, s)) { float_raise(float_flag_invalid, s); - nan =3D float16_maybe_silence_nan(f16, s); + nan =3D float16_silence_nan(f16, s); } if (s->default_nan_mode) { nan =3D float16_default_nan(s); @@ -11970,7 +11970,7 @@ float32 HELPER(rsqrte_f32)(float32 input, void *fps= tp) float32 nan =3D f32; if (float32_is_signaling_nan(f32, s)) { float_raise(float_flag_invalid, s); - nan =3D float32_maybe_silence_nan(f32, s); + nan =3D float32_silence_nan(f32, s); } if (s->default_nan_mode) { nan =3D float32_default_nan(s); @@ -12013,7 +12013,7 @@ float64 HELPER(rsqrte_f64)(float64 input, void *fps= tp) float64 nan =3D f64; if (float64_is_signaling_nan(f64, s)) { float_raise(float_flag_invalid, s); - nan =3D float64_maybe_silence_nan(f64, s); + nan =3D float64_silence_nan(f64, s); } if (s->default_nan_mode) { nan =3D float64_default_nan(s); --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.26.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:26:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cSZ33bwDEVkNnz6+2oRZOYUtCrbSKbPYkMTqNAn1iAA=; b=i1rLlJTSSyxjMrSTIMlmOSqMPS8oD+rlPDDc7bnZ7lmOOl7/IgHfRps7hwoV/7n0lr DvWGTMpwGh9T9i10xt9hYGNR8JSW/g940W1UJrz7KV459Ggr3tU22uNHT2xolXpTOTPV kZW5Y0gzvfj1I5UEezp+jtEUvmRQtfPVQr89o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cSZ33bwDEVkNnz6+2oRZOYUtCrbSKbPYkMTqNAn1iAA=; b=OD+Tj71TwN4V7ryt6YRNF6carzoQoLzsDxUpJeb1VpxN8M2mnKUaa4jP5ZHASlxp5F csR15ICLt34d+pPzTlHbkNiO6Kl/UAd3gQJmanAoAqD9R9AJxL/Fan/+vDj112tXThaj zABHuIpCAZVaEXFAKNu6UqQxkNqIy8oXlJZWI0V+kWrbNiIoh22+2NCM/Th+LFZZyTFs JPzpFpNxOeiPYxoIi5WIp9lTOUpI2OB9WGAAvyMnByjT2iRX07Nn0/Ggf9PvbP3O2R59 5CN4ohfCGvgtq6mL8W/jxqnas56vGn9sZwiSxjNffHLjlSfnejqRKFKlNQwPEVrwROWM i0Pg== X-Gm-Message-State: ALKqPwcjebgGdL1pf5qJI7pvkAKFe8xflinsNPcXjjCHSA7vDyAijttk ikOuFfoGYuIVKQTILy7vAu7CtyL8f1w= X-Google-Smtp-Source: AB8JxZoUoa4XfeZQPbxB+Aa+3t+q8PyhrkLgkT7vTXyEX+ifNkkgAnY9p22nXlLwI0KcLKUEaX0Fnw== X-Received: by 2002:a63:7154:: with SMTP id b20-v6mr13713715pgn.13.1526423164059; Tue, 15 May 2018 15:26:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:26 -0700 Message-Id: <20180515222540.9988-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v6 14/28] target/arm: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This is now handled properly by the generic softfloat code. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 1 - target/arm/helper.c | 12 ++---------- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 6f0eb83661..f92bdea732 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -466,7 +466,6 @@ float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState= *env) set_float_rounding_mode(float_round_to_zero, &tstat); set_float_exception_flags(0, &tstat); r =3D float64_to_float32(a, &tstat); - r =3D float32_maybe_silence_nan(r, &tstat); exflags =3D get_float_exception_flags(&tstat); if (exflags & float_flag_inexact) { r =3D make_float32(float32_val(r) | 1); diff --git a/target/arm/helper.c b/target/arm/helper.c index e05c7230d4..db8bbe52a6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11348,20 +11348,12 @@ FLOAT_CONVS(ui, d, 64, u) /* floating point conversion */ float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) { - float64 r =3D float32_to_float64(x, &env->vfp.fp_status); - /* ARM requires that S<->D conversion of any kind of NaN generates - * a quiet NaN by forcing the most significant frac bit to 1. - */ - return float64_maybe_silence_nan(r, &env->vfp.fp_status); + return float32_to_float64(x, &env->vfp.fp_status); } =20 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) { - float32 r =3D float64_to_float32(x, &env->vfp.fp_status); - /* ARM requires that S<->D conversion of any kind of NaN generates - * a quiet NaN by forcing the most significant frac bit to 1. - */ - return float32_maybe_silence_nan(r, &env->vfp.fp_status); + return float64_to_float32(x, &env->vfp.fp_status); } =20 /* VFP3 fixed point conversion. */ --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526424117110383.0222355057032; Tue, 15 May 2018 15:41:57 -0700 (PDT) Received: from localhost ([::1]:36390 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIido-0006fJ-7X for importer@patchew.org; Tue, 15 May 2018 18:41:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39661) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOY-0003Zq-BL for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOU-00069t-Pr for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:10 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:36935) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOU-00063D-IB for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:06 -0400 Received: by mail-pf0-x244.google.com with SMTP id e9-v6so739533pfi.4 for ; Tue, 15 May 2018 15:26:06 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.26.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:26:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TD/lOXrmVofLedG4op9ymEqylnQt6zN7ClswSrkMaZc=; b=gfUfEM+eS6AMAtZyR5vvMtMKdNmSK47YrEK52A8d+w/+UdsXIuSsQnRIi+KmLpHBbA uBxKc0fFTwgt0ZQJ4UIn91ZEZdsde1NEhd3tE9IWzBOV3vp1aDyvKoOloeQ3ytBYOviy hZZqKwEzUa9DZenAazT5kSxSHEIqth4TFYo5M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TD/lOXrmVofLedG4op9ymEqylnQt6zN7ClswSrkMaZc=; b=LX07O8C/TWcjbzAB9n0UOIBt7I+qtBTd9rAixFFieLHl1vgMz88Y0ka8fL838HPILw bKn0S79oPy8nfuHyTsPJnZBs61QYbuylIiK6DpdtuAjxIgEnhIHNceWUXqpvs55TnLa0 rjxulQltlk604rJmPVPr+NQbFEwL76mr6pJDiA+mZ9p7H5LaYoqjBfX/mjtazmP4auhF VnQb/fn2Y8QuQMg2g0aszXoNO1uXaYisHNfhI5bFqPbWFG4sDhozYmj4DgacuWjU6YWc FBqKFsK7UrrHXRdOohuqA01wIkvVESdJ0KIk0agoqgmx+ulbDrdS3XUTEYXYizYkokMu c7Yw== X-Gm-Message-State: ALKqPwfUbKemU+0Oh8ZokAp1VFzW9yp4gEJnZr7wC++VsSlA2MS2yF3X e5+E8YUdtvj5W3fWDRoy7up1RGF9fFs= X-Google-Smtp-Source: AB8JxZoOknLrC0XzhcC2sdV6I3BfzuupdKRw0dlP7gvKvFFNBjnq6b1sB6we3zD0303i5puU1t9PrQ== X-Received: by 2002:a63:9d0d:: with SMTP id i13-v6mr13429243pgd.288.1526423165321; Tue, 15 May 2018 15:26:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:27 -0700 Message-Id: <20180515222540.9988-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v6 15/28] target/hppa: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This is now handled properly by the generic softfloat code. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/hppa/op_helper.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index a3af62daf7..912e8d5be4 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -341,7 +341,6 @@ float64 HELPER(fdiv_d)(CPUHPPAState *env, float64 a, fl= oat64 b) float64 HELPER(fcnv_s_d)(CPUHPPAState *env, float32 arg) { float64 ret =3D float32_to_float64(arg, &env->fp_status); - ret =3D float64_maybe_silence_nan(ret, &env->fp_status); update_fr0_op(env, GETPC()); return ret; } @@ -349,7 +348,6 @@ float64 HELPER(fcnv_s_d)(CPUHPPAState *env, float32 arg) float32 HELPER(fcnv_d_s)(CPUHPPAState *env, float64 arg) { float32 ret =3D float64_to_float32(arg, &env->fp_status); - ret =3D float32_maybe_silence_nan(ret, &env->fp_status); update_fr0_op(env, GETPC()); return ret; } --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526424294186931.5473480932643; Tue, 15 May 2018 15:44:54 -0700 (PDT) Received: from localhost ([::1]:36405 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIigf-0000gK-9D for importer@patchew.org; Tue, 15 May 2018 18:44:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39659) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOY-0003Zg-6p for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOW-0006NB-1y for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:10 -0400 Received: from mail-pl0-x233.google.com ([2607:f8b0:400e:c01::233]:43770) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOV-0006Fg-Qn for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:07 -0400 Received: by mail-pl0-x233.google.com with SMTP id c41-v6so858688plj.10 for ; Tue, 15 May 2018 15:26:07 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.26.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:26:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SPBg1TyIEk4O+QgkODhyiPa2jhkA37Z3ZFJ5t7jC9gU=; b=DuguPOGswdB9I+iaUQaFCtoG4zmMo+eoDc99lykdLjPP0EI68SXigN3ERT2Gc1nUcz FuGijAmKurThyz44mpWXdk/Da+vC94MHSbH/Ab+Ul8rY+gtkiatsAymtjwOF/rnEr1Fl Zug/UnwqJUox6UUhOF0bcqh1H9rn19DGrqf84= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SPBg1TyIEk4O+QgkODhyiPa2jhkA37Z3ZFJ5t7jC9gU=; b=RbMhtpbfGNj+nibZzYvA5Lx1C6Fic3e76bhHCS7gXExrXnlO2F+WI0iHTRjCwQwoQt sRRRNOkxiClg+Bs0Qu+kW/1W7EDqxgMYBy9BgRTQ4xc7E+G4BG4xMV5rNRiGllbq/xAl ehrFW7JI3VLDNkTpxZ3T3Mc4/YtMA4A1AukNY6jDTDe82gQsaM8bnIiz0SR+eyTLYuFw clTV0g98mIXS9K+ATmH/yV8nw9X7uycPUwW6lSrH3cs9ASqA7DNeXIJ2iU4fprZkPVco PZE3hmNITG5rK40kNt3n/SApJu02vj//Jm0W9nRiWkfZzB0c1FtjP9BmlEyGpG8N0aQl VOFw== X-Gm-Message-State: ALKqPwcre7rqSl0UFswMtPUwZhOy3HD+OZiVWlw7Er0/bNt+nSQi4zjn F5nVy09SVMEPwg3TZDL+tZttxYi+6vE= X-Google-Smtp-Source: AB8JxZotgEQgr+vf5ryvMpKGYkHtBKNPVkpreRudkrDZid2mWw6/3jh2kS+TzLFTD26inWCt1oGoAg== X-Received: by 2002:a17:902:7046:: with SMTP id h6-v6mr16407627plt.249.1526423166570; Tue, 15 May 2018 15:26:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:28 -0700 Message-Id: <20180515222540.9988-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::233 Subject: [Qemu-devel] [PATCH v6 16/28] target/m68k: Use floatX_silence_nan when we have already checked for SNaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/m68k/softfloat.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/m68k/softfloat.c b/target/m68k/softfloat.c index d093997219..b45a5e8690 100644 --- a/target/m68k/softfloat.c +++ b/target/m68k/softfloat.c @@ -31,13 +31,14 @@ static floatx80 propagateFloatx80NaNOneArg(floatx80 a, = float_status *status) { if (floatx80_is_signaling_nan(a, status)) { float_raise(float_flag_invalid, status); + a =3D floatx80_silence_nan(a, status); } =20 if (status->default_nan_mode) { return floatx80_default_nan(status); } =20 - return floatx80_maybe_silence_nan(a, status); + return a; } =20 /*------------------------------------------------------------------------= ---- --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526424439777249.6965330218327; Tue, 15 May 2018 15:47:19 -0700 (PDT) Received: from localhost ([::1]:36895 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIij1-0003KN-2a for importer@patchew.org; Tue, 15 May 2018 18:47:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39664) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOY-0003a6-Lx for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOX-0006Zb-6s for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:10 -0400 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:43388) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOX-0006SX-0a for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:09 -0400 Received: by mail-pl0-x242.google.com with SMTP id c41-v6so858715plj.10 for ; Tue, 15 May 2018 15:26:08 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.26.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:26:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YG4WDuvg/nU14CtfIK1nI16sf1EHjyzdnNJh8QSrA1M=; b=UK67F6jq8EY4j5t47umQwH2Uv5vEfs29p5trfVXU25UlfmDmgvRZ3+b1iN4kBZUrLj pT7S+zm+5/bOm9nFBSh33jIwmm4cbqEqy3mXGKUScPWDNLnvoDbydgdhTJS/qPnv/7jN EamAjNnIaQggkQlv7zSaC2rlXavMp7fTFH4xw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YG4WDuvg/nU14CtfIK1nI16sf1EHjyzdnNJh8QSrA1M=; b=t9amAgvZLXfbHLq2lJdz9ZMVqm+ne878It0XsIrNXef7JYQ0M38cZSN7OdLibm7nXl Z51CvG1YVZP3Y26g20Pl/P3ziMh9MeNfKTYLCYRuCL+DWCkxN2cxC7WaOkkeh+mMMMg2 5Jjqg0XAIZ26YcFVa7zXdizselfTq1IVTx6KzsTukN915qcJzrWO/ijsk0SErirqymfc eyIAk/M0EOH94Bwru23zoWuAtL1T7bzjZE2WemP6QZOp295yl2FBV2r5hnkMlogOJaCF LI9ITLy+4PzQMar9jDP8akeGnYj9jP97WeJA0fhwBwN3dXAOcF8KYwDimlPMkyxjbxOj Sx2g== X-Gm-Message-State: ALKqPweVp64y6dHn3XOndVwOku5u6xkH3wN0UEiJOZGv0oLYRMK8nJ3/ K7r0piU8MmRPVeAC6t6bZMz9cOwyywI= X-Google-Smtp-Source: AB8JxZoqZLeW9gn3IIVh0uZb2Wd4IlbophVeY7/3ARK4zn0/pHh6dHJ8KMn/giOCen+i4wZMVKhNCg== X-Received: by 2002:a17:902:d24:: with SMTP id 33-v6mr16129786plu.22.1526423167725; Tue, 15 May 2018 15:26:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:29 -0700 Message-Id: <20180515222540.9988-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v6 17/28] target/mips: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Yongbok Kim , alex.bennee@linaro.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is now handled properly by the generic softfloat code. Cc: Aurelien Jarno Cc: Yongbok Kim Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/mips/msa_helper.c | 4 ---- target/mips/op_helper.c | 2 -- 2 files changed, 6 deletions(-) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 8fb7a369ca..c74e3cdc65 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1615,7 +1615,6 @@ static inline float16 float16_from_float32(int32_t a,= flag ieee, float16 f_val; =20 f_val =3D float32_to_float16((float32)a, ieee, status); - f_val =3D float16_maybe_silence_nan(f_val, status); =20 return a < 0 ? (f_val | (1 << 15)) : f_val; } @@ -1625,7 +1624,6 @@ static inline float32 float32_from_float64(int64_t a,= float_status *status) float32 f_val; =20 f_val =3D float64_to_float32((float64)a, status); - f_val =3D float32_maybe_silence_nan(f_val, status); =20 return a < 0 ? (f_val | (1 << 31)) : f_val; } @@ -1636,7 +1634,6 @@ static inline float32 float32_from_float16(int16_t a,= flag ieee, float32 f_val; =20 f_val =3D float16_to_float32((float16)a, ieee, status); - f_val =3D float32_maybe_silence_nan(f_val, status); =20 return a < 0 ? (f_val | (1 << 31)) : f_val; } @@ -1646,7 +1643,6 @@ static inline float64 float64_from_float32(int32_t a,= float_status *status) float64 f_val; =20 f_val =3D float32_to_float64((float64)a, status); - f_val =3D float64_maybe_silence_nan(f_val, status); =20 return a < 0 ? (f_val | (1ULL << 63)) : f_val; } diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 798cdad030..9025f42366 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2700,7 +2700,6 @@ uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint3= 2_t fst0) uint64_t fdt2; =20 fdt2 =3D float32_to_float64(fst0, &env->active_fpu.fp_status); - fdt2 =3D float64_maybe_silence_nan(fdt2, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return fdt2; } @@ -2790,7 +2789,6 @@ uint32_t helper_float_cvts_d(CPUMIPSState *env, uint6= 4_t fdt0) uint32_t fst2; =20 fst2 =3D float64_to_float32(fdt0, &env->active_fpu.fp_status); - fst2 =3D float32_maybe_silence_nan(fst2, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return fst2; } --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526423712308986.5958059520593; Tue, 15 May 2018 15:35:12 -0700 (PDT) Received: from localhost ([::1]:36351 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiXH-0001BC-Hq for importer@patchew.org; Tue, 15 May 2018 18:35:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39688) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOa-0003bQ-1S for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOY-0006oY-MO for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:12 -0400 Received: from mail-pl0-x22d.google.com ([2607:f8b0:400e:c01::22d]:45193) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOY-0006hj-F6 for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:10 -0400 Received: by mail-pl0-x22d.google.com with SMTP id bi12-v6so854122plb.12 for ; Tue, 15 May 2018 15:26:10 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.26.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:26:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lFbjHgIjVdntVwEG8TX8Zn/QYQH/a160DBSlPiGyBN4=; b=ZKA1cgEe/1kC1iXJY+08BCUNPqLiu9+Vc0pFv+xR4u5pZcJ6T6MOEhKx2HNm9mXJqM LBl9RrgSDfyu/HUNnWcdUxpsJzZwajfhlAZJEjDabjoSFvJGeb00jHUwOym7LbH0bITJ tkSOofNijTRWrRme1AfWx3t6W2wbUbolbz5Ss= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lFbjHgIjVdntVwEG8TX8Zn/QYQH/a160DBSlPiGyBN4=; b=LLQbfFthk0+WSoi6q0/k1qVckvYN90aGt9UYwCcbZWc0bQdbDdTRISVEL5Dpxo2IkN 4VDwrLQOZXiQA3aZIHl5hHuJUs+Neyx3a5D/CSW6VdhCztx+fWhpGRRiD92prul01eJN J94u0bvCZqyeZ8DlITTasXI2f1zzGjqpzMuJueFTZqwJosppQnOlf8+w325VqsLZdtyh U1PRCvHLVxb6dHrJ2wRdd9VmsTZOCj9tiGXQoTlnXT7mHZM7/l2bwVI67HLK2Bfuxwjo C8fuZzxftgZNeiTJBzf/s+6zp/z4qgCH4qpeOqk2eIhGRbc8LfWX1bzrAhMYHFwULwrs TgaA== X-Gm-Message-State: ALKqPwckbjQnqbnH+I24lOmiARYsmV+Bjp6seB/MAhGxLqbPb2WQsCIX BqGzhZP8cIBheeoPRAkNisfPalld6cY= X-Google-Smtp-Source: AB8JxZotAm2NvUdL7C1+dPQ4hsN9Dla0FvF8uV2dSc3KB8U5H6WCD83nspDaVzqmT8jQIULgVRkSeg== X-Received: by 2002:a17:902:9a8b:: with SMTP id w11-v6mr16319356plp.75.1526423169236; Tue, 15 May 2018 15:26:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:30 -0700 Message-Id: <20180515222540.9988-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22d Subject: [Qemu-devel] [PATCH v6 18/28] target/riscv: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Palmer Dabbelt , alex.bennee@linaro.org, Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is now handled properly by the generic softfloat code. Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Reviewed-by: Michael Clark Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/riscv/fpu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index abbadead5c..fdb87d8d82 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -279,14 +279,12 @@ uint64_t helper_fmax_d(CPURISCVState *env, uint64_t f= rs1, uint64_t frs2) =20 uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1) { - rs1 =3D float64_to_float32(rs1, &env->fp_status); - return float32_maybe_silence_nan(rs1, &env->fp_status); + return float64_to_float32(rs1, &env->fp_status); } =20 uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1) { - rs1 =3D float32_to_float64(rs1, &env->fp_status); - return float64_maybe_silence_nan(rs1, &env->fp_status); + return float32_to_float64(rs1, &env->fp_status); } =20 uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1) --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526424650400916.451619491817; Tue, 15 May 2018 15:50:50 -0700 (PDT) Received: from localhost ([::1]:37204 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIimP-00069I-NW for importer@patchew.org; Tue, 15 May 2018 18:50:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39701) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOb-0003cq-Et for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOa-00072Q-4i for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:13 -0400 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:40066) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOZ-0006uI-Tp for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:12 -0400 Received: by mail-pl0-x241.google.com with SMTP id t12-v6so863499plo.7 for ; Tue, 15 May 2018 15:26:11 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.26.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:26:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=N/MQDXmC5P0rKEPWLGL6olcs6gD/4PAiety6G0UTpec=; b=HlTzi/xAFRV0csDlNwlWCAF9B3+CRQo8RPaqeKUUNOZ0DOcP/ON814vCLgM4Zb1Fwr t3sDjDVnpEwx+OEZWMCOeMEqcj6w9pAix0twJCV7eQNczmavTcydC39fTkdyqFtAQPDB TTjlRYN4pKGQXtWwYt8oV94etFJw0zOpIzj/Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=N/MQDXmC5P0rKEPWLGL6olcs6gD/4PAiety6G0UTpec=; b=HNIRrSRaY3uYF5EARuIIDRBNtUIKfav9JSTlYsoD6fmsfPsxXlKl4R/F3+A3Howceu JmbSyKq+4a8mDd0BNuFH8w3hpunnxEDEdWaxbnHJW1Vqm/M8QyhfRV67H6yDhWxr3UPs 7PGZb5RMpx6Je30WLtAeqYjBjq625XKkKyjWIzTvw5MZ/gjVBrBFN/+qJujDJeucBeqm 6nBAA1bhegqDNlfMjjI9j9NCWjUjmG+YSVo3kS8RX13mAOb5gYaOeuE87SOlq5MRD753 Gv8ot5FFhaDHUYuo4Dx5dQCzY7W1fQwW3g8Hd1lqPE2FtLYtMzbBDnJN0Pr7Y1rrk7BI SQ9A== X-Gm-Message-State: ALKqPwdNP+VZ4J3KB9Zt3JaBsBX3gM6p3O1GiAigivpLh/jh26TSHYa8 aRlgFzHFVkyTNrngHYTSn9Iy1q7W2PY= X-Google-Smtp-Source: AB8JxZqYuWOzKNINNRu7PhZrFmWi1WpYvRlxl20Rv63DK6eBC2WWCvMzyhU1RrvoHyHMABR5nwt5rw== X-Received: by 2002:a17:902:8d8e:: with SMTP id v14-v6mr16504899plo.387.1526423170584; Tue, 15 May 2018 15:26:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:31 -0700 Message-Id: <20180515222540.9988-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v6 19/28] target/s390x: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, Alexander Graf Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is now handled properly by the generic softfloat code. Cc: Alexander Graf Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/s390x/fpu_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c index 43f8bf1c94..5c5b451b3b 100644 --- a/target/s390x/fpu_helper.c +++ b/target/s390x/fpu_helper.c @@ -269,7 +269,7 @@ uint64_t HELPER(ldeb)(CPUS390XState *env, uint64_t f2) { float64 ret =3D float32_to_float64(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return float64_maybe_silence_nan(ret, &env->fpu_status); + return ret; } =20 /* convert 128-bit float to 64-bit float */ @@ -277,7 +277,7 @@ uint64_t HELPER(ldxb)(CPUS390XState *env, uint64_t ah, = uint64_t al) { float64 ret =3D float128_to_float64(make_float128(ah, al), &env->fpu_s= tatus); handle_exceptions(env, GETPC()); - return float64_maybe_silence_nan(ret, &env->fpu_status); + return ret; } =20 /* convert 64-bit float to 128-bit float */ @@ -285,7 +285,7 @@ uint64_t HELPER(lxdb)(CPUS390XState *env, uint64_t f2) { float128 ret =3D float64_to_float128(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return RET128(float128_maybe_silence_nan(ret, &env->fpu_status)); + return RET128(ret); } =20 /* convert 32-bit float to 128-bit float */ @@ -293,7 +293,7 @@ uint64_t HELPER(lxeb)(CPUS390XState *env, uint64_t f2) { float128 ret =3D float32_to_float128(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return RET128(float128_maybe_silence_nan(ret, &env->fpu_status)); + return RET128(ret); } =20 /* convert 64-bit float to 32-bit float */ @@ -301,7 +301,7 @@ uint64_t HELPER(ledb)(CPUS390XState *env, uint64_t f2) { float32 ret =3D float64_to_float32(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return float32_maybe_silence_nan(ret, &env->fpu_status); + return ret; } =20 /* convert 128-bit float to 32-bit float */ @@ -309,7 +309,7 @@ uint64_t HELPER(lexb)(CPUS390XState *env, uint64_t ah, = uint64_t al) { float32 ret =3D float128_to_float32(make_float128(ah, al), &env->fpu_s= tatus); handle_exceptions(env, GETPC()); - return float32_maybe_silence_nan(ret, &env->fpu_status); + return ret; } =20 /* 32-bit FP compare */ --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526423894814360.5064459568597; Tue, 15 May 2018 15:38:14 -0700 (PDT) Received: from localhost ([::1]:36371 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiaD-0003cq-VH for importer@patchew.org; Tue, 15 May 2018 18:38:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39715) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOd-0003e8-9C for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOb-0007FY-BK for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:15 -0400 Received: from mail-pl0-x243.google.com ([2607:f8b0:400e:c01::243]:36071) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOb-00076y-30 for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:13 -0400 Received: by mail-pl0-x243.google.com with SMTP id v24-v6so867966plo.3 for ; Tue, 15 May 2018 15:26:13 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.26.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:26:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h62BzzH4LLhuXxYTEWEspmGWZCobGiYio26vYR2atOs=; b=dG/xZhgeY2F4oeLMMrjrKsM0posSP6czvUIjoYS2uh2eaEk+VhZ7p1Im+mppzx3fGN DnzdZzJByN+uZkqxvKxeKkasHFViG441iyxfELM0X1RW59GXv8KJBOASupfg/DX1lS2j 94xvoG5CSUhY8VW08F/TlQ9CkBDCoaPSG/omc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h62BzzH4LLhuXxYTEWEspmGWZCobGiYio26vYR2atOs=; b=plDoHw847LuAs0avMk/stcQwCseq+8TYP6v9INocRQfOYf35V2/CYqooZtdKAjLBhs 5svuEX4IUvbiY+jgzidmRY63GBa5D8HhLH14qeDb+sD0DCoxvZNctCXV2RaCKv+StAh+ MzQauKRBWw8Lb/7Ljw+AyKAlsddABEGEXIWk8wzAABs5f5UyrEi4WhPdpiVImNz1xlFi F0w+araI54W/BnQgnypTb8W1Rwl92/7TehtW0EaNs/PlOmXaGApnO65wbMI7VfPD/0+C ia4TzJ3DyHepevMViy99aa2El2ek6/Fab7dnlG30A9OLRwXXDlGIllYZEfg6ARYoxLKR IdJA== X-Gm-Message-State: ALKqPwflVQxX+yxJoUTS6T4t5P0JLN6yfQbb8PXrvUN+M2iWTq9rKb5c ntgxaD3TRm7t9U+QeKhis7rj4fVDX8E= X-Google-Smtp-Source: AB8JxZquEeFcdDXoPV60Xh6CebarkDhhjITHZ+83m2tShacFxkxmHTuwdC9uVRl/UfjOBp9AyJHdcQ== X-Received: by 2002:a17:902:8647:: with SMTP id y7-v6mr16127970plt.86.1526423171779; Tue, 15 May 2018 15:26:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:32 -0700 Message-Id: <20180515222540.9988-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v6 20/28] fpu/softfloat: Use float*_silence_nan in propagateFloat*NaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 We have already checked the arguments for SNaN; we don't need to do it again. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 44 +++++++++++++++++++++++++++++--------- 1 file changed, 34 insertions(+), 10 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 995a0132c6..4fa068a5dc 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -498,7 +498,7 @@ static float32 commonNaNToFloat32(commonNaNT a, float_s= tatus *status) | The routine is passed various bits of information about the | two NaNs and should return 0 to select NaN a and 1 for NaN b. | Note that signalling NaNs are always squashed to quiet NaNs -| by the caller, by calling floatXX_maybe_silence_nan() before +| by the caller, by calling floatXX_silence_nan() before | returning them. | | aIsLargerSignificand is only valid if both a and b are NaNs @@ -536,7 +536,7 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIs= QNaN, flag bIsSNaN, { /* According to MIPS specifications, if one of the two operands is * a sNaN, a new qNaN has to be generated. This is done in - * floatXX_maybe_silence_nan(). For qNaN inputs the specifications + * floatXX_silence_nan(). For qNaN inputs the specifications * says: "When possible, this QNaN result is one of the operand QNaN * values." In practice it seems that most implementations choose * the first operand if both operands are qNaN. In short this gives @@ -788,9 +788,15 @@ static float32 propagateFloat32NaN(float32 a, float32 = b, float_status *status) =20 if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return float32_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return float32_silence_nan(b, status); + } + return b; } else { - return float32_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return float32_silence_nan(a, status); + } + return a; } } =20 @@ -950,9 +956,15 @@ static float64 propagateFloat64NaN(float64 a, float64 = b, float_status *status) =20 if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return float64_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return float64_silence_nan(b, status); + } + return b; } else { - return float64_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return float64_silence_nan(a, status); + } + return a; } } =20 @@ -1121,9 +1133,15 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b= , float_status *status) =20 if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return floatx80_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return floatx80_silence_nan(b, status); + } + return b; } else { - return floatx80_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return floatx80_silence_nan(a, status); + } + return a; } } =20 @@ -1270,8 +1288,14 @@ static float128 propagateFloat128NaN(float128 a, flo= at128 b, =20 if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return float128_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return float128_silence_nan(b, status); + } + return b; } else { - return float128_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return float128_silence_nan(a, status); + } + return a; } } --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526424082704124.72895123326953; Tue, 15 May 2018 15:41:22 -0700 (PDT) Received: from localhost ([::1]:36389 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIidF-0006Aj-PZ for importer@patchew.org; Tue, 15 May 2018 18:41:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39726) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOe-0003fV-Vk for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOc-0007VA-SK for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:16 -0400 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:45624) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOc-0007Lc-Hn for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:14 -0400 Received: by mail-pl0-x244.google.com with SMTP id bi12-v6so854212plb.12 for ; Tue, 15 May 2018 15:26:14 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.26.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:26:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RsqR6JXjuFwzF6uI5jtDfE8pIEemv36hmgqjkM16TQs=; b=LGBhHPeagXfuCO0ARHAZMKcRNaRtq6p4Rpz31E35mKotSzHt7gYBvu4tIW3d5VYnrr XlyOMpxBW2LSxG6++xm4fCxGBij0oN0QXVqBhMfio3RLTXHAk3ryl4sS2tqOmk8bMfbi mTmHiFCXIdCmaLBkcfSACiNmBrHcjQoVTMgNs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RsqR6JXjuFwzF6uI5jtDfE8pIEemv36hmgqjkM16TQs=; b=F639k6vAsIMIAPQ4MCgckjMguxfE0YS8WXrXkvYrsly4f+V4G8xwqzqjuhkgaeBlKV kwUgUVKyxVcQQCrCZtfG5wNajrWWqErjMSargfaczrxCJr2gQr7dxnNtU0DTdVmQihlu jaB1Q88LmRX2JhHNnsMYSiAdmssgBQeu86o6i+M8JP3kzNKnhvDI1NCRPu9JWgCbtyPn Gzbpub4az4j/EYgDNVsEep7kWv9H4SjABSqQivErlcQeZ4PtKGDUXgcc/gQ7faDQOcHa qDIOLROYI0vtzV1ldU74LSYzle/Yei+AJJUEPZIe628CP41j3+BZ5xoxcbjXOoqX1kQm J5Bg== X-Gm-Message-State: ALKqPwc6jAF2GUrm3R4jUZxtKCvBKknVQYaTKthc2BOBCBXkyta7iFDn MGjN0mNZEDczxp3qxyH4k74EIw28utI= X-Google-Smtp-Source: AB8JxZqUFrOSgf1OABM2sEiu/1oiLr9793M8c1j7udNNaRvUaMTUHOydxdUohscvV9q0aCGc5zBA/w== X-Received: by 2002:a17:902:aa94:: with SMTP id d20-v6mr16822742plr.323.1526423173136; Tue, 15 May 2018 15:26:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:33 -0700 Message-Id: <20180515222540.9988-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v6 21/28] fpu/softfloat: Remove floatX_maybe_silence_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 These functions are now unused. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 63 -------------------------------------- include/fpu/softfloat.h | 5 --- 2 files changed, 68 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 4fa068a5dc..d7033b7757 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -364,19 +364,6 @@ float16 float16_silence_nan(float16 a, float_status *s= tatus) #endif } =20 -/*------------------------------------------------------------------------= ---- -| Returns a quiet NaN if the half-precision floating point value `a' is a -| signaling NaN; otherwise returns `a'. -*-------------------------------------------------------------------------= ---*/ - -float16 float16_maybe_silence_nan(float16 a, float_status *status) -{ - if (float16_is_signaling_nan(a, status)) { - return float16_silence_nan(a, status); - } - return a; -} - /*------------------------------------------------------------------------= ---- | Returns 1 if the single-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -438,18 +425,6 @@ float32 float32_silence_nan(float32 a, float_status *s= tatus) } #endif } -/*------------------------------------------------------------------------= ---- -| Returns a quiet NaN if the single-precision floating point value `a' is a -| signaling NaN; otherwise returns `a'. -*-------------------------------------------------------------------------= ---*/ - -float32 float32_maybe_silence_nan(float32 a, float_status *status) -{ - if (float32_is_signaling_nan(a, status)) { - return float32_silence_nan(a, status); - } - return a; -} =20 /*------------------------------------------------------------------------= ---- | Returns the result of converting the single-precision floating-point NaN @@ -864,18 +839,6 @@ float64 float64_silence_nan(float64 a, float_status *s= tatus) #endif } =20 -/*------------------------------------------------------------------------= ---- -| Returns a quiet NaN if the double-precision floating point value `a' is a -| signaling NaN; otherwise returns `a'. -*-------------------------------------------------------------------------= ---*/ - -float64 float64_maybe_silence_nan(float64 a, float_status *status) -{ - if (float64_is_signaling_nan(a, status)) { - return float64_silence_nan(a, status); - } - return a; -} =20 /*------------------------------------------------------------------------= ---- | Returns the result of converting the double-precision floating-point NaN @@ -1037,19 +1000,6 @@ floatx80 floatx80_silence_nan(floatx80 a, float_stat= us *status) #endif } =20 -/*------------------------------------------------------------------------= ---- -| Returns a quiet NaN if the extended double-precision floating point value -| `a' is a signaling NaN; otherwise returns `a'. -*-------------------------------------------------------------------------= ---*/ - -floatx80 floatx80_maybe_silence_nan(floatx80 a, float_status *status) -{ - if (floatx80_is_signaling_nan(a, status)) { - return floatx80_silence_nan(a, status); - } - return a; -} - /*------------------------------------------------------------------------= ---- | Returns the result of converting the extended double-precision floating- | point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, t= he @@ -1204,19 +1154,6 @@ float128 float128_silence_nan(float128 a, float_stat= us *status) #endif } =20 -/*------------------------------------------------------------------------= ---- -| Returns a quiet NaN if the quadruple-precision floating point value `a' = is -| a signaling NaN; otherwise returns `a'. -*-------------------------------------------------------------------------= ---*/ - -float128 float128_maybe_silence_nan(float128 a, float_status *status) -{ - if (float128_is_signaling_nan(a, status)) { - return float128_silence_nan(a, status); - } - return a; -} - /*------------------------------------------------------------------------= ---- | Returns the result of converting the quadruple-precision floating-point = NaN | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index a6860e858d..69f4dbc4db 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -258,7 +258,6 @@ int float16_compare_quiet(float16, float16, float_statu= s *status); int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); float16 float16_silence_nan(float16, float_status *status); -float16 float16_maybe_silence_nan(float16, float_status *status); =20 static inline int float16_is_any_nan(float16 a) { @@ -370,7 +369,6 @@ float32 float32_maxnummag(float32, float32, float_statu= s *status); int float32_is_quiet_nan(float32, float_status *status); int float32_is_signaling_nan(float32, float_status *status); float32 float32_silence_nan(float32, float_status *status); -float32 float32_maybe_silence_nan(float32, float_status *status); float32 float32_scalbn(float32, int, float_status *status); =20 static inline float32 float32_abs(float32 a) @@ -500,7 +498,6 @@ float64 float64_maxnummag(float64, float64, float_statu= s *status); int float64_is_quiet_nan(float64 a, float_status *status); int float64_is_signaling_nan(float64, float_status *status); float64 float64_silence_nan(float64, float_status *status); -float64 float64_maybe_silence_nan(float64, float_status *status); float64 float64_scalbn(float64, int, float_status *status); =20 static inline float64 float64_abs(float64 a) @@ -604,7 +601,6 @@ int floatx80_compare_quiet(floatx80, floatx80, float_st= atus *status); int floatx80_is_quiet_nan(floatx80, float_status *status); int floatx80_is_signaling_nan(floatx80, float_status *status); floatx80 floatx80_silence_nan(floatx80, float_status *status); -floatx80 floatx80_maybe_silence_nan(floatx80, float_status *status); floatx80 floatx80_scalbn(floatx80, int, float_status *status); =20 static inline floatx80 floatx80_abs(floatx80 a) @@ -816,7 +812,6 @@ int float128_compare_quiet(float128, float128, float_st= atus *status); int float128_is_quiet_nan(float128, float_status *status); int float128_is_signaling_nan(float128, float_status *status); float128 float128_silence_nan(float128, float_status *status); -float128 float128_maybe_silence_nan(float128, float_status *status); float128 float128_scalbn(float128, int, float_status *status); =20 static inline float128 float128_abs(float128 a) --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526424262579964.5735850480664; Tue, 15 May 2018 15:44:22 -0700 (PDT) Received: from localhost ([::1]:36404 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIig9-0000Cb-M3 for importer@patchew.org; Tue, 15 May 2018 18:44:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39750) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOi-0003hR-Bq for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOe-0007jM-C4 for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:20 -0400 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:45622) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOe-0007bH-0K for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:16 -0400 Received: by mail-pl0-x241.google.com with SMTP id bi12-v6so854230plb.12 for ; Tue, 15 May 2018 15:26:15 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.26.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:26:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QX6s0T1/IZNDx7UzuxtEEhPLHsnQGR5YfG/MYvbkKCg=; b=Ez1j8UHxrRUrISS02YQXkq6lXowuTPpjk6xsduzhDAz9MMc5jngQhQFTyfSoCQHewt E9VmVkDP72yJupE3VmnZFlF2LlbJx6uigFvWoG2EQUsGCTGT5ObwgQSVWKgKhaq0BrMb +CvC1T3UJb1r8o4EGwSaFPMhKVQU/GJ7xQF/A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QX6s0T1/IZNDx7UzuxtEEhPLHsnQGR5YfG/MYvbkKCg=; b=uILy6iDNLER+YrFFWpZvbByGCF1jT71JYrb1fp4r+aQoSAGmHOwaCE251k/gAZwBoW +84KeRsgSjsOQ8jl8eyhlqkDJTUJ/CxxzXcxS18gb4nsXRwp2u/hvM7s8xPfH3TmVFZ6 MKwL+enBK7lyHy63ob6m2nKKqUazOTvtsZDz15NW4l3/aq+g0w4NQdhl2hE4vK4xZ3cP j1uOr+VH7Npu7XeCsRinC7uUFQdVhA8abcBtP9ri+uc7BrzUAgut/goni+LBmmoPpq+A PUbwWhSLr3YtK1QZWyHB6i7roXgn80O0RhE0kbweFHYS5yUSjWM3X2Fp96KJ71AoF2Z2 bFlw== X-Gm-Message-State: ALKqPwc/nMaBNCXJ8kzrUuMyQHG+FtIOq7Edg5zd5IdtnUwdsgw78kgA 9fkyhXYdC79dKQPtySke1ER5SPpMSZE= X-Google-Smtp-Source: AB8JxZoiQ7kRzqmOlz4ehPtlPbpb52cjy4rUJmXY1spKDXSaBbc2WkEt9OKvfaS65MR0ajN8qLykdw== X-Received: by 2002:a17:902:9a4b:: with SMTP id x11-v6mr16463114plv.176.1526423174518; Tue, 15 May 2018 15:26:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:34 -0700 Message-Id: <20180515222540.9988-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v6 22/28] fpu/softfloat: Specialize on snan_bit_is_one X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, Alexander Graf , Guan Xuetao , Yongbok Kim , Aurelien Jarno , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Only MIPS requires snan_bit_is_one to be variable. While we are specializing softfloat behaviour, allow other targets to eliminate this runtime check. Cc: Aurelien Jarno Cc: Yongbok Kim Cc: David Gibson Cc: Alexander Graf Cc: Guan Xuetao Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v5 - do not remove the set_snan_bit_is_one function - tidy the language in the snan_bit_is_one block comment --- fpu/softfloat-specialize.h | 68 ++++++++++++++++++++++------------- include/fpu/softfloat-types.h | 1 + target/hppa/cpu.c | 1 - target/ppc/fpu_helper.c | 1 - target/sh4/cpu.c | 1 - target/unicore32/cpu.c | 2 -- 6 files changed, 44 insertions(+), 30 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index d7033b7757..d1e06da75b 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -79,13 +79,31 @@ this code that are retained. * version 2 or later. See the COPYING file in the top-level directory. */ =20 -#if defined(TARGET_XTENSA) /* Define for architectures which deviate from IEEE in not supporting * signaling NaNs (so all NaNs are treated as quiet). */ +#if defined(TARGET_XTENSA) #define NO_SIGNALING_NANS 1 #endif =20 +/* Define how the architecture discriminates signaling NaNs. + * This done with the most significant bit of the fraction. + * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008 + * the msb must be zero. MIPS is (so far) unique in supporting both the + * 2008 revision and backward compatibility with their original choice. + * Thus for MIPS we must make the choice at runtime. + */ +static inline flag snan_bit_is_one(float_status *status) +{ +#if defined(TARGET_MIPS) + return status->snan_bit_is_one; +#elif defined(TARGET_HPPA) || defined(TARGET_UNICORE32) || defined(TARGET_= SH4) + return 1; +#else + return 0; +#endif +} + /*------------------------------------------------------------------------= ---- | For the deconstructed floating-point with fraction FRAC, return true | if the fraction represents a signalling NaN; otherwise false. @@ -97,7 +115,7 @@ static bool parts_is_snan_frac(uint64_t frac, float_stat= us *status) return false; #else flag msb =3D extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); - return msb =3D=3D status->snan_bit_is_one; + return msb =3D=3D snan_bit_is_one(status); #endif } =20 @@ -118,7 +136,7 @@ static FloatParts parts_default_nan(float_status *statu= s) #elif defined(TARGET_HPPA) frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { frac =3D (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; } else { #if defined(TARGET_MIPS) @@ -151,7 +169,7 @@ static FloatParts parts_silence_nan(FloatParts a, float= _status *status) a.frac &=3D ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); a.frac |=3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return parts_default_nan(status); } else { a.frac |=3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); @@ -169,7 +187,7 @@ float16 float16_default_nan(float_status *status) #if defined(TARGET_ARM) return const_float16(0x7E00); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return const_float16(0x7DFF); } else { #if defined(TARGET_MIPS) @@ -195,7 +213,7 @@ float32 float32_default_nan(float_status *status) #elif defined(TARGET_HPPA) return const_float32(0x7FA00000); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return const_float32(0x7FBFFFFF); } else { #if defined(TARGET_MIPS) @@ -220,7 +238,7 @@ float64 float64_default_nan(float_status *status) #elif defined(TARGET_HPPA) return const_float64(LIT64(0x7FF4000000000000)); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return const_float64(LIT64(0x7FF7FFFFFFFFFFFF)); } else { #if defined(TARGET_MIPS) @@ -242,7 +260,7 @@ floatx80 floatx80_default_nan(float_status *status) r.low =3D LIT64(0xFFFFFFFFFFFFFFFF); r.high =3D 0x7FFF; #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { r.low =3D LIT64(0xBFFFFFFFFFFFFFFF); r.high =3D 0x7FFF; } else { @@ -274,7 +292,7 @@ float128 float128_default_nan(float_status *status) { float128 r; =20 - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { r.low =3D LIT64(0xFFFFFFFFFFFFFFFF); r.high =3D LIT64(0x7FFF7FFFFFFFFFFF); } else { @@ -319,7 +337,7 @@ int float16_is_quiet_nan(float16 a_, float_status *stat= us) return float16_is_any_nan(a_); #else uint16_t a =3D float16_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return (((a >> 9) & 0x3F) =3D=3D 0x3E) && (a & 0x1FF); } else { return ((a & ~0x8000) >=3D 0x7C80); @@ -338,7 +356,7 @@ int float16_is_signaling_nan(float16 a_, float_status *= status) return 0; #else uint16_t a =3D float16_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((a & ~0x8000) >=3D 0x7C80); } else { return (((a >> 9) & 0x3F) =3D=3D 0x3E) && (a & 0x1FF); @@ -356,7 +374,7 @@ float16 float16_silence_nan(float16 a, float_status *st= atus) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return float16_default_nan(status); } else { return a | (1 << 9); @@ -375,7 +393,7 @@ int float32_is_quiet_nan(float32 a_, float_status *stat= us) return float32_is_any_nan(a_); #else uint32_t a =3D float32_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return (((a >> 22) & 0x1FF) =3D=3D 0x1FE) && (a & 0x003FFFFF); } else { return ((uint32_t)(a << 1) >=3D 0xFF800000); @@ -394,7 +412,7 @@ int float32_is_signaling_nan(float32 a_, float_status *= status) return 0; #else uint32_t a =3D float32_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((uint32_t)(a << 1) >=3D 0xFF800000); } else { return (((a >> 22) & 0x1FF) =3D=3D 0x1FE) && (a & 0x003FFFFF); @@ -412,7 +430,7 @@ float32 float32_silence_nan(float32 a, float_status *st= atus) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { # ifdef TARGET_HPPA a &=3D ~0x00400000; a |=3D 0x00200000; @@ -651,7 +669,7 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, fl= ag bIsQNaN, flag bIsSNaN, return 3; } =20 - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { /* Prefer sNaN over qNaN, in the a, b, c order. */ if (aIsSNaN) { return 0; @@ -786,7 +804,7 @@ int float64_is_quiet_nan(float64 a_, float_status *stat= us) return float64_is_any_nan(a_); #else uint64_t a =3D float64_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return (((a >> 51) & 0xFFF) =3D=3D 0xFFE) && (a & 0x0007FFFFFFFFFFFFULL); } else { @@ -806,7 +824,7 @@ int float64_is_signaling_nan(float64 a_, float_status *= status) return 0; #else uint64_t a =3D float64_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((a << 1) >=3D 0xFFF0000000000000ULL); } else { return (((a >> 51) & 0xFFF) =3D=3D 0xFFE) @@ -825,7 +843,7 @@ float64 float64_silence_nan(float64 a, float_status *st= atus) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { # ifdef TARGET_HPPA a &=3D ~0x0008000000000000ULL; a |=3D 0x0004000000000000ULL; @@ -942,7 +960,7 @@ int floatx80_is_quiet_nan(floatx80 a, float_status *sta= tus) #ifdef NO_SIGNALING_NANS return floatx80_is_any_nan(a); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { uint64_t aLow; =20 aLow =3D a.low & ~0x4000000000000000ULL; @@ -967,7 +985,7 @@ int floatx80_is_signaling_nan(floatx80 a, float_status = *status) #ifdef NO_SIGNALING_NANS return 0; #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((a.high & 0x7FFF) =3D=3D 0x7FFF) && ((a.low << 1) >=3D 0x8000000000000000ULL); } else { @@ -991,7 +1009,7 @@ floatx80 floatx80_silence_nan(floatx80 a, float_status= *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return floatx80_default_nan(status); } else { a.low |=3D LIT64(0xC000000000000000); @@ -1105,7 +1123,7 @@ int float128_is_quiet_nan(float128 a, float_status *s= tatus) #ifdef NO_SIGNALING_NANS return float128_is_any_nan(a); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return (((a.high >> 47) & 0xFFFF) =3D=3D 0xFFFE) && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); } else { @@ -1125,7 +1143,7 @@ int float128_is_signaling_nan(float128 a, float_statu= s *status) #ifdef NO_SIGNALING_NANS return 0; #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((a.high << 1) >=3D 0xFFFF000000000000ULL) && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); } else { @@ -1145,7 +1163,7 @@ float128 float128_silence_nan(float128 a, float_statu= s *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return float128_default_nan(status); } else { a.high |=3D LIT64(0x0000800000000000); diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 4e378cb612..2aae6a89b1 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -173,6 +173,7 @@ typedef struct float_status { /* should denormalised inputs go to zero and set the input_denormal fl= ag? */ flag flush_inputs_to_zero; flag default_nan_mode; + /* not always used -- see snan_bit_is_one() in softfloat-specialize.h = */ flag snan_bit_is_one; } float_status; =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index c261b6b090..00bf444620 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -141,7 +141,6 @@ static void hppa_cpu_initfn(Object *obj) cs->env_ptr =3D env; cs->exception_index =3D -1; cpu_hppa_loaded_fr0(env); - set_snan_bit_is_one(true, &env->fp_status); cpu_hppa_put_psw(env, PSW_W); } =20 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 9ae418a577..d31a933cbb 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -3382,7 +3382,6 @@ void helper_xssqrtqp(CPUPPCState *env, uint32_t opcod= e) xt.f128 =3D xb.f128; } else if (float128_is_neg(xb.f128) && !float128_is_zero(xb.f128))= { float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); - set_snan_bit_is_one(0, &env->fp_status); xt.f128 =3D float128_default_nan(&env->fp_status); } } diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 541ffc2d97..b9f393b7c7 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -71,7 +71,6 @@ static void superh_cpu_reset(CPUState *s) set_flush_to_zero(1, &env->fp_status); #endif set_default_nan_mode(1, &env->fp_status); - set_snan_bit_is_one(1, &env->fp_status); } =20 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *inf= o) diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 29d160a88d..68f978d80b 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -70,7 +70,6 @@ static void unicore_ii_cpu_initfn(Object *obj) =20 set_feature(env, UC32_HWCAP_CMOV); set_feature(env, UC32_HWCAP_UCF64); - set_snan_bit_is_one(1, &env->ucf64.fp_status); } =20 static void uc32_any_cpu_initfn(Object *obj) @@ -83,7 +82,6 @@ static void uc32_any_cpu_initfn(Object *obj) =20 set_feature(env, UC32_HWCAP_CMOV); set_feature(env, UC32_HWCAP_UCF64); - set_snan_bit_is_one(1, &env->ucf64.fp_status); } =20 static void uc32_cpu_realizefn(DeviceState *dev, Error **errp) --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152642455851176.43072780142802; Tue, 15 May 2018 15:49:18 -0700 (PDT) Received: from localhost ([::1]:36942 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiks-0004gI-Ca for importer@patchew.org; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.26.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:26:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=69KH6e0KmS/GOAScDljSvnKlAK/69zrvY+8SeGJmqVM=; b=bFp9WkdeNIlJNVtQmBjEZ0ulT8QovOgNVU3//9pLDGW4RV9CXtyTfw2CP3CB8bKDjf i1Ygl/1RjsYB1flATX/BMJPrnfaqQyy942wm4JesQIYZ4ZWyy3lmzlnf9mzq1GbvEmVJ avmiF7hsM1qwp7gBjT7Izz30iySatmdugcwzI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=69KH6e0KmS/GOAScDljSvnKlAK/69zrvY+8SeGJmqVM=; b=ohQFoPMaFPIC7YfsPzoxowAFwVQa3znPW2NRr/q9sA7YfvoPvkN3Qmkfz/0sU1ZLrb ZouwQa+XBcLJsG5caSVtl0764rurFzGW0bzTHLfiksXyEhQVKtK5yxCSILQWBmoddRA1 hT2H/oBqYzDYDCygnFW3Mrs4wkRn3Qpc4V3zhpuQbnjuaWeobOP7nwkDRgtw5Xvorx8/ K+BP/8J3IB6WfTp44VI9FGim/wgkjlArLjlv/dtTzvhPWl81suU5vqaierkogz5PW3A9 PG8n7/a5pHpTO78AKwJvEVDPbCJ7KIXa/R8zNMqD4geYokCel+I0w52p2uT42r32zS+/ i/xA== X-Gm-Message-State: ALKqPwdw4+wFBQqEZidjZfNTOn/+yL0DIXpUBJh1f8BZiZkSiluKbNKp +SnbEJBPQGlEIrSMeuyvUG1oimIlOK4= X-Google-Smtp-Source: AB8JxZobpY5S8xdneEyJX8BuhnuI/RVdpmrSv34BjKK+V8uvBJLbjdAfbR4Ts+nZ/BCx2Rd3zvciAg== X-Received: by 2002:a17:902:6006:: with SMTP id r6-v6mr16006071plj.70.1526423175924; Tue, 15 May 2018 15:26:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:35 -0700 Message-Id: <20180515222540.9988-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v6 23/28] fpu/softfloat: Make is_nan et al available to softfloat-specialize.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 We will need these helpers within softfloat-specialize.h, so move the definitions above the include. After specialization, they will not always be used so mark them to avoid the Werror. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 55e6701f26..ea252e0c84 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -181,6 +181,22 @@ typedef enum __attribute__ ((__packed__)) { float_class_snan, } FloatClass; =20 +/* Simple helpers for checking if, or what kind of, NaN we have */ +static inline __attribute__((unused)) bool is_nan(FloatClass c) +{ + return unlikely(c >=3D float_class_qnan); +} + +static inline __attribute__((unused)) bool is_snan(FloatClass c) +{ + return c =3D=3D float_class_snan; +} + +static inline __attribute__((unused)) bool is_qnan(FloatClass c) +{ + return c =3D=3D float_class_qnan; +} + /* * Structure holding all of the decomposed parts of a float. The * exponent is unbiased and the fraction is normalized. All @@ -536,20 +552,6 @@ static float64 float64_round_pack_canonical(FloatParts= p, float_status *s) return float64_pack_raw(round_canonical(p, s, &float64_params)); } =20 -/* Simple helpers for checking if what NaN we have */ -static bool is_nan(FloatClass c) -{ - return unlikely(c >=3D float_class_qnan); -} -static bool is_snan(FloatClass c) -{ - return c =3D=3D float_class_snan; -} -static bool is_qnan(FloatClass c) -{ - return c =3D=3D float_class_qnan; -} - static FloatParts return_nan(FloatParts a, float_status *s) { switch (a.cls) { --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526424732049948.5983259776114; Tue, 15 May 2018 15:52:12 -0700 (PDT) Received: from localhost ([::1]:37363 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIinj-00078b-7D for importer@patchew.org; Tue, 15 May 2018 18:52:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39775) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOk-0003k2-IS for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOh-0008BA-Cg for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:22 -0400 Received: from mail-pf0-x234.google.com ([2607:f8b0:400e:c00::234]:43863) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOh-00084T-3B for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:19 -0400 Received: by mail-pf0-x234.google.com with SMTP id j20-v6so733114pff.10 for ; Tue, 15 May 2018 15:26:19 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.26.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:26:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CnatWtYyDMAbIeE888hytjlz3MRjvKQhD+a4WDjwIBs=; b=E05y5hGGa9G8xQDAXgaGOLBj3XZ0np6A3YR7WDkjJ3JOQcVb1NmXdIzZ2zOZM6rjaT fhJ4rfrqHAs+xXI4SipMVKZVYG1Yf5NoY+qfJENBJ0+7rt/xW6fSbAOje/2v2mfaLHNz 1a9S+X4HaQlAbCd/lCvZImp3ySvgXOue+YhuU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CnatWtYyDMAbIeE888hytjlz3MRjvKQhD+a4WDjwIBs=; b=fWBFZLugIeIo5I/+mzt73vtNrEtr5AJWC+ur+ylarLwNSknalSupm2LL/UAL0SFAec lyDRleZ603lcLTnX6ShO9x78cpdKSHqTCfOdxCWv5udNyGWOE3Xcsa9rAV+3iEvT20jE 67gfBMoXMDsjaIYpYeBqiWbDtdFfFygmSwJ34TjWzi6eKlsbmuCMv8cVgsyVQlF37rQi TPrngijA1klSwhbBOl7/I4o+KpSgnJjqDd06XYTzJSK3f3UZrDJzwfP9mSZkkfWQsv3e +JkV49sXpIPa3wZRrFF1CkOJF1PYv/OB2lCZIqWVa/9yTSblo6PdQiSQ0RjcI9xwA1lw MwRA== X-Gm-Message-State: ALKqPwdGjZvfDv6yYUXOQGY8tpDy1QDDyHx2VtRBBAswItBZcpfY/3tT vdp9TQrlqCxsJgq4+IPmbyRUZ9F9e2o= X-Google-Smtp-Source: AB8JxZrlicpC0VOS5QxbWx7vZpJE0WP7+m7p0dMIVOANR8/5ZTZxeZrJB5GSRwn7fqCcKQMM8u2O2w== X-Received: by 2002:a62:d8c7:: with SMTP id e190-v6mr16964511pfg.161.1526423177680; Tue, 15 May 2018 15:26:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:36 -0700 Message-Id: <20180515222540.9988-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::234 Subject: [Qemu-devel] [PATCH v6 24/28] fpu/softfloat: Pass FloatClass to pickNaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For each operand, pass a single enumeration instead of a pair of booleans. The commit also merges multiple different ifdef-selected implementations of pickNaN into a single function whose body is ifdef-selected. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- fpu/softfloat-specialize.h | 168 ++++++++++++++++++------------------- fpu/softfloat.c | 3 +- 2 files changed, 82 insertions(+), 89 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index d1e06da75b..2695183188 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -501,10 +501,10 @@ static float32 commonNaNToFloat32(commonNaNT a, float= _status *status) | tie-break rule. *-------------------------------------------------------------------------= ---*/ =20 -#if defined(TARGET_ARM) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, +static int pickNaN(FloatClass a_cls, FloatClass b_cls, flag aIsLargerSignificand) { +#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take * the first of: * 1. A if it is signaling @@ -513,20 +513,6 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bI= sQNaN, flag bIsSNaN, * 4. B (quiet) * A signaling NaN is always quietened before returning it. */ - if (aIsSNaN) { - return 0; - } else if (bIsSNaN) { - return 1; - } else if (aIsQNaN) { - return 0; - } else { - return 1; - } -} -#elif defined(TARGET_MIPS) || defined(TARGET_HPPA) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ /* According to MIPS specifications, if one of the two operands is * a sNaN, a new qNaN has to be generated. This is done in * floatXX_silence_nan(). For qNaN inputs the specifications @@ -540,35 +526,21 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag b= IsQNaN, flag bIsSNaN, * 4. B (quiet) * A signaling NaN is always silenced before returning it. */ - if (aIsSNaN) { + if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; } else { return 1; } -} -#elif defined(TARGET_PPC) || defined(TARGET_XTENSA) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ +#elif defined(TARGET_PPC) || defined(TARGET_XTENSA) || defined(TARGET_M68K) /* PowerPC propagation rules: * 1. A if it sNaN or qNaN * 2. B if it sNaN or qNaN * A signaling NaN is always silenced before returning it. */ - if (aIsSNaN || aIsQNaN) { - return 0; - } else { - return 1; - } -} -#elif defined(TARGET_M68K) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL * 3.4 FLOATING-POINT INSTRUCTION DETAILS * If either operand, but not both operands, of an operation is a @@ -583,16 +555,12 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag b= IsQNaN, flag bIsSNaN, * a nonsignaling NaN. The operation then continues as described in the * preceding paragraph for nonsignaling NaNs. */ - if (aIsQNaN || aIsSNaN) { /* a is the destination operand */ - return 0; /* return the destination operand */ + if (is_nan(a_cls)) { + return 0; } else { - return 1; /* return b */ + return 1; } -} #else -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ /* This implements x87 NaN propagation rules: * SNaN + QNaN =3D> return the QNaN * two SNaNs =3D> return the one with the larger significand, silenced @@ -603,13 +571,13 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag b= IsQNaN, flag bIsSNaN, * If we get down to comparing significands and they are the same, * return the NaN with the positive sign bit (if any). */ - if (aIsSNaN) { - if (bIsSNaN) { + if (is_snan(a_cls)) { + if (is_snan(b_cls)) { return aIsLargerSignificand ? 0 : 1; } - return bIsQNaN ? 1 : 0; - } else if (aIsQNaN) { - if (bIsSNaN || !bIsQNaN) { + return is_qnan(b_cls) ? 1 : 0; + } else if (is_qnan(a_cls)) { + if (is_snan(b_cls) || !is_qnan(b_cls)) { return 0; } else { return aIsLargerSignificand ? 0 : 1; @@ -617,8 +585,8 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIs= QNaN, flag bIsSNaN, } else { return 1; } -} #endif +} =20 /*------------------------------------------------------------------------= ---- | Select which NaN to propagate for a three-input operation. @@ -752,18 +720,26 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, = flag bIsQNaN, flag bIsSNaN, =20 static float32 propagateFloat32NaN(float32 a, float32 b, float_status *sta= tus) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; uint32_t av, bv; + FloatClass a_cls, b_cls; + + /* This is not complete, but is good enough for pickNaN. */ + a_cls =3D (!float32_is_any_nan(a) + ? float_class_normal + : float32_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls =3D (!float32_is_any_nan(b) + ? float_class_normal + : float32_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); =20 - aIsQuietNaN =3D float32_is_quiet_nan(a, status); - aIsSignalingNaN =3D float32_is_signaling_nan(a, status); - bIsQuietNaN =3D float32_is_quiet_nan(b, status); - bIsSignalingNaN =3D float32_is_signaling_nan(b, status); av =3D float32_val(a); bv =3D float32_val(b); =20 - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } =20 @@ -779,14 +755,13 @@ static float32 propagateFloat32NaN(float32 a, float32= b, float_status *status) aIsLargerSignificand =3D (av < bv) ? 1 : 0; } =20 - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return float32_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return float32_silence_nan(a, status); } return a; @@ -908,18 +883,26 @@ static float64 commonNaNToFloat64(commonNaNT a, float= _status *status) =20 static float64 propagateFloat64NaN(float64 a, float64 b, float_status *sta= tus) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; uint64_t av, bv; + FloatClass a_cls, b_cls; + + /* This is not complete, but is good enough for pickNaN. */ + a_cls =3D (!float64_is_any_nan(a) + ? float_class_normal + : float64_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls =3D (!float64_is_any_nan(b) + ? float_class_normal + : float64_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); =20 - aIsQuietNaN =3D float64_is_quiet_nan(a, status); - aIsSignalingNaN =3D float64_is_signaling_nan(a, status); - bIsQuietNaN =3D float64_is_quiet_nan(b, status); - bIsSignalingNaN =3D float64_is_signaling_nan(b, status); av =3D float64_val(a); bv =3D float64_val(b); =20 - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } =20 @@ -935,14 +918,13 @@ static float64 propagateFloat64NaN(float64 a, float64= b, float_status *status) aIsLargerSignificand =3D (av < bv) ? 1 : 0; } =20 - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return float64_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return float64_silence_nan(a, status); } return a; @@ -1075,15 +1057,22 @@ static floatx80 commonNaNToFloatx80(commonNaNT a, f= loat_status *status) =20 floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; + FloatClass a_cls, b_cls; =20 - aIsQuietNaN =3D floatx80_is_quiet_nan(a, status); - aIsSignalingNaN =3D floatx80_is_signaling_nan(a, status); - bIsQuietNaN =3D floatx80_is_quiet_nan(b, status); - bIsSignalingNaN =3D floatx80_is_signaling_nan(b, status); + /* This is not complete, but is good enough for pickNaN. */ + a_cls =3D (!floatx80_is_any_nan(a) + ? float_class_normal + : floatx80_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls =3D (!floatx80_is_any_nan(b) + ? float_class_normal + : floatx80_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); =20 - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } =20 @@ -1099,14 +1088,13 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 = b, float_status *status) aIsLargerSignificand =3D (a.high < b.high) ? 1 : 0; } =20 - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return floatx80_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return floatx80_silence_nan(a, status); } return a; @@ -1217,15 +1205,22 @@ static float128 commonNaNToFloat128(commonNaNT a, f= loat_status *status) static float128 propagateFloat128NaN(float128 a, float128 b, float_status *status) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; + FloatClass a_cls, b_cls; =20 - aIsQuietNaN =3D float128_is_quiet_nan(a, status); - aIsSignalingNaN =3D float128_is_signaling_nan(a, status); - bIsQuietNaN =3D float128_is_quiet_nan(b, status); - bIsSignalingNaN =3D float128_is_signaling_nan(b, status); + /* This is not complete, but is good enough for pickNaN. */ + a_cls =3D (!float128_is_any_nan(a) + ? float_class_normal + : float128_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls =3D (!float128_is_any_nan(b) + ? float_class_normal + : float128_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); =20 - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } =20 @@ -1241,14 +1236,13 @@ static float128 propagateFloat128NaN(float128 a, fl= oat128 b, aIsLargerSignificand =3D (a.high < b.high) ? 1 : 0; } =20 - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return float128_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return float128_silence_nan(a, status); } return a; diff --git a/fpu/softfloat.c b/fpu/softfloat.c index ea252e0c84..55954385ff 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -580,8 +580,7 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, = float_status *s) if (s->default_nan_mode) { return parts_default_nan(s); } else { - if (pickNaN(is_qnan(a.cls), is_snan(a.cls), - is_qnan(b.cls), is_snan(b.cls), + if (pickNaN(a.cls, b.cls, a.frac > b.frac || (a.frac =3D=3D b.frac && a.sign < b.sign))) { a =3D b; --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526423671628523.5073516095817; Tue, 15 May 2018 15:34:31 -0700 (PDT) Received: from localhost ([::1]:36349 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiWY-0000YG-10 for importer@patchew.org; Tue, 15 May 2018 18:34:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39781) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOl-0003ky-Cg for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOi-0008MA-Qs for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:23 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:39648) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOi-0008GI-Eq for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:20 -0400 Received: by mail-pf0-x244.google.com with SMTP id a22-v6so736580pfn.6 for ; Tue, 15 May 2018 15:26:20 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.26.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:26:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Km/+APAHOTa+3ERJ5Q07DMLbXDW6tlSNA1trH1+jvLU=; b=LsRIqkB3yY3wVH2rqU72vl8SPgpIB34DRbFinY4lKxi4/AHiyqgDBsNlyMKSZ8fFXF wGwdgNBQTj7sAHqvASqgMQVaPOdMBu7KAG6LHrFJ0mJ4uj8LW2WLRnoOOEJ8uGuGzL6q Iw8oKdQ4f0gVKYOzhZykuvJlfF6uQ0sN12esY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Km/+APAHOTa+3ERJ5Q07DMLbXDW6tlSNA1trH1+jvLU=; b=M/NqePcLA1mNwkziXoA6JpAsZK857rqQm12qdO5h+lkof3djwKJ+JRTZRdcwcwbvyg AUtKPaG7JSKNY7NXpB8kNhduuaH4M4+fbJBvnBxNp3J1x6pDfS//+hijG9j/z9htC+Ea 0QEzJ24XnMsEZd0cagArQHe0gslAPPDN1q+iyTcLfeUG2MooYPn/JESjPpiOlAJKE/2G aw0oJU2lGTfcAGi9/8Efi3ShnoVu74nZxGsm+0PJrFDJS3a3M056zrUFDUB+XL6R7hX8 dZz6+lzV74/2TzgnforiChpfE1QbgMNlGO9B+ymNBclgnDzFGvqiKCS4rgxeHGUrrPT7 rUdA== X-Gm-Message-State: ALKqPwc5Nzy4lKXkTR1Qenr6qWWueX3QAm9O6Voujbaxq+iclbUSQVeY 82ZlGSahO76EqPiEMvxszgYIvCray8A= X-Google-Smtp-Source: AB8JxZru/+0OeMEIedHgs+QYwAtIAT8dkbPgtFdG4a+CHJmQVFkKIb7LcgnHvhpCawO8y8RTVDGZVw== X-Received: by 2002:a62:5841:: with SMTP id m62-v6mr16803537pfb.116.1526423179092; Tue, 15 May 2018 15:26:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:37 -0700 Message-Id: <20180515222540.9988-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v6 25/28] fpu/softfloat: Pass FloatClass to pickNaNMulAdd X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For each operand, pass a single enumeration instead of a pair of booleans. The commit also merges multiple different ifdef-selected implementations of pickNaNMulAdd into a single function whose body is ifdef-selected. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- fpu/softfloat-specialize.h | 70 +++++++++++++++----------------------- fpu/softfloat.c | 5 +-- 2 files changed, 28 insertions(+), 47 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 2695183188..0399dfe011 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -594,15 +594,14 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | information. | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN *-------------------------------------------------------------------------= ---*/ -#if defined(TARGET_ARM) -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bI= sSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) +static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_= cls, + bool infzero, float_status *status) { +#if defined(TARGET_ARM) /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns * the default NaN */ - if (infzero && cIsQNaN) { + if (infzero && is_qnan(c_cls)) { float_raise(float_flag_invalid, status); return 3; } @@ -610,25 +609,20 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, = flag bIsQNaN, flag bIsSNaN, /* This looks different from the ARM ARM pseudocode, because the ARM A= RM * puts the operands to a fused mac operation (a*b)+c in the order c,a= ,b. */ - if (cIsSNaN) { + if (is_snan(c_cls)) { return 2; - } else if (aIsSNaN) { + } else if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (cIsQNaN) { + } else if (is_qnan(c_cls)) { return 2; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; } else { return 1; } -} #elif defined(TARGET_MIPS) -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bI= sSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) -{ /* For MIPS, the (inf,zero,qnan) case sets InvalidOp and returns * the default NaN */ @@ -639,41 +633,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, = flag bIsQNaN, flag bIsSNaN, =20 if (snan_bit_is_one(status)) { /* Prefer sNaN over qNaN, in the a, b, c order. */ - if (aIsSNaN) { + if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (cIsSNaN) { + } else if (is_snan(c_cls)) { return 2; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; - } else if (bIsQNaN) { + } else if (is_qnan(b_cls)) { return 1; } else { return 2; } } else { /* Prefer sNaN over qNaN, in the c, a, b order. */ - if (cIsSNaN) { + if (is_snan(c_cls)) { return 2; - } else if (aIsSNaN) { + } else if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (cIsQNaN) { + } else if (is_qnan(c_cls)) { return 2; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; } else { return 1; } } -} #elif defined(TARGET_PPC) -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bI= sSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) -{ /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer * to return an input NaN if we have one (ie c) rather than generating * a default NaN @@ -686,31 +675,26 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, = flag bIsQNaN, flag bIsSNaN, /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB */ - if (aIsSNaN || aIsQNaN) { + if (is_nan(a_cls)) { return 0; - } else if (cIsSNaN || cIsQNaN) { + } else if (is_nan(c_cls)) { return 2; } else { return 1; } -} #else -/* A default implementation: prefer a to b to c. - * This is unlikely to actually match any real implementation. - */ -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bI= sSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) -{ - if (aIsSNaN || aIsQNaN) { + /* A default implementation: prefer a to b to c. + * This is unlikely to actually match any real implementation. + */ + if (is_nan(a_cls)) { return 0; - } else if (bIsSNaN || bIsQNaN) { + } else if (is_nan(b_cls)) { return 1; } else { return 2; } -} #endif +} =20 /*------------------------------------------------------------------------= ---- | Takes two single-precision floating-point values `a' and `b', one of whi= ch diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 55954385ff..8e97602ace 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -601,10 +601,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatP= arts b, FloatParts c, s->float_exception_flags |=3D float_flag_invalid; } =20 - which =3D pickNaNMulAdd(is_qnan(a.cls), is_snan(a.cls), - is_qnan(b.cls), is_snan(b.cls), - is_qnan(c.cls), is_snan(c.cls), - inf_zero, s); + which =3D pickNaNMulAdd(a.cls, b.cls, c.cls, inf_zero, s); =20 if (s->default_nan_mode) { /* Note that this check is after pickNaNMulAdd so that function --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526423866032155.06513032647058; Tue, 15 May 2018 15:37:46 -0700 (PDT) Received: from localhost ([::1]:36368 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiZY-00033U-LR for importer@patchew.org; Tue, 15 May 2018 18:37:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39804) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOm-0003mF-SP for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOk-00007Q-BN for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:24 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:34162) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOj-0008RU-Vc for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:22 -0400 Received: by mail-pf0-x241.google.com with SMTP id a14-v6so744678pfi.1 for ; Tue, 15 May 2018 15:26:21 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.26.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:26:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Y25lAzfnv8gI3ibuqOopXm3qR8DDCg/tqJ8Ij3Eb+FY=; b=Tte1pk7QoUcBiFFBYxFrBrLsDZ79/cG9LJiXAlyj3RKRL+ieAMIjk0hHYp2PN9fqww ZKlFX9FFRHoh8Y5wU9SuHAMhE7HkAG4F1C778rqzHuSjqx5HVt+vUC/Gr3Y2WAlwbQje 4q3o8QJza3UUArkvDaH4k6xpipIuszaLlHmHg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Y25lAzfnv8gI3ibuqOopXm3qR8DDCg/tqJ8Ij3Eb+FY=; b=Y/keLwBXHTRWouYw4r/nL5DNa16fq05Yc/w14znFvWlaVb/8CcjgROiOGnITUY49eF d1A08KP3yPZz0CJlPa/OX1cXFS+TOCzwebe4xT0fzRqQfWq5tMc6l+cbGMn5fmOM92YG fSHlblb/mo9ZS13zSyrfVjCwnWkJNb8aF4CykswuHUY7YPQbBhYtJtTDQ1x0St/LnMbx ALlvvXiMwxde2eDAqNm62L8ioMVTHllvMbwrdL1dCDptc3hraJx68+YC/axmsDeWyXhN g0k6QdFDJKKhBShLBI9KRSlQVXqWWM6iVLM9iGetxFDisR/uqmDDFa6OIw0cbp8GuL49 I3+Q== X-Gm-Message-State: ALKqPwfFg27yr5/BtnM1vTL3wTlgW9qCh6uk1UxMUhEVyHJ1EtECyTln G6tOBGyQUknhLSBEwupNfUw2s4a6vJk= X-Google-Smtp-Source: AB8JxZon6hirt/R3TpNhSSj/y10X6Paksan+yyoVaFFiONBEahF9/juZNIiwgwqHb1dvzDBteWC/gQ== X-Received: by 2002:a63:aa07:: with SMTP id e7-v6mr9068003pgf.331.1526423180538; Tue, 15 May 2018 15:26:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:38 -0700 Message-Id: <20180515222540.9988-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v6 26/28] fpu/softfloat: Define floatN_default_nan in terms of parts_default_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Isolate the target-specific choice to 2 functions instead of 6. The code in float16_default_nan was only correct for ARM, MIPS, and X86. Though float16 support is rare among our targets. The code in float128_default_nan was arguably wrong for Sparc. While QEMU supports the Sparc 128-bit insns, no real cpu enables it. The code in floatx80_default_nan tried to be over-general. There are only two targets that support this format: x86 and m68k. Thus there is no point in inventing a value for snan_bit_is_one. Move routines that no longer have ifdefs out of softfloat-specialize.h. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- v6 - shift the nan fraction into place before raw packing --- fpu/softfloat-specialize.h | 105 +++---------------------------------- fpu/softfloat.c | 41 +++++++++++++++ 2 files changed, 47 insertions(+), 99 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 0399dfe011..9d562ed504 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -179,94 +179,22 @@ static FloatParts parts_silence_nan(FloatParts a, flo= at_status *status) return a; } =20 -/*------------------------------------------------------------------------= ---- -| The pattern for a default generated half-precision NaN. -*-------------------------------------------------------------------------= ---*/ -float16 float16_default_nan(float_status *status) -{ -#if defined(TARGET_ARM) - return const_float16(0x7E00); -#else - if (snan_bit_is_one(status)) { - return const_float16(0x7DFF); - } else { -#if defined(TARGET_MIPS) - return const_float16(0x7E00); -#else - return const_float16(0xFE00); -#endif - } -#endif -} - -/*------------------------------------------------------------------------= ---- -| The pattern for a default generated single-precision NaN. -*-------------------------------------------------------------------------= ---*/ -float32 float32_default_nan(float_status *status) -{ -#if defined(TARGET_SPARC) || defined(TARGET_M68K) - return const_float32(0x7FFFFFFF); -#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) = || \ - defined(TARGET_XTENSA) || defined(TARGET_S390X) || \ - defined(TARGET_TRICORE) || defined(TARGET_RISCV) - return const_float32(0x7FC00000); -#elif defined(TARGET_HPPA) - return const_float32(0x7FA00000); -#else - if (snan_bit_is_one(status)) { - return const_float32(0x7FBFFFFF); - } else { -#if defined(TARGET_MIPS) - return const_float32(0x7FC00000); -#else - return const_float32(0xFFC00000); -#endif - } -#endif -} - -/*------------------------------------------------------------------------= ---- -| The pattern for a default generated double-precision NaN. -*-------------------------------------------------------------------------= ---*/ -float64 float64_default_nan(float_status *status) -{ -#if defined(TARGET_SPARC) || defined(TARGET_M68K) - return const_float64(LIT64(0x7FFFFFFFFFFFFFFF)); -#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) = || \ - defined(TARGET_S390X) || defined(TARGET_RISCV) - return const_float64(LIT64(0x7FF8000000000000)); -#elif defined(TARGET_HPPA) - return const_float64(LIT64(0x7FF4000000000000)); -#else - if (snan_bit_is_one(status)) { - return const_float64(LIT64(0x7FF7FFFFFFFFFFFF)); - } else { -#if defined(TARGET_MIPS) - return const_float64(LIT64(0x7FF8000000000000)); -#else - return const_float64(LIT64(0xFFF8000000000000)); -#endif - } -#endif -} - /*------------------------------------------------------------------------= ---- | The pattern for a default generated extended double-precision NaN. *-------------------------------------------------------------------------= ---*/ floatx80 floatx80_default_nan(float_status *status) { floatx80 r; + + /* None of the targets that have snan_bit_is_one use floatx80. */ + assert(!snan_bit_is_one(status)); #if defined(TARGET_M68K) r.low =3D LIT64(0xFFFFFFFFFFFFFFFF); r.high =3D 0x7FFF; #else - if (snan_bit_is_one(status)) { - r.low =3D LIT64(0xBFFFFFFFFFFFFFFF); - r.high =3D 0x7FFF; - } else { - r.low =3D LIT64(0xC000000000000000); - r.high =3D 0xFFFF; - } + /* X86 */ + r.low =3D LIT64(0xC000000000000000); + r.high =3D 0xFFFF; #endif return r; } @@ -285,27 +213,6 @@ floatx80 floatx80_default_nan(float_status *status) const floatx80 floatx80_infinity =3D make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); =20 -/*------------------------------------------------------------------------= ---- -| The pattern for a default generated quadruple-precision NaN. -*-------------------------------------------------------------------------= ---*/ -float128 float128_default_nan(float_status *status) -{ - float128 r; - - if (snan_bit_is_one(status)) { - r.low =3D LIT64(0xFFFFFFFFFFFFFFFF); - r.high =3D LIT64(0x7FFF7FFFFFFFFFFF); - } else { - r.low =3D LIT64(0x0000000000000000); -#if defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_RISCV) - r.high =3D LIT64(0x7FFF800000000000); -#else - r.high =3D LIT64(0xFFFF800000000000); -#endif - } - return r; -} - /*------------------------------------------------------------------------= ---- | Raises the exceptions specified by `flags'. Floating-point traps can be | defined here if desired. It is currently not possible for such a trap diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 8e97602ace..c8b33e35f4 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2092,6 +2092,47 @@ float64 __attribute__((flatten)) float64_sqrt(float6= 4 a, float_status *status) return float64_round_pack_canonical(pr, status); } =20 +/*------------------------------------------------------------------------= ---- +| The pattern for a default generated NaN. +*-------------------------------------------------------------------------= ---*/ + +float16 float16_default_nan(float_status *status) +{ + FloatParts p =3D parts_default_nan(status); + p.frac >>=3D float16_params.frac_shift; + return float16_pack_raw(p); +} + +float32 float32_default_nan(float_status *status) +{ + FloatParts p =3D parts_default_nan(status); + p.frac >>=3D float32_params.frac_shift; + return float32_pack_raw(p); +} + +float64 float64_default_nan(float_status *status) +{ + FloatParts p =3D parts_default_nan(status); + p.frac >>=3D float64_params.frac_shift; + return float64_pack_raw(p); +} + +float128 float128_default_nan(float_status *status) +{ + FloatParts p =3D parts_default_nan(status); + float128 r; + + /* Extrapolate from the choices made by parts_default_nan to fill + * in the quad-floating format. If the low bit is set, assume we + * want to set all non-snan bits. + */ + r.low =3D -(p.frac & 1); + r.high =3D p.frac >> (DECOMPOSED_BINARY_POINT - 48); + r.high |=3D LIT64(0x7FFF000000000000); + r.high |=3D (uint64_t)p.sign << 63; + + return r; +} =20 /*------------------------------------------------------------------------= ---- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526424038335613.7964665714042; Tue, 15 May 2018 15:40:38 -0700 (PDT) Received: from localhost ([::1]:36382 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIicX-0005Uz-EI for importer@patchew.org; Tue, 15 May 2018 18:40:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39823) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOn-0003n4-JP for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOl-0000H5-K3 for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:25 -0400 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:37956) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOl-0000BB-B8 for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:23 -0400 Received: by mail-pl0-x244.google.com with SMTP id c11-v6so869410plr.5 for ; Tue, 15 May 2018 15:26:23 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.26.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:26:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MmSgSLwT1JZjRsPCpF/ZgIgh9cLg8HFIxpF7qjon1YU=; b=KzdFckTK521/0yY+p61wzTsH8069QqwmpChagtbtfVhgUQzCeIaU03KAY0A0w7zi3m QAvl2OdkZuMogPzmBrFH6/+eHJbwKuoY7c6oKMjZd4BMj3zwtidu57GlEZAK9+IVsuAw +5fDim49lTzBuvophXTjJmUsf+JparrWRyVuM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MmSgSLwT1JZjRsPCpF/ZgIgh9cLg8HFIxpF7qjon1YU=; b=bL4AQ5y8ZIaFmWcpBYaqR5yNpocl87QTakPMLqHN+tqyQooxQBHOquLdwFXzzFDy0c byGMSnH/o0pkmIVY8mtuTi7YEnQo9ymkwrb0thhfJM+brzluqfeE2PMDZ6zirP9UucmF LYbj/q0svXKCFOWRgkJVn6IcH3PVglbipe+2WjPXB7WUci9GRDuNa3Jj4XTOZ2y+Gw7N f0jbthF4zm3CKlEEIGHKXy0Hj7pnyK2pKqFK51Nwn/LEYq0VniGVP1N5EDZxauUUnQ1v mEGXH1NdJPsogGrqerVtQxV/Ns31XFKSVPQqusV0irbMkY13hoFqHGANfYuZQ0KyE6G8 YO1Q== X-Gm-Message-State: ALKqPweAaqjhafhe6iroQF5hVkL9YUHvQdqhNPKRA+AfrIuf35EhwAqA FdXiwDEdm3qQ1x1AY6W6QCDWo+zwnIc= X-Google-Smtp-Source: AB8JxZomL6SWS4o75dZefOkf4VPgezKe9iqTRh6MZ9ynoJMJXxO3dkYw73UeqQKBAafAu683ByXL1A== X-Received: by 2002:a17:902:4b:: with SMTP id 69-v6mr16672828pla.178.1526423182023; Tue, 15 May 2018 15:26:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:39 -0700 Message-Id: <20180515222540.9988-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v6 27/28] fpu/softfloat: Clean up parts_default_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reduce the number of ifdefs. Correct the result for OpenRISC and TriCore (although TriCore fixed in target-specific code). Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- fpu/softfloat-specialize.h | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 9d562ed504..ec4fb6ba8b 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -129,22 +129,29 @@ static FloatParts parts_default_nan(float_status *sta= tus) uint64_t frac; =20 #if defined(TARGET_SPARC) || defined(TARGET_M68K) + /* !snan_bit_is_one, set all bits */ frac =3D (1ULL << DECOMPOSED_BINARY_POINT) - 1; -#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) = || \ - defined(TARGET_S390X) || defined(TARGET_RISCV) +#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ + || defined(TARGET_MICROBLAZE) + /* !snan_bit_is_one, set sign and msb */ frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); + sign =3D 1; #elif defined(TARGET_HPPA) + /* snan_bit_is_one, set msb-1. */ frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); #else + /* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, + * S390, SH4, TriCore, and Xtensa. I cannot find documentation + * for Unicore32; the choice from the original commit is unchanged. + * Our other supported targets, CRIS, LM32, Moxie, Nios2, and Tile, + * do not have floating-point. + */ if (snan_bit_is_one(status)) { + /* set all bits other than msb */ frac =3D (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; } else { -#if defined(TARGET_MIPS) + /* set msb */ frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); -#else - frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); - sign =3D 1; -#endif } #endif =20 --=20 2.17.0 From nobody Wed Apr 24 16:36:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526424221015766.4203613635256; Tue, 15 May 2018 15:43:41 -0700 (PDT) Received: from localhost ([::1]:36402 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIifL-0007yV-08 for importer@patchew.org; Tue, 15 May 2018 18:43:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39853) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIiOp-0003od-DZ for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIiOn-0000SV-4E for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:27 -0400 Received: from mail-pl0-x243.google.com ([2607:f8b0:400e:c01::243]:34604) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIiOm-0000M1-Mp for qemu-devel@nongnu.org; Tue, 15 May 2018 18:26:24 -0400 Received: by mail-pl0-x243.google.com with SMTP id ay10-v6so874617plb.1 for ; Tue, 15 May 2018 15:26:24 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id g11-v6sm941419pgq.62.2018.05.15.15.26.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 15:26:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vX12ZtlpQa6Nv7/rq1wfPxTqdC3HQkrlkn2HkZRVyV4=; b=IYK+B3BY4uF2ehyfhzGCfgJtgOysuc5Vfvtm/7lmqhAgx2TnGa+sqYebvU7OXILqGW 0v52Qrq8OpUMDJ3q2zhnHbAiBghgTyePh/WXs7W4KJxSSDXaoxxFmzxvjwgXjq76gaf4 5xTehqn5UbreL6+EIYFEoZYXNN/pzMsNMLX6Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vX12ZtlpQa6Nv7/rq1wfPxTqdC3HQkrlkn2HkZRVyV4=; b=QTDMohCZ43ZUBG+NHtUPjxrti3bvMP6qLVBxwhZwIZwgi6QgMHEi0DSobXnejzN87r o42yPEFf0mKVaT9MPqeW6z4ACPABhVVPbO/N8y6sNiG5fiMtGw5sZiC7nKQaJv3tOjds G4D4xbplo05GadlMDmVriDnC8TgRoNzQ8qgbTnTwLxGwFSksY4Y+21rqrH8kfTLqUV1C qHZR2oGIWHsERpf/92G1MqHcOXCz9rOB+2UcSMbZ+PvI1xFzfLQHgEzjP1Iu/0CpG4vd EfN/sI5o/kq8uGseQ5alcNTUQUx2DmafzI4je8dbeHc5s/J+EUc52aZwypuYCyTsDGsZ zE+A== X-Gm-Message-State: ALKqPwf8enf6i0SmLLs8XaXfFwoIyFcv9/kOVwpiPYh10Yi2DTdFeL/s xbkDI87GH9lsIdjKYGoFtgLd7g0XBZ4= X-Google-Smtp-Source: AB8JxZrHDd2UcV8MzE69Dwfy3D6Yg6pMANbrn0ucUNabMmC0fHuQqU6qjfq7ow1gOI3xN1Yvs+cGeg== X-Received: by 2002:a17:902:c6b:: with SMTP id 98-v6mr6136415pls.270.1526423183331; Tue, 15 May 2018 15:26:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 15:25:40 -0700 Message-Id: <20180515222540.9988-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515222540.9988-1-richard.henderson@linaro.org> References: <20180515222540.9988-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v6 28/28] fpu/softfloat: Define floatN_silence_nan in terms of parts_silence_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Isolate the target-specific choice to 3 functions instead of 6. The code in floatx80_default_nan tried to be over-general. There are only two targets that support this format: x86 and m68k. Thus there is no point in inventing a mechanism for snan_bit_is_one. Move routines that no longer have ifdefs out of softfloat-specialize.h. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- fpu/softfloat-specialize.h | 81 ++------------------------------------ fpu/softfloat.c | 31 +++++++++++++++ 2 files changed, 35 insertions(+), 77 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index ec4fb6ba8b..16c0bcb6fa 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -278,24 +278,6 @@ int float16_is_signaling_nan(float16 a_, float_status = *status) #endif } =20 -/*------------------------------------------------------------------------= ---- -| Returns a quiet NaN from a signalling NaN for the half-precision -| floating point value `a'. -*-------------------------------------------------------------------------= ---*/ - -float16 float16_silence_nan(float16 a, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - g_assert_not_reached(); -#else - if (snan_bit_is_one(status)) { - return float16_default_nan(status); - } else { - return a | (1 << 9); - } -#endif -} - /*------------------------------------------------------------------------= ---- | Returns 1 if the single-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -334,30 +316,6 @@ int float32_is_signaling_nan(float32 a_, float_status = *status) #endif } =20 -/*------------------------------------------------------------------------= ---- -| Returns a quiet NaN from a signalling NaN for the single-precision -| floating point value `a'. -*-------------------------------------------------------------------------= ---*/ - -float32 float32_silence_nan(float32 a, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - g_assert_not_reached(); -#else - if (snan_bit_is_one(status)) { -# ifdef TARGET_HPPA - a &=3D ~0x00400000; - a |=3D 0x00200000; - return a; -# else - return float32_default_nan(status); -# endif - } else { - return a | (1 << 22); - } -#endif -} - /*------------------------------------------------------------------------= ---- | Returns the result of converting the single-precision floating-point NaN | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid @@ -706,31 +664,6 @@ int float64_is_signaling_nan(float64 a_, float_status = *status) #endif } =20 -/*------------------------------------------------------------------------= ---- -| Returns a quiet NaN from a signalling NaN for the double-precision -| floating point value `a'. -*-------------------------------------------------------------------------= ---*/ - -float64 float64_silence_nan(float64 a, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - g_assert_not_reached(); -#else - if (snan_bit_is_one(status)) { -# ifdef TARGET_HPPA - a &=3D ~0x0008000000000000ULL; - a |=3D 0x0004000000000000ULL; - return a; -# else - return float64_default_nan(status); -# endif - } else { - return a | LIT64(0x0008000000000000); - } -#endif -} - - /*------------------------------------------------------------------------= ---- | Returns the result of converting the double-precision floating-point NaN | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid @@ -886,16 +819,10 @@ int floatx80_is_signaling_nan(floatx80 a, float_statu= s *status) =20 floatx80 floatx80_silence_nan(floatx80 a, float_status *status) { -#ifdef NO_SIGNALING_NANS - g_assert_not_reached(); -#else - if (snan_bit_is_one(status)) { - return floatx80_default_nan(status); - } else { - a.low |=3D LIT64(0xC000000000000000); - return a; - } -#endif + /* None of the targets that have snan_bit_is_one use floatx80. */ + assert(!snan_bit_is_one(status)); + a.low |=3D LIT64(0xC000000000000000); + return a; } =20 /*------------------------------------------------------------------------= ---- diff --git a/fpu/softfloat.c b/fpu/softfloat.c index c8b33e35f4..8cd2400081 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2134,6 +2134,37 @@ float128 float128_default_nan(float_status *status) return r; } =20 +/*------------------------------------------------------------------------= ---- +| Returns a quiet NaN from a signalling NaN for the floating point value `= a'. +*-------------------------------------------------------------------------= ---*/ + +float16 float16_silence_nan(float16 a, float_status *status) +{ + FloatParts p =3D float16_unpack_raw(a); + p.frac <<=3D float16_params.frac_shift; + p =3D parts_silence_nan(p, status); + p.frac >>=3D float16_params.frac_shift; + return float16_pack_raw(p); +} + +float32 float32_silence_nan(float32 a, float_status *status) +{ + FloatParts p =3D float32_unpack_raw(a); + p.frac <<=3D float32_params.frac_shift; + p =3D parts_silence_nan(p, status); + p.frac >>=3D float32_params.frac_shift; + return float32_pack_raw(p); +} + +float64 float64_silence_nan(float64 a, float_status *status) +{ + FloatParts p =3D float64_unpack_raw(a); + p.frac <<=3D float64_params.frac_shift; + p =3D parts_silence_nan(p, status); + p.frac >>=3D float64_params.frac_shift; + return float64_pack_raw(p); +} + /*------------------------------------------------------------------------= ---- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 | and 7, and returns the properly rounded 32-bit integer corresponding to = the --=20 2.17.0