From nobody Sat Apr 20 15:00:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526386654403752.1126231023824; Tue, 15 May 2018 05:17:34 -0700 (PDT) Received: from localhost ([::1]:34922 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIYtZ-0000mO-Gh for importer@patchew.org; Tue, 15 May 2018 08:17:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40656) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIYrO-00081P-Nm for qemu-devel@nongnu.org; Tue, 15 May 2018 08:15:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIYrJ-0000lA-MD for qemu-devel@nongnu.org; Tue, 15 May 2018 08:15:18 -0400 Received: from mx1.redhat.com ([209.132.183.28]:43379) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fIYrJ-0000jt-3t for qemu-devel@nongnu.org; Tue, 15 May 2018 08:15:13 -0400 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 31195148FFD; Tue, 15 May 2018 12:15:12 +0000 (UTC) Received: from localhost (ovpn-116-28.phx2.redhat.com [10.3.116.28]) by smtp.corp.redhat.com (Postfix) with ESMTP id AAECA2A192; Tue, 15 May 2018 12:14:41 +0000 (UTC) From: =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 14:14:30 +0200 Message-Id: <20180515121433.6112-2-marcandre.lureau@redhat.com> In-Reply-To: <20180515121433.6112-1-marcandre.lureau@redhat.com> References: <20180515121433.6112-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Tue, 15 May 2018 12:15:12 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v3 1/4] tpm: implement virtual memory device for TPM PPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , "Michael S. Tsirkin" , stefanb@linux.vnet.ibm.com, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Igor Mammedov , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Stefan Berger Implement a virtual memory device for the TPM Physical Presence interface. The memory is located at 0xfffef000 and used by ACPI to send messages to the firmware (BIOS) and by the firmware to provide parameters for each one of the supported codes. This device should be used by all TPM interfaces on x86 and can be added by calling tpm_ppi_init_io(). Signed-off-by: Stefan Berger Signed-off-by: Marc-Andr=C3=A9 Lureau --- v3 (Marc-Andr=C3=A9): - merge CRB support - use trace events instead of DEBUG printf - headers inclusion simplification v2: - moved to byte access since an infrequently used device; this simplifies code - increase size of device to 0x400 - move device to 0xfffef000 since SeaBIOS has some code at 0xffff0000: 'On the emulators, the bios at 0xf0000 is also at 0xffff0000' --- hw/tpm/tpm_ppi.h | 26 ++++++++++++++++++++ include/hw/acpi/tpm.h | 6 +++++ hw/tpm/tpm_crb.c | 5 ++++ hw/tpm/tpm_ppi.c | 56 +++++++++++++++++++++++++++++++++++++++++++ hw/tpm/tpm_tis.c | 5 ++++ hw/tpm/Makefile.objs | 2 +- hw/tpm/trace-events | 4 ++++ 7 files changed, 103 insertions(+), 1 deletion(-) create mode 100644 hw/tpm/tpm_ppi.h create mode 100644 hw/tpm/tpm_ppi.c diff --git a/hw/tpm/tpm_ppi.h b/hw/tpm/tpm_ppi.h new file mode 100644 index 0000000000..17030bd989 --- /dev/null +++ b/hw/tpm/tpm_ppi.h @@ -0,0 +1,26 @@ +/* + * TPM Physical Presence Interface + * + * Copyright (C) 2018 IBM Corporation + * + * Authors: + * Stefan Berger + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ +#ifndef TPM_TPM_PPI_H +#define TPM_TPM_PPI_H + +#include "hw/acpi/tpm.h" +#include "exec/address-spaces.h" + +typedef struct TPMPPI { + MemoryRegion mmio; + + uint8_t ram[TPM_PPI_ADDR_SIZE]; +} TPMPPI; + +void tpm_ppi_init_io(TPMPPI *tpmppi, struct MemoryRegion *m, Object *obj); + +#endif /* TPM_TPM_PPI_H */ diff --git a/include/hw/acpi/tpm.h b/include/hw/acpi/tpm.h index 46ac4dc581..c082df7d1d 100644 --- a/include/hw/acpi/tpm.h +++ b/include/hw/acpi/tpm.h @@ -187,4 +187,10 @@ REG32(CRB_DATA_BUFFER, 0x80) #define TPM2_START_METHOD_MMIO 6 #define TPM2_START_METHOD_CRB 7 =20 +/* + * Physical Presence Interface + */ +#define TPM_PPI_ADDR_SIZE 0x400 +#define TPM_PPI_ADDR_BASE 0xFED45000 + #endif /* HW_ACPI_TPM_H */ diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c index a92dd50437..4f585564d9 100644 --- a/hw/tpm/tpm_crb.c +++ b/hw/tpm/tpm_crb.c @@ -29,6 +29,7 @@ #include "sysemu/reset.h" #include "tpm_int.h" #include "tpm_util.h" +#include "tpm_ppi.h" #include "trace.h" =20 typedef struct CRBState { @@ -41,6 +42,8 @@ typedef struct CRBState { MemoryRegion cmdmem; =20 size_t be_buffer_size; + + TPMPPI ppi; } CRBState; =20 #define CRB(obj) OBJECT_CHECK(CRBState, (obj), TYPE_TPM_CRB) @@ -291,6 +294,8 @@ static void tpm_crb_realize(DeviceState *dev, Error **e= rrp) memory_region_add_subregion(get_system_memory(), TPM_CRB_ADDR_BASE + sizeof(s->regs), &s->cmdmem); =20 + tpm_ppi_init_io(&s->ppi, get_system_memory(), OBJECT(s)); + qemu_register_reset(tpm_crb_reset, dev); } =20 diff --git a/hw/tpm/tpm_ppi.c b/hw/tpm/tpm_ppi.c new file mode 100644 index 0000000000..0019c3e6fc --- /dev/null +++ b/hw/tpm/tpm_ppi.c @@ -0,0 +1,56 @@ +/* + * tpm_ppi.c - TPM Physical Presence Interface + * + * Copyright (C) 2018 IBM Corporation + * + * Authors: + * Stefan Berger + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" + +#include "tpm_ppi.h" +#include "trace.h" + +static uint64_t tpm_ppi_mmio_read(void *opaque, hwaddr addr, + unsigned size) +{ + TPMPPI *s =3D opaque; + + trace_tpm_ppi_mmio_read(addr, size, s->ram[addr]); + + return s->ram[addr]; +} + +static void tpm_ppi_mmio_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + TPMPPI *s =3D opaque; + + trace_tpm_ppi_mmio_write(addr, size, val); + + s->ram[addr] =3D val; +} + +static const MemoryRegionOps tpm_ppi_memory_ops =3D { + .read =3D tpm_ppi_mmio_read, + .write =3D tpm_ppi_mmio_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +void tpm_ppi_init_io(TPMPPI *tpmppi, struct MemoryRegion *m, Object *obj) +{ + memory_region_init_io(&tpmppi->mmio, obj, &tpm_ppi_memory_ops, + tpmppi, "tpm-ppi-mmio", + TPM_PPI_ADDR_SIZE); + + memory_region_add_subregion(m, TPM_PPI_ADDR_BASE, &tpmppi->mmio); +} diff --git a/hw/tpm/tpm_tis.c b/hw/tpm/tpm_tis.c index 12f5c9a759..9a2fec455a 100644 --- a/hw/tpm/tpm_tis.c +++ b/hw/tpm/tpm_tis.c @@ -31,6 +31,7 @@ #include "sysemu/tpm_backend.h" #include "tpm_int.h" #include "tpm_util.h" +#include "tpm_ppi.h" #include "trace.h" =20 #define TPM_TIS_NUM_LOCALITIES 5 /* per spec */ @@ -81,6 +82,8 @@ typedef struct TPMState { TPMVersion be_tpm_version; =20 size_t be_buffer_size; + + TPMPPI ppi; } TPMState; =20 #define TPM(obj) OBJECT_CHECK(TPMState, (obj), TYPE_TPM_TIS) @@ -976,6 +979,8 @@ static void tpm_tis_realizefn(DeviceState *dev, Error *= *errp) =20 memory_region_add_subregion(isa_address_space(ISA_DEVICE(dev)), TPM_TIS_ADDR_BASE, &s->mmio); + + tpm_ppi_init_io(&s->ppi, isa_address_space(ISA_DEVICE(dev)), OBJECT(s)= ); } =20 static void tpm_tis_initfn(Object *obj) diff --git a/hw/tpm/Makefile.objs b/hw/tpm/Makefile.objs index 1dc9f8bf2c..eedd8b6858 100644 --- a/hw/tpm/Makefile.objs +++ b/hw/tpm/Makefile.objs @@ -1,4 +1,4 @@ -common-obj-y +=3D tpm_util.o +common-obj-y +=3D tpm_util.o tpm_ppi.o common-obj-$(CONFIG_TPM_TIS) +=3D tpm_tis.o common-obj-$(CONFIG_TPM_CRB) +=3D tpm_crb.o common-obj-$(CONFIG_TPM_PASSTHROUGH) +=3D tpm_passthrough.o diff --git a/hw/tpm/trace-events b/hw/tpm/trace-events index 25bee0cecf..81f9923401 100644 --- a/hw/tpm/trace-events +++ b/hw/tpm/trace-events @@ -8,6 +8,10 @@ tpm_crb_mmio_write(uint64_t addr, unsigned size, uint32_t = val) "CRB write 0x" TA tpm_passthrough_handle_request(void *cmd) "processing command %p" tpm_passthrough_reset(void) "reset" =20 +# hw/tpm/tpm_ppi.c +tpm_ppi_mmio_read(uint64_t addr, unsigned size, uint32_t val) "PPI read 0x= " TARGET_FMT_plx " len:%u val: 0x%" PRIx32 +tpm_ppi_mmio_write(uint64_t addr, unsigned size, uint32_t val) "PPI write = 0x" TARGET_FMT_plx " len:%u val: 0x%" PRIx32 + # hw/tpm/tpm_util.c tpm_util_get_buffer_size_hdr_len(uint32_t len, size_t expected) "tpm_resp-= >hdr.len =3D %u, expected =3D %zu" tpm_util_get_buffer_size_len(uint32_t len, size_t expected) "tpm_resp->len= =3D %u, expected =3D %zu" --=20 2.17.0.253.g3dd125b46d From nobody Sat Apr 20 15:00:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526386797401623.5248832761689; Tue, 15 May 2018 05:19:57 -0700 (PDT) Received: from localhost ([::1]:35005 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIYvk-0002bq-D1 for importer@patchew.org; Tue, 15 May 2018 08:19:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40715) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIYrk-0008GY-PJ for qemu-devel@nongnu.org; Tue, 15 May 2018 08:15:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIYrg-00013s-Kp for qemu-devel@nongnu.org; Tue, 15 May 2018 08:15:40 -0400 Received: from mx1.redhat.com ([209.132.183.28]:40608) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fIYrg-000135-Bt for qemu-devel@nongnu.org; Tue, 15 May 2018 08:15:36 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3A86633263B3; Tue, 15 May 2018 12:15:35 +0000 (UTC) Received: from localhost (ovpn-116-28.phx2.redhat.com [10.3.116.28]) by smtp.corp.redhat.com (Postfix) with ESMTP id 85E3163122; Tue, 15 May 2018 12:15:13 +0000 (UTC) From: =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 14:14:31 +0200 Message-Id: <20180515121433.6112-3-marcandre.lureau@redhat.com> In-Reply-To: <20180515121433.6112-1-marcandre.lureau@redhat.com> References: <20180515121433.6112-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.41]); Tue, 15 May 2018 12:15:35 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v3 2/4] acpi: add fw_cfg file for TPM and PPI virtual memory device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , "Michael S. Tsirkin" , stefanb@linux.vnet.ibm.com, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Igor Mammedov , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Stefan Berger To avoid having to hard code the base address of the PPI virtual memory device we introduce a fw_cfg file etc/tpm/config that holds the base address of the PPI device, the version of the PPI interface and the version of the attached TPM. Signed-off-by: Stefan Berger [ Marc-Andr=C3=A9: renamed to etc/tpm/config, made it static, document it ] Signed-off-by: Marc-Andr=C3=A9 Lureau --- include/hw/acpi/tpm.h | 3 +++ hw/i386/acpi-build.c | 17 +++++++++++++++++ docs/specs/tpm.txt | 20 ++++++++++++++++++++ 3 files changed, 40 insertions(+) diff --git a/include/hw/acpi/tpm.h b/include/hw/acpi/tpm.h index c082df7d1d..f79d68a77a 100644 --- a/include/hw/acpi/tpm.h +++ b/include/hw/acpi/tpm.h @@ -193,4 +193,7 @@ REG32(CRB_DATA_BUFFER, 0x80) #define TPM_PPI_ADDR_SIZE 0x400 #define TPM_PPI_ADDR_BASE 0xFED45000 =20 +#define TPM_PPI_VERSION_NONE 0 +#define TPM_PPI_VERSION_1_30 1 + #endif /* HW_ACPI_TPM_H */ diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 9bc6d97ea1..f6d447f03a 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -119,6 +119,12 @@ typedef struct AcpiBuildPciBusHotplugState { bool pcihp_bridge_en; } AcpiBuildPciBusHotplugState; =20 +typedef struct FWCfgTPMConfig { + uint32_t tpmppi_address; + uint8_t tpm_version; + uint8_t tpmppi_version; +} QEMU_PACKED FWCfgTPMConfig; + static void init_common_fadt_data(Object *o, AcpiFadtData *data) { uint32_t io =3D object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, N= ULL); @@ -2873,6 +2879,7 @@ void acpi_setup(void) AcpiBuildTables tables; AcpiBuildState *build_state; Object *vmgenid_dev; + static FWCfgTPMConfig tpm_config; =20 if (!pcms->fw_cfg) { ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); @@ -2907,6 +2914,16 @@ void acpi_setup(void) fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, acpi_data_len(tables.tcpalog)); =20 + if (tpm_find()) { + tpm_config =3D (FWCfgTPMConfig) { + .tpmppi_address =3D cpu_to_le32(TPM_PPI_ADDR_BASE), + .tpm_version =3D cpu_to_le32(tpm_get_version(tpm_find())), + .tpmppi_version =3D cpu_to_le32(TPM_PPI_VERSION_NONE) + }; + fw_cfg_add_file(pcms->fw_cfg, "etc/tpm/config", + &tpm_config, sizeof tpm_config); + } + vmgenid_dev =3D find_vmgenid_dev(); if (vmgenid_dev) { vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), pcms->fw_cfg, diff --git a/docs/specs/tpm.txt b/docs/specs/tpm.txt index c230c4c93e..2ddb768084 100644 --- a/docs/specs/tpm.txt +++ b/docs/specs/tpm.txt @@ -20,6 +20,26 @@ QEMU files related to TPM TIS interface: - hw/tpm/tpm_tis.h =20 =20 +=3D fw_cfg interface =3D + +The bios/firmware may use the "etc/tpm/config" fw_cfg entry for +configuring the guest appropriately. + +The entry of 6 bytes has the following content, in little-endian: + + #define TPM_VERSION_UNSPEC 0 + #define TPM_VERSION_1_2 1 + #define TPM_VERSION_2_0 2 + + #define TPM_PPI_VERSION_NONE 0 + #define TPM_PPI_VERSION_1_30 1 + + struct FWCfgTPMConfig { + uint32_t tpmppi_address; /* PPI memory location */ + uint8_t tpm_version; /* TPM version */ + uint8_t tpmppi_version; /* PPI version */ + }; + =3D ACPI Interface =3D =20 The TPM device is defined with ACPI ID "PNP0C31". QEMU builds a SSDT and p= asses --=20 2.17.0.253.g3dd125b46d From nobody Sat Apr 20 15:00:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152638666238315.069348242952628; Tue, 15 May 2018 05:17:42 -0700 (PDT) Received: from localhost ([::1]:34939 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIYth-0000tw-Gq for importer@patchew.org; Tue, 15 May 2018 08:17:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40745) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIYro-0008Iw-V3 for qemu-devel@nongnu.org; Tue, 15 May 2018 08:15:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIYri-00015V-61 for qemu-devel@nongnu.org; Tue, 15 May 2018 08:15:44 -0400 Received: from mx1.redhat.com ([209.132.183.28]:52338) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fIYrh-00014P-T0 for qemu-devel@nongnu.org; Tue, 15 May 2018 08:15:38 -0400 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.25]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 1BADE30B27C5; Tue, 15 May 2018 12:15:37 +0000 (UTC) Received: from localhost (ovpn-116-28.phx2.redhat.com [10.3.116.28]) by smtp.corp.redhat.com (Postfix) with ESMTP id 76BF82016BE0; Tue, 15 May 2018 12:15:36 +0000 (UTC) From: =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 14:14:32 +0200 Message-Id: <20180515121433.6112-4-marcandre.lureau@redhat.com> In-Reply-To: <20180515121433.6112-1-marcandre.lureau@redhat.com> References: <20180515121433.6112-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.25 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.48]); Tue, 15 May 2018 12:15:37 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v3 3/4] acpi: build TPM Physical Presence interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , "Michael S. Tsirkin" , stefanb@linux.vnet.ibm.com, Igor Mammedov , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Stefan Berger The TPM Physical Presence interface consists of an ACPI part, a shared memory part, and code in the firmware. Users can send messages to the firmware by writing a code into the shared memory through invoking the ACPI code. When a reboot happens, the firmware looks for the code and acts on it by sending sequences of commands to the TPM. This patch adds the ACPI code. It is similar to the one in EDK2 but doesn't assume that SMIs are necessary to use. It uses a similar datastructure for the shared memory as EDK2 does so that EDK2 and SeaBIOS could both make use of it. I extended the shared memory data structure with an array of 256 bytes, one for each code that could be implemented. The array contains flags describing the individual codes. This decouples the ACPI implementati= on from the firmware implementation. The underlying TCG specification is accessible from the following page. https://trustedcomputinggroup.org/tcg-physical-presence-interface-specifica= tion/ This patch implements version 1.30. Signed-off-by: Stefan Berger --- v4 (Marc-Andr=C3=A9): - replace 'DerefOf (FUNC [N])' with a function, to fix Windows ACPI handling. - replace 'return Package (..) {} ' with scoped variables, to fix Windows ACPI handling. v3: - add support for PPI to CRB - split up OperationRegion TPPI into two parts, one containing the registers (TPP1) and the other one the flags (TPP2); switched the order of the flags versus registers in the code - adapted ACPI code to small changes to the array of flags where previous flag 0 was removed and now shifting right wasn't always necessary anymore v2: - get rid of FAIL variable; function 5 was using it and always returns 0; the value is related to the ACPI function call not a possible failure of the TPM function call. - extend shared memory data structure with per-opcode entries holding flags and use those flags to determine what to return to caller - implement interface version 1.3 --- include/hw/acpi/tpm.h | 21 +++ hw/i386/acpi-build.c | 294 +++++++++++++++++++++++++++++++++++++++++- 2 files changed, 314 insertions(+), 1 deletion(-) diff --git a/include/hw/acpi/tpm.h b/include/hw/acpi/tpm.h index f79d68a77a..fc53f08827 100644 --- a/include/hw/acpi/tpm.h +++ b/include/hw/acpi/tpm.h @@ -196,4 +196,25 @@ REG32(CRB_DATA_BUFFER, 0x80) #define TPM_PPI_VERSION_NONE 0 #define TPM_PPI_VERSION_1_30 1 =20 +struct tpm_ppi { + uint8_t func[256]; /* 0x000: per TPM function implementation fla= gs; + set by BIOS */ +/* whether function is blocked by BIOS settings; bits 0, 1, 2 */ +#define TPM_PPI_FUNC_NOT_IMPLEMENTED (0 << 0) +#define TPM_PPI_FUNC_BIOS_ONLY (1 << 0) +#define TPM_PPI_FUNC_BLOCKED (2 << 0) +#define TPM_PPI_FUNC_ALLOWED_USR_REQ (3 << 0) +#define TPM_PPI_FUNC_ALLOWED_USR_NOT_REQ (4 << 0) +#define TPM_PPI_FUNC_MASK (7 << 0) + uint8_t ppin; /* 0x100 : set by BIOS */ + uint32_t ppip; /* 0x101 : set by ACPI; not used */ + uint32_t pprp; /* 0x105 : response from TPM; set by BIOS */ + uint32_t pprq; /* 0x109 : opcode; set by ACPI */ + uint32_t pprm; /* 0x10d : parameter for opcode; set by ACPI = */ + uint32_t lppr; /* 0x111 : last opcode; set by BIOS */ + uint32_t fret; /* 0x115 : set by ACPI; not used */ + uint8_t res1[0x40]; /* 0x119 : reserved for future use */ + uint8_t next_step; /* 0x159 : next step after reboot; set by BIO= S */ +} QEMU_PACKED; + #endif /* HW_ACPI_TPM_H */ diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index f6d447f03a..95be4f0710 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -43,6 +43,7 @@ #include "hw/acpi/memory_hotplug.h" #include "sysemu/tpm.h" #include "hw/acpi/tpm.h" +#include "hw/tpm/tpm_ppi.h" #include "hw/acpi/vmgenid.h" #include "sysemu/tpm_backend.h" #include "hw/timer/mc146818rtc_regs.h" @@ -1789,6 +1790,292 @@ static Aml *build_q35_osc_method(void) return method; } =20 +static void +build_tpm_ppi(Aml *dev) +{ + Aml *method, *name, *field, *ifctx, *ifctx2, *ifctx3, *pak; + struct tpm_ppi *tpm_ppi =3D NULL; + int i; + + /* + * TPP1 is for the flags that indicate which PPI operations + * are supported by the firmware. The firmware is expected to + * write these flags. + */ + aml_append(dev, + aml_operation_region("TPP1", AML_SYSTEM_MEMORY, + aml_int(TPM_PPI_ADDR_BASE), + sizeof(tpm_ppi->func))); + field =3D aml_field("TPP1", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); + for (i =3D 0; i < sizeof(tpm_ppi->func); i++) { + char *tmp =3D g_strdup_printf("FN%02X", i); + aml_append(field, aml_named_field(tmp, BITS_PER_BYTE)); + g_free(tmp); + } + aml_append(dev, field); + + /* + * TPP2 is for the registers that ACPI code used to pass + * the PPI code and parameter (PPRQ, PPRM) to the firmware. + */ + aml_append(dev, + aml_operation_region("TPP2", AML_SYSTEM_MEMORY, + aml_int(TPM_PPI_ADDR_BASE + + offsetof(struct tpm_ppi, ppin)= ), + sizeof(struct tpm_ppi) - + sizeof(tpm_ppi->func))); + field =3D aml_field("TPP2", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); + aml_append(field, aml_named_field("PPIN", + sizeof(uint8_t) * BITS_PER_BYTE)); + aml_append(field, aml_named_field("PPIP", + sizeof(uint32_t) * BITS_PER_BYTE)); + aml_append(field, aml_named_field("PPRP", + sizeof(uint32_t) * BITS_PER_BYTE)); + aml_append(field, aml_named_field("PPRQ", + sizeof(uint32_t) * BITS_PER_BYTE)); + aml_append(field, aml_named_field("PPRM", + sizeof(uint32_t) * BITS_PER_BYTE)); + aml_append(field, aml_named_field("LPPR", + sizeof(uint32_t) * BITS_PER_BYTE)); + aml_append(dev, field); + + method =3D aml_method("TPFN", 1, AML_SERIALIZED); + { + for (i =3D 0; i < sizeof(tpm_ppi->func); i++) { + ifctx =3D aml_if(aml_equal(aml_int(i), aml_arg(0))); + { + aml_append(ifctx, aml_return(aml_name("FN%02X", i))); + } + aml_append(method, ifctx); + } + aml_append(method, aml_return(aml_int(0))); + } + aml_append(dev, method); + + pak =3D aml_package(2); + aml_append(pak, aml_int(0)); + aml_append(pak, aml_int(0)); + name =3D aml_name_decl("TPM2", pak); + aml_append(dev, name); + + pak =3D aml_package(3); + aml_append(pak, aml_int(0)); + aml_append(pak, aml_int(0)); + aml_append(pak, aml_int(0)); + name =3D aml_name_decl("TPM3", pak); + aml_append(dev, name); + + method =3D aml_method("_DSM", 4, AML_SERIALIZED); + { + uint8_t zerobyte[1] =3D { 0 }; + + ifctx =3D aml_if( + aml_equal(aml_arg(0), + aml_touuid("3DDDFAA6-361B-4EB4-A424-8D10089D1653"))); + { + aml_append(ifctx, + aml_store(aml_to_integer(aml_arg(2)), aml_local(0))= ); + + /* standard DSM query function */ + ifctx2 =3D aml_if(aml_equal(aml_local(0), aml_int(0))); + { + uint8_t byte_list[2] =3D { 0xff, 0x01 }; + aml_append(ifctx2, aml_return(aml_buffer(2, byte_list))); + } + aml_append(ifctx, ifctx2); + + /* interface version: 1.3 */ + ifctx2 =3D aml_if(aml_equal(aml_local(0), aml_int(1))); + { + aml_append(ifctx2, aml_return(aml_string("1.3"))); + } + aml_append(ifctx, ifctx2); + + /* submit TPM operation */ + ifctx2 =3D aml_if(aml_equal(aml_local(0), aml_int(2))); + { + /* get opcode */ + aml_append(ifctx2, + aml_store(aml_derefof(aml_index(aml_arg(3), + aml_int(0))), + aml_local(0))); + /* get opcode flags */ + aml_append(ifctx2, + aml_store(aml_call1("TPFN", aml_local(0)), + aml_local(1))); + ifctx3 =3D aml_if( + aml_equal( + aml_and(aml_local(1), aml_int(TPM_PPI_FUNC_MASK), = NULL), + aml_int(TPM_PPI_FUNC_NOT_IMPLEMENTED))); + { + /* 1: not implemented */ + aml_append(ifctx3, aml_return(aml_int(1))); + } + aml_append(ifctx2, ifctx3); + aml_append(ifctx2, aml_store(aml_local(0), aml_name("PPRQ"= ))); + aml_append(ifctx2, aml_store(aml_int(0), aml_name("PPRM"))= ); + /* 0: success */ + aml_append(ifctx2, aml_return(aml_int(0))); + } + aml_append(ifctx, ifctx2); + + /* get pending TPM operation */ + ifctx2 =3D aml_if(aml_equal(aml_local(0), aml_int(3))); + { + /* revision to integer */ + aml_append(ifctx2, + aml_store( + aml_to_integer(aml_arg(1)), + aml_local(1))); + ifctx3 =3D aml_if(aml_equal(aml_local(1), aml_int(1))); + { + aml_append(ifctx3, + aml_store( + aml_name("PPRQ"), + aml_index(aml_name("TPM2"), aml_int(1))= )); + aml_append(ifctx3, aml_return(aml_name("TPM2"))); + } + aml_append(ifctx2, ifctx3); + + ifctx3 =3D aml_if(aml_equal(aml_local(1), aml_int(2))); + { + aml_append(ifctx3, + aml_store( + aml_name("PPRQ"), + aml_index(aml_name("TPM3"), aml_int(1))= )); + aml_append(ifctx3, + aml_store( + aml_name("PPRM"), + aml_index(aml_name("TPM3"), aml_int(2))= )); + aml_append(ifctx3, aml_return(aml_name("TPM3"))); + } + aml_append(ifctx2, ifctx3); + } + aml_append(ifctx, ifctx2); + + /* get platform-specific action to transition to pre-OS env. */ + ifctx2 =3D aml_if(aml_equal(aml_local(0), aml_int(4))); + { + /* reboot */ + aml_append(ifctx2, aml_return(aml_int(2))); + } + aml_append(ifctx, ifctx2); + + /* get TPM operation response */ + ifctx2 =3D aml_if(aml_equal(aml_local(0), aml_int(5))); + { + aml_append(ifctx2, + aml_store( + aml_name("LPPR"), + aml_index(aml_name("TPM3"), aml_int(1)))); + aml_append(ifctx2, + aml_store( + aml_name("PPRP"), + aml_index(aml_name("TPM3"), aml_int(2)))); + aml_append(ifctx2, aml_return(aml_name("TPM3"))); + } + aml_append(ifctx, ifctx2); + + /* submit preferred user language */ + ifctx2 =3D aml_if(aml_equal(aml_local(0), aml_int(6))); + { + /* 3 =3D not implemented */ + aml_append(ifctx2, aml_return(aml_int(3))); + } + aml_append(ifctx, ifctx2); + + /* submit TPM operation v2 */ + ifctx2 =3D aml_if(aml_equal(aml_local(0), aml_int(7))); + { + /* get opcode */ + aml_append(ifctx2, + aml_store(aml_derefof(aml_index(aml_arg(3), + aml_int(0))), + aml_local(0))); + /* get opcode flags */ + aml_append(ifctx2, + aml_store(aml_call1("TPFN", aml_local(0)), + aml_local(1))); + ifctx3 =3D aml_if( + aml_equal( + aml_and(aml_local(1), aml_int(TPM_PPI_FUNC_MASK), = NULL), + aml_int(TPM_PPI_FUNC_NOT_IMPLEMENTED))); + { + /* 1: not implemented */ + aml_append(ifctx3, aml_return(aml_int(1))); + } + aml_append(ifctx2, ifctx3); + + ifctx3 =3D aml_if( + aml_equal( + aml_and(aml_local(1), aml_int(TPM_PPI_FUNC_MASK), = NULL), + aml_int(TPM_PPI_FUNC_BLOCKED))); + { + /* 3: blocked by firmware */ + aml_append(ifctx3, aml_return(aml_int(3))); + } + aml_append(ifctx2, ifctx3); + + /* revision to integer */ + aml_append(ifctx2, + aml_store( + aml_to_integer(aml_arg(1)), + aml_local(1))); + + ifctx3 =3D aml_if(aml_equal(aml_local(1), aml_int(1))); + { + /* revision 1 */ + aml_append(ifctx3, aml_store(aml_local(0), + aml_name("PPRQ"))); + aml_append(ifctx3, aml_store(aml_int(0), + aml_name("PPRM"))); + } + aml_append(ifctx2, ifctx3); + + ifctx3 =3D aml_if(aml_equal(aml_local(1), aml_int(2))); + { + /* revision 2 */ + aml_append(ifctx3, + aml_store(aml_local(0), aml_name("PPRQ"))); + aml_append(ifctx3, + aml_store( + aml_derefof(aml_index(aml_arg(3), + aml_int(1))), + aml_name("PPRM"))); + } + aml_append(ifctx2, ifctx3); + /* 0: success */ + aml_append(ifctx2, aml_return(aml_int(0))); + } + aml_append(ifctx, ifctx2); + + /* get user confirmation status for operation */ + ifctx2 =3D aml_if(aml_equal(aml_local(0), aml_int(8))); + { + /* get opcode */ + aml_append(ifctx2, + aml_store(aml_derefof(aml_index(aml_arg(3), + aml_int(0))), + aml_local(0))); + /* get opcode flags */ + aml_append(ifctx2, + aml_store(aml_call1("TPFN", aml_local(0)), + aml_local(1))); + /* return confirmation status code */ + aml_append(ifctx2, + aml_return( + aml_and(aml_local(1), + aml_int(TPM_PPI_FUNC_MASK), NULL))); + } + aml_append(ifctx, ifctx2); + + aml_append(ifctx, aml_return(aml_buffer(1, zerobyte))); + } + aml_append(method, ifctx); + } + aml_append(dev, method); +} + static void build_dsdt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm, AcpiMiscInfo *misc, @@ -2153,6 +2440,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, */ /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ aml_append(dev, aml_name_decl("_CRS", crs)); + + build_tpm_ppi(dev); + aml_append(scope, dev); } =20 @@ -2172,6 +2462,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(method, aml_return(aml_int(0x0f))); aml_append(dev, method); =20 + build_tpm_ppi(dev); + aml_append(sb_scope, dev); } =20 @@ -2918,7 +3210,7 @@ void acpi_setup(void) tpm_config =3D (FWCfgTPMConfig) { .tpmppi_address =3D cpu_to_le32(TPM_PPI_ADDR_BASE), .tpm_version =3D cpu_to_le32(tpm_get_version(tpm_find())), - .tpmppi_version =3D cpu_to_le32(TPM_PPI_VERSION_NONE) + .tpmppi_version =3D cpu_to_le32(TPM_PPI_VERSION_1_30) }; fw_cfg_add_file(pcms->fw_cfg, "etc/tpm/config", &tpm_config, sizeof tpm_config); --=20 2.17.0.253.g3dd125b46d From nobody Sat Apr 20 15:00:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152638673675689.27583745203117; Tue, 15 May 2018 05:18:56 -0700 (PDT) Received: from localhost ([::1]:34957 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIYut-0001lf-SC for importer@patchew.org; Tue, 15 May 2018 08:18:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40747) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIYrp-0008J0-1G for qemu-devel@nongnu.org; Tue, 15 May 2018 08:15:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIYrk-00016z-3R for qemu-devel@nongnu.org; Tue, 15 May 2018 08:15:44 -0400 Received: from mx1.redhat.com ([209.132.183.28]:22623) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fIYrj-00016H-Ti for qemu-devel@nongnu.org; Tue, 15 May 2018 08:15:40 -0400 Received: from smtp.corp.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 0CBD1157711; Tue, 15 May 2018 12:15:39 +0000 (UTC) Received: from localhost (ovpn-116-28.phx2.redhat.com [10.3.116.28]) by smtp.corp.redhat.com (Postfix) with ESMTP id 764EF9BD43; Tue, 15 May 2018 12:15:38 +0000 (UTC) From: =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= To: qemu-devel@nongnu.org Date: Tue, 15 May 2018 14:14:33 +0200 Message-Id: <20180515121433.6112-5-marcandre.lureau@redhat.com> In-Reply-To: <20180515121433.6112-1-marcandre.lureau@redhat.com> References: <20180515121433.6112-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.27 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Tue, 15 May 2018 12:15:39 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v3 4/4] tpm: add a fake ACPI memory clear interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , "Michael S. Tsirkin" , stefanb@linux.vnet.ibm.com, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Igor Mammedov , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This allows to pass the last failing test from the Windows HLK TPM 2.0 TCG PPI 1.3 tests. The interface is described in the "TCG Platform Reset Attack Mitigation Specification", chapter 6 "ACPI _DSM Function". Whether or not we should have a real implementation remains an open question to me. Signed-off-by: Marc-Andr=C3=A9 Lureau --- hw/i386/acpi-build.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 95be4f0710..392a1e50bd 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -2072,6 +2072,15 @@ build_tpm_ppi(Aml *dev) aml_append(ifctx, aml_return(aml_buffer(1, zerobyte))); } aml_append(method, ifctx); + + /* dummy MOR Memory Clear for the sake of WLK PPI test */ + ifctx =3D aml_if( + aml_equal(aml_arg(0), + aml_touuid("376054ED-CC13-4675-901C-4756D7F2D45D"))); + { + aml_append(ifctx, aml_return(aml_int(0))); + } + aml_append(method, ifctx); } aml_append(dev, method); } --=20 2.17.0.253.g3dd125b46d