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X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH] fpu/softfloat: check for Inf / x or 0 / x before /0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 The re-factoring of div_floats changed the order of checking meaning an operation like -inf/0 erroneously raises the divbyzero flag. IEEE-754 (2008) specifies this should only occur for operations on finite operands. We fix this by moving the check on the dividend being Inf/0 to before the divisor is zero check. Signed-off-by: Alex Benn=C3=A9e Cc: Bastian Koppelmann Reviewed-by: Bastian Koppelmann Tested-by: Bastian Koppelmann --- fpu/softfloat.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index b46dccc63e..a7d0f3ff56 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1146,6 +1146,11 @@ static FloatParts div_floats(FloatParts a, FloatPart= s b, float_status *s) a.cls =3D float_class_dnan; return a; } + /* Inf / x or 0 / x */ + if (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero) { + a.sign =3D sign; + return a; + } /* Div 0 =3D> Inf */ if (b.cls =3D=3D float_class_zero) { s->float_exception_flags |=3D float_flag_divbyzero; @@ -1153,11 +1158,6 @@ static FloatParts div_floats(FloatParts a, FloatPart= s b, float_status *s) a.sign =3D sign; return a; } - /* Inf / x or 0 / x */ - if (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero) { - a.sign =3D sign; - return a; - } /* Div by Inf */ if (b.cls =3D=3D float_class_inf) { a.cls =3D float_class_zero; --=20 2.17.0