From nobody Sat May 11 03:00:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1523629599339762.528003012197; Fri, 13 Apr 2018 07:26:39 -0700 (PDT) Received: from localhost ([::1]:57387 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f6zes-0005Kg-F5 for importer@patchew.org; Fri, 13 Apr 2018 10:26:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58830) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f6zcC-0003NH-4m for qemu-devel@nongnu.org; Fri, 13 Apr 2018 10:23:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f6zcB-0004JK-6a for qemu-devel@nongnu.org; Fri, 13 Apr 2018 10:23:48 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40824) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f6zcA-0004De-VA for qemu-devel@nongnu.org; Fri, 13 Apr 2018 10:23:47 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1f6zc1-0001wi-G8; Fri, 13 Apr 2018 15:23:37 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 13 Apr 2018 15:23:36 +0100 Message-Id: <20180413142336.32163-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH for-2.12] tcg/mips: Handle large offsets from target env to tlb_table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , "Michael S. Tsirkin" , Yongbok Kim , Aurelien Jarno , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 The MIPS TCG target makes the assumption that the offset from the target env pointer to the tlb_table is less than about 64K. This used to be true, but gradual addition of features to the Arm target means that it's no longer true there. This results in the build-time assertion failing: In file included from /home/pm215/qemu/include/qemu/osdep.h:36:0, from /home/pm215/qemu/tcg/tcg.c:28: /home/pm215/qemu/tcg/mips/tcg-target.inc.c: In function =E2=80=98tcg_out_tl= b_load=E2=80=99: /home/pm215/qemu/include/qemu/compiler.h:90:36: error: static assertion fai= led: "not expecting: offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1][1])= > 0x7ff0 + 0x7fff" #define QEMU_BUILD_BUG_MSG(x, msg) _Static_assert(!(x), msg) ^ /home/pm215/qemu/include/qemu/compiler.h:98:30: note: in expansion of macro= =E2=80=98QEMU_BUILD_BUG_MSG=E2=80=99 #define QEMU_BUILD_BUG_ON(x) QEMU_BUILD_BUG_MSG(x, "not expecting: " #x) ^ /home/pm215/qemu/tcg/mips/tcg-target.inc.c:1236:9: note: in expansion of ma= cro =E2=80=98QEMU_BUILD_BUG_ON=E2=80=99 QEMU_BUILD_BUG_ON(offsetof(CPUArchState, ^ /home/pm215/qemu/rules.mak:66: recipe for target 'tcg/tcg.o' failed An ideal long term approach would be to rearrange the CPU state so that the tlb_table was not so far along it, but this is tricky because it would move it from the "not cleared on CPU reset" part of the struct to the "cleared on CPU reset" part. As a simple fix for the 2.12 release, make the MIPS TCG target handle an arbitrary offset by emitting more add instructions. This will mean an extra instruction in the fastpath for TCG loads and stores for the affected guests (currently just aarch64-softmmu). Signed-off-by: Peter Maydell Acked-by: Michael S. Tsirkin Reviewed-by: Richard Henderson --- This is sufficient that on MIPS host we can now at least build and run an aarch64 guest kernel. I haven't tried 'make check' because the only MIPS system I have access to is way too slow... tcg/mips/tcg-target.inc.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 4b55ab8856..ca5f1d4894 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -1229,13 +1229,10 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg = base, TCGReg addrl, tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, TCG_REG_A0, TCG_AREG0); =20 /* Compensate for very large offsets. */ - if (add_off >=3D 0x8000) { - /* Most target env are smaller than 32k; none are larger than 64k. - Simplify the logic here merely to offset by 0x7ff0, giving us a - range just shy of 64k. Check this assumption. */ - QEMU_BUILD_BUG_ON(offsetof(CPUArchState, - tlb_table[NB_MMU_MODES - 1][1]) - > 0x7ff0 + 0x7fff); + while (add_off >=3D 0x8000) { + /* Most target env are smaller than 32k, but a few are larger than= 64k, + * so handle an arbitrarily large offset. + */ tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, TCG_REG_A0, 0x7ff0); cmp_off -=3D 0x7ff0; add_off -=3D 0x7ff0; --=20 2.16.2