From nobody Thu May 2 19:04:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1523355281683391.404990945023; Tue, 10 Apr 2018 03:14:41 -0700 (PDT) Received: from localhost ([::1]:60333 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f5qIN-0007ha-3s for importer@patchew.org; Tue, 10 Apr 2018 06:14:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36545) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f5qHN-0007Hu-C8 for qemu-devel@nongnu.org; Tue, 10 Apr 2018 06:13:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f5qHK-0007an-IX for qemu-devel@nongnu.org; Tue, 10 Apr 2018 06:13:33 -0400 Received: from mail-pf0-x22b.google.com ([2607:f8b0:400e:c00::22b]:45242) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f5qHK-0007aL-6N for qemu-devel@nongnu.org; Tue, 10 Apr 2018 06:13:30 -0400 Received: by mail-pf0-x22b.google.com with SMTP id l27so7880099pfk.12 for ; Tue, 10 Apr 2018 03:13:30 -0700 (PDT) Received: from cloudburst.twiddle.net ([2001:8000:10e0:a000:c673:a6b6:fdef:1933]) by smtp.gmail.com with ESMTPSA id 67sm4711688pfz.57.2018.04.10.03.13.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Apr 2018 03:13:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=5vW/5BtQU2gm2FEcgF0AtuoXEU2Cdjf0y5fDU6gf154=; b=JdbjClQvu1su0fqSHZeV0NxWPPTz24t4EOop2iG1bPzQTxkWFmckIOw6mdvTkv4I/D zJohqGeXX8y9+0uIhpwSAf50WwRa4DkTu7YASLAp62gj+TTG2UG6otWBirU7UR/dSAQe X1qDWHoVCZf6G2b4AHNcDwZ79Y7UJNx1psM8o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=5vW/5BtQU2gm2FEcgF0AtuoXEU2Cdjf0y5fDU6gf154=; b=Dfb0fa/vJTQpTgm/wNnIf0sHleVJDzdEJerxkBd7MS0Oq0XDpEahkDvryfmvHfMs7H Ng0DQZrabMe2Q/Rkiis/E8d+pwDPHBNErPGa6gPwtKXmbgQMwoyZxHh6EgKs7Agn5N1d DVkYjhr+HJ/79HFy8wwDqLPmPtUIh6BfOQ9qKb5IwYG8sH5wApY41vBwi+7vvcplb3Jd tA6EpWfk+sryWuP9AShS5J3r6m8STT+uFtOA+kng/F+4eeThdH/Rc1Bou87p3Xw3vwSI riodPapdhCLKolA+/+DZBwaeikgNEF7esam56/o9CAcB6e3+4DDCLTZO9we6pDW4Mkyq Msaw== X-Gm-Message-State: ALQs6tBGN6LeCtermeTZNySkQEvtan4ir8pYE3NyojGt9/WLjBEUf/Mc SRkhBAY4yV1ht9UlJodHBOaCIiDs6rA= X-Google-Smtp-Source: AIpwx4+HVK5Hfw80l/SncDYTvcyW9YbtUAkGySKSE5+XZxeVzSiEwD3TgLZq7P7v6AdXbGqmDntNow== X-Received: by 10.99.107.196 with SMTP id g187mr18741808pgc.384.1523355208541; Tue, 10 Apr 2018 03:13:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 10 Apr 2018 20:13:19 +1000 Message-Id: <20180410101319.2519-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22b Subject: [Qemu-devel] [PATCH v2 for-2.12] icount: fix cpu_restore_state_from_tb for non-tb-exit cases X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bonzini@redhat.com, Pavel Dovgalyuk Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Pavel Dovgalyuk In icount mode, instructions that access io memory spaces in the middle of the translation block invoke TB recompilation. After recompilation, such instructions become last in the TB and are allowed to access io memory spaces. When the code includes instruction like i386 'xchg eax, 0xffffd080' which accesses APIC, QEMU goes into an infinite loop of the recompilation. This instruction includes two memory accesses - one read and one write. After the first access, APIC calls cpu_report_tpr_access, which restores the CPU state to get the current eip. But cpu_restore_state_from_tb resets the cpu->can_do_io flag which makes the second memory access invalid. Therefore the second memory access causes a recompilation of the block. Then these operations repeat again and again. This patch moves resetting cpu->can_do_io flag from cpu_restore_state_from_tb to cpu_loop_exit* functions. It also adds a parameter for cpu_restore_state which controls restoring icount. There is no need to restore icount when we only query CPU state without breaking the TB. Restoring it in such cases leads to the incorrect flow of the virtual time. In most cases new parameter is true (icount should be recalculated). But there are two cases in i386 and openrisc when the CPU state is only queried without the need to break the TB. This patch fixes both of these cases. Signed-off-by: Pavel Dovgalyuk Message-Id: <20180409091320.12504.35329.stgit@pasha-VirtualBox> [rth: Make can_do_io setting unconditional; move from cpu_exec; make cpu_loop_exit_{noexc,restore} call cpu_loop_exit.] Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 5 ++++- accel/tcg/cpu-exec-common.c | 10 +++++----- accel/tcg/cpu-exec.c | 1 - accel/tcg/translate-all.c | 27 ++++++++++++++------------- accel/tcg/user-exec.c | 2 +- hw/misc/mips_itu.c | 3 +-- target/alpha/helper.c | 2 +- target/alpha/mem_helper.c | 6 ++---- target/arm/op_helper.c | 6 +++--- target/cris/op_helper.c | 4 ++-- target/i386/helper.c | 2 +- target/i386/svm_helper.c | 2 +- target/m68k/op_helper.c | 4 ++-- target/moxie/helper.c | 2 +- target/openrisc/sys_helper.c | 8 ++++---- target/tricore/op_helper.c | 2 +- target/xtensa/op_helper.c | 4 ++-- 17 files changed, 45 insertions(+), 45 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index e5afd2e6d3..bd68328ed9 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -50,13 +50,16 @@ void cpu_gen_init(void); * cpu_restore_state: * @cpu: the vCPU state is to be restore to * @searched_pc: the host PC the fault occurred at + * @will_exit: true if the TB executed will be interrupted after some + cpu adjustments. Required for maintaining the correct + icount valus * @return: true if state was restored, false otherwise * * Attempt to restore the state for a fault occurring in translated * code. If the searched_pc is not in translated code no state is * restored and the function returns false. */ -bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); +bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc, bool will_exi= t); =20 void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu); void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index dac5aac477..2988fde650 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -27,10 +27,8 @@ bool tcg_allowed; /* exit the current TB, but without causing any exception to be raised */ void cpu_loop_exit_noexc(CPUState *cpu) { - /* XXX: restore cpu registers saved in host registers */ - cpu->exception_index =3D -1; - siglongjmp(cpu->jmp_env, 1); + cpu_loop_exit(cpu); } =20 #if defined(CONFIG_SOFTMMU) @@ -65,15 +63,17 @@ void cpu_reloading_memory_map(void) =20 void cpu_loop_exit(CPUState *cpu) { + /* Undo the setting in cpu_tb_exec. */ + cpu->can_do_io =3D 1; siglongjmp(cpu->jmp_env, 1); } =20 void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc) { if (pc) { - cpu_restore_state(cpu, pc); + cpu_restore_state(cpu, pc, true); } - siglongjmp(cpu->jmp_env, 1); + cpu_loop_exit(cpu); } =20 void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 9cc697205c..81153e7a13 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -704,7 +704,6 @@ int cpu_exec(CPUState *cpu) g_assert(cpu =3D=3D current_cpu); g_assert(cc =3D=3D CPU_GET_CLASS(cpu)); #endif /* buggy compiler */ - cpu->can_do_io =3D 1; tb_lock_reset(); if (qemu_mutex_iothread_locked()) { qemu_mutex_unlock_iothread(); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index d4190602d1..f409d42d54 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -299,9 +299,11 @@ static int encode_search(TranslationBlock *tb, uint8_t= *block) =20 /* The cpu state corresponding to 'searched_pc' is restored. * Called with tb_lock held. + * When reset_icount is true, current TB will be interrupted and + * icount should be recalculated. */ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, - uintptr_t searched_pc) + uintptr_t searched_pc, bool reset_ico= unt) { target_ulong data[TARGET_INSN_START_WORDS] =3D { tb->pc }; uintptr_t host_pc =3D (uintptr_t)tb->tc.ptr; @@ -333,14 +335,12 @@ static int cpu_restore_state_from_tb(CPUState *cpu, T= ranslationBlock *tb, return -1; =20 found: - if (tb->cflags & CF_USE_ICOUNT) { + if (reset_icount && (tb->cflags & CF_USE_ICOUNT)) { assert(use_icount); - /* Reset the cycle counter to the start of the block. */ - cpu->icount_decr.u16.low +=3D num_insns; - /* Clear the IO flag. */ - cpu->can_do_io =3D 0; + /* Reset the cycle counter to the start of the block + and shift if to the number of actually executed instructions */ + cpu->icount_decr.u16.low +=3D num_insns - i; } - cpu->icount_decr.u16.low -=3D i; restore_state_to_opc(env, tb, data); =20 #ifdef CONFIG_PROFILER @@ -351,7 +351,7 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tra= nslationBlock *tb, return 0; } =20 -bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc) +bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit) { TranslationBlock *tb; bool r =3D false; @@ -377,7 +377,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc) tb_lock(); tb =3D tb_find_pc(host_pc); if (tb) { - cpu_restore_state_from_tb(cpu, tb, host_pc); + cpu_restore_state_from_tb(cpu, tb, host_pc, will_exit); if (tb->cflags & CF_NOCACHE) { /* one-shot translation, invalidate it immediately */ tb_phys_invalidate(tb, -1); @@ -1511,7 +1511,8 @@ void tb_invalidate_phys_page_range(tb_page_addr_t sta= rt, tb_page_addr_t end, restore the CPU state */ =20 current_tb_modified =3D 1; - cpu_restore_state_from_tb(cpu, current_tb, cpu->mem_io_pc); + cpu_restore_state_from_tb(cpu, current_tb, + cpu->mem_io_pc, true); cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, ¤t_flags); } @@ -1634,7 +1635,7 @@ static bool tb_invalidate_phys_page(tb_page_addr_t ad= dr, uintptr_t pc) restore the CPU state */ =20 current_tb_modified =3D 1; - cpu_restore_state_from_tb(cpu, current_tb, pc); + cpu_restore_state_from_tb(cpu, current_tb, pc, true); cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, ¤t_flags); } @@ -1700,7 +1701,7 @@ void tb_check_watchpoint(CPUState *cpu) tb =3D tb_find_pc(cpu->mem_io_pc); if (tb) { /* We can use retranslation to find the PC. */ - cpu_restore_state_from_tb(cpu, tb, cpu->mem_io_pc); + cpu_restore_state_from_tb(cpu, tb, cpu->mem_io_pc, true); tb_phys_invalidate(tb, -1); } else { /* The exception probably happened in a helper. The CPU state sho= uld @@ -1736,7 +1737,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retadd= r) cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=3D%p", (void *)retaddr); } - cpu_restore_state_from_tb(cpu, tb, retaddr); + cpu_restore_state_from_tb(cpu, tb, retaddr, true); =20 /* On MIPS and SH, delay slot instructions can only be restarted if they were already the first instruction in the TB. If this is not diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 77899584f2..26a3ffbba1 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -168,7 +168,7 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, } =20 /* Now we have a real cpu fault. */ - cpu_restore_state(cpu, pc); + cpu_restore_state(cpu, pc, true); =20 sigprocmask(SIG_SETMASK, old_set, NULL); cpu_loop_exit(cpu); diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index ef935b51a8..c84a48bbb7 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -174,10 +174,9 @@ static void wake_blocked_threads(ITCStorageCell *c) static void QEMU_NORETURN block_thread_and_exit(ITCStorageCell *c) { c->blocked_threads |=3D 1ULL << current_cpu->cpu_index; - cpu_restore_state(current_cpu, current_cpu->mem_io_pc); current_cpu->halted =3D 1; current_cpu->exception_index =3D EXCP_HLT; - cpu_loop_exit(current_cpu); + cpu_loop_exit_restore(current_cpu, current_cpu->mem_io_pc); } =20 /* ITC Bypass View */ diff --git a/target/alpha/helper.c b/target/alpha/helper.c index bbf72cadfb..8a6a948572 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -482,7 +482,7 @@ void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uin= tptr_t retaddr, cs->exception_index =3D excp; env->error_code =3D error; if (retaddr) { - cpu_restore_state(cs, retaddr); + cpu_restore_state(cs, retaddr, true); /* Floating-point exceptions (our only users) point to the next PC= . */ env->pc +=3D 4; } diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index e19ab91ec9..011bc73dca 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -34,7 +34,7 @@ void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr ad= dr, uint64_t pc; uint32_t insn; =20 - cpu_restore_state(cs, retaddr); + cpu_restore_state(cs, retaddr, true); =20 pc =3D env->pc; insn =3D cpu_ldl_code(env, pc); @@ -56,13 +56,11 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, AlphaCPU *cpu =3D ALPHA_CPU(cs); CPUAlphaState *env =3D &cpu->env; =20 - cpu_restore_state(cs, retaddr); - env->trap_arg0 =3D addr; env->trap_arg1 =3D access_type =3D=3D MMU_DATA_STORE ? 1 : 0; cs->exception_index =3D EXCP_MCHK; env->error_code =3D 0; - cpu_loop_exit(cs); + cpu_loop_exit_restore(cs, retaddr); } =20 /* try to fill the TLB and return an exception if error. If retaddr is diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index a266cc0116..84f08bf815 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -180,7 +180,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, ARMCPU *cpu =3D ARM_CPU(cs); =20 /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); + cpu_restore_state(cs, retaddr, true); =20 deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } @@ -195,7 +195,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr va= ddr, ARMMMUFaultInfo fi =3D {}; =20 /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); + cpu_restore_state(cs, retaddr, true); =20 fi.type =3D ARMFault_Alignment; deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); @@ -215,7 +215,7 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr= physaddr, ARMMMUFaultInfo fi =3D {}; =20 /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); + cpu_restore_state(cs, retaddr, true); =20 fi.ea =3D arm_extabort_type(response); fi.type =3D ARMFault_SyncExternal; diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c index becd831b6b..0ee3a3117b 100644 --- a/target/cris/op_helper.c +++ b/target/cris/op_helper.c @@ -54,8 +54,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, if (unlikely(ret)) { if (retaddr) { /* now we have a real cpu fault */ - if (cpu_restore_state(cs, retaddr)) { - /* Evaluate flags after retranslation. */ + if (cpu_restore_state(cs, retaddr, true)) { + /* Evaluate flags after retranslation. */ helper_top_evaluate_flags(env); } } diff --git a/target/i386/helper.c b/target/i386/helper.c index 9fba146b7f..e695f8ba7a 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -991,7 +991,7 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess = access) =20 cpu_interrupt(cs, CPU_INTERRUPT_TPR); } else if (tcg_enabled()) { - cpu_restore_state(cs, cs->mem_io_pc); + cpu_restore_state(cs, cs->mem_io_pc, false); =20 apic_handle_tpr_access_report(cpu->apic_state, env->eip, access); } diff --git a/target/i386/svm_helper.c b/target/i386/svm_helper.c index 303106981c..350492359c 100644 --- a/target/i386/svm_helper.c +++ b/target/i386/svm_helper.c @@ -584,7 +584,7 @@ void cpu_vmexit(CPUX86State *env, uint32_t exit_code, u= int64_t exit_info_1, { CPUState *cs =3D CPU(x86_env_get_cpu(env)); =20 - cpu_restore_state(cs, retaddr); + cpu_restore_state(cs, retaddr, true); =20 qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmexit(%08x, %016" PRIx64 ", %016" PRIx64 ", " TARGET_FMT_lx ")!\n", diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index ffea9693fc..3a7f7f2219 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -1056,7 +1056,7 @@ void HELPER(chk)(CPUM68KState *env, int32_t val, int3= 2_t ub) CPUState *cs =3D CPU(m68k_env_get_cpu(env)); =20 /* Recover PC and CC_OP for the beginning of the insn. */ - cpu_restore_state(cs, GETPC()); + cpu_restore_state(cs, GETPC(), true); =20 /* flags have been modified by gen_flush_flags() */ env->cc_op =3D CC_OP_FLAGS; @@ -1087,7 +1087,7 @@ void HELPER(chk2)(CPUM68KState *env, int32_t val, int= 32_t lb, int32_t ub) CPUState *cs =3D CPU(m68k_env_get_cpu(env)); =20 /* Recover PC and CC_OP for the beginning of the insn. */ - cpu_restore_state(cs, GETPC()); + cpu_restore_state(cs, GETPC(), true); =20 /* flags have been modified by gen_flush_flags() */ env->cc_op =3D CC_OP_FLAGS; diff --git a/target/moxie/helper.c b/target/moxie/helper.c index b8e86560da..5b1532b837 100644 --- a/target/moxie/helper.c +++ b/target/moxie/helper.c @@ -48,7 +48,7 @@ void helper_raise_exception(CPUMoxieState *env, int ex) /* Stash the exception type. */ env->sregs[2] =3D ex; /* Stash the address where the exception occurred. */ - cpu_restore_state(cs, GETPC()); + cpu_restore_state(cs, GETPC(), true); env->sregs[5] =3D env->pc; /* Jump to the exception handline routine. */ env->pc =3D env->sregs[1]; diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 9fb7d86b4b..b284064381 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -46,7 +46,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, break; =20 case TO_SPR(0, 16): /* NPC */ - cpu_restore_state(cs, GETPC()); + cpu_restore_state(cs, GETPC(), true); /* ??? Mirror or1ksim in not trashing delayed branch state when "jumping" to the current instruction. */ if (env->pc !=3D rb) { @@ -146,7 +146,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(8, 0): /* PMR */ env->pmr =3D rb; if (env->pmr & PMR_DME || env->pmr & PMR_SME) { - cpu_restore_state(cs, GETPC()); + cpu_restore_state(cs, GETPC(), true); env->pc +=3D 4; cs->halted =3D 1; raise_exception(cpu, EXCP_HALTED); @@ -230,14 +230,14 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, return env->evbar; =20 case TO_SPR(0, 16): /* NPC (equals PC) */ - cpu_restore_state(cs, GETPC()); + cpu_restore_state(cs, GETPC(), false); return env->pc; =20 case TO_SPR(0, 17): /* SR */ return cpu_get_sr(env); =20 case TO_SPR(0, 18): /* PPC */ - cpu_restore_state(cs, GETPC()); + cpu_restore_state(cs, GETPC(), false); return env->ppc; =20 case TO_SPR(0, 32): /* EPCR */ diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index 16955f273e..b57f35387d 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -31,7 +31,7 @@ raise_exception_sync_internal(CPUTriCoreState *env, uint3= 2_t class, int tin, { CPUState *cs =3D CPU(tricore_env_get_cpu(env)); /* in case we come from a helper-call we need to restore the PC */ - cpu_restore_state(cs, pc); + cpu_restore_state(cs, pc, true); =20 /* Tin is loaded into d[15] */ env->gpr_d[15] =3D tin; diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index d401105d09..e3bcbe10d6 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -52,7 +52,7 @@ void xtensa_cpu_do_unaligned_access(CPUState *cs, =20 if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTI= ON) && !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT= )) { - cpu_restore_state(CPU(cpu), retaddr); + cpu_restore_state(CPU(cpu), retaddr, true); HELPER(exception_cause_vaddr)(env, env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr); } @@ -78,7 +78,7 @@ void tlb_fill(CPUState *cs, target_ulong vaddr, int size, paddr & TARGET_PAGE_MASK, access, mmu_idx, page_size); } else { - cpu_restore_state(cs, retaddr); + cpu_restore_state(cs, retaddr, true); HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); } } --=20 2.14.3