From nobody Fri May 3 00:07:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1523270450811669.1142254896382; Mon, 9 Apr 2018 03:40:50 -0700 (PDT) Received: from localhost ([::1]:55474 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f5UEE-0000p3-4E for importer@patchew.org; Mon, 09 Apr 2018 06:40:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54011) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f5UCL-00081q-5Y for qemu-devel@nongnu.org; Mon, 09 Apr 2018 06:38:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f5UCK-0003mO-98 for qemu-devel@nongnu.org; Mon, 09 Apr 2018 06:38:53 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40724) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f5UCG-0003iC-5v; Mon, 09 Apr 2018 06:38:48 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1f5UC4-00057C-65; Mon, 09 Apr 2018 11:38:36 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 9 Apr 2018 11:38:34 +0100 Message-Id: <20180409103834.11285-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH for-2.12] target/arm: Don't corrupt insn_start arguments on 32-bit hosts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alarson@ddci.com, Richard Henderson , qemu-stable@nongnu.org, patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For the Arm target, we have a 3-operand tcg_insn_start, where the 3 arguments are the PC, condexec bits, and a syndrome value. We set it up like this: tcg_gen_insn_start(dc->pc, (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), 0); dc->insn_start =3D tcg_last_op(); and then we patch in the 3rd operand later in disas_set_insn_syndrome(): tcg_set_insn_param(s->insn_start, 2, syn); Unfortunately, if we're running on a setup where TARGET_LONG_BITS > TCG_TARGET_REG_BITS (ie 64 bit guest on 32 bit host), tcg_gen_insn_start() has under the hood split the 3 operands we gave it into 6, and so we end up patching a syndrome value into the condexec bits. This means we'll end up with corrupted guest condexec state if we have to do a cpu_restore_state(), which happens often when using icount and occasionally for load/store instructions that fault. Fix the bug by using the correct operand offset for the 64-on-32 case. Cc: qemu-stable@nongnu.org Reported-by: alarson@ddci.com Signed-off-by: Peter Maydell --- This doesn't apply as-is to the stable branch, but the difference is minor (insn_start was insn_start_idx, but the 2 vs 4 for argument 2 is still the same.) --- target/arm/translate.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/translate.h b/target/arm/translate.h index c47febf99d..f04ece9cfd 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -120,7 +120,15 @@ static inline void disas_set_insn_syndrome(DisasContex= t *s, uint32_t syn) =20 /* We check and clear insn_start_idx to catch multiple updates. */ assert(s->insn_start !=3D NULL); +#if TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS tcg_set_insn_param(s->insn_start, 2, syn); +#else + /* tcg_gen_insn_start has split every target_ulong argument to + * op_insn_start into two 32-bit arguments, so we want the low + * half of the 3rd argument, which is at index 4. + */ + tcg_set_insn_param(s->insn_start, 4, syn); +#endif s->insn_start =3D NULL; } =20 --=20 2.16.2