From nobody Mon Apr 29 10:10:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522895022453578.856394350476; Wed, 4 Apr 2018 19:23:42 -0700 (PDT) Received: from localhost ([::1]:48556 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uYp-0008E4-LM for importer@patchew.org; Wed, 04 Apr 2018 22:23:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35207) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uQL-0001XV-H0 for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f3uQH-0000s9-3S for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:49 -0400 Received: from ozlabs.org ([103.22.144.67]:59325) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f3uQG-0000n3-NE; Wed, 04 Apr 2018 22:14:45 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40GmcJ6C8dz9s21; Thu, 5 Apr 2018 12:14:40 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1522894480; bh=LXWfAo9UTiQSEz/sbaJROzS/+MnqLuBzxfvsOYlW8wA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FzOal88Gst4Ux7SyfeUAPoM2rnf5e7KiOLX/OZSmfXj4Zo9iz2r8OqJsfZOXO+Lxa 72vbwRimXNXo4c19FG+6SpFD3+2sh6kaEuKRviQHfuUEQcBHzKQ66y+EPu7I02INiE 39Un3oXkZCMfTpowdRp0sTuvK6Tp/cu3kw78HAtg= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org Date: Thu, 5 Apr 2018 12:14:25 +1000 Message-Id: <20180405021437.16761-2-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180405021437.16761-1-david@gibson.dropbear.id.au> References: <20180405021437.16761-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PATCH for-2.13 01/13] target/ppc: Standardize instance_init and realize function names X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bharata@linux.vnet.ibm.com, qemu-devel@nongnu.org, David Gibson , clg@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Because of the various hooks called some variant on "init" - and the rather greater number that used to exist, I'm always wondering when a function called simply "*_init" or "*_initfn" will be called. To make it easier on myself, and maybe others, rename the instance_init hooks for ppc cpus to *_instance_init(). While we're at it rename the realize time hooks to *_realize() (from *_realizefn()) which seems to be the more common current convention. Signed-off-by: David Gibson Reviewed-by: Greg Kurz --- target/ppc/translate_init.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 391b94b97d..56b80a204a 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -9726,7 +9726,7 @@ static inline bool ppc_cpu_is_valid(PowerPCCPUClass *= pcc) #endif } =20 -static void ppc_cpu_realizefn(DeviceState *dev, Error **errp) +static void ppc_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); PowerPCCPU *cpu =3D POWERPC_CPU(dev); @@ -9952,7 +9952,7 @@ unrealize: cpu_exec_unrealizefn(cs); } =20 -static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp) +static void ppc_cpu_unrealize(DeviceState *dev, Error **errp) { PowerPCCPU *cpu =3D POWERPC_CPU(dev); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); @@ -10438,7 +10438,7 @@ static bool ppc_cpu_is_big_endian(CPUState *cs) } #endif =20 -static void ppc_cpu_initfn(Object *obj) +static void ppc_cpu_instance_init(Object *obj) { CPUState *cs =3D CPU(obj); PowerPCCPU *cpu =3D POWERPC_CPU(obj); @@ -10561,9 +10561,9 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) CPUClass *cc =3D CPU_CLASS(oc); DeviceClass *dc =3D DEVICE_CLASS(oc); =20 - device_class_set_parent_realize(dc, ppc_cpu_realizefn, + device_class_set_parent_realize(dc, ppc_cpu_realize, &pcc->parent_realize); - device_class_set_parent_unrealize(dc, ppc_cpu_unrealizefn, + device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, &pcc->parent_unrealize); pcc->pvr_match =3D ppc_pvr_match_default; pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_always; @@ -10623,7 +10623,7 @@ static const TypeInfo ppc_cpu_type_info =3D { .name =3D TYPE_POWERPC_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(PowerPCCPU), - .instance_init =3D ppc_cpu_initfn, + .instance_init =3D ppc_cpu_instance_init, .abstract =3D true, .class_size =3D sizeof(PowerPCCPUClass), .class_init =3D ppc_cpu_class_init, --=20 2.14.3 From nobody Mon Apr 29 10:10:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 152289463881817.176683368760905; Wed, 4 Apr 2018 19:17:18 -0700 (PDT) Received: from localhost ([::1]:48443 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uSa-0002qW-Mn for importer@patchew.org; Wed, 04 Apr 2018 22:17:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35133) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uQH-0001U9-M8 for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f3uQG-0000rL-Ls for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:45 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:47919) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f3uQG-0000my-7t; Wed, 04 Apr 2018 22:14:44 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40GmcJ54F2z9s0q; Thu, 5 Apr 2018 12:14:40 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1522894480; bh=MK1b+rBjAZy6r3XcbwbT9qEr7KE/+bRQFXtrMSQ5wFs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Se/asnCJCA5f4y1I3zl7Ia7y/a+9b/q0sTf2o+CK/yNtCqzh9BJ6GERn8CHDSysjp +Tujg4SWNNQf7MWVTUh7Dn7quYqbvFtGCeOUZpo/fyYEJee8umkQi5e8ziBqYXsPSF FATWkV8tGOltKPYOhMlZjl+mwBsQkzsXyI3UxjDc= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org Date: Thu, 5 Apr 2018 12:14:26 +1000 Message-Id: <20180405021437.16761-3-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180405021437.16761-1-david@gibson.dropbear.id.au> References: <20180405021437.16761-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PATCH for-2.13 02/13] target/ppc: Simplify cpu valid check in ppc_cpu_realize X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bharata@linux.vnet.ibm.com, qemu-devel@nongnu.org, David Gibson , clg@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The #if isn't necessary, because there's a suitable one inside ppc_cpu_is_valid(). We've already filtered for suitable cpu models in the functions that search and register them. So by the time we get to realize having an invalid one indicates a code error, not a user error, so an assert() is more appropriate than error_setg(). Signed-off-by: David Gibson Reviewed-by: Thomas Huth Reviewed-by: Greg Kurz --- target/ppc/translate_init.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 56b80a204a..2ae718242a 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -9749,14 +9749,7 @@ static void ppc_cpu_realize(DeviceState *dev, Error = **errp) } } =20 -#if defined(TARGET_PPCEMB) - if (!ppc_cpu_is_valid(pcc)) { - error_setg(errp, "CPU does not possess a BookE or 4xx MMU. " - "Please use qemu-system-ppc or qemu-system-ppc64 instea= d " - "or choose another CPU model."); - goto unrealize; - } -#endif + assert(ppc_cpu_is_valid(pcc)); =20 create_ppc_opcodes(cpu, &local_err); if (local_err !=3D NULL) { --=20 2.14.3 From nobody Mon Apr 29 10:10:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522894841073597.033626346952; Wed, 4 Apr 2018 19:20:41 -0700 (PDT) Received: from localhost ([::1]:48464 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uW0-0005dx-6E for importer@patchew.org; Wed, 04 Apr 2018 22:20:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35209) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uQL-0001XW-Hd for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f3uQH-0000sH-5m for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:49 -0400 Received: from ozlabs.org ([103.22.144.67]:40003) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f3uQG-0000n4-HV; Wed, 04 Apr 2018 22:14:45 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40GmcK0ltfz9s1p; Thu, 5 Apr 2018 12:14:40 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1522894481; bh=okMhW1w2+oZ9K0PWFMshkbBSXlDafeevGt48DIlXTjA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y6pVT0MOX0700KWSTi8bbO0FutO0c2mN9pZ+npNOTQdFCFn+WcdPwxrHW2upT2FCc Hr/G9mQfFirxsllBVpRAFzbLN2CHrx8ZlBYhjTW7jm6SrHGbZqEKD4+SNXI/TCuZVw vg+oMBPDr0NQ0doRuudto6APZwW6/wXDwn2mc3eY= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org Date: Thu, 5 Apr 2018 12:14:27 +1000 Message-Id: <20180405021437.16761-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180405021437.16761-1-david@gibson.dropbear.id.au> References: <20180405021437.16761-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PATCH for-2.13 03/13] target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bharata@linux.vnet.ibm.com, qemu-devel@nongnu.org, David Gibson , clg@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" As a rule we prefer to pass PowerPCCPU instead of CPUPPCState, and this change will make some things simpler later on. Signed-off-by: David Gibson Reviewed-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/fdt.c | 5 +++-- hw/ppc/pnv.c | 4 ++-- hw/ppc/spapr.c | 4 ++-- include/hw/ppc/fdt.h | 2 +- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/hw/ppc/fdt.c b/hw/ppc/fdt.c index 2ffc5866e4..2721603ffa 100644 --- a/hw/ppc/fdt.c +++ b/hw/ppc/fdt.c @@ -13,9 +13,10 @@ #include "hw/ppc/fdt.h" =20 #if defined(TARGET_PPC64) -size_t ppc_create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, - size_t maxsize) +size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop, + size_t maxsize) { + CPUPPCState *env =3D &cpu->env; size_t maxcells =3D maxsize / sizeof(uint32_t); int i, j, count; uint32_t *p =3D prop; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 98ee3c607a..5a79b24828 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -209,8 +209,8 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, voi= d *fdt) _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); } =20 - page_sizes_prop_size =3D ppc_create_page_sizes_prop(env, page_sizes_pr= op, - sizeof(page_sizes_prop)); + page_sizes_prop_size =3D ppc_create_page_sizes_prop(cpu, page_sizes_pr= op, + sizeof(page_sizes_pr= op)); if (page_sizes_prop_size) { _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", page_sizes_prop, page_sizes_prop_size))); diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e764f999c5..14c31f82fa 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -581,8 +581,8 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *f= dt, int offset, _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); } =20 - page_sizes_prop_size =3D ppc_create_page_sizes_prop(env, page_sizes_pr= op, - sizeof(page_sizes_prop)); + page_sizes_prop_size =3D ppc_create_page_sizes_prop(cpu, page_sizes_pr= op, + sizeof(page_sizes_pr= op)); if (page_sizes_prop_size) { _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", page_sizes_prop, page_sizes_prop_size))); diff --git a/include/hw/ppc/fdt.h b/include/hw/ppc/fdt.h index bd5b0a8c3d..a8cd85069f 100644 --- a/include/hw/ppc/fdt.h +++ b/include/hw/ppc/fdt.h @@ -23,7 +23,7 @@ } \ } while (0) =20 -size_t ppc_create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, +size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop, size_t maxsize); =20 #endif /* PPC_FDT_H */ --=20 2.14.3 From nobody Mon Apr 29 10:10:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522895019112646.2899592566326; Wed, 4 Apr 2018 19:23:39 -0700 (PDT) Received: from localhost ([::1]:48555 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uYo-0008Cg-IK for importer@patchew.org; Wed, 04 Apr 2018 22:23:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35199) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uQL-0001X4-7b for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f3uQJ-0000tW-GG for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:49 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:48193) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f3uQI-0000sD-UJ; Wed, 04 Apr 2018 22:14:47 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40GmcK3V2Jz9s2Y; Thu, 5 Apr 2018 12:14:40 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1522894481; bh=Oc11+mHydWV++yFz1KC/LIwT9w14MNm/XGsgxGz0KlM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Cz7p/AeJ6eeiNYNjbbzs6GDFgRH+hDmO37DaBv9bxwMuvIshCC/hyEvGz3ubr+06n MfgV+QNiZMFmHnATyg9cM2r4ZR9E/We4K7JKDfJY8O9H2ulaojwaanT4Pa7ephZ2Qw tHwu0pmckqNG4TPVrO8tWL5bb/VRhKY1RyFqCfRo= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org Date: Thu, 5 Apr 2018 12:14:28 +1000 Message-Id: <20180405021437.16761-5-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180405021437.16761-1-david@gibson.dropbear.id.au> References: <20180405021437.16761-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PATCH for-2.13 04/13] target/ppc: Avoid taking "env" parameter to mmu-hash64 functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bharata@linux.vnet.ibm.com, qemu-devel@nongnu.org, David Gibson , clg@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In most cases we prefer to pass a PowerPCCPU rather than the (embedded) CPUPPCState. For ppc_hash64_update_{rmls,vrma}() change to take "cpu" instead of "env". For ppc_hash64_set_{dsi,isi}() remove the redundant "env" parameter. In theory this makes more work for the functions, but since "cs", "cpu" and "env" are related by at most constant offsets, the compiler should be able to optimize out the difference at effectively zero cost. helper_*() functions are left alone - since they're more closely tied to the TCG generated code, passing "env" is still the standard there. While we're there, fix an incorrect indentation. Signed-off-by: David Gibson Reviewed-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/mmu-hash64.c | 35 +++++++++++++++++++---------------- target/ppc/mmu-hash64.h | 4 ++-- target/ppc/translate_init.c | 4 ++-- 3 files changed, 23 insertions(+), 20 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index c9b72b7429..a87fa7c83f 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -633,9 +633,9 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *c= pu, return 0; } =20 -static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env, - uint64_t error_code) +static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code) { + CPUPPCState *env =3D &POWERPC_CPU(cs)->env; bool vpm; =20 if (msr_ir) { @@ -659,9 +659,9 @@ static void ppc_hash64_set_isi(CPUState *cs, CPUPPCStat= e *env, env->error_code =3D error_code; } =20 -static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState *env, uint64_t da= r, - uint64_t dsisr) +static void ppc_hash64_set_dsi(CPUState *cs, uint64_t dar, uint64_t dsisr) { + CPUPPCState *env =3D &POWERPC_CPU(cs)->env; bool vpm; =20 if (msr_dr) { @@ -741,13 +741,13 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vadd= r eaddr, } else { /* The access failed, generate the approriate interrupt */ if (rwx =3D=3D 2) { - ppc_hash64_set_isi(cs, env, SRR1_PROTFAULT); + ppc_hash64_set_isi(cs, SRR1_PROTFAULT); } else { int dsisr =3D DSISR_PROTFAULT; if (rwx =3D=3D 1) { dsisr |=3D DSISR_ISSTORE; } - ppc_hash64_set_dsi(cs, env, eaddr, dsisr); + ppc_hash64_set_dsi(cs, eaddr, dsisr); } return 1; } @@ -783,7 +783,7 @@ skip_slb_search: =20 /* 3. Check for segment level no-execute violation */ if ((rwx =3D=3D 2) && (slb->vsid & SLB_VSID_N)) { - ppc_hash64_set_isi(cs, env, SRR1_NOEXEC_GUARD); + ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD); return 1; } =20 @@ -791,13 +791,13 @@ skip_slb_search: ptex =3D ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift); if (ptex =3D=3D -1) { if (rwx =3D=3D 2) { - ppc_hash64_set_isi(cs, env, SRR1_NOPTE); + ppc_hash64_set_isi(cs, SRR1_NOPTE); } else { int dsisr =3D DSISR_NOPTE; if (rwx =3D=3D 1) { dsisr |=3D DSISR_ISSTORE; } - ppc_hash64_set_dsi(cs, env, eaddr, dsisr); + ppc_hash64_set_dsi(cs, eaddr, dsisr); } return 1; } @@ -824,7 +824,7 @@ skip_slb_search: if (PAGE_EXEC & ~amr_prot) { srr1 |=3D SRR1_IAMR; /* Access violates virt pg class key = prot */ } - ppc_hash64_set_isi(cs, env, srr1); + ppc_hash64_set_isi(cs, srr1); } else { int dsisr =3D 0; if (need_prot[rwx] & ~pp_prot) { @@ -836,7 +836,7 @@ skip_slb_search: if (need_prot[rwx] & ~amr_prot) { dsisr |=3D DSISR_AMR; } - ppc_hash64_set_dsi(cs, env, eaddr, dsisr); + ppc_hash64_set_dsi(cs, eaddr, dsisr); } return 1; } @@ -942,8 +942,9 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_= ulong ptex, cpu->env.tlb_need_flush =3D TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLU= SH; } =20 -void ppc_hash64_update_rmls(CPUPPCState *env) +void ppc_hash64_update_rmls(PowerPCCPU *cpu) { + CPUPPCState *env =3D &cpu->env; uint64_t lpcr =3D env->spr[SPR_LPCR]; =20 /* @@ -976,8 +977,9 @@ void ppc_hash64_update_rmls(CPUPPCState *env) } } =20 -void ppc_hash64_update_vrma(CPUPPCState *env) +void ppc_hash64_update_vrma(PowerPCCPU *cpu) { + CPUPPCState *env =3D &cpu->env; const struct ppc_one_seg_page_size *sps =3D NULL; target_ulong esid, vsid, lpcr; ppc_slb_t *slb =3D &env->vrma_slb; @@ -1002,7 +1004,7 @@ void ppc_hash64_update_vrma(CPUPPCState *env) vsid |=3D (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP); esid =3D SLB_ESID_V; =20 - for (i =3D 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { + for (i =3D 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { const struct ppc_one_seg_page_size *sps1 =3D &env->sps.sps[i]; =20 if (!sps1->page_shift) { @@ -1028,6 +1030,7 @@ void ppc_hash64_update_vrma(CPUPPCState *env) =20 void helper_store_lpcr(CPUPPCState *env, target_ulong val) { + PowerPCCPU *cpu =3D ppc_env_get_cpu(env); uint64_t lpcr =3D 0; =20 /* Filter out bits */ @@ -1089,6 +1092,6 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong= val) ; } env->spr[SPR_LPCR] =3D lpcr; - ppc_hash64_update_rmls(env); - ppc_hash64_update_vrma(env); + ppc_hash64_update_rmls(cpu); + ppc_hash64_update_vrma(cpu); } diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index d297b97d37..95a8c330d6 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -17,8 +17,8 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong pte0, target_ulong pte1); unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, uint64_t pte0, uint64_t pte1); -void ppc_hash64_update_vrma(CPUPPCState *env); -void ppc_hash64_update_rmls(CPUPPCState *env); +void ppc_hash64_update_vrma(PowerPCCPU *cpu); +void ppc_hash64_update_rmls(PowerPCCPU *cpu); #endif =20 /* diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 2ae718242a..29bd6f3654 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8975,8 +8975,8 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHype= rvisor *vhyp) env->spr[SPR_AMOR] =3D amor->default_value =3D 0xffffffffffffffffull; =20 /* Update some env bits based on new LPCR value */ - ppc_hash64_update_rmls(env); - ppc_hash64_update_vrma(env); + ppc_hash64_update_rmls(cpu); + ppc_hash64_update_vrma(cpu); =20 /* Tell KVM that we're in PAPR mode */ if (kvm_enabled()) { --=20 2.14.3 From nobody Mon Apr 29 10:10:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522895192130740.2212605565421; Wed, 4 Apr 2018 19:26:32 -0700 (PDT) Received: from localhost ([::1]:48581 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3ubb-0002V9-OA for importer@patchew.org; Wed, 04 Apr 2018 22:26:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35222) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uQL-0001Xl-Re for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f3uQJ-0000uI-Uy for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:49 -0400 Received: from ozlabs.org ([103.22.144.67]:55263) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f3uQJ-0000sK-A0; Wed, 04 Apr 2018 22:14:47 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40GmcK2QQ2z9s35; Thu, 5 Apr 2018 12:14:40 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1522894481; bh=+PCKl8tl8/OBKDrVWNJRQ5OyfhvYdu6t4APLsMKIfmY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IlCdUVZr3Wyj7aZozQgYpQrkys6ufQQEh1n22eVcTKaHELfNWvteADVh3+WPjoCa0 L5ls2deNel9vHbh8DeG1ZBNdi3bfVINVWOI7F0qbW7221vBKsIYY2p1Y2e3Tc4Ysph e78fiqRnHqz18o2om/OGqbVY8v2G5VnFLVbPvbNM= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org Date: Thu, 5 Apr 2018 12:14:29 +1000 Message-Id: <20180405021437.16761-6-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180405021437.16761-1-david@gibson.dropbear.id.au> References: <20180405021437.16761-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PATCH for-2.13 05/13] target/ppc: Remove fallback 64k pagesize information X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bharata@linux.vnet.ibm.com, qemu-devel@nongnu.org, David Gibson , clg@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" CPU definitions for cpus with the 64-bit hash MMU can include a table of available pagesizes. If this isn't supplied ppc_cpu_instance_init() will fill it in a fallback table based on the POWERPC_MMU_64K bit in mmu_model. However, it turns out all the cpus which support 64K pages already include an explicit table of page sizes, so there's no point to the fallback table including 64k pages. That removes the only place which tests POWERPC_MMU_64K, so we can remove it. Which in turn allows some logic to be removed from kvm_fixup_page_sizes(). Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- target/ppc/cpu-qom.h | 4 ---- target/ppc/kvm.c | 7 ------- target/ppc/translate_init.c | 20 ++------------------ 3 files changed, 2 insertions(+), 29 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index deaa46a14b..9bbb05cf62 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -70,7 +70,6 @@ enum powerpc_mmu_t { #define POWERPC_MMU_64 0x00010000 #define POWERPC_MMU_1TSEG 0x00020000 #define POWERPC_MMU_AMR 0x00040000 -#define POWERPC_MMU_64K 0x00080000 #define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */ /* 64 bits PowerPC MMU */ POWERPC_MMU_64B =3D POWERPC_MMU_64 | 0x00000001, @@ -78,15 +77,12 @@ enum powerpc_mmu_t { POWERPC_MMU_2_03 =3D POWERPC_MMU_64 | 0x00000002, /* Architecture 2.06 variant */ POWERPC_MMU_2_06 =3D POWERPC_MMU_64 | POWERPC_MMU_1TSEG - | POWERPC_MMU_64K | POWERPC_MMU_AMR | 0x00000003, /* Architecture 2.07 variant */ POWERPC_MMU_2_07 =3D POWERPC_MMU_64 | POWERPC_MMU_1TSEG - | POWERPC_MMU_64K | POWERPC_MMU_AMR | 0x00000004, /* Architecture 3.00 variant */ POWERPC_MMU_3_00 =3D POWERPC_MMU_64 | POWERPC_MMU_1TSEG - | POWERPC_MMU_64K | POWERPC_MMU_AMR | POWERPC_MMU_V3 | 0x00000005, }; diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 79a436a384..6160356a4a 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -425,7 +425,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu) static bool has_smmu_info; CPUPPCState *env =3D &cpu->env; int iq, ik, jq, jk; - bool has_64k_pages =3D false; =20 /* We only handle page sizes for 64-bit server guests for now */ if (!(env->mmu_model & POWERPC_MMU_64)) { @@ -471,9 +470,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu) ksps->enc[jk].page_shift)) { continue; } - if (ksps->enc[jk].page_shift =3D=3D 16) { - has_64k_pages =3D true; - } qsps->enc[jq].page_shift =3D ksps->enc[jk].page_shift; qsps->enc[jq].pte_enc =3D ksps->enc[jk].pte_enc; if (++jq >=3D PPC_PAGE_SIZES_MAX_SZ) { @@ -488,9 +484,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu) if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) { env->mmu_model &=3D ~POWERPC_MMU_1TSEG; } - if (!has_64k_pages) { - env->mmu_model &=3D ~POWERPC_MMU_64K; - } } =20 bool kvmppc_is_mem_backend_page_size_ok(const char *obj_path) diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 29bd6f3654..99be6fcd68 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -10469,7 +10469,7 @@ static void ppc_cpu_instance_init(Object *obj) env->sps =3D *pcc->sps; } else if (env->mmu_model & POWERPC_MMU_64) { /* Use default sets of page sizes. We don't support MPSS */ - static const struct ppc_segment_page_sizes defsps_4k =3D { + static const struct ppc_segment_page_sizes defsps =3D { .sps =3D { { .page_shift =3D 12, /* 4K */ .slb_enc =3D 0, @@ -10481,23 +10481,7 @@ static void ppc_cpu_instance_init(Object *obj) }, }, }; - static const struct ppc_segment_page_sizes defsps_64k =3D { - .sps =3D { - { .page_shift =3D 12, /* 4K */ - .slb_enc =3D 0, - .enc =3D { { .page_shift =3D 12, .pte_enc =3D 0 } } - }, - { .page_shift =3D 16, /* 64K */ - .slb_enc =3D 0x110, - .enc =3D { { .page_shift =3D 16, .pte_enc =3D 1 } } - }, - { .page_shift =3D 24, /* 16M */ - .slb_enc =3D 0x100, - .enc =3D { { .page_shift =3D 24, .pte_enc =3D 0 } } - }, - }, - }; - env->sps =3D (env->mmu_model & POWERPC_MMU_64K) ? defsps_64k : def= sps_4k; + env->sps =3D defsps; } #endif /* defined(TARGET_PPC64) */ } --=20 2.14.3 From nobody Mon Apr 29 10:10:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522894640898802.7766080077341; Wed, 4 Apr 2018 19:17:20 -0700 (PDT) Received: from localhost ([::1]:48444 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uSc-0002rv-81 for importer@patchew.org; Wed, 04 Apr 2018 22:17:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35137) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uQH-0001UD-TE for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f3uQG-0000rg-OA for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:45 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:47323) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f3uQG-0000mz-5D; Wed, 04 Apr 2018 22:14:44 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40GmcK1XB7z9s25; Thu, 5 Apr 2018 12:14:41 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1522894481; bh=xhDy7aonv/WG8FC2brwH1sg9nw3vR0bAPDSNVzL52xQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PNzk4e/Z0B7sNiqR3k9TeXDLKboX2nQ2d70Dk9dwsAtVYZFoZYNKKvtsnx63KCv0s b8w/oTMO5AbIlkXJcjI7tjIUYI/6qECzrSWoFkZ/mtKSXohaUAGXcIrynEJL1TVJUt kqcgpN7aPOGfPnGcLmnT1crEueRpP41iSHbtvDMY= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org Date: Thu, 5 Apr 2018 12:14:30 +1000 Message-Id: <20180405021437.16761-7-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180405021437.16761-1-david@gibson.dropbear.id.au> References: <20180405021437.16761-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PATCH for-2.13 06/13] target/ppc: Move page size setup to helper function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bharata@linux.vnet.ibm.com, qemu-devel@nongnu.org, David Gibson , clg@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Initialization of the env->sps structure at the end of instance_init is specific to the 64-bit hash MMU, so move the code into a helper function in mmu-hash64.c. We also create a corresponding function to be called at finalize time - it's empty for now, but we'll need it shortly. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- target/ppc/mmu-hash64.c | 29 +++++++++++++++++++++++++++++ target/ppc/mmu-hash64.h | 11 +++++++++++ target/ppc/translate_init.c | 29 +++++++++-------------------- 3 files changed, 49 insertions(+), 20 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index a87fa7c83f..4cb7d1cf07 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1095,3 +1095,32 @@ void helper_store_lpcr(CPUPPCState *env, target_ulon= g val) ppc_hash64_update_rmls(cpu); ppc_hash64_update_vrma(cpu); } + +void ppc_hash64_init(PowerPCCPU *cpu) +{ + CPUPPCState *env =3D &cpu->env; + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); + + if (pcc->sps) { + env->sps =3D *pcc->sps; + } else if (env->mmu_model & POWERPC_MMU_64) { + /* Use default sets of page sizes. We don't support MPSS */ + static const struct ppc_segment_page_sizes defsps =3D { + .sps =3D { + { .page_shift =3D 12, /* 4K */ + .slb_enc =3D 0, + .enc =3D { { .page_shift =3D 12, .pte_enc =3D 0 } } + }, + { .page_shift =3D 24, /* 16M */ + .slb_enc =3D 0x100, + .enc =3D { { .page_shift =3D 24, .pte_enc =3D 0 } } + }, + }, + }; + env->sps =3D defsps; + } +} + +void ppc_hash64_finalize(PowerPCCPU *cpu) +{ +} diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index 95a8c330d6..074ded4c27 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -19,6 +19,8 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, uint64_t pte0, uint64_t pte1); void ppc_hash64_update_vrma(PowerPCCPU *cpu); void ppc_hash64_update_rmls(PowerPCCPU *cpu); +void ppc_hash64_init(PowerPCCPU *cpu); +void ppc_hash64_finalize(PowerPCCPU *cpu); #endif =20 /* @@ -136,4 +138,13 @@ static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cp= u, =20 #endif /* CONFIG_USER_ONLY */ =20 +#if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64) +static inline void ppc_hash64_init(PowerPCCPU *cpu) +{ +} +static inline void ppc_hash64_finalize(PowerPCCPU *cpu) +{ +} +#endif + #endif /* MMU_HASH64_H */ diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 99be6fcd68..aa63a5dcb3 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -10464,26 +10464,14 @@ static void ppc_cpu_instance_init(Object *obj) env->has_hv_mode =3D !!(env->msr_mask & MSR_HVB); #endif =20 -#if defined(TARGET_PPC64) - if (pcc->sps) { - env->sps =3D *pcc->sps; - } else if (env->mmu_model & POWERPC_MMU_64) { - /* Use default sets of page sizes. We don't support MPSS */ - static const struct ppc_segment_page_sizes defsps =3D { - .sps =3D { - { .page_shift =3D 12, /* 4K */ - .slb_enc =3D 0, - .enc =3D { { .page_shift =3D 12, .pte_enc =3D 0 } } - }, - { .page_shift =3D 24, /* 16M */ - .slb_enc =3D 0x100, - .enc =3D { { .page_shift =3D 24, .pte_enc =3D 0 } } - }, - }, - }; - env->sps =3D defsps; - } -#endif /* defined(TARGET_PPC64) */ + ppc_hash64_init(cpu); +} + +static void ppc_cpu_instance_finalize(Object *obj) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(obj); + + ppc_hash64_finalize(cpu); } =20 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) @@ -10601,6 +10589,7 @@ static const TypeInfo ppc_cpu_type_info =3D { .parent =3D TYPE_CPU, .instance_size =3D sizeof(PowerPCCPU), .instance_init =3D ppc_cpu_instance_init, + .instance_finalize =3D ppc_cpu_instance_finalize, .abstract =3D true, .class_size =3D sizeof(PowerPCCPUClass), .class_init =3D ppc_cpu_class_init, --=20 2.14.3 From nobody Mon Apr 29 10:10:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522895053322727.2571028678532; Wed, 4 Apr 2018 19:24:13 -0700 (PDT) Received: from localhost ([::1]:48560 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uZP-0000G6-NC for importer@patchew.org; Wed, 04 Apr 2018 22:24:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35262) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uQN-0001Yv-1O for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f3uQJ-0000tz-T2 for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:50 -0400 Received: from ozlabs.org ([103.22.144.67]:49341) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f3uQJ-0000sR-7C; Wed, 04 Apr 2018 22:14:47 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40GmcK5Zyhz9s3p; Thu, 5 Apr 2018 12:14:41 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1522894481; bh=a81OkRE3peVsC/2U1aIN61tLU2B1gNZGg1F8D/edbSY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QsTScD21msV66St0xVHFhW41qKqcvFPVmBShTIuOaqRzjhkBrONnPqA9waIkgWJsf 74AlAP/Zg2w4QbPHoK8xT8Ga7WsTYJ9CZZ4/xNPOxtg9iIApWkizL7DYM/EzZMNmjz osTitj5QvwmH2OCczN7EfY8WvL+OdQwyAUbsTRcg= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org Date: Thu, 5 Apr 2018 12:14:31 +1000 Message-Id: <20180405021437.16761-8-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180405021437.16761-1-david@gibson.dropbear.id.au> References: <20180405021437.16761-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PATCH for-2.13 07/13] target/ppc: Split page size information into a separate allocation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bharata@linux.vnet.ibm.com, qemu-devel@nongnu.org, David Gibson , clg@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" env->sps contains page size encoding information as an embedded structure. Since this information is specific to 64-bit hash MMUs, split it out into a separately allocated structure, to reduce the basic env size for other cpus. Along the way we make a few other cleanups: * Rename to PPCHash64Options which is more in line with qemu name conventions, and reflects that we're going to merge some more hash64 mmu specific details in there in future. Also rename its substructures to match qemu conventions. * Move structure definitions to the mmu-hash64.[ch] files. Signed-off-by: David Gibson Reviewed-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/fdt.c | 4 +-- target/ppc/cpu-qom.h | 4 +-- target/ppc/cpu.h | 26 +++---------------- target/ppc/kvm.c | 4 +-- target/ppc/mmu-hash64.c | 61 +++++++++++++++++++++++++++++++++--------= ---- target/ppc/mmu-hash64.h | 22 ++++++++++++++++ target/ppc/translate_init.c | 36 +++----------------------- 7 files changed, 80 insertions(+), 77 deletions(-) diff --git a/hw/ppc/fdt.c b/hw/ppc/fdt.c index 2721603ffa..0828ad7254 100644 --- a/hw/ppc/fdt.c +++ b/hw/ppc/fdt.c @@ -9,6 +9,7 @@ =20 #include "qemu/osdep.h" #include "target/ppc/cpu.h" +#include "target/ppc/mmu-hash64.h" =20 #include "hw/ppc/fdt.h" =20 @@ -16,13 +17,12 @@ size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop, size_t maxsize) { - CPUPPCState *env =3D &cpu->env; size_t maxcells =3D maxsize / sizeof(uint32_t); int i, j, count; uint32_t *p =3D prop; =20 for (i =3D 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { - struct ppc_one_seg_page_size *sps =3D &env->sps.sps[i]; + PPCHash64SegmentPageSizes *sps =3D &cpu->hash64_opts->sps[i]; =20 if (!sps->page_shift) { break; diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 9bbb05cf62..3e5ef7375f 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -160,7 +160,7 @@ enum powerpc_input_t { PPC_FLAGS_INPUT_RCPU, }; =20 -struct ppc_segment_page_sizes; +typedef struct PPCHash64Options PPCHash64Options; =20 /** * PowerPCCPUClass: @@ -194,7 +194,7 @@ typedef struct PowerPCCPUClass { uint32_t flags; int bfd_mach; uint32_t l1_dcache_size, l1_icache_size; - const struct ppc_segment_page_sizes *sps; + const PPCHash64Options *hash64_opts; struct ppc_radix_page_info *radix_page_info; void (*init_proc)(CPUPPCState *env); int (*check_pow)(CPUPPCState *env); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index c621a6bd5e..1c5c33ca11 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -327,11 +327,13 @@ union ppc_tlb_t { #define TLB_MAS 3 #endif =20 +typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes; + typedef struct ppc_slb_t ppc_slb_t; struct ppc_slb_t { uint64_t esid; uint64_t vsid; - const struct ppc_one_seg_page_size *sps; + const PPCHash64SegmentPageSizes *sps; }; =20 #define MAX_SLB_ENTRIES 64 @@ -948,28 +950,8 @@ enum { =20 #define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63) =20 -/*************************************************************************= ****/ -/* Segment page size information, used by recent hash MMUs - * The format of this structure mirrors kvm_ppc_smmu_info - */ - #define PPC_PAGE_SIZES_MAX_SZ 8 =20 -struct ppc_one_page_size { - uint32_t page_shift; /* Page shift (or 0) */ - uint32_t pte_enc; /* Encoding in the HPTE (>>12) */ -}; - -struct ppc_one_seg_page_size { - uint32_t page_shift; /* Base page shift of segment (or 0) */ - uint32_t slb_enc; /* SLB encoding for BookS */ - struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ]; -}; - -struct ppc_segment_page_sizes { - struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ]; -}; - struct ppc_radix_page_info { uint32_t count; uint32_t entries[PPC_PAGE_SIZES_MAX_SZ]; @@ -1106,7 +1088,6 @@ struct CPUPPCState { uint64_t insns_flags; uint64_t insns_flags2; #if defined(TARGET_PPC64) - struct ppc_segment_page_sizes sps; ppc_slb_t vrma_slb; target_ulong rmls; bool ci_large_pages; @@ -1227,6 +1208,7 @@ struct PowerPCCPU { PPCVirtualHypervisor *vhyp; Object *intc; int32_t node_id; /* NUMA node this CPU belongs to */ + PPCHash64Options *hash64_opts; =20 /* Fields related to migration compatibility hacks */ bool pre_2_8_migration; diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 6160356a4a..bc6d0a8314 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -442,7 +442,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu) } =20 /* Convert to QEMU form */ - memset(&env->sps, 0, sizeof(env->sps)); + memset(cpu->hash64_opts, 0, sizeof(*cpu->hash64_opts)); =20 /* If we have HV KVM, we need to forbid CI large pages if our * host page size is smaller than 64K. @@ -456,7 +456,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu) * the selected CPU has with the capabilities that KVM supports. */ for (ik =3D iq =3D 0; ik < KVM_PPC_PAGE_SIZES_MAX_SZ; ik++) { - struct ppc_one_seg_page_size *qsps =3D &env->sps.sps[iq]; + PPCHash64SegmentPageSizes *qsps =3D &cpu->hash64_opts->sps[iq]; struct kvm_ppc_one_seg_page_size *ksps =3D &smmu_info.sps[ik]; =20 if (!kvm_valid_page_size(smmu_info.flags, max_cpu_page_size, diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 4cb7d1cf07..6758afd9de 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -148,7 +148,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, { CPUPPCState *env =3D &cpu->env; ppc_slb_t *slb =3D &env->slb[slot]; - const struct ppc_one_seg_page_size *sps =3D NULL; + const PPCHash64SegmentPageSizes *sps =3D NULL; int i; =20 if (slot >=3D env->slb_nr) { @@ -165,7 +165,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, } =20 for (i =3D 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { - const struct ppc_one_seg_page_size *sps1 =3D &env->sps.sps[i]; + const PPCHash64SegmentPageSizes *sps1 =3D &cpu->hash64_opts->sps[i= ]; =20 if (!sps1->page_shift) { break; @@ -451,8 +451,8 @@ void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_= hash_pte64_t *hptes, false, n * HASH_PTE_SIZE_64); } =20 -static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps, - uint64_t pte0, uint64_t pte1) +static unsigned hpte_page_shift(const PPCHash64SegmentPageSizes *sps, + uint64_t pte0, uint64_t pte1) { int i; =20 @@ -466,7 +466,7 @@ static unsigned hpte_page_shift(const struct ppc_one_se= g_page_size *sps, } =20 for (i =3D 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { - const struct ppc_one_page_size *ps =3D &sps->enc[i]; + const PPCHash64PageSize *ps =3D &sps->enc[i]; uint64_t mask; =20 if (!ps->page_shift) { @@ -489,7 +489,7 @@ static unsigned hpte_page_shift(const struct ppc_one_se= g_page_size *sps, } =20 static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash, - const struct ppc_one_seg_page_size *s= ps, + const PPCHash64SegmentPageSizes *sps, target_ulong ptem, ppc_hash_pte64_t *pte, unsigned *pshi= ft) { @@ -543,7 +543,7 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu, CPUPPCState *env =3D &cpu->env; hwaddr hash, ptex; uint64_t vsid, epnmask, epn, ptem; - const struct ppc_one_seg_page_size *sps =3D slb->sps; + const PPCHash64SegmentPageSizes *sps =3D slb->sps; =20 /* The SLB store path should prevent any bad page size encodings * getting in there, so: */ @@ -552,7 +552,7 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu, /* If ISL is set in LPCR we need to clamp the page size to 4K */ if (env->spr[SPR_LPCR] & LPCR_ISL) { /* We assume that when using TCG, 4k is first entry of SPS */ - sps =3D &env->sps.sps[0]; + sps =3D &cpu->hash64_opts->sps[0]; assert(sps->page_shift =3D=3D 12); } =20 @@ -605,7 +605,6 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu, unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, uint64_t pte0, uint64_t pte1) { - CPUPPCState *env =3D &cpu->env; int i; =20 if (!(pte0 & HPTE64_V_LARGE)) { @@ -617,7 +616,7 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *c= pu, * this gives an unambiguous result. */ for (i =3D 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { - const struct ppc_one_seg_page_size *sps =3D &env->sps.sps[i]; + const PPCHash64SegmentPageSizes *sps =3D &cpu->hash64_opts->sps[i]; unsigned shift; =20 if (!sps->page_shift) { @@ -980,7 +979,7 @@ void ppc_hash64_update_rmls(PowerPCCPU *cpu) void ppc_hash64_update_vrma(PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; - const struct ppc_one_seg_page_size *sps =3D NULL; + const PPCHash64SegmentPageSizes *sps =3D NULL; target_ulong esid, vsid, lpcr; ppc_slb_t *slb =3D &env->vrma_slb; uint32_t vrmasd; @@ -1005,7 +1004,7 @@ void ppc_hash64_update_vrma(PowerPCCPU *cpu) esid =3D SLB_ESID_V; =20 for (i =3D 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { - const struct ppc_one_seg_page_size *sps1 =3D &env->sps.sps[i]; + const PPCHash64SegmentPageSizes *sps1 =3D &cpu->hash64_opts->sps[i= ]; =20 if (!sps1->page_shift) { break; @@ -1101,11 +1100,12 @@ void ppc_hash64_init(PowerPCCPU *cpu) CPUPPCState *env =3D &cpu->env; PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); =20 - if (pcc->sps) { - env->sps =3D *pcc->sps; + if (pcc->hash64_opts) { + cpu->hash64_opts =3D g_memdup(pcc->hash64_opts, + sizeof(*cpu->hash64_opts)); } else if (env->mmu_model & POWERPC_MMU_64) { /* Use default sets of page sizes. We don't support MPSS */ - static const struct ppc_segment_page_sizes defsps =3D { + static const PPCHash64Options defopts =3D { .sps =3D { { .page_shift =3D 12, /* 4K */ .slb_enc =3D 0, @@ -1117,10 +1117,39 @@ void ppc_hash64_init(PowerPCCPU *cpu) }, }, }; - env->sps =3D defsps; + cpu->hash64_opts =3D g_memdup(&defopts, sizeof(*cpu->hash64_opts)); } } =20 void ppc_hash64_finalize(PowerPCCPU *cpu) { + g_free(cpu->hash64_opts); } + +const PPCHash64Options ppc_hash64_opts_POWER7 =3D { + .sps =3D { + { + .page_shift =3D 12, /* 4K */ + .slb_enc =3D 0, + .enc =3D { { .page_shift =3D 12, .pte_enc =3D 0 }, + { .page_shift =3D 16, .pte_enc =3D 0x7 }, + { .page_shift =3D 24, .pte_enc =3D 0x38 }, }, + }, + { + .page_shift =3D 16, /* 64K */ + .slb_enc =3D SLB_VSID_64K, + .enc =3D { { .page_shift =3D 16, .pte_enc =3D 0x1 }, + { .page_shift =3D 24, .pte_enc =3D 0x8 }, }, + }, + { + .page_shift =3D 24, /* 16M */ + .slb_enc =3D SLB_VSID_16M, + .enc =3D { { .page_shift =3D 24, .pte_enc =3D 0 }, }, + }, + { + .page_shift =3D 34, /* 16G */ + .slb_enc =3D SLB_VSID_16G, + .enc =3D { { .page_shift =3D 34, .pte_enc =3D 0x3 }, }, + }, + } +}; diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index 074ded4c27..957bd68e33 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -136,6 +136,28 @@ static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cp= u, return ldq_p(&(hptes[i].pte1)); } =20 +/* + * MMU Options + */ + +struct PPCHash64PageSize { + uint32_t page_shift; /* Page shift (or 0) */ + uint32_t pte_enc; /* Encoding in the HPTE (>>12) */ +}; +typedef struct PPCHash64PageSize PPCHash64PageSize; + +struct PPCHash64SegmentPageSizes { + uint32_t page_shift; /* Base page shift of segment (or 0) */ + uint32_t slb_enc; /* SLB encoding for BookS */ + PPCHash64PageSize enc[PPC_PAGE_SIZES_MAX_SZ]; +}; + +struct PPCHash64Options { + PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ]; +}; + +extern const PPCHash64Options ppc_hash64_opts_POWER7; + #endif /* CONFIG_USER_ONLY */ =20 #if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64) diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index aa63a5dcb3..040d6fbac3 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8368,36 +8368,6 @@ static Property powerpc_servercpu_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -#ifdef CONFIG_SOFTMMU -static const struct ppc_segment_page_sizes POWER7_POWER8_sps =3D { - .sps =3D { - { - .page_shift =3D 12, /* 4K */ - .slb_enc =3D 0, - .enc =3D { { .page_shift =3D 12, .pte_enc =3D 0 }, - { .page_shift =3D 16, .pte_enc =3D 0x7 }, - { .page_shift =3D 24, .pte_enc =3D 0x38 }, }, - }, - { - .page_shift =3D 16, /* 64K */ - .slb_enc =3D SLB_VSID_64K, - .enc =3D { { .page_shift =3D 16, .pte_enc =3D 0x1 }, - { .page_shift =3D 24, .pte_enc =3D 0x8 }, }, - }, - { - .page_shift =3D 24, /* 16M */ - .slb_enc =3D SLB_VSID_16M, - .enc =3D { { .page_shift =3D 24, .pte_enc =3D 0 }, }, - }, - { - .page_shift =3D 34, /* 16G */ - .slb_enc =3D SLB_VSID_16G, - .enc =3D { { .page_shift =3D 34, .pte_enc =3D 0x3 }, }, - }, - } -}; -#endif /* CONFIG_SOFTMMU */ - static void init_proc_POWER7(CPUPPCState *env) { /* Common Registers */ @@ -8526,7 +8496,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->mmu_model =3D POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; - pcc->sps =3D &POWER7_POWER8_sps; + pcc->hash64_opts =3D &ppc_hash64_opts_POWER7; #endif pcc->excp_model =3D POWERPC_EXCP_POWER7; pcc->bus_model =3D PPC_FLAGS_INPUT_POWER7; @@ -8698,7 +8668,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->mmu_model =3D POWERPC_MMU_2_07; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; - pcc->sps =3D &POWER7_POWER8_sps; + pcc->hash64_opts =3D &ppc_hash64_opts_POWER7; #endif pcc->excp_model =3D POWERPC_EXCP_POWER8; pcc->bus_model =3D PPC_FLAGS_INPUT_POWER7; @@ -8893,7 +8863,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault =3D ppc64_v3_handle_mmu_fault; /* segment page size remain the same */ - pcc->sps =3D &POWER7_POWER8_sps; + pcc->hash64_opts =3D &ppc_hash64_opts_POWER7; pcc->radix_page_info =3D &POWER9_radix_page_info; #endif pcc->excp_model =3D POWERPC_EXCP_POWER8; --=20 2.14.3 From nobody Mon Apr 29 10:10:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522894833957121.88937327092594; Wed, 4 Apr 2018 19:20:33 -0700 (PDT) Received: from localhost ([::1]:48462 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uVr-0005ab-5v for importer@patchew.org; Wed, 04 Apr 2018 22:20:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35215) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uQL-0001Xb-Ja for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f3uQK-0000uO-04 for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:49 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:46053) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f3uQJ-0000sb-E6; Wed, 04 Apr 2018 22:14:47 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40GmcL0Tb4z9s3c; Thu, 5 Apr 2018 12:14:41 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1522894482; bh=kLD5mg3EX3/VQhyKaZLPnxprNWAaAJh76U/Oxb3qEIA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LEEWwga8DRFBPf2YvcZOsuiqUTyIeKG2S7ER15i2ZRu5Qs/VCHUxyTLIz1eTfi08A Pnv3ObAErcUly9nI0qN9ALuoQcQT5eH0mI/4vOPyPzNplvUm3ItP/7NQK004mtFUQj KqhjisYOdQriXgNP5ltLtOveriAc6TFxqh6AYS54= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org Date: Thu, 5 Apr 2018 12:14:32 +1000 Message-Id: <20180405021437.16761-9-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180405021437.16761-1-david@gibson.dropbear.id.au> References: <20180405021437.16761-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PATCH for-2.13 08/13] target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bharata@linux.vnet.ibm.com, qemu-devel@nongnu.org, David Gibson , clg@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Currently some cpus set the hash64_opts field in the class structure, with specific details of their variant of the 64-bit hash mmu. For the remaining cpus with that mmu, ppc_hash64_realize() fills in defaults. But there are only a couple of cpus that use those fallbacks, so just have them to set the has64_opts field instead, simplifying the logic. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- target/ppc/mmu-hash64.c | 36 ++++++++++++++++++------------------ target/ppc/mmu-hash64.h | 1 + target/ppc/translate_init.c | 2 ++ 3 files changed, 21 insertions(+), 18 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 6758afd9de..2809c31170 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1100,25 +1100,12 @@ void ppc_hash64_init(PowerPCCPU *cpu) CPUPPCState *env =3D &cpu->env; PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); =20 - if (pcc->hash64_opts) { - cpu->hash64_opts =3D g_memdup(pcc->hash64_opts, - sizeof(*cpu->hash64_opts)); - } else if (env->mmu_model & POWERPC_MMU_64) { - /* Use default sets of page sizes. We don't support MPSS */ - static const PPCHash64Options defopts =3D { - .sps =3D { - { .page_shift =3D 12, /* 4K */ - .slb_enc =3D 0, - .enc =3D { { .page_shift =3D 12, .pte_enc =3D 0 } } - }, - { .page_shift =3D 24, /* 16M */ - .slb_enc =3D 0x100, - .enc =3D { { .page_shift =3D 24, .pte_enc =3D 0 } } - }, - }, - }; - cpu->hash64_opts =3D g_memdup(&defopts, sizeof(*cpu->hash64_opts)); + if (!pcc->hash64_opts) { + assert(!(env->mmu_model & POWERPC_MMU_64)); + return; } + + cpu->hash64_opts =3D g_memdup(pcc->hash64_opts, sizeof(*cpu->hash64_op= ts)); } =20 void ppc_hash64_finalize(PowerPCCPU *cpu) @@ -1126,6 +1113,19 @@ void ppc_hash64_finalize(PowerPCCPU *cpu) g_free(cpu->hash64_opts); } =20 +const PPCHash64Options ppc_hash64_opts_basic =3D { + .sps =3D { + { .page_shift =3D 12, /* 4K */ + .slb_enc =3D 0, + .enc =3D { { .page_shift =3D 12, .pte_enc =3D 0 } } + }, + { .page_shift =3D 24, /* 16M */ + .slb_enc =3D 0x100, + .enc =3D { { .page_shift =3D 24, .pte_enc =3D 0 } } + }, + }, +}; + const PPCHash64Options ppc_hash64_opts_POWER7 =3D { .sps =3D { { diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index 957bd68e33..341c1524c2 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -156,6 +156,7 @@ struct PPCHash64Options { PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ]; }; =20 +extern const PPCHash64Options ppc_hash64_opts_basic; extern const PPCHash64Options ppc_hash64_opts_POWER7; =20 #endif /* CONFIG_USER_ONLY */ diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 040d6fbac3..ae005b2a54 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8242,6 +8242,7 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data) pcc->mmu_model =3D POWERPC_MMU_64B; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; + pcc->hash64_opts =3D &ppc_hash64_opts_basic; #endif pcc->excp_model =3D POWERPC_EXCP_970; pcc->bus_model =3D PPC_FLAGS_INPUT_970; @@ -8319,6 +8320,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) pcc->mmu_model =3D POWERPC_MMU_2_03; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; + pcc->hash64_opts =3D &ppc_hash64_opts_basic; #endif pcc->excp_model =3D POWERPC_EXCP_970; pcc->bus_model =3D PPC_FLAGS_INPUT_970; --=20 2.14.3 From nobody Mon Apr 29 10:10:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522895376696134.76116490880975; Wed, 4 Apr 2018 19:29:36 -0700 (PDT) Received: from localhost ([::1]:48689 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3ueV-00057q-FN for importer@patchew.org; Wed, 04 Apr 2018 22:29:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35226) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uQM-0001Xv-2I for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f3uQJ-0000uD-UZ for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:50 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:41111) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f3uQJ-0000sP-Bi; Wed, 04 Apr 2018 22:14:47 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40GmcK6J5Jz9s3M; Thu, 5 Apr 2018 12:14:41 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1522894481; bh=t9ElQVZacUjSOCBeokLj/dxt0nZbE07yQhJRgnfGwow=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lDLrE1IwnbnR24BVYGi+jft0xuIUIJYEZ6dX9lKm6yCcfNDJAH+4fPMzKkgpQ4nrE 1pkZPXjh3plXul9I+Nm4UllViw1Cn/QjLf2tYs9vhQYjvmYAy1qnERBgz0K91devg3 56LWi8q1VIYk+dbk6C7VMvP4Ox2pYRyzDQBTb4+c= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org Date: Thu, 5 Apr 2018 12:14:33 +1000 Message-Id: <20180405021437.16761-10-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180405021437.16761-1-david@gibson.dropbear.id.au> References: <20180405021437.16761-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PATCH for-2.13 09/13] target/ppc: Move 1T segment and AMR options to PPCHash64Options X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bharata@linux.vnet.ibm.com, qemu-devel@nongnu.org, David Gibson , clg@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Currently env->mmu_model is a bit of an unholy mess of an enum of distinct MMU types, with various flag bits as well. This makes which bits of the field should be compared pretty confusing. Make a start on cleaning that up by moving two of the flags bits - POWERPC_MMU_1TSEG and POWERPC_MMU_AMR - which are specific to the 64-bit hash MMU into a new flags field in PPCHash64Options structure. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- hw/ppc/pnv.c | 3 ++- hw/ppc/spapr.c | 2 +- target/ppc/cpu-qom.h | 11 +++-------- target/ppc/kvm.c | 4 ++-- target/ppc/mmu-hash64.c | 6 ++++-- target/ppc/mmu-hash64.h | 8 ++++++++ 6 files changed, 20 insertions(+), 14 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 5a79b24828..5905be3f71 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -36,6 +36,7 @@ #include "monitor/monitor.h" #include "hw/intc/intc.h" #include "hw/ipmi/ipmi.h" +#include "target/ppc/mmu-hash64.h" =20 #include "hw/ppc/xics.h" #include "hw/ppc/pnv_xscom.h" @@ -187,7 +188,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, voi= d *fdt) _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); } =20 - if (env->mmu_model & POWERPC_MMU_1TSEG) { + if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", segs, sizeof(segs)))); } diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 14c31f82fa..f86cb09080 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -557,7 +557,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *f= dt, int offset, _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); } =20 - if (env->mmu_model & POWERPC_MMU_1TSEG) { + if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", segs, sizeof(segs)))); } diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 3e5ef7375f..2bd58b2a84 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -68,22 +68,17 @@ enum powerpc_mmu_t { /* PowerPC 601 MMU model (specific BATs format) */ POWERPC_MMU_601 =3D 0x0000000A, #define POWERPC_MMU_64 0x00010000 -#define POWERPC_MMU_1TSEG 0x00020000 -#define POWERPC_MMU_AMR 0x00040000 #define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */ /* 64 bits PowerPC MMU */ POWERPC_MMU_64B =3D POWERPC_MMU_64 | 0x00000001, /* Architecture 2.03 and later (has LPCR) */ POWERPC_MMU_2_03 =3D POWERPC_MMU_64 | 0x00000002, /* Architecture 2.06 variant */ - POWERPC_MMU_2_06 =3D POWERPC_MMU_64 | POWERPC_MMU_1TSEG - | POWERPC_MMU_AMR | 0x00000003, + POWERPC_MMU_2_06 =3D POWERPC_MMU_64 | 0x00000003, /* Architecture 2.07 variant */ - POWERPC_MMU_2_07 =3D POWERPC_MMU_64 | POWERPC_MMU_1TSEG - | POWERPC_MMU_AMR | 0x00000004, + POWERPC_MMU_2_07 =3D POWERPC_MMU_64 | 0x00000004, /* Architecture 3.00 variant */ - POWERPC_MMU_3_00 =3D POWERPC_MMU_64 | POWERPC_MMU_1TSEG - | POWERPC_MMU_AMR | POWERPC_MMU_V3 + POWERPC_MMU_3_00 =3D POWERPC_MMU_64 | POWERPC_MMU_V3 | 0x00000005, }; #define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF)) diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index bc6d0a8314..22487cef06 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -302,7 +302,7 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, /* HV KVM has backing store size restrictions */ info->flags =3D KVM_PPC_PAGE_SIZES_REAL; =20 - if (env->mmu_model & POWERPC_MMU_1TSEG) { + if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { info->flags |=3D KVM_PPC_1T_SEGMENTS; } =20 @@ -482,7 +482,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu) } env->slb_nr =3D smmu_info.slb_size; if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) { - env->mmu_model &=3D ~POWERPC_MMU_1TSEG; + cpu->hash64_opts->flags &=3D ~PPC_HASH64_1TSEG; } } =20 diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 2809c31170..c9ee55e1ea 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -160,7 +160,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) { return -1; /* Bad segment size */ } - if ((vsid & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) { + if ((vsid & SLB_VSID_B) && !(ppc_hash64_has(cpu, PPC_HASH64_1TSEG))) { return -1; /* 1T segment on MMU that doesn't support it */ } =20 @@ -369,7 +369,7 @@ static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_has= h_pte64_t pte) int prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; =20 /* Only recent MMUs implement Virtual Page Class Key Protection */ - if (!(env->mmu_model & POWERPC_MMU_AMR)) { + if (!ppc_hash64_has(cpu, PPC_HASH64_AMR)) { return prot; } =20 @@ -1114,6 +1114,7 @@ void ppc_hash64_finalize(PowerPCCPU *cpu) } =20 const PPCHash64Options ppc_hash64_opts_basic =3D { + .flags =3D 0, .sps =3D { { .page_shift =3D 12, /* 4K */ .slb_enc =3D 0, @@ -1127,6 +1128,7 @@ const PPCHash64Options ppc_hash64_opts_basic =3D { }; =20 const PPCHash64Options ppc_hash64_opts_POWER7 =3D { + .flags =3D PPC_HASH64_1TSEG | PPC_HASH64_AMR, .sps =3D { { .page_shift =3D 12, /* 4K */ diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index 341c1524c2..b2b5d25238 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -153,12 +153,20 @@ struct PPCHash64SegmentPageSizes { }; =20 struct PPCHash64Options { +#define PPC_HASH64_1TSEG 0x00001 +#define PPC_HASH64_AMR 0x00002 + unsigned flags; PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ]; }; =20 extern const PPCHash64Options ppc_hash64_opts_basic; extern const PPCHash64Options ppc_hash64_opts_POWER7; =20 +static inline bool ppc_hash64_has(PowerPCCPU *cpu, unsigned feature) +{ + return !!(cpu->hash64_opts->flags & feature); +} + #endif /* CONFIG_USER_ONLY */ =20 #if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64) --=20 2.14.3 From nobody Mon Apr 29 10:10:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522894661140907.321267560415; Wed, 4 Apr 2018 19:17:41 -0700 (PDT) Received: from localhost ([::1]:48446 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uT6-0003EA-9t for importer@patchew.org; Wed, 04 Apr 2018 22:17:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35223) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uQL-0001Xn-S0 for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f3uQJ-0000u6-UI for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:49 -0400 Received: from ozlabs.org ([103.22.144.67]:51373) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f3uQJ-0000sT-8G; Wed, 04 Apr 2018 22:14:47 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40GmcK71FTz9s3Z; Thu, 5 Apr 2018 12:14:41 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1522894481; bh=io48Tlk3xvX/pu8qXLM+9Y85/z4YnuJdsdT3v4MdFt8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I8imxib8gAahwi//NMJiYo4flkYKsX96q6fy2qr0pIZXr/317tAKWrnNrFAIkUttw 9M4fKCOfi4ChgGv1NwZb97+5ERODVggevNe9IQXL4hpkzsLWvJzus/+pb1eVaKHPfr 0FM032L8kFaW+NICnKaRvLsuccxn8bgSZOJXoHDA= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org Date: Thu, 5 Apr 2018 12:14:34 +1000 Message-Id: <20180405021437.16761-11-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180405021437.16761-1-david@gibson.dropbear.id.au> References: <20180405021437.16761-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PATCH for-2.13 10/13] target/ppc: Fold ci_large_pages flag into PPCHash64Options X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bharata@linux.vnet.ibm.com, qemu-devel@nongnu.org, David Gibson , clg@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The ci_large_pages boolean in CPUPPCState is only relevant to 64-bit hash MMU machines, indicating whether it's possible to map large (> 4kiB) pages as cache-inhibitied (i.e. for IO, rather than memory). Fold it as another flag into the PPCHash64Options structure. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- hw/ppc/spapr.c | 3 +-- target/ppc/cpu.h | 1 - target/ppc/kvm.c | 6 +++++- target/ppc/mmu-hash64.c | 2 +- target/ppc/mmu-hash64.h | 1 + target/ppc/translate_init.c | 3 --- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index f86cb09080..60bc8417b6 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -263,7 +263,6 @@ static void spapr_populate_pa_features(sPAPRMachineStat= e *spapr, void *fdt, int offset, bool legacy_guest) { - CPUPPCState *env =3D &cpu->env; uint8_t pa_features_206[] =3D { 6, 0, 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; uint8_t pa_features_207[] =3D { 24, 0, @@ -315,7 +314,7 @@ static void spapr_populate_pa_features(sPAPRMachineStat= e *spapr, return; } =20 - if (env->ci_large_pages) { + if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { /* * Note: we keep CI large pages off by default because a 64K capab= le * guest provisioned with large pages might otherwise try to map a= qemu diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 1c5c33ca11..c0c44fb91d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1090,7 +1090,6 @@ struct CPUPPCState { #if defined(TARGET_PPC64) ppc_slb_t vrma_slb; target_ulong rmls; - bool ci_large_pages; #endif =20 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 22487cef06..fff2c601e0 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -448,7 +448,11 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu) * host page size is smaller than 64K. */ if (smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL) { - env->ci_large_pages =3D getpagesize() >=3D 0x10000; + if (getpagesize() >=3D 0x10000) { + cpu->hash64_opts->flags |=3D PPC_HASH64_CI_LARGEPAGE; + } else { + cpu->hash64_opts->flags &=3D ~PPC_HASH64_CI_LARGEPAGE; + } } =20 /* diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index c9ee55e1ea..f341714550 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1128,7 +1128,7 @@ const PPCHash64Options ppc_hash64_opts_basic =3D { }; =20 const PPCHash64Options ppc_hash64_opts_POWER7 =3D { - .flags =3D PPC_HASH64_1TSEG | PPC_HASH64_AMR, + .flags =3D PPC_HASH64_1TSEG | PPC_HASH64_AMR | PPC_HASH64_CI_LARGEPAGE, .sps =3D { { .page_shift =3D 12, /* 4K */ diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index b2b5d25238..f1babb0afc 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -155,6 +155,7 @@ struct PPCHash64SegmentPageSizes { struct PPCHash64Options { #define PPC_HASH64_1TSEG 0x00001 #define PPC_HASH64_AMR 0x00002 +#define PPC_HASH64_CI_LARGEPAGE 0x00004 unsigned flags; PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ]; }; diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index ae005b2a54..a925cf5cd3 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8392,7 +8392,6 @@ static void init_proc_POWER7(CPUPPCState *env) #if !defined(CONFIG_USER_ONLY) env->slb_nr =3D 32; #endif - env->ci_large_pages =3D true; env->dcache_line_size =3D 128; env->icache_line_size =3D 128; =20 @@ -8547,7 +8546,6 @@ static void init_proc_POWER8(CPUPPCState *env) #if !defined(CONFIG_USER_ONLY) env->slb_nr =3D 32; #endif - env->ci_large_pages =3D true; env->dcache_line_size =3D 128; env->icache_line_size =3D 128; =20 @@ -8748,7 +8746,6 @@ static void init_proc_POWER9(CPUPPCState *env) #if !defined(CONFIG_USER_ONLY) env->slb_nr =3D 32; #endif - env->ci_large_pages =3D true; env->dcache_line_size =3D 128; env->icache_line_size =3D 128; =20 --=20 2.14.3 From nobody Mon Apr 29 10:10:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522894640841655.370712081139; Wed, 4 Apr 2018 19:17:20 -0700 (PDT) Received: from localhost ([::1]:48445 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uSj-0002vK-S0 for importer@patchew.org; Wed, 04 Apr 2018 22:17:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35179) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uQK-0001Wb-JC for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f3uQJ-0000tO-EQ for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:48 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:39827) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f3uQJ-0000sM-3i; Wed, 04 Apr 2018 22:14:47 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40GmcK4slzz9s2L; Thu, 5 Apr 2018 12:14:41 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1522894481; bh=fwBUo/CenoAFYKsKaY5lHR/UywDCegJd3wDjI48vASg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DsIi3V6CtIkYdiLexvOkcOkcBQT3IqcDwwqkjd25af+U6oWoNHYvMO4s89mcraiTl xRWDwLLpMwmCeENLYwMNjNXEj6pAhdtOH6NFSZA1Nbp2ZqUSv9pkwNbEmHlMLU5Efz wrBgCXVB412F5sGJOvSkph4Lq0hvHhI/ytC6n0+A= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org Date: Thu, 5 Apr 2018 12:14:35 +1000 Message-Id: <20180405021437.16761-12-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180405021437.16761-1-david@gibson.dropbear.id.au> References: <20180405021437.16761-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PATCH for-2.13 11/13] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bharata@linux.vnet.ibm.com, qemu-devel@nongnu.org, David Gibson , clg@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The only place we test this flag is in conjunction with ppc64_use_proc_tbl(). That checks for the LPCR_UPRT bit, which we already ensure can't be set except on a machine with a v3 MMU (i.e. POWER9). Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- target/ppc/cpu-qom.h | 4 +--- target/ppc/mmu-hash64.c | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 2bd58b2a84..ef96d42cf2 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -68,7 +68,6 @@ enum powerpc_mmu_t { /* PowerPC 601 MMU model (specific BATs format) */ POWERPC_MMU_601 =3D 0x0000000A, #define POWERPC_MMU_64 0x00010000 -#define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */ /* 64 bits PowerPC MMU */ POWERPC_MMU_64B =3D POWERPC_MMU_64 | 0x00000001, /* Architecture 2.03 and later (has LPCR) */ @@ -78,8 +77,7 @@ enum powerpc_mmu_t { /* Architecture 2.07 variant */ POWERPC_MMU_2_07 =3D POWERPC_MMU_64 | 0x00000004, /* Architecture 3.00 variant */ - POWERPC_MMU_3_00 =3D POWERPC_MMU_64 | POWERPC_MMU_V3 - | 0x00000005, + POWERPC_MMU_3_00 =3D POWERPC_MMU_64 | 0x00000005, }; #define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF)) #define POWERPC_MMU_VER_64B POWERPC_MMU_VER(POWERPC_MMU_64B) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index f341714550..df26a03c15 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -761,7 +761,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr = eaddr, slb =3D slb_lookup(cpu, eaddr); if (!slb) { /* No entry found, check if in-memory segment tables are in use */ - if ((env->mmu_model & POWERPC_MMU_V3) && ppc64_use_proc_tbl(cpu)) { + if (ppc64_use_proc_tbl(cpu)) { /* TODO - Unsupported */ error_report("Segment Table Support Unimplemented"); exit(1); --=20 2.14.3 From nobody Mon Apr 29 10:10:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522895226350467.34130084613014; Wed, 4 Apr 2018 19:27:06 -0700 (PDT) Received: from localhost ([::1]:48582 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3ucD-00030R-4m for importer@patchew.org; Wed, 04 Apr 2018 22:27:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35306) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uQO-0001aY-8y for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f3uQM-0000vr-DP for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:52 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:42371) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f3uQL-0000u1-Nx; Wed, 04 Apr 2018 22:14:50 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40GmcL22n2z9s4X; Thu, 5 Apr 2018 12:14:41 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1522894482; bh=4DiSC1EgxYRGFghImREsxk5HqyHqElPv/sgfKencStc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XMzKQzNUCbJOjZbXbeOD/KOYWv7Doo693skcdtpKZ5wP48PKjBtAntDIUKW7eMH6l UdS5GXNEQdkrHXQsXgDdXGTkGwqgnaPizUlCglK/6cqefymi2lxSDmNGuktgzbyUKr lTz7ZdBOKHCOzbONtbJj2VuMPUbcI5ewoZvQVvcw= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org Date: Thu, 5 Apr 2018 12:14:36 +1000 Message-Id: <20180405021437.16761-13-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180405021437.16761-1-david@gibson.dropbear.id.au> References: <20180405021437.16761-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PATCH for-2.13 12/13] target/ppc: Get rid of POWERPC_MMU_VER() macros X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bharata@linux.vnet.ibm.com, qemu-devel@nongnu.org, David Gibson , clg@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" These macros were introduced to deal with the fact that the mmu_model field has bit flags mixed in with what's otherwise an enum of various mmu types. We've now eliminated all those flags except for one, and that one - POWERPC_MMU_64 - is already included/compared in the MMU_VER macros. So, we can get rid of those macros and just directly compare mmu_model values in the places it was used. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- target/ppc/cpu-qom.h | 6 ------ target/ppc/kvm.c | 8 ++++---- target/ppc/mmu-hash64.c | 12 ++++++------ target/ppc/mmu_helper.c | 24 ++++++++++++------------ target/ppc/translate.c | 12 ++++++------ 5 files changed, 28 insertions(+), 34 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index ef96d42cf2..433a71e484 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -79,12 +79,6 @@ enum powerpc_mmu_t { /* Architecture 3.00 variant */ POWERPC_MMU_3_00 =3D POWERPC_MMU_64 | 0x00000005, }; -#define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF)) -#define POWERPC_MMU_VER_64B POWERPC_MMU_VER(POWERPC_MMU_64B) -#define POWERPC_MMU_VER_2_03 POWERPC_MMU_VER(POWERPC_MMU_2_03) -#define POWERPC_MMU_VER_2_06 POWERPC_MMU_VER(POWERPC_MMU_2_06) -#define POWERPC_MMU_VER_2_07 POWERPC_MMU_VER(POWERPC_MMU_2_07) -#define POWERPC_MMU_VER_3_00 POWERPC_MMU_VER(POWERPC_MMU_3_00) =20 /*************************************************************************= ****/ /* Exception model = */ diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index fff2c601e0..b329cd8173 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -306,8 +306,8 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, info->flags |=3D KVM_PPC_1T_SEGMENTS; } =20 - if (POWERPC_MMU_VER(env->mmu_model) =3D=3D POWERPC_MMU_VER_2_06 || - POWERPC_MMU_VER(env->mmu_model) =3D=3D POWERPC_MMU_VER_2_07) { + if (env->mmu_model =3D=3D POWERPC_MMU_2_06 || + env->mmu_model =3D=3D POWERPC_MMU_2_07) { info->slb_size =3D 32; } else { info->slb_size =3D 64; @@ -321,8 +321,8 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, i++; =20 /* 64K on MMU 2.06 and later */ - if (POWERPC_MMU_VER(env->mmu_model) =3D=3D POWERPC_MMU_VER_2_06 || - POWERPC_MMU_VER(env->mmu_model) =3D=3D POWERPC_MMU_VER_2_07) { + if (env->mmu_model =3D=3D POWERPC_MMU_2_06 || + env->mmu_model =3D=3D POWERPC_MMU_2_07) { info->sps[i].page_shift =3D 16; info->sps[i].slb_enc =3D 0x110; info->sps[i].enc[0].page_shift =3D 16; diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index df26a03c15..a5570c8774 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1033,8 +1033,8 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong= val) uint64_t lpcr =3D 0; =20 /* Filter out bits */ - switch (POWERPC_MMU_VER(env->mmu_model)) { - case POWERPC_MMU_VER_64B: /* 970 */ + switch (env->mmu_model) { + case POWERPC_MMU_64B: /* 970 */ if (val & 0x40) { lpcr |=3D LPCR_LPES0; } @@ -1060,26 +1060,26 @@ void helper_store_lpcr(CPUPPCState *env, target_ulo= ng val) * to dig HRMOR out of HID5 */ break; - case POWERPC_MMU_VER_2_03: /* P5p */ + case POWERPC_MMU_2_03: /* P5p */ lpcr =3D val & (LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | LPCR_RMI | LPCR_HDICE); break; - case POWERPC_MMU_VER_2_06: /* P7 */ + case POWERPC_MMU_2_06: /* P7 */ lpcr =3D val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE); break; - case POWERPC_MMU_VER_2_07: /* P8 */ + case POWERPC_MMU_2_07: /* P8 */ lpcr =3D val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE); break; - case POWERPC_MMU_VER_3_00: /* P9 */ + case POWERPC_MMU_3_00: /* P9 */ lpcr =3D val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL= | LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 5568d1642b..8075b7149a 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1266,7 +1266,7 @@ static void mmu6xx_dump_mmu(FILE *f, fprintf_function= cpu_fprintf, =20 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) { - switch (POWERPC_MMU_VER(env->mmu_model)) { + switch (env->mmu_model) { case POWERPC_MMU_BOOKE: mmubooke_dump_mmu(f, cpu_fprintf, env); break; @@ -1278,13 +1278,13 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf= , CPUPPCState *env) mmu6xx_dump_mmu(f, cpu_fprintf, env); break; #if defined(TARGET_PPC64) - case POWERPC_MMU_VER_64B: - case POWERPC_MMU_VER_2_03: - case POWERPC_MMU_VER_2_06: - case POWERPC_MMU_VER_2_07: + case POWERPC_MMU_64B: + case POWERPC_MMU_2_03: + case POWERPC_MMU_2_06: + case POWERPC_MMU_2_07: dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env)); break; - case POWERPC_MMU_VER_3_00: + case POWERPC_MMU_3_00: if (ppc64_radix_guest(ppc_env_get_cpu(env))) { /* TODO - Unsupported */ } else { @@ -1423,14 +1423,14 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, va= ddr addr) CPUPPCState *env =3D &cpu->env; mmu_ctx_t ctx; =20 - switch (POWERPC_MMU_VER(env->mmu_model)) { + switch (env->mmu_model) { #if defined(TARGET_PPC64) - case POWERPC_MMU_VER_64B: - case POWERPC_MMU_VER_2_03: - case POWERPC_MMU_VER_2_06: - case POWERPC_MMU_VER_2_07: + case POWERPC_MMU_64B: + case POWERPC_MMU_2_03: + case POWERPC_MMU_2_06: + case POWERPC_MMU_2_07: return ppc_hash64_get_phys_page_debug(cpu, addr); - case POWERPC_MMU_VER_3_00: + case POWERPC_MMU_3_00: if (ppc64_radix_guest(ppc_env_get_cpu(env))) { return ppc_radix64_get_phys_page_debug(cpu, addr); } else { diff --git a/target/ppc/translate.c b/target/ppc/translate.c index b0d79a3fb9..3beaa1e2f0 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7121,17 +7121,17 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fpri= ntf_function cpu_fprintf, if (env->spr_cb[SPR_LPCR].name) cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); =20 - switch (POWERPC_MMU_VER(env->mmu_model)) { + switch (env->mmu_model) { case POWERPC_MMU_32B: case POWERPC_MMU_601: case POWERPC_MMU_SOFT_6xx: case POWERPC_MMU_SOFT_74xx: #if defined(TARGET_PPC64) - case POWERPC_MMU_VER_64B: - case POWERPC_MMU_VER_2_03: - case POWERPC_MMU_VER_2_06: - case POWERPC_MMU_VER_2_07: - case POWERPC_MMU_VER_3_00: + case POWERPC_MMU_64B: + case POWERPC_MMU_2_03: + case POWERPC_MMU_2_06: + case POWERPC_MMU_2_07: + case POWERPC_MMU_3_00: #endif if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); --=20 2.14.3 From nobody Mon Apr 29 10:10:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522895502299446.7511608859369; Wed, 4 Apr 2018 19:31:42 -0700 (PDT) Received: from localhost ([::1]:49215 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3ugb-0007dU-No for importer@patchew.org; Wed, 04 Apr 2018 22:31:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35273) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3uQN-0001Z3-6p for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f3uQK-0000uV-94 for qemu-devel@nongnu.org; Wed, 04 Apr 2018 22:14:51 -0400 Received: from ozlabs.org ([103.22.144.67]:42873) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f3uQJ-0000se-K2; Wed, 04 Apr 2018 22:14:48 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40GmcL1R29z9s3R; Thu, 5 Apr 2018 12:14:41 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1522894482; bh=BhW3G6y6keGIc5APPzSkrKyysSiBsUt8Cazeti2YokY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YpvKeVmxggFwoY55S7G9P0NhkOpBJm+FOJY9LZPSmY4zvmJEdzshVjLhTID908OeO CulWoGzEQ7LyBIZF/FXWhq0MECSZA9PHqdeYV7hSs/Cxh7UvN4sHxAFOMm1tfZhwUj uG6z17PO9EqOdLpRQiiJVtaJOr8OZ8MIGcbfWDF4= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org Date: Thu, 5 Apr 2018 12:14:37 +1000 Message-Id: <20180405021437.16761-14-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180405021437.16761-1-david@gibson.dropbear.id.au> References: <20180405021437.16761-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PATCH for-2.13 13/13] target/ppc: Fold slb_nr into PPCHash64Options X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bharata@linux.vnet.ibm.com, qemu-devel@nongnu.org, David Gibson , clg@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The env->slb_nr field gives the size of the SLB (Segment Lookaside Buffer). This is another static-after-initialization parameter of the specific version of the 64-bit hash MMU in the CPU. So, this patch folds the field into PPCHash64Options with the other hash MMU options. This is a bit more complicated that the things previously put in there, because slb_nr was foolishly included in the migration stream. So we need some of the usual dance to handle backwards compatible migration. Signed-off-by: David Gibson Reviewed-by: Greg Kurz Tested-by: Greg Kurz --- hw/ppc/pnv.c | 2 +- hw/ppc/spapr.c | 11 ++++++++--- target/ppc/cpu.h | 3 ++- target/ppc/kvm.c | 2 +- target/ppc/machine.c | 23 ++++++++++++++++++++--- target/ppc/mmu-hash64.c | 15 +++++++++------ target/ppc/mmu-hash64.h | 1 + target/ppc/translate_init.c | 15 --------------- 8 files changed, 42 insertions(+), 30 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 5905be3f71..53f672afa8 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -180,7 +180,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, voi= d *fdt) =20 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); - _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); + _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->= slb_size))); _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); =20 diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 60bc8417b6..6021631722 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -547,8 +547,8 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *f= dt, int offset, =20 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); - _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); - _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); + _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_= size))); + _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->= slb_size))); _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); =20 @@ -4000,7 +4000,12 @@ DEFINE_SPAPR_MACHINE(2_13, "2.13", true); * pseries-2.12 */ #define SPAPR_COMPAT_2_12 \ - HW_COMPAT_2_12 + HW_COMPAT_2_12 \ + { \ + .driver =3D TYPE_POWERPC_CPU, \ + .property =3D "pre-2.13-migration", \ + .value =3D "on", \ + }, =20 static void spapr_machine_2_12_instance_options(MachineState *machine) { diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index c0c44fb91d..8c9e03f54d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1025,7 +1025,6 @@ struct CPUPPCState { #if defined(TARGET_PPC64) /* PowerPC 64 SLB area */ ppc_slb_t slb[MAX_SLB_ENTRIES]; - int32_t slb_nr; /* tcg TLB needs flush (deferred slb inval instruction typically) */ #endif /* segment registers */ @@ -1216,6 +1215,8 @@ struct PowerPCCPU { uint64_t mig_insns_flags2; uint32_t mig_nb_BATs; bool pre_2_10_migration; + bool pre_2_13_migration; + int32_t mig_slb_nr; }; =20 static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env) diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index b329cd8173..1bd38c6a90 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -484,7 +484,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu) break; } } - env->slb_nr =3D smmu_info.slb_size; + cpu->hash64_opts->slb_size =3D smmu_info.slb_size; if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) { cpu->hash64_opts->flags &=3D ~PPC_HASH64_1TSEG; } diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 0634cdb295..3d6434a006 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -18,6 +18,9 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int ve= rsion_id) unsigned int i, j; target_ulong sdr1; uint32_t fpscr; +#if defined(TARGET_PPC64) + int32_t slb_nr; +#endif target_ulong xer; =20 for (i =3D 0; i < 32; i++) @@ -49,7 +52,7 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int ve= rsion_id) qemu_get_sbe32s(f, &env->access_type); #if defined(TARGET_PPC64) qemu_get_betls(f, &env->spr[SPR_ASR]); - qemu_get_sbe32s(f, &env->slb_nr); + qemu_get_sbe32s(f, &slb_nr); #endif qemu_get_betls(f, &sdr1); for (i =3D 0; i < 32; i++) @@ -146,6 +149,15 @@ static bool cpu_pre_2_8_migration(void *opaque, int ve= rsion_id) return cpu->pre_2_8_migration; } =20 +#if defined(TARGET_PPC64) +static bool cpu_pre_2_13_migration(void *opaque, int version_id) +{ + PowerPCCPU *cpu =3D opaque; + + return cpu->pre_2_13_migration; +} +#endif + static int cpu_pre_save(void *opaque) { PowerPCCPU *cpu =3D opaque; @@ -203,6 +215,11 @@ static int cpu_pre_save(void *opaque) cpu->mig_insns_flags2 =3D env->insns_flags2 & insns_compat_mask2; cpu->mig_nb_BATs =3D env->nb_BATs; } + if (cpu->pre_2_13_migration) { + if (cpu->hash64_opts) { + cpu->mig_slb_nr =3D cpu->hash64_opts->slb_size; + } + } =20 return 0; } @@ -478,7 +495,7 @@ static int slb_post_load(void *opaque, int version_id) =20 /* We've pulled in the raw esid and vsid values from the migration * stream, but we need to recompute the page size pointers */ - for (i =3D 0; i < env->slb_nr; i++) { + for (i =3D 0; i < cpu->hash64_opts->slb_size; i++) { if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0)= { /* Migration source had bad values in its SLB */ return -1; @@ -495,7 +512,7 @@ static const VMStateDescription vmstate_slb =3D { .needed =3D slb_needed, .post_load =3D slb_post_load, .fields =3D (VMStateField[]) { - VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU, NULL), + VMSTATE_INT32_TEST(mig_slb_nr, PowerPCCPU, cpu_pre_2_13_migration), VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES), VMSTATE_END_OF_LIST() } diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index a5570c8774..7e0adecfd9 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -52,7 +52,7 @@ static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulon= g eaddr) esid_256M =3D (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V; esid_1T =3D (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V; =20 - for (n =3D 0; n < env->slb_nr; n++) { + for (n =3D 0; n < cpu->hash64_opts->slb_size; n++) { ppc_slb_t *slb =3D &env->slb[n]; =20 LOG_SLB("%s: slot %d %016" PRIx64 " %016" @@ -80,7 +80,7 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, Powe= rPCCPU *cpu) cpu_synchronize_state(CPU(cpu)); =20 cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n"); - for (i =3D 0; i < env->slb_nr; i++) { + for (i =3D 0; i < cpu->hash64_opts->slb_size; i++) { slbe =3D env->slb[i].esid; slbv =3D env->slb[i].vsid; if (slbe =3D=3D 0 && slbv =3D=3D 0) { @@ -93,10 +93,11 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, Po= werPCCPU *cpu) =20 void helper_slbia(CPUPPCState *env) { + PowerPCCPU *cpu =3D ppc_env_get_cpu(env); int n; =20 /* XXX: Warning: slbia never invalidates the first segment */ - for (n =3D 1; n < env->slb_nr; n++) { + for (n =3D 1; n < cpu->hash64_opts->slb_size; n++) { ppc_slb_t *slb =3D &env->slb[n]; =20 if (slb->esid & SLB_ESID_V) { @@ -151,7 +152,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, const PPCHash64SegmentPageSizes *sps =3D NULL; int i; =20 - if (slot >=3D env->slb_nr) { + if (slot >=3D cpu->hash64_opts->slb_size) { return -1; /* Bad slot number */ } if (esid & ~(SLB_ESID_ESID | SLB_ESID_V)) { @@ -202,7 +203,7 @@ static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ul= ong rb, int slot =3D rb & 0xfff; ppc_slb_t *slb =3D &env->slb[slot]; =20 - if (slot >=3D env->slb_nr) { + if (slot >=3D cpu->hash64_opts->slb_size) { return -1; } =20 @@ -217,7 +218,7 @@ static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ul= ong rb, int slot =3D rb & 0xfff; ppc_slb_t *slb =3D &env->slb[slot]; =20 - if (slot >=3D env->slb_nr) { + if (slot >=3D cpu->hash64_opts->slb_size) { return -1; } =20 @@ -1115,6 +1116,7 @@ void ppc_hash64_finalize(PowerPCCPU *cpu) =20 const PPCHash64Options ppc_hash64_opts_basic =3D { .flags =3D 0, + .slb_size =3D 64, .sps =3D { { .page_shift =3D 12, /* 4K */ .slb_enc =3D 0, @@ -1129,6 +1131,7 @@ const PPCHash64Options ppc_hash64_opts_basic =3D { =20 const PPCHash64Options ppc_hash64_opts_POWER7 =3D { .flags =3D PPC_HASH64_1TSEG | PPC_HASH64_AMR | PPC_HASH64_CI_LARGEPAGE, + .slb_size =3D 32, .sps =3D { { .page_shift =3D 12, /* 4K */ diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index f1babb0afc..d5fc03441d 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -157,6 +157,7 @@ struct PPCHash64Options { #define PPC_HASH64_AMR 0x00002 #define PPC_HASH64_CI_LARGEPAGE 0x00004 unsigned flags; + unsigned slb_size; PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ]; }; =20 diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index a925cf5cd3..2f63acd310 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8195,9 +8195,6 @@ static void init_proc_970(CPUPPCState *env) gen_spr_970_dbg(env); =20 /* env variables */ -#if !defined(CONFIG_USER_ONLY) - env->slb_nr =3D 64; -#endif env->dcache_line_size =3D 128; env->icache_line_size =3D 128; =20 @@ -8272,9 +8269,6 @@ static void init_proc_power5plus(CPUPPCState *env) gen_spr_power5p_ear(env); =20 /* env variables */ -#if !defined(CONFIG_USER_ONLY) - env->slb_nr =3D 64; -#endif env->dcache_line_size =3D 128; env->icache_line_size =3D 128; =20 @@ -8389,9 +8383,6 @@ static void init_proc_POWER7(CPUPPCState *env) gen_spr_power7_book4(env); =20 /* env variables */ -#if !defined(CONFIG_USER_ONLY) - env->slb_nr =3D 32; -#endif env->dcache_line_size =3D 128; env->icache_line_size =3D 128; =20 @@ -8543,9 +8534,6 @@ static void init_proc_POWER8(CPUPPCState *env) gen_spr_power8_rpr(env); =20 /* env variables */ -#if !defined(CONFIG_USER_ONLY) - env->slb_nr =3D 32; -#endif env->dcache_line_size =3D 128; env->icache_line_size =3D 128; =20 @@ -8743,9 +8731,6 @@ static void init_proc_POWER9(CPUPPCState *env) KVM_REG_PPC_PSSCR, 0); =20 /* env variables */ -#if !defined(CONFIG_USER_ONLY) - env->slb_nr =3D 32; -#endif env->dcache_line_size =3D 128; env->icache_line_size =3D 128; =20 --=20 2.14.3