From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152209229769616.632651070338056; Mon, 26 Mar 2018 12:24:57 -0700 (PDT) Received: from localhost ([::1]:58688 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xjk-0002EV-ET for importer@patchew.org; Mon, 26 Mar 2018 15:24:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58523) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xbq-0003M5-Gj for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0Xbm-0001aB-8y for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:46 -0400 Received: from mout.kundenserver.de ([212.227.126.133]:46329) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0Xbl-0001YN-QJ; Mon, 26 Mar 2018 15:16:42 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MDJ3g-1emIXN18Xc-00GZ9p; Mon, 26 Mar 2018 21:16:18 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:15:45 +0200 Message-Id: <20180326191603.10217-2-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:wM7KIuKFpzdHynutrca0BAJLIihVNOsolv7fSAJvUG3TcsdPpxA EmOBsG8qLuvR1iViYF3Rv39dmNoUFshGtkG7NTAmICo64zsBsolfbrC1aXc4i/y+ur3NJNJ F099Y63M2vQySAduk37hcxBZQ8AlKDeGWBPIY4xfkmUafe2A6rYDOldRHgmG6GyP5xSECIz mGYJmp2do7DuwnhXNDeFw== X-UI-Out-Filterresults: notjunk:1;V01:K0:YRUtaap245s=:kOEK+9Z2+KyaHNdK/PANWM NZ1bjWnCp8PsXIkZS/RXO2kWZkibTd3GRm53m+P8TEV7CeMu8O+dW4NejrOxheVxiSA5Z083w 0wikPeTl4HtOujNdzHqpxFTmkMuJ5ZQ/IBuslHHk6fgiSu5a8RZICrKDUUTQedi8HiwD7IA5j LeM8K2FBN++n5MNFp6iX5miKDqFu5ZSB54vFNY6f2VBTt+Sm6ESPwz/6KQFQn73iID1j0v061 DqOf/IpikOidd4lqfkhiyFEbye5ohFv6OEdnpRE93t3xcsofgorfhLkhI5Wne8zuVlewsFYZT W72qzoGuF8+rFqDyQf/hOHOFlf8svwdJZqXmp/LgpkNVIynMXIDZTYNbOkPtZBrmoXa56A2/o XkhAb4thGBH7g6M81peitEI811eZRUkdibCQN/N5lwKlkj/wUSWNerDINHrNbJ4BxD/ZlIMfy 58P2xayKCEBxnCdPl7DnoCGGJWFJ3Hbr2zXd1phgNvLisgKkUFuGD1Sbwnoxs93Zx3Tk6Wv2P n8QE9dnLCv9zluVWHvJlOyE9B7k7SohaN8jC/kXC8xJysjj2hcDNpJIr/P3p69u+FDsPuFRDA 2t/E4n1OtHfuqUg13WbTqIYa4e/HvLt4wEEWZ+vqffoAUFl4TdEV4dTyQHjbKS+8a6kJwaO+s LHqV6GgnuiIYXe/FfDmOisshKm++owl70t8lUZ5wrPvZ53Fs9EiJwQUQMnPg2zZ+6i0iONO5q o9hES396OFGtZPyNvTJYatbh22G+Jz6xpyevyA== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.133 Subject: [Qemu-devel] [PATCH for 2.13 01/19] linux-user: create a dummy per arch cpu_loop.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Create a cpu_loop-common.h for future use by these new files and use it in the existing main.c Introduce target_cpu_copy_regs(): declare the function in cpu_loop-common.h and an empty function for each target, to move all the cpu_loop prologues to this function. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- linux-user/Makefile.objs | 3 ++- linux-user/aarch64/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/alpha/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/arm/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/cpu_loop-common.h | 37 +++++++++++++++++++++++++++++++++++++ linux-user/cris/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/hppa/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/i386/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/m68k/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/main.c | 17 +++-------------- linux-user/microblaze/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/mips/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/mips64/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/nios2/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/openrisc/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/ppc/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/riscv/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/s390x/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/sh4/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/sparc/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/sparc64/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/tilegx/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/x86_64/cpu_loop.c | 26 ++++++++++++++++++++++++++ linux-user/xtensa/cpu_loop.c | 26 ++++++++++++++++++++++++++ 24 files changed, 588 insertions(+), 15 deletions(-) create mode 100644 linux-user/aarch64/cpu_loop.c create mode 100644 linux-user/alpha/cpu_loop.c create mode 100644 linux-user/arm/cpu_loop.c create mode 100644 linux-user/cpu_loop-common.h create mode 100644 linux-user/cris/cpu_loop.c create mode 100644 linux-user/hppa/cpu_loop.c create mode 100644 linux-user/i386/cpu_loop.c create mode 100644 linux-user/m68k/cpu_loop.c create mode 100644 linux-user/microblaze/cpu_loop.c create mode 100644 linux-user/mips/cpu_loop.c create mode 100644 linux-user/mips64/cpu_loop.c create mode 100644 linux-user/nios2/cpu_loop.c create mode 100644 linux-user/openrisc/cpu_loop.c create mode 100644 linux-user/ppc/cpu_loop.c create mode 100644 linux-user/riscv/cpu_loop.c create mode 100644 linux-user/s390x/cpu_loop.c create mode 100644 linux-user/sh4/cpu_loop.c create mode 100644 linux-user/sparc/cpu_loop.c create mode 100644 linux-user/sparc64/cpu_loop.c create mode 100644 linux-user/tilegx/cpu_loop.c create mode 100644 linux-user/x86_64/cpu_loop.c create mode 100644 linux-user/xtensa/cpu_loop.c diff --git a/linux-user/Makefile.objs b/linux-user/Makefile.objs index 811a7f5ce5..59a5c17354 100644 --- a/linux-user/Makefile.objs +++ b/linux-user/Makefile.objs @@ -1,6 +1,7 @@ obj-y =3D main.o syscall.o strace.o mmap.o signal.o \ elfload.o linuxload.o uaccess.o uname.o \ - safe-syscall.o $(TARGET_ABI_DIR)/signal.o + safe-syscall.o $(TARGET_ABI_DIR)/signal.o \ + $(TARGET_ABI_DIR)/cpu_loop.o =20 obj-$(TARGET_HAS_BFLT) +=3D flatload.o obj-$(TARGET_I386) +=3D vm86.o diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/aarch64/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/alpha/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/arm/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/cpu_loop-common.h b/linux-user/cpu_loop-common.h new file mode 100644 index 0000000000..ffe3fe9ad5 --- /dev/null +++ b/linux-user/cpu_loop-common.h @@ -0,0 +1,37 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef CPU_LOOP_COMMON_H +#define CPU_LOOP_COMMON_H + +#include "exec/log.h" + +#define EXCP_DUMP(env, fmt, ...) \ +do { \ + CPUState *cs =3D ENV_GET_CPU(env); \ + fprintf(stderr, fmt , ## __VA_ARGS__); \ + cpu_dump_state(cs, stderr, fprintf, 0); \ + if (qemu_log_separate()) { \ + qemu_log(fmt, ## __VA_ARGS__); \ + log_cpu_state(cs, 0); \ + } \ +} while (0) + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs); +#endif diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/cris/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/hppa/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/i386/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/m68k/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/main.c b/linux-user/main.c index ba09b7d0c8..a2ce9df46f 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -33,9 +33,9 @@ #include "qemu/timer.h" #include "qemu/envlist.h" #include "elf.h" -#include "exec/log.h" #include "trace/control.h" #include "target_elf.h" +#include "cpu_loop-common.h" =20 char *exec_path; =20 @@ -50,17 +50,6 @@ unsigned long mmap_min_addr; unsigned long guest_base; int have_guest_base; =20 -#define EXCP_DUMP(env, fmt, ...) \ -do { \ - CPUState *cs =3D ENV_GET_CPU(env); \ - fprintf(stderr, fmt , ## __VA_ARGS__); \ - cpu_dump_state(cs, stderr, fprintf, 0); \ - if (qemu_log_separate()) { \ - qemu_log(fmt, ## __VA_ARGS__); \ - log_cpu_state(cs, 0); \ - } \ -} while (0) - /* * When running 32-on-64 we should make sure we can fit all of the possible * guest address space into a contiguous chunk of virtual host memory. @@ -4733,6 +4722,8 @@ int main(int argc, char **argv, char **envp) tcg_prologue_init(tcg_ctx); tcg_region_init(); =20 + target_cpu_copy_regs(env, regs); + #if defined(TARGET_I386) env->cr[0] =3D CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; env->hflags |=3D HF_PE_MASK | HF_CPL_MASK; @@ -5122,8 +5113,6 @@ int main(int argc, char **argv, char **envp) env->sregs[WINDOW_START] =3D regs->windowstart; env->pc =3D regs->pc; } -#else -#error unsupported target CPU #endif =20 #if defined(TARGET_ARM) || defined(TARGET_M68K) diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_l= oop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/microblaze/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/mips/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/mips64/cpu_loop.c b/linux-user/mips64/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/mips64/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/nios2/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/openrisc/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/ppc/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/riscv/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/s390x/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/sh4/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/sparc/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/sparc64/cpu_loop.c b/linux-user/sparc64/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/sparc64/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/tilegx/cpu_loop.c b/linux-user/tilegx/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/tilegx/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/x86_64/cpu_loop.c b/linux-user/x86_64/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/x86_64/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c new file mode 100644 index 0000000000..b7700a5561 --- /dev/null +++ b/linux-user/xtensa/cpu_loop.c @@ -0,0 +1,26 @@ +/* + * qemu user cpu loop + * + * Copyright (c) 2003-2008 Fabrice Bellard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu_loop-common.h" + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ +} --=20 2.14.3 From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522092470831990.3844928383511; Mon, 26 Mar 2018 12:27:50 -0700 (PDT) Received: from localhost ([::1]:58711 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0XmX-0004pD-RB for importer@patchew.org; Mon, 26 Mar 2018 15:27:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58557) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xbs-0003NM-3C for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0Xbo-0001cm-T4 for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:48 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:55451) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0Xbi-0001Ub-Ew; Mon, 26 Mar 2018 15:16:38 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MB68W-1ess6h0RNc-009wO5; Mon, 26 Mar 2018 21:16:19 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:15:46 +0200 Message-Id: <20180326191603.10217-3-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:k7Ud+YQHNJ/XtYJt5ZgIJ1lohSyDV3sH9v15ZreMrHdSqpC3YBG zxLgEmqM7vuuCevdPsPVUc2spHTkhr+1GfC9B4MEfrQavVhRVRVo2RqHu+zhOaLN6+up/Zz 0ljWeFq1Co4wKhYrKZsKGi/mtWjR2UqU5Z+rLyiZnNkPHtq9jZv2S9ibVu66V3aJzJiEY3g fGlBHi/Kyvbe/cNdNnz5A== X-UI-Out-Filterresults: notjunk:1;V01:K0:phYmefyv9Js=:STrOuoCmP1EAJ9z6Ad14rk mpXryUsYNr9gm0XMZaXqI4YS+LP0ei876ywf7RoBiqOibVPfqI+vYBgQZ2s3B3a03NQAjHSMP 3w/MuCv4SOMOZVIgEBmhFd6SoIgZv9CYTI9VR5aBRJScCJXGRz66GbWpNUOgM22H3Bz56xUh1 KT0uhFHiz1fITpyBVhez1ZEdfpaMQGB2ZC/r9PpyqRnJkTp5xqAs8TraxVr4uhQByPIrx1sLr mb4ic++6xSpEkNmmfmLx2NDceEiMENCN1tebET7ev+Tsm/QdUTsyl6B+olXxHCsPSKFjy8VKk WjiV/u6dD/eMyVLcmfm+83SPZSAi/H2wmFYMuqLi7Ljr8eN06HjynoVrwkda8/PJtG4Oxj3Xb NpNIGUHDJZM4xHWHBXxlMDBP+nr4c6nHNfHalNqOTJPyZdXZmFR6apxzLCy5/woyr1ecTxKy0 r1CleWey4/Gl6lKx/VjMfaEg646903NcHYNaKxHPb0FHkst+k+s0ODNLLID1rFHm1E7bDhGxo 52RZvtbkQdzaYqTpscKm2IgnEKEtmvjC3uZyry33G1lrSekd7V4FXvvATZ10OET68dMXaX4/d HiCUW21vFObMOAZUSAzVZ/hpucrOyUH/H5nzpSSyNK0ncivr+fbk38ixXcNeeYVIlH/hBa1ib nEiIWAqSDLwaMUb2pY2DMX7yOn8LinZ7ebPjJzbCs4SVpyJKhRPQCei++ATAjRSkSr79wJZSm pcgyx4Pbrzrn+pp+xrn05sI17TfN80o1F/+YEw== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PATCH for 2.13 02/19] linux-user: move i386/x86_64 cpu loop to i386 directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to i386/cpu_loop.c. Include i386/cpu_loop.c in x86_64/cpu_loop.c to avoid to duplicate code. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- linux-user/i386/cpu_loop.c | 343 +++++++++++++++++++++++++++++++++++++++= +++ linux-user/main.c | 348 +--------------------------------------= ---- linux-user/x86_64/cpu_loop.c | 8 +- 3 files changed, 345 insertions(+), 354 deletions(-) diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index b7700a5561..2374abfd0b 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -21,6 +21,349 @@ #include "qemu.h" #include "cpu_loop-common.h" =20 +/***********************************************************/ +/* CPUX86 core interface */ + +uint64_t cpu_get_tsc(CPUX86State *env) +{ + return cpu_get_host_ticks(); +} + +static void write_dt(void *ptr, unsigned long addr, unsigned long limit, + int flags) +{ + unsigned int e1, e2; + uint32_t *p; + e1 =3D (addr << 16) | (limit & 0xffff); + e2 =3D ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f00= 00); + e2 |=3D flags; + p =3D ptr; + p[0] =3D tswap32(e1); + p[1] =3D tswap32(e2); +} + +static uint64_t *idt_table; +#ifdef TARGET_X86_64 +static void set_gate64(void *ptr, unsigned int type, unsigned int dpl, + uint64_t addr, unsigned int sel) +{ + uint32_t *p, e1, e2; + e1 =3D (addr & 0xffff) | (sel << 16); + e2 =3D (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); + p =3D ptr; + p[0] =3D tswap32(e1); + p[1] =3D tswap32(e2); + p[2] =3D tswap32(addr >> 32); + p[3] =3D 0; +} +/* only dpl matters as we do only user space emulation */ +static void set_idt(int n, unsigned int dpl) +{ + set_gate64(idt_table + n * 2, 0, dpl, 0, 0); +} +#else +static void set_gate(void *ptr, unsigned int type, unsigned int dpl, + uint32_t addr, unsigned int sel) +{ + uint32_t *p, e1, e2; + e1 =3D (addr & 0xffff) | (sel << 16); + e2 =3D (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); + p =3D ptr; + p[0] =3D tswap32(e1); + p[1] =3D tswap32(e2); +} + +/* only dpl matters as we do only user space emulation */ +static void set_idt(int n, unsigned int dpl) +{ + set_gate(idt_table + n, 0, dpl, 0, 0); +} +#endif + +void cpu_loop(CPUX86State *env) +{ + CPUState *cs =3D CPU(x86_env_get_cpu(env)); + int trapnr; + abi_ulong pc; + abi_ulong ret; + target_siginfo_t info; + + for(;;) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch(trapnr) { + case 0x80: + /* linux syscall from int $0x80 */ + ret =3D do_syscall(env, + env->regs[R_EAX], + env->regs[R_EBX], + env->regs[R_ECX], + env->regs[R_EDX], + env->regs[R_ESI], + env->regs[R_EDI], + env->regs[R_EBP], + 0, 0); + if (ret =3D=3D -TARGET_ERESTARTSYS) { + env->eip -=3D 2; + } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { + env->regs[R_EAX] =3D ret; + } + break; +#ifndef TARGET_ABI32 + case EXCP_SYSCALL: + /* linux syscall from syscall instruction */ + ret =3D do_syscall(env, + env->regs[R_EAX], + env->regs[R_EDI], + env->regs[R_ESI], + env->regs[R_EDX], + env->regs[10], + env->regs[8], + env->regs[9], + 0, 0); + if (ret =3D=3D -TARGET_ERESTARTSYS) { + env->eip -=3D 2; + } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { + env->regs[R_EAX] =3D ret; + } + break; +#endif + case EXCP0B_NOSEG: + case EXCP0C_STACK: + info.si_signo =3D TARGET_SIGBUS; + info.si_errno =3D 0; + info.si_code =3D TARGET_SI_KERNEL; + info._sifields._sigfault._addr =3D 0; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP0D_GPF: + /* XXX: potential problem if ABI32 */ +#ifndef TARGET_X86_64 + if (env->eflags & VM_MASK) { + handle_vm86_fault(env); + } else +#endif + { + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info.si_code =3D TARGET_SI_KERNEL; + info._sifields._sigfault._addr =3D 0; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + break; + case EXCP0E_PAGE: + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + if (!(env->error_code & 1)) + info.si_code =3D TARGET_SEGV_MAPERR; + else + info.si_code =3D TARGET_SEGV_ACCERR; + info._sifields._sigfault._addr =3D env->cr[2]; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP00_DIVZ: +#ifndef TARGET_X86_64 + if (env->eflags & VM_MASK) { + handle_vm86_trap(env, trapnr); + } else +#endif + { + /* division by zero */ + info.si_signo =3D TARGET_SIGFPE; + info.si_errno =3D 0; + info.si_code =3D TARGET_FPE_INTDIV; + info._sifields._sigfault._addr =3D env->eip; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + break; + case EXCP01_DB: + case EXCP03_INT3: +#ifndef TARGET_X86_64 + if (env->eflags & VM_MASK) { + handle_vm86_trap(env, trapnr); + } else +#endif + { + info.si_signo =3D TARGET_SIGTRAP; + info.si_errno =3D 0; + if (trapnr =3D=3D EXCP01_DB) { + info.si_code =3D TARGET_TRAP_BRKPT; + info._sifields._sigfault._addr =3D env->eip; + } else { + info.si_code =3D TARGET_SI_KERNEL; + info._sifields._sigfault._addr =3D 0; + } + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + break; + case EXCP04_INTO: + case EXCP05_BOUND: +#ifndef TARGET_X86_64 + if (env->eflags & VM_MASK) { + handle_vm86_trap(env, trapnr); + } else +#endif + { + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info.si_code =3D TARGET_SI_KERNEL; + info._sifields._sigfault._addr =3D 0; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + break; + case EXCP06_ILLOP: + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D TARGET_ILL_ILLOPN; + info._sifields._sigfault._addr =3D env->eip; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case EXCP_DEBUG: + { + int sig; + + sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); + if (sig) + { + info.si_signo =3D sig; + info.si_errno =3D 0; + info.si_code =3D TARGET_TRAP_BRKPT; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + } + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + default: + pc =3D env->segs[R_CS].base + env->eip; + EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - = aborting\n", + (long)pc, trapnr); + abort(); + } + process_pending_signals(env); + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + env->cr[0] =3D CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; + env->hflags |=3D HF_PE_MASK | HF_CPL_MASK; + if (env->features[FEAT_1_EDX] & CPUID_SSE) { + env->cr[4] |=3D CR4_OSFXSR_MASK; + env->hflags |=3D HF_OSFXSR_MASK; + } +#ifndef TARGET_ABI32 + /* enable 64 bit mode if possible */ + if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) { + fprintf(stderr, "The selected x86 CPU does not support 64 bit mode= \n"); + exit(EXIT_FAILURE); + } + env->cr[4] |=3D CR4_PAE_MASK; + env->efer |=3D MSR_EFER_LMA | MSR_EFER_LME; + env->hflags |=3D HF_LMA_MASK; +#endif + + /* flags setup : we activate the IRQs by default as in user mode */ + env->eflags |=3D IF_MASK; + + /* linux register setup */ +#ifndef TARGET_ABI32 + env->regs[R_EAX] =3D regs->rax; + env->regs[R_EBX] =3D regs->rbx; + env->regs[R_ECX] =3D regs->rcx; + env->regs[R_EDX] =3D regs->rdx; + env->regs[R_ESI] =3D regs->rsi; + env->regs[R_EDI] =3D regs->rdi; + env->regs[R_EBP] =3D regs->rbp; + env->regs[R_ESP] =3D regs->rsp; + env->eip =3D regs->rip; +#else + env->regs[R_EAX] =3D regs->eax; + env->regs[R_EBX] =3D regs->ebx; + env->regs[R_ECX] =3D regs->ecx; + env->regs[R_EDX] =3D regs->edx; + env->regs[R_ESI] =3D regs->esi; + env->regs[R_EDI] =3D regs->edi; + env->regs[R_EBP] =3D regs->ebp; + env->regs[R_ESP] =3D regs->esp; + env->eip =3D regs->eip; +#endif + + /* linux interrupt setup */ +#ifndef TARGET_ABI32 + env->idt.limit =3D 511; +#else + env->idt.limit =3D 255; +#endif + env->idt.base =3D target_mmap(0, sizeof(uint64_t) * (env->idt.limit + = 1), + PROT_READ|PROT_WRITE, + MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); + idt_table =3D g2h(env->idt.base); + set_idt(0, 0); + set_idt(1, 0); + set_idt(2, 0); + set_idt(3, 3); + set_idt(4, 3); + set_idt(5, 0); + set_idt(6, 0); + set_idt(7, 0); + set_idt(8, 0); + set_idt(9, 0); + set_idt(10, 0); + set_idt(11, 0); + set_idt(12, 0); + set_idt(13, 0); + set_idt(14, 0); + set_idt(15, 0); + set_idt(16, 0); + set_idt(17, 0); + set_idt(18, 0); + set_idt(19, 0); + set_idt(0x80, 3); + + /* linux segment setup */ + { + uint64_t *gdt_table; + env->gdt.base =3D target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENT= RIES, + PROT_READ|PROT_WRITE, + MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); + env->gdt.limit =3D sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; + gdt_table =3D g2h(env->gdt.base); +#ifdef TARGET_ABI32 + write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, + DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | + (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); +#else + /* 64 bit code segment */ + write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, + DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | + DESC_L_MASK | + (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); +#endif + write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff, + DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | + (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT)); + } + cpu_x86_load_seg(env, R_CS, __USER_CS); + cpu_x86_load_seg(env, R_SS, __USER_DS); +#ifdef TARGET_ABI32 + cpu_x86_load_seg(env, R_DS, __USER_DS); + cpu_x86_load_seg(env, R_ES, __USER_DS); + cpu_x86_load_seg(env, R_FS, __USER_DS); + cpu_x86_load_seg(env, R_GS, __USER_DS); + /* This hack makes Wine work... */ + env->segs[R_FS].selector =3D 0; +#else + cpu_x86_load_seg(env, R_DS, 0); + cpu_x86_load_seg(env, R_ES, 0); + cpu_x86_load_seg(env, R_FS, 0); + cpu_x86_load_seg(env, R_GS, 0); +#endif } diff --git a/linux-user/main.c b/linux-user/main.c index a2ce9df46f..0b792024ce 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -149,238 +149,6 @@ void fork_end(int child) } } =20 -#ifdef TARGET_I386 -/***********************************************************/ -/* CPUX86 core interface */ - -uint64_t cpu_get_tsc(CPUX86State *env) -{ - return cpu_get_host_ticks(); -} - -static void write_dt(void *ptr, unsigned long addr, unsigned long limit, - int flags) -{ - unsigned int e1, e2; - uint32_t *p; - e1 =3D (addr << 16) | (limit & 0xffff); - e2 =3D ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f00= 00); - e2 |=3D flags; - p =3D ptr; - p[0] =3D tswap32(e1); - p[1] =3D tswap32(e2); -} - -static uint64_t *idt_table; -#ifdef TARGET_X86_64 -static void set_gate64(void *ptr, unsigned int type, unsigned int dpl, - uint64_t addr, unsigned int sel) -{ - uint32_t *p, e1, e2; - e1 =3D (addr & 0xffff) | (sel << 16); - e2 =3D (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); - p =3D ptr; - p[0] =3D tswap32(e1); - p[1] =3D tswap32(e2); - p[2] =3D tswap32(addr >> 32); - p[3] =3D 0; -} -/* only dpl matters as we do only user space emulation */ -static void set_idt(int n, unsigned int dpl) -{ - set_gate64(idt_table + n * 2, 0, dpl, 0, 0); -} -#else -static void set_gate(void *ptr, unsigned int type, unsigned int dpl, - uint32_t addr, unsigned int sel) -{ - uint32_t *p, e1, e2; - e1 =3D (addr & 0xffff) | (sel << 16); - e2 =3D (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); - p =3D ptr; - p[0] =3D tswap32(e1); - p[1] =3D tswap32(e2); -} - -/* only dpl matters as we do only user space emulation */ -static void set_idt(int n, unsigned int dpl) -{ - set_gate(idt_table + n, 0, dpl, 0, 0); -} -#endif - -void cpu_loop(CPUX86State *env) -{ - CPUState *cs =3D CPU(x86_env_get_cpu(env)); - int trapnr; - abi_ulong pc; - abi_ulong ret; - target_siginfo_t info; - - for(;;) { - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - switch(trapnr) { - case 0x80: - /* linux syscall from int $0x80 */ - ret =3D do_syscall(env, - env->regs[R_EAX], - env->regs[R_EBX], - env->regs[R_ECX], - env->regs[R_EDX], - env->regs[R_ESI], - env->regs[R_EDI], - env->regs[R_EBP], - 0, 0); - if (ret =3D=3D -TARGET_ERESTARTSYS) { - env->eip -=3D 2; - } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { - env->regs[R_EAX] =3D ret; - } - break; -#ifndef TARGET_ABI32 - case EXCP_SYSCALL: - /* linux syscall from syscall instruction */ - ret =3D do_syscall(env, - env->regs[R_EAX], - env->regs[R_EDI], - env->regs[R_ESI], - env->regs[R_EDX], - env->regs[10], - env->regs[8], - env->regs[9], - 0, 0); - if (ret =3D=3D -TARGET_ERESTARTSYS) { - env->eip -=3D 2; - } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { - env->regs[R_EAX] =3D ret; - } - break; -#endif - case EXCP0B_NOSEG: - case EXCP0C_STACK: - info.si_signo =3D TARGET_SIGBUS; - info.si_errno =3D 0; - info.si_code =3D TARGET_SI_KERNEL; - info._sifields._sigfault._addr =3D 0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP0D_GPF: - /* XXX: potential problem if ABI32 */ -#ifndef TARGET_X86_64 - if (env->eflags & VM_MASK) { - handle_vm86_fault(env); - } else -#endif - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SI_KERNEL; - info._sifields._sigfault._addr =3D 0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; - case EXCP0E_PAGE: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - if (!(env->error_code & 1)) - info.si_code =3D TARGET_SEGV_MAPERR; - else - info.si_code =3D TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr =3D env->cr[2]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP00_DIVZ: -#ifndef TARGET_X86_64 - if (env->eflags & VM_MASK) { - handle_vm86_trap(env, trapnr); - } else -#endif - { - /* division by zero */ - info.si_signo =3D TARGET_SIGFPE; - info.si_errno =3D 0; - info.si_code =3D TARGET_FPE_INTDIV; - info._sifields._sigfault._addr =3D env->eip; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; - case EXCP01_DB: - case EXCP03_INT3: -#ifndef TARGET_X86_64 - if (env->eflags & VM_MASK) { - handle_vm86_trap(env, trapnr); - } else -#endif - { - info.si_signo =3D TARGET_SIGTRAP; - info.si_errno =3D 0; - if (trapnr =3D=3D EXCP01_DB) { - info.si_code =3D TARGET_TRAP_BRKPT; - info._sifields._sigfault._addr =3D env->eip; - } else { - info.si_code =3D TARGET_SI_KERNEL; - info._sifields._sigfault._addr =3D 0; - } - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; - case EXCP04_INTO: - case EXCP05_BOUND: -#ifndef TARGET_X86_64 - if (env->eflags & VM_MASK) { - handle_vm86_trap(env, trapnr); - } else -#endif - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SI_KERNEL; - info._sifields._sigfault._addr =3D 0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; - case EXCP06_ILLOP: - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D TARGET_ILL_ILLOPN; - info._sifields._sigfault._addr =3D env->eip; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_INTERRUPT: - /* just indicate that signals should be handled asap */ - break; - case EXCP_DEBUG: - { - int sig; - - sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (sig) - { - info.si_signo =3D sig; - info.si_errno =3D 0; - info.si_code =3D TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - } - break; - case EXCP_ATOMIC: - cpu_exec_step_atomic(cs); - break; - default: - pc =3D env->segs[R_CS].base + env->eip; - EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - = aborting\n", - (long)pc, trapnr); - abort(); - } - process_pending_signals(env); - } -} -#endif - #ifdef TARGET_ARM =20 #define get_user_code_u32(x, gaddr, env) \ @@ -4724,121 +4492,7 @@ int main(int argc, char **argv, char **envp) =20 target_cpu_copy_regs(env, regs); =20 -#if defined(TARGET_I386) - env->cr[0] =3D CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; - env->hflags |=3D HF_PE_MASK | HF_CPL_MASK; - if (env->features[FEAT_1_EDX] & CPUID_SSE) { - env->cr[4] |=3D CR4_OSFXSR_MASK; - env->hflags |=3D HF_OSFXSR_MASK; - } -#ifndef TARGET_ABI32 - /* enable 64 bit mode if possible */ - if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) { - fprintf(stderr, "The selected x86 CPU does not support 64 bit mode= \n"); - exit(EXIT_FAILURE); - } - env->cr[4] |=3D CR4_PAE_MASK; - env->efer |=3D MSR_EFER_LMA | MSR_EFER_LME; - env->hflags |=3D HF_LMA_MASK; -#endif - - /* flags setup : we activate the IRQs by default as in user mode */ - env->eflags |=3D IF_MASK; - - /* linux register setup */ -#ifndef TARGET_ABI32 - env->regs[R_EAX] =3D regs->rax; - env->regs[R_EBX] =3D regs->rbx; - env->regs[R_ECX] =3D regs->rcx; - env->regs[R_EDX] =3D regs->rdx; - env->regs[R_ESI] =3D regs->rsi; - env->regs[R_EDI] =3D regs->rdi; - env->regs[R_EBP] =3D regs->rbp; - env->regs[R_ESP] =3D regs->rsp; - env->eip =3D regs->rip; -#else - env->regs[R_EAX] =3D regs->eax; - env->regs[R_EBX] =3D regs->ebx; - env->regs[R_ECX] =3D regs->ecx; - env->regs[R_EDX] =3D regs->edx; - env->regs[R_ESI] =3D regs->esi; - env->regs[R_EDI] =3D regs->edi; - env->regs[R_EBP] =3D regs->ebp; - env->regs[R_ESP] =3D regs->esp; - env->eip =3D regs->eip; -#endif - - /* linux interrupt setup */ -#ifndef TARGET_ABI32 - env->idt.limit =3D 511; -#else - env->idt.limit =3D 255; -#endif - env->idt.base =3D target_mmap(0, sizeof(uint64_t) * (env->idt.limit + = 1), - PROT_READ|PROT_WRITE, - MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); - idt_table =3D g2h(env->idt.base); - set_idt(0, 0); - set_idt(1, 0); - set_idt(2, 0); - set_idt(3, 3); - set_idt(4, 3); - set_idt(5, 0); - set_idt(6, 0); - set_idt(7, 0); - set_idt(8, 0); - set_idt(9, 0); - set_idt(10, 0); - set_idt(11, 0); - set_idt(12, 0); - set_idt(13, 0); - set_idt(14, 0); - set_idt(15, 0); - set_idt(16, 0); - set_idt(17, 0); - set_idt(18, 0); - set_idt(19, 0); - set_idt(0x80, 3); - - /* linux segment setup */ - { - uint64_t *gdt_table; - env->gdt.base =3D target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENT= RIES, - PROT_READ|PROT_WRITE, - MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); - env->gdt.limit =3D sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; - gdt_table =3D g2h(env->gdt.base); -#ifdef TARGET_ABI32 - write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, - DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | - (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); -#else - /* 64 bit code segment */ - write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, - DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | - DESC_L_MASK | - (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); -#endif - write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff, - DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | - (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT)); - } - cpu_x86_load_seg(env, R_CS, __USER_CS); - cpu_x86_load_seg(env, R_SS, __USER_DS); -#ifdef TARGET_ABI32 - cpu_x86_load_seg(env, R_DS, __USER_DS); - cpu_x86_load_seg(env, R_ES, __USER_DS); - cpu_x86_load_seg(env, R_FS, __USER_DS); - cpu_x86_load_seg(env, R_GS, __USER_DS); - /* This hack makes Wine work... */ - env->segs[R_FS].selector =3D 0; -#else - cpu_x86_load_seg(env, R_DS, 0); - cpu_x86_load_seg(env, R_ES, 0); - cpu_x86_load_seg(env, R_FS, 0); - cpu_x86_load_seg(env, R_GS, 0); -#endif -#elif defined(TARGET_AARCH64) +#if defined(TARGET_AARCH64) { int i; =20 diff --git a/linux-user/x86_64/cpu_loop.c b/linux-user/x86_64/cpu_loop.c index b7700a5561..8b5af8ea1f 100644 --- a/linux-user/x86_64/cpu_loop.c +++ b/linux-user/x86_64/cpu_loop.c @@ -17,10 +17,4 @@ * along with this program; if not, see . */ =20 -#include "qemu/osdep.h" -#include "qemu.h" -#include "cpu_loop-common.h" - -void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) -{ -} +#include "../i386/cpu_loop.c" --=20 2.14.3 From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522091930526902.3872716068443; Mon, 26 Mar 2018 12:18:50 -0700 (PDT) Received: from localhost ([::1]:58644 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xdg-0004TD-Cl for importer@patchew.org; Mon, 26 Mar 2018 15:18:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58376) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xbe-0003Cm-CT for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0Xbc-0001OL-Vl for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:34 -0400 Received: from mout.kundenserver.de ([212.227.126.135]:56185) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0Xbc-0001Mi-Kq; Mon, 26 Mar 2018 15:16:32 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0M47EN-1ejHdP1w3f-00rpMQ; Mon, 26 Mar 2018 21:16:20 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:15:47 +0200 Message-Id: <20180326191603.10217-4-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:JS1HHyhuTgiaYS30sJHt+D98Ff8qI9nkauIVRpDrTZoUlGjEwJh lsChkROW8ZtoRXHP0iQqKidyeb8n5v7DmqrHHeEywqTvOe7YwP9ZhRbtIzatkqLg+j114hS yuRHah25ER/lkWjO7++klFIgsKkCHwGxo828s6J+bQ6R0PO9ocUAleuvfAZGhLB5va2eXS9 6luhqdqclQsPj8rsjMSLg== X-UI-Out-Filterresults: notjunk:1;V01:K0:1Cr4rlUCe1I=:Mt2Sorb4dRyQxxuBN4dDse +gWxqL6366lKfEm0bH7RQJ4b1IM++6pFkqQ1ul1bn/jj6CvOR1Gk1U3RiwbFA4y8aPIal4aPq IXlfFjl5XxQhPBW51btFTznmQQH3cYtl2D2OoN0supnVygI49woSwIs9yd12h8dCzxCrxi9Tj OZi0n9BT7iR5GOz69PVmNnKYteRe8pd4p9r3/3bWK26zsew0LmbgIOLUHPnZG7HAiw1RZjaWD nZFtDPvG+jWorNthq3fJsz7ALDMY64iIzdnNLmkNmUbM36+/CBVpRDd1rfYkB1VvZOX5zLmAm 0DrygZoCa0pOOhvd/SAJQzz1FMU4V5uAbpyN6k34XJ/++bWSRQC5VLQkNGfAfGnOpk3Z41qbl N2qQ+r3grNHy4celtisxURVOn1jhqrjuK4A+hYdG2McLNtNYyjgVgw6FNBqDs23pfm2qmuLX0 IG1z1rv/hWTIO47LHrCymWrz1Wmi6VLMc2HVHJ9YuFpwsOJ2AXxYoELNmsEK65su7LrmVghS9 cphdNkCCEqEg61xHPIISoH6Y+SfG9967ocH80DWzBJbSgCr1GrdDUxme6QDhceMbN7MVBXSWy ofnkuMhsWUTk4fhJtxujEA4Zp+zwNpBWH6BtmBQXnir5HT88MdOEhr1clikztDvEP5xShhm/Z ewWFyBeqhKzUlNmZDfJsb0lj2eI2hIrvCQ1wqIpAL07R7LW4s4/V05dkgTn86GHIH0aHzhsQq U+dBvrZfSsVOZlJJQj6W6O4LrDRTyFL5DpcBmQ== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.135 Subject: [Qemu-devel] [PATCH for 2.13 03/19] linux-user: move aarch64 cpu loop to aarch64 directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to aarch64/cpu_loop.c and duplicate some macro defined for both arm and aarch64. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 156 ++++++++++++++++++++++++++++++++++++++= ++++ linux-user/main.c | 109 +---------------------------- 2 files changed, 158 insertions(+), 107 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index b7700a5561..c97a646546 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -21,6 +21,162 @@ #include "qemu.h" #include "cpu_loop-common.h" =20 +#define get_user_code_u32(x, gaddr, env) \ + ({ abi_long __r =3D get_user_u32((x), (gaddr)); \ + if (!__r && bswap_code(arm_sctlr_b(env))) { \ + (x) =3D bswap32(x); \ + } \ + __r; \ + }) + +#define get_user_code_u16(x, gaddr, env) \ + ({ abi_long __r =3D get_user_u16((x), (gaddr)); \ + if (!__r && bswap_code(arm_sctlr_b(env))) { \ + (x) =3D bswap16(x); \ + } \ + __r; \ + }) + +#define get_user_data_u32(x, gaddr, env) \ + ({ abi_long __r =3D get_user_u32((x), (gaddr)); \ + if (!__r && arm_cpu_bswap_data(env)) { \ + (x) =3D bswap32(x); \ + } \ + __r; \ + }) + +#define get_user_data_u16(x, gaddr, env) \ + ({ abi_long __r =3D get_user_u16((x), (gaddr)); \ + if (!__r && arm_cpu_bswap_data(env)) { \ + (x) =3D bswap16(x); \ + } \ + __r; \ + }) + +#define put_user_data_u32(x, gaddr, env) \ + ({ typeof(x) __x =3D (x); \ + if (arm_cpu_bswap_data(env)) { \ + __x =3D bswap32(__x); \ + } \ + put_user_u32(__x, (gaddr)); \ + }) + +#define put_user_data_u16(x, gaddr, env) \ + ({ typeof(x) __x =3D (x); \ + if (arm_cpu_bswap_data(env)) { \ + __x =3D bswap16(__x); \ + } \ + put_user_u16(__x, (gaddr)); \ + }) + +/* AArch64 main loop */ +void cpu_loop(CPUARMState *env) +{ + CPUState *cs =3D CPU(arm_env_get_cpu(env)); + int trapnr, sig; + abi_long ret; + target_siginfo_t info; + + for (;;) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch (trapnr) { + case EXCP_SWI: + ret =3D do_syscall(env, + env->xregs[8], + env->xregs[0], + env->xregs[1], + env->xregs[2], + env->xregs[3], + env->xregs[4], + env->xregs[5], + 0, 0); + if (ret =3D=3D -TARGET_ERESTARTSYS) { + env->pc -=3D 4; + } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { + env->xregs[0] =3D ret; + } + break; + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case EXCP_UDEF: + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D TARGET_ILL_ILLOPN; + info._sifields._sigfault._addr =3D env->pc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_PREFETCH_ABORT: + case EXCP_DATA_ABORT: + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + /* XXX: check env->error_code */ + info.si_code =3D TARGET_SEGV_MAPERR; + info._sifields._sigfault._addr =3D env->exception.vaddress; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_DEBUG: + case EXCP_BKPT: + sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); + if (sig) { + info.si_signo =3D sig; + info.si_errno =3D 0; + info.si_code =3D TARGET_TRAP_BRKPT; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + break; + case EXCP_SEMIHOST: + env->xregs[0] =3D do_arm_semihosting(env); + break; + case EXCP_YIELD: + /* nothing to do here for user-mode, just resume guest code */ + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + default: + EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\= n", trapnr); + abort(); + } + process_pending_signals(env); + /* Exception return on AArch64 always clears the exclusive monitor, + * so any return to running guest code implies this. + */ + env->exclusive_addr =3D -1; + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + CPUState *cpu =3D ENV_GET_CPU(env); + TaskState *ts =3D cpu->opaque; + struct image_info *info =3D ts->info; + int i; + + if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { + fprintf(stderr, + "The selected ARM CPU does not support 64 bit mode\n"); + exit(EXIT_FAILURE); + } + + for (i =3D 0; i < 31; i++) { + env->xregs[i] =3D regs->regs[i]; + } + env->pc =3D regs->pc; + env->xregs[31] =3D regs->sp; +#ifdef TARGET_WORDS_BIGENDIAN + env->cp15.sctlr_el[1] |=3D SCTLR_E0E; + for (i =3D 1; i < 4; ++i) { + env->cp15.sctlr_el[i] |=3D SCTLR_EE; + } +#endif + + ts->stack_base =3D info->start_stack; + ts->heap_base =3D info->brk; + /* This will be filled in on the first SYS_HEAPINFO call. */ + ts->heap_limit =3D 0; } diff --git a/linux-user/main.c b/linux-user/main.c index 0b792024ce..40be5cf201 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -555,89 +555,6 @@ void cpu_loop(CPUARMState *env) process_pending_signals(env); } } - -#else - -/* AArch64 main loop */ -void cpu_loop(CPUARMState *env) -{ - CPUState *cs =3D CPU(arm_env_get_cpu(env)); - int trapnr, sig; - abi_long ret; - target_siginfo_t info; - - for (;;) { - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - switch (trapnr) { - case EXCP_SWI: - ret =3D do_syscall(env, - env->xregs[8], - env->xregs[0], - env->xregs[1], - env->xregs[2], - env->xregs[3], - env->xregs[4], - env->xregs[5], - 0, 0); - if (ret =3D=3D -TARGET_ERESTARTSYS) { - env->pc -=3D 4; - } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { - env->xregs[0] =3D ret; - } - break; - case EXCP_INTERRUPT: - /* just indicate that signals should be handled asap */ - break; - case EXCP_UDEF: - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D TARGET_ILL_ILLOPN; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_PREFETCH_ABORT: - case EXCP_DATA_ABORT: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->exception.vaddress; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_DEBUG: - case EXCP_BKPT: - sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (sig) { - info.si_signo =3D sig; - info.si_errno =3D 0; - info.si_code =3D TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; - case EXCP_SEMIHOST: - env->xregs[0] =3D do_arm_semihosting(env); - break; - case EXCP_YIELD: - /* nothing to do here for user-mode, just resume guest code */ - break; - case EXCP_ATOMIC: - cpu_exec_step_atomic(cs); - break; - default: - EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\= n", trapnr); - abort(); - } - process_pending_signals(env); - /* Exception return on AArch64 always clears the exclusive monitor, - * so any return to running guest code implies this. - */ - env->exclusive_addr =3D -1; - } -} #endif /* ndef TARGET_ABI32 */ =20 #endif @@ -4492,29 +4409,7 @@ int main(int argc, char **argv, char **envp) =20 target_cpu_copy_regs(env, regs); =20 -#if defined(TARGET_AARCH64) - { - int i; - - if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { - fprintf(stderr, - "The selected ARM CPU does not support 64 bit mode\n"); - exit(EXIT_FAILURE); - } - - for (i =3D 0; i < 31; i++) { - env->xregs[i] =3D regs->regs[i]; - } - env->pc =3D regs->pc; - env->xregs[31] =3D regs->sp; -#ifdef TARGET_WORDS_BIGENDIAN - env->cp15.sctlr_el[1] |=3D SCTLR_E0E; - for (i =3D 1; i < 4; ++i) { - env->cp15.sctlr_el[i] |=3D SCTLR_EE; - } -#endif - } -#elif defined(TARGET_ARM) +#if defined(TARGET_ARM) && !defined(TARGET_AARCH64) { int i; cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC, @@ -4769,7 +4664,7 @@ int main(int argc, char **argv, char **envp) } #endif =20 -#if defined(TARGET_ARM) || defined(TARGET_M68K) +#if (defined(TARGET_ARM) && !defined(TARGET_AARCH64)) || defined(TARGET_M6= 8K) ts->stack_base =3D info->start_stack; ts->heap_base =3D info->brk; /* This will be filled in on the first SYS_HEAPINFO call. */ --=20 2.14.3 From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522092097827332.181962056365; Mon, 26 Mar 2018 12:21:37 -0700 (PDT) Received: from localhost ([::1]:58667 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0XgW-0007My-SQ for importer@patchew.org; Mon, 26 Mar 2018 15:21:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58561) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xbs-0003NX-9l for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0Xbo-0001cs-Tt for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:48 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:47973) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0Xbg-0001SF-IC; Mon, 26 Mar 2018 15:16:36 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MReYO-1f77Cn3gK0-00SiE5; Mon, 26 Mar 2018 21:16:22 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:15:48 +0200 Message-Id: <20180326191603.10217-5-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:8B16CMBKucg2y+/Y6OSrphH//9jwRR5CdBa5cac+I7al9fXBjz+ tYbeZ+C7gac3+hmVuZODfxlglejlIBfIGsRP/lEtSQ45cdSLlv9uAqB9HCmxuX2MSaUqXAo FsB1YB1jSr8mGMGJcUUmGa0XEGnMlyRyPlG9SF+VLn7QYytfEVjNatpRcWg53W4ODPw0PY6 fwJPOxWKj1+kGtj0rSinQ== X-UI-Out-Filterresults: notjunk:1;V01:K0:l2rusAnjvEQ=:ar6sEn4EHJFDH/Gh4L5gpf ldyP4RDPkg45MrPFE1+lNbBnc7VQ7pdns12A955wyO+K2cCwdxpVFLm89bCtitSbpPg+GzNQm xYReGbww4lrFa0GNGBhRG65kbtCUHQdTwWM56eRzaWZpWQtUpf5Ht2NvuqD3y4Wbrx9pIEv/0 QxSfUZx/k7BCZzK1GBLzgiHnKwT0izjA9tRrjklIWYmR35JqhkCqzWY0XvqJzHT0ksPPWnXsE 4UeRHjzjfU4FIDWwOkdIgOl55eYkeGQd/dBP4igpUA7b4wqn5Rrq31SQl9M4c56fOImDRMGkp /hctkNFkUa3bbe4iya/+RxT3nr5erpZowuXD7bA2orLKKovv36ay+C9TvAvFccsykVdoGikDz cFTzKiOTpuh2NyFyGcwT7FUOLzhdegnjXxmP9sl1LVx3ov5UMIFR31W1rmhXntxesBOWJNAGU GAIm7S1hK8PE9SlKeVXpuc3AaMiR2rFsEBqF+W6RXlBQSpIX7MbmZ+1LdfEgWVnfP7qL7hcq3 OnKI5ctYILfVGzTBjrmpRGWE4kJidKpG9BloNDlkRFpejhHnFRTGTYMiRVzU17fOVpdlvB6Bj zXOUpa1sF8kcDz03oPYkFxILbNiJ+9vIrNBhi+8xoYch+H54iaypdVm1TDGyKiJ2XAmevopgd SYhj50Xy1/PKxotoHv79+C32Y/hqFxPfmkdP8VCMOiIQuxNYJBa85YuUyxt3P7/kNW+/zHKR5 PsFxCDJdtMKLwthvBd6m6TanVQRSDvBeF+/9pg== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PATCH for 2.13 04/19] linux-user: move arm cpu loop to arm directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to arm/cpu_loop.c and duplicate some macro defined for both arm and aarch64. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- linux-user/arm/cpu_loop.c | 430 ++++++++++++++++++++++++++++++++++++++++++= +++ linux-user/main.c | 433 +-----------------------------------------= ---- 2 files changed, 432 insertions(+), 431 deletions(-) diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index b7700a5561..d911929bf6 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -19,8 +19,438 @@ =20 #include "qemu/osdep.h" #include "qemu.h" +#include "elf.h" #include "cpu_loop-common.h" =20 +#define get_user_code_u32(x, gaddr, env) \ + ({ abi_long __r =3D get_user_u32((x), (gaddr)); \ + if (!__r && bswap_code(arm_sctlr_b(env))) { \ + (x) =3D bswap32(x); \ + } \ + __r; \ + }) + +#define get_user_code_u16(x, gaddr, env) \ + ({ abi_long __r =3D get_user_u16((x), (gaddr)); \ + if (!__r && bswap_code(arm_sctlr_b(env))) { \ + (x) =3D bswap16(x); \ + } \ + __r; \ + }) + +#define get_user_data_u32(x, gaddr, env) \ + ({ abi_long __r =3D get_user_u32((x), (gaddr)); \ + if (!__r && arm_cpu_bswap_data(env)) { \ + (x) =3D bswap32(x); \ + } \ + __r; \ + }) + +#define get_user_data_u16(x, gaddr, env) \ + ({ abi_long __r =3D get_user_u16((x), (gaddr)); \ + if (!__r && arm_cpu_bswap_data(env)) { \ + (x) =3D bswap16(x); \ + } \ + __r; \ + }) + +#define put_user_data_u32(x, gaddr, env) \ + ({ typeof(x) __x =3D (x); \ + if (arm_cpu_bswap_data(env)) { \ + __x =3D bswap32(__x); \ + } \ + put_user_u32(__x, (gaddr)); \ + }) + +#define put_user_data_u16(x, gaddr, env) \ + ({ typeof(x) __x =3D (x); \ + if (arm_cpu_bswap_data(env)) { \ + __x =3D bswap16(__x); \ + } \ + put_user_u16(__x, (gaddr)); \ + }) + +/* Commpage handling -- there is no commpage for AArch64 */ + +/* + * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt + * Input: + * r0 =3D pointer to oldval + * r1 =3D pointer to newval + * r2 =3D pointer to target value + * + * Output: + * r0 =3D 0 if *ptr was changed, non-0 if no exchange happened + * C set if *ptr was changed, clear if no exchange happened + * + * Note segv's in kernel helpers are a bit tricky, we can set the + * data address sensibly but the PC address is just the entry point. + */ +static void arm_kernel_cmpxchg64_helper(CPUARMState *env) +{ + uint64_t oldval, newval, val; + uint32_t addr, cpsr; + target_siginfo_t info; + + /* Based on the 32 bit code in do_kernel_trap */ + + /* XXX: This only works between threads, not between processes. + It's probably possible to implement this with native host + operations. However things like ldrex/strex are much harder so + there's not much point trying. */ + start_exclusive(); + cpsr =3D cpsr_read(env); + addr =3D env->regs[2]; + + if (get_user_u64(oldval, env->regs[0])) { + env->exception.vaddress =3D env->regs[0]; + goto segv; + }; + + if (get_user_u64(newval, env->regs[1])) { + env->exception.vaddress =3D env->regs[1]; + goto segv; + }; + + if (get_user_u64(val, addr)) { + env->exception.vaddress =3D addr; + goto segv; + } + + if (val =3D=3D oldval) { + val =3D newval; + + if (put_user_u64(val, addr)) { + env->exception.vaddress =3D addr; + goto segv; + }; + + env->regs[0] =3D 0; + cpsr |=3D CPSR_C; + } else { + env->regs[0] =3D -1; + cpsr &=3D ~CPSR_C; + } + cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); + end_exclusive(); + return; + +segv: + end_exclusive(); + /* We get the PC of the entry address - which is as good as anything, + on a real kernel what you get depends on which mode it uses. */ + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + /* XXX: check env->error_code */ + info.si_code =3D TARGET_SEGV_MAPERR; + info._sifields._sigfault._addr =3D env->exception.vaddress; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); +} + +/* Handle a jump to the kernel code page. */ +static int +do_kernel_trap(CPUARMState *env) +{ + uint32_t addr; + uint32_t cpsr; + uint32_t val; + + switch (env->regs[15]) { + case 0xffff0fa0: /* __kernel_memory_barrier */ + /* ??? No-op. Will need to do better for SMP. */ + break; + case 0xffff0fc0: /* __kernel_cmpxchg */ + /* XXX: This only works between threads, not between processes. + It's probably possible to implement this with native host + operations. However things like ldrex/strex are much harder so + there's not much point trying. */ + start_exclusive(); + cpsr =3D cpsr_read(env); + addr =3D env->regs[2]; + /* FIXME: This should SEGV if the access fails. */ + if (get_user_u32(val, addr)) + val =3D ~env->regs[0]; + if (val =3D=3D env->regs[0]) { + val =3D env->regs[1]; + /* FIXME: Check for segfaults. */ + put_user_u32(val, addr); + env->regs[0] =3D 0; + cpsr |=3D CPSR_C; + } else { + env->regs[0] =3D -1; + cpsr &=3D ~CPSR_C; + } + cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); + end_exclusive(); + break; + case 0xffff0fe0: /* __kernel_get_tls */ + env->regs[0] =3D cpu_get_tls(env); + break; + case 0xffff0f60: /* __kernel_cmpxchg64 */ + arm_kernel_cmpxchg64_helper(env); + break; + + default: + return 1; + } + /* Jump back to the caller. */ + addr =3D env->regs[14]; + if (addr & 1) { + env->thumb =3D 1; + addr &=3D ~1; + } + env->regs[15] =3D addr; + + return 0; +} + +void cpu_loop(CPUARMState *env) +{ + CPUState *cs =3D CPU(arm_env_get_cpu(env)); + int trapnr; + unsigned int n, insn; + target_siginfo_t info; + uint32_t addr; + abi_ulong ret; + + for(;;) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch(trapnr) { + case EXCP_UDEF: + case EXCP_NOCP: + case EXCP_INVSTATE: + { + TaskState *ts =3D cs->opaque; + uint32_t opcode; + int rc; + + /* we handle the FPU emulation here, as Linux */ + /* we get the opcode */ + /* FIXME - what to do if get_user() fails? */ + get_user_code_u32(opcode, env->regs[15], env); + + rc =3D EmulateAll(opcode, &ts->fpa, env); + if (rc =3D=3D 0) { /* illegal instruction */ + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D TARGET_ILL_ILLOPN; + info._sifields._sigfault._addr =3D env->regs[15]; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } else if (rc < 0) { /* FP exception */ + int arm_fpe=3D0; + + /* translate softfloat flags to FPSR flags */ + if (-rc & float_flag_invalid) + arm_fpe |=3D BIT_IOC; + if (-rc & float_flag_divbyzero) + arm_fpe |=3D BIT_DZC; + if (-rc & float_flag_overflow) + arm_fpe |=3D BIT_OFC; + if (-rc & float_flag_underflow) + arm_fpe |=3D BIT_UFC; + if (-rc & float_flag_inexact) + arm_fpe |=3D BIT_IXC; + + FPSR fpsr =3D ts->fpa.fpsr; + //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe); + + if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ + info.si_signo =3D TARGET_SIGFPE; + info.si_errno =3D 0; + + /* ordered by priority, least first */ + if (arm_fpe & BIT_IXC) info.si_code =3D TARGET_FPE_F= LTRES; + if (arm_fpe & BIT_UFC) info.si_code =3D TARGET_FPE_F= LTUND; + if (arm_fpe & BIT_OFC) info.si_code =3D TARGET_FPE_F= LTOVF; + if (arm_fpe & BIT_DZC) info.si_code =3D TARGET_FPE_F= LTDIV; + if (arm_fpe & BIT_IOC) info.si_code =3D TARGET_FPE_F= LTINV; + + info._sifields._sigfault._addr =3D env->regs[15]; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &inf= o); + } else { + env->regs[15] +=3D 4; + } + + /* accumulate unenabled exceptions */ + if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) + fpsr |=3D BIT_IXC; + if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) + fpsr |=3D BIT_UFC; + if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) + fpsr |=3D BIT_OFC; + if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) + fpsr |=3D BIT_DZC; + if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) + fpsr |=3D BIT_IOC; + ts->fpa.fpsr=3Dfpsr; + } else { /* everything OK */ + /* increment PC */ + env->regs[15] +=3D 4; + } + } + break; + case EXCP_SWI: + case EXCP_BKPT: + { + env->eabi =3D 1; + /* system call */ + if (trapnr =3D=3D EXCP_BKPT) { + if (env->thumb) { + /* FIXME - what to do if get_user() fails? */ + get_user_code_u16(insn, env->regs[15], env); + n =3D insn & 0xff; + env->regs[15] +=3D 2; + } else { + /* FIXME - what to do if get_user() fails? */ + get_user_code_u32(insn, env->regs[15], env); + n =3D (insn & 0xf) | ((insn >> 4) & 0xff0); + env->regs[15] +=3D 4; + } + } else { + if (env->thumb) { + /* FIXME - what to do if get_user() fails? */ + get_user_code_u16(insn, env->regs[15] - 2, env); + n =3D insn & 0xff; + } else { + /* FIXME - what to do if get_user() fails? */ + get_user_code_u32(insn, env->regs[15] - 4, env); + n =3D insn & 0xffffff; + } + } + + if (n =3D=3D ARM_NR_cacheflush) { + /* nop */ + } else if (n =3D=3D ARM_NR_semihosting + || n =3D=3D ARM_NR_thumb_semihosting) { + env->regs[0] =3D do_arm_semihosting (env); + } else if (n =3D=3D 0 || n >=3D ARM_SYSCALL_BASE || env->t= humb) { + /* linux syscall */ + if (env->thumb || n =3D=3D 0) { + n =3D env->regs[7]; + } else { + n -=3D ARM_SYSCALL_BASE; + env->eabi =3D 0; + } + if ( n > ARM_NR_BASE) { + switch (n) { + case ARM_NR_cacheflush: + /* nop */ + break; + case ARM_NR_set_tls: + cpu_set_tls(env, env->regs[0]); + env->regs[0] =3D 0; + break; + case ARM_NR_breakpoint: + env->regs[15] -=3D env->thumb ? 2 : 4; + goto excp_debug; + default: + gemu_log("qemu: Unsupported ARM syscall: 0x%x\= n", + n); + env->regs[0] =3D -TARGET_ENOSYS; + break; + } + } else { + ret =3D do_syscall(env, + n, + env->regs[0], + env->regs[1], + env->regs[2], + env->regs[3], + env->regs[4], + env->regs[5], + 0, 0); + if (ret =3D=3D -TARGET_ERESTARTSYS) { + env->regs[15] -=3D env->thumb ? 2 : 4; + } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { + env->regs[0] =3D ret; + } + } + } else { + goto error; + } + } + break; + case EXCP_SEMIHOST: + env->regs[0] =3D do_arm_semihosting(env); + break; + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case EXCP_PREFETCH_ABORT: + case EXCP_DATA_ABORT: + addr =3D env->exception.vaddress; + { + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + /* XXX: check env->error_code */ + info.si_code =3D TARGET_SEGV_MAPERR; + info._sifields._sigfault._addr =3D addr; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + break; + case EXCP_DEBUG: + excp_debug: + { + int sig; + + sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); + if (sig) + { + info.si_signo =3D sig; + info.si_errno =3D 0; + info.si_code =3D TARGET_TRAP_BRKPT; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + } + break; + case EXCP_KERNEL_TRAP: + if (do_kernel_trap(env)) + goto error; + break; + case EXCP_YIELD: + /* nothing to do here for user-mode, just resume guest code */ + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + default: + error: + EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\= n", trapnr); + abort(); + } + process_pending_signals(env); + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + CPUState *cpu =3D ENV_GET_CPU(env); + TaskState *ts =3D cpu->opaque; + struct image_info *info =3D ts->info; + int i; + + cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC, + CPSRWriteByInstr); + for(i =3D 0; i < 16; i++) { + env->regs[i] =3D regs->uregs[i]; + } +#ifdef TARGET_WORDS_BIGENDIAN + /* Enable BE8. */ + if (EF_ARM_EABI_VERSION(info->elf_flags) >=3D EF_ARM_EABI_VER4 + && (info->elf_flags & EF_ARM_BE8)) { + env->uncached_cpsr |=3D CPSR_E; + env->cp15.sctlr_el[1] |=3D SCTLR_E0E; + } else { + env->cp15.sctlr_el[1] |=3D SCTLR_B; + } +#endif + + ts->stack_base =3D info->start_stack; + ts->heap_base =3D info->brk; + /* This will be filled in on the first SYS_HEAPINFO call. */ + ts->heap_limit =3D 0; } diff --git a/linux-user/main.c b/linux-user/main.c index 40be5cf201..f8ea0c8b96 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -149,416 +149,6 @@ void fork_end(int child) } } =20 -#ifdef TARGET_ARM - -#define get_user_code_u32(x, gaddr, env) \ - ({ abi_long __r =3D get_user_u32((x), (gaddr)); \ - if (!__r && bswap_code(arm_sctlr_b(env))) { \ - (x) =3D bswap32(x); \ - } \ - __r; \ - }) - -#define get_user_code_u16(x, gaddr, env) \ - ({ abi_long __r =3D get_user_u16((x), (gaddr)); \ - if (!__r && bswap_code(arm_sctlr_b(env))) { \ - (x) =3D bswap16(x); \ - } \ - __r; \ - }) - -#define get_user_data_u32(x, gaddr, env) \ - ({ abi_long __r =3D get_user_u32((x), (gaddr)); \ - if (!__r && arm_cpu_bswap_data(env)) { \ - (x) =3D bswap32(x); \ - } \ - __r; \ - }) - -#define get_user_data_u16(x, gaddr, env) \ - ({ abi_long __r =3D get_user_u16((x), (gaddr)); \ - if (!__r && arm_cpu_bswap_data(env)) { \ - (x) =3D bswap16(x); \ - } \ - __r; \ - }) - -#define put_user_data_u32(x, gaddr, env) \ - ({ typeof(x) __x =3D (x); \ - if (arm_cpu_bswap_data(env)) { \ - __x =3D bswap32(__x); \ - } \ - put_user_u32(__x, (gaddr)); \ - }) - -#define put_user_data_u16(x, gaddr, env) \ - ({ typeof(x) __x =3D (x); \ - if (arm_cpu_bswap_data(env)) { \ - __x =3D bswap16(__x); \ - } \ - put_user_u16(__x, (gaddr)); \ - }) - -#ifdef TARGET_ABI32 -/* Commpage handling -- there is no commpage for AArch64 */ - -/* - * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt - * Input: - * r0 =3D pointer to oldval - * r1 =3D pointer to newval - * r2 =3D pointer to target value - * - * Output: - * r0 =3D 0 if *ptr was changed, non-0 if no exchange happened - * C set if *ptr was changed, clear if no exchange happened - * - * Note segv's in kernel helpers are a bit tricky, we can set the - * data address sensibly but the PC address is just the entry point. - */ -static void arm_kernel_cmpxchg64_helper(CPUARMState *env) -{ - uint64_t oldval, newval, val; - uint32_t addr, cpsr; - target_siginfo_t info; - - /* Based on the 32 bit code in do_kernel_trap */ - - /* XXX: This only works between threads, not between processes. - It's probably possible to implement this with native host - operations. However things like ldrex/strex are much harder so - there's not much point trying. */ - start_exclusive(); - cpsr =3D cpsr_read(env); - addr =3D env->regs[2]; - - if (get_user_u64(oldval, env->regs[0])) { - env->exception.vaddress =3D env->regs[0]; - goto segv; - }; - - if (get_user_u64(newval, env->regs[1])) { - env->exception.vaddress =3D env->regs[1]; - goto segv; - }; - - if (get_user_u64(val, addr)) { - env->exception.vaddress =3D addr; - goto segv; - } - - if (val =3D=3D oldval) { - val =3D newval; - - if (put_user_u64(val, addr)) { - env->exception.vaddress =3D addr; - goto segv; - }; - - env->regs[0] =3D 0; - cpsr |=3D CPSR_C; - } else { - env->regs[0] =3D -1; - cpsr &=3D ~CPSR_C; - } - cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); - end_exclusive(); - return; - -segv: - end_exclusive(); - /* We get the PC of the entry address - which is as good as anything, - on a real kernel what you get depends on which mode it uses. */ - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->exception.vaddress; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); -} - -/* Handle a jump to the kernel code page. */ -static int -do_kernel_trap(CPUARMState *env) -{ - uint32_t addr; - uint32_t cpsr; - uint32_t val; - - switch (env->regs[15]) { - case 0xffff0fa0: /* __kernel_memory_barrier */ - /* ??? No-op. Will need to do better for SMP. */ - break; - case 0xffff0fc0: /* __kernel_cmpxchg */ - /* XXX: This only works between threads, not between processes. - It's probably possible to implement this with native host - operations. However things like ldrex/strex are much harder so - there's not much point trying. */ - start_exclusive(); - cpsr =3D cpsr_read(env); - addr =3D env->regs[2]; - /* FIXME: This should SEGV if the access fails. */ - if (get_user_u32(val, addr)) - val =3D ~env->regs[0]; - if (val =3D=3D env->regs[0]) { - val =3D env->regs[1]; - /* FIXME: Check for segfaults. */ - put_user_u32(val, addr); - env->regs[0] =3D 0; - cpsr |=3D CPSR_C; - } else { - env->regs[0] =3D -1; - cpsr &=3D ~CPSR_C; - } - cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); - end_exclusive(); - break; - case 0xffff0fe0: /* __kernel_get_tls */ - env->regs[0] =3D cpu_get_tls(env); - break; - case 0xffff0f60: /* __kernel_cmpxchg64 */ - arm_kernel_cmpxchg64_helper(env); - break; - - default: - return 1; - } - /* Jump back to the caller. */ - addr =3D env->regs[14]; - if (addr & 1) { - env->thumb =3D 1; - addr &=3D ~1; - } - env->regs[15] =3D addr; - - return 0; -} - -void cpu_loop(CPUARMState *env) -{ - CPUState *cs =3D CPU(arm_env_get_cpu(env)); - int trapnr; - unsigned int n, insn; - target_siginfo_t info; - uint32_t addr; - abi_ulong ret; - - for(;;) { - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - switch(trapnr) { - case EXCP_UDEF: - case EXCP_NOCP: - case EXCP_INVSTATE: - { - TaskState *ts =3D cs->opaque; - uint32_t opcode; - int rc; - - /* we handle the FPU emulation here, as Linux */ - /* we get the opcode */ - /* FIXME - what to do if get_user() fails? */ - get_user_code_u32(opcode, env->regs[15], env); - - rc =3D EmulateAll(opcode, &ts->fpa, env); - if (rc =3D=3D 0) { /* illegal instruction */ - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D TARGET_ILL_ILLOPN; - info._sifields._sigfault._addr =3D env->regs[15]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } else if (rc < 0) { /* FP exception */ - int arm_fpe=3D0; - - /* translate softfloat flags to FPSR flags */ - if (-rc & float_flag_invalid) - arm_fpe |=3D BIT_IOC; - if (-rc & float_flag_divbyzero) - arm_fpe |=3D BIT_DZC; - if (-rc & float_flag_overflow) - arm_fpe |=3D BIT_OFC; - if (-rc & float_flag_underflow) - arm_fpe |=3D BIT_UFC; - if (-rc & float_flag_inexact) - arm_fpe |=3D BIT_IXC; - - FPSR fpsr =3D ts->fpa.fpsr; - //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe); - - if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ - info.si_signo =3D TARGET_SIGFPE; - info.si_errno =3D 0; - - /* ordered by priority, least first */ - if (arm_fpe & BIT_IXC) info.si_code =3D TARGET_FPE_F= LTRES; - if (arm_fpe & BIT_UFC) info.si_code =3D TARGET_FPE_F= LTUND; - if (arm_fpe & BIT_OFC) info.si_code =3D TARGET_FPE_F= LTOVF; - if (arm_fpe & BIT_DZC) info.si_code =3D TARGET_FPE_F= LTDIV; - if (arm_fpe & BIT_IOC) info.si_code =3D TARGET_FPE_F= LTINV; - - info._sifields._sigfault._addr =3D env->regs[15]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &inf= o); - } else { - env->regs[15] +=3D 4; - } - - /* accumulate unenabled exceptions */ - if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) - fpsr |=3D BIT_IXC; - if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) - fpsr |=3D BIT_UFC; - if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) - fpsr |=3D BIT_OFC; - if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) - fpsr |=3D BIT_DZC; - if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) - fpsr |=3D BIT_IOC; - ts->fpa.fpsr=3Dfpsr; - } else { /* everything OK */ - /* increment PC */ - env->regs[15] +=3D 4; - } - } - break; - case EXCP_SWI: - case EXCP_BKPT: - { - env->eabi =3D 1; - /* system call */ - if (trapnr =3D=3D EXCP_BKPT) { - if (env->thumb) { - /* FIXME - what to do if get_user() fails? */ - get_user_code_u16(insn, env->regs[15], env); - n =3D insn & 0xff; - env->regs[15] +=3D 2; - } else { - /* FIXME - what to do if get_user() fails? */ - get_user_code_u32(insn, env->regs[15], env); - n =3D (insn & 0xf) | ((insn >> 4) & 0xff0); - env->regs[15] +=3D 4; - } - } else { - if (env->thumb) { - /* FIXME - what to do if get_user() fails? */ - get_user_code_u16(insn, env->regs[15] - 2, env); - n =3D insn & 0xff; - } else { - /* FIXME - what to do if get_user() fails? */ - get_user_code_u32(insn, env->regs[15] - 4, env); - n =3D insn & 0xffffff; - } - } - - if (n =3D=3D ARM_NR_cacheflush) { - /* nop */ - } else if (n =3D=3D ARM_NR_semihosting - || n =3D=3D ARM_NR_thumb_semihosting) { - env->regs[0] =3D do_arm_semihosting (env); - } else if (n =3D=3D 0 || n >=3D ARM_SYSCALL_BASE || env->t= humb) { - /* linux syscall */ - if (env->thumb || n =3D=3D 0) { - n =3D env->regs[7]; - } else { - n -=3D ARM_SYSCALL_BASE; - env->eabi =3D 0; - } - if ( n > ARM_NR_BASE) { - switch (n) { - case ARM_NR_cacheflush: - /* nop */ - break; - case ARM_NR_set_tls: - cpu_set_tls(env, env->regs[0]); - env->regs[0] =3D 0; - break; - case ARM_NR_breakpoint: - env->regs[15] -=3D env->thumb ? 2 : 4; - goto excp_debug; - default: - gemu_log("qemu: Unsupported ARM syscall: 0x%x\= n", - n); - env->regs[0] =3D -TARGET_ENOSYS; - break; - } - } else { - ret =3D do_syscall(env, - n, - env->regs[0], - env->regs[1], - env->regs[2], - env->regs[3], - env->regs[4], - env->regs[5], - 0, 0); - if (ret =3D=3D -TARGET_ERESTARTSYS) { - env->regs[15] -=3D env->thumb ? 2 : 4; - } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { - env->regs[0] =3D ret; - } - } - } else { - goto error; - } - } - break; - case EXCP_SEMIHOST: - env->regs[0] =3D do_arm_semihosting(env); - break; - case EXCP_INTERRUPT: - /* just indicate that signals should be handled asap */ - break; - case EXCP_PREFETCH_ABORT: - case EXCP_DATA_ABORT: - addr =3D env->exception.vaddress; - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D addr; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; - case EXCP_DEBUG: - excp_debug: - { - int sig; - - sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (sig) - { - info.si_signo =3D sig; - info.si_errno =3D 0; - info.si_code =3D TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - } - break; - case EXCP_KERNEL_TRAP: - if (do_kernel_trap(env)) - goto error; - break; - case EXCP_YIELD: - /* nothing to do here for user-mode, just resume guest code */ - break; - case EXCP_ATOMIC: - cpu_exec_step_atomic(cs); - break; - default: - error: - EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\= n", trapnr); - abort(); - } - process_pending_signals(env); - } -} -#endif /* ndef TARGET_ABI32 */ - -#endif - #ifdef TARGET_SPARC #define SPARC64_STACK_BIAS 2047 =20 @@ -4409,26 +3999,7 @@ int main(int argc, char **argv, char **envp) =20 target_cpu_copy_regs(env, regs); =20 -#if defined(TARGET_ARM) && !defined(TARGET_AARCH64) - { - int i; - cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC, - CPSRWriteByInstr); - for(i =3D 0; i < 16; i++) { - env->regs[i] =3D regs->uregs[i]; - } -#ifdef TARGET_WORDS_BIGENDIAN - /* Enable BE8. */ - if (EF_ARM_EABI_VERSION(info->elf_flags) >=3D EF_ARM_EABI_VER4 - && (info->elf_flags & EF_ARM_BE8)) { - env->uncached_cpsr |=3D CPSR_E; - env->cp15.sctlr_el[1] |=3D SCTLR_E0E; - } else { - env->cp15.sctlr_el[1] |=3D SCTLR_B; - } -#endif - } -#elif defined(TARGET_SPARC) +#if defined(TARGET_SPARC) { int i; env->pc =3D regs->pc; @@ -4664,7 +4235,7 @@ int main(int argc, char **argv, char **envp) } #endif =20 -#if (defined(TARGET_ARM) && !defined(TARGET_AARCH64)) || defined(TARGET_M6= 8K) +#if defined(TARGET_M68K) ts->stack_base =3D info->start_stack; ts->heap_base =3D info->brk; /* This will be filled in on the first SYS_HEAPINFO call. */ --=20 2.14.3 From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522092125759588.4034322344285; Mon, 26 Mar 2018 12:22:05 -0700 (PDT) Received: from localhost ([::1]:58670 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xgy-0007ml-Of for importer@patchew.org; Mon, 26 Mar 2018 15:22:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58550) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xbr-0003NB-Qe for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0Xbp-0001d2-4K for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:47 -0400 Received: from mout.kundenserver.de ([212.227.126.131]:58555) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0Xbh-0001Ty-Qk; Mon, 26 Mar 2018 15:16:38 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MdArm-1fIcS52POU-00IDYp; Mon, 26 Mar 2018 21:16:24 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:15:49 +0200 Message-Id: <20180326191603.10217-6-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:5qsmOuRlt9sQuoBihR2JutSmBHbVPBWMIpTAVo13ilnZfQufYHn PBSJarvsFg8AnG3K31eDp9ThOwaGopX7MveEfUulYVVJPpJvIa8DNmT2Rw9mKSANbMxkBgP IbAYJLALCmGPK3OtmlLWKxBg38FT3YNx5ev3K6oZrqphXCC6qTcvSza4mnNb9hdzAPe+zI+ laEyaBImUgAT7ReEX4TCw== X-UI-Out-Filterresults: notjunk:1;V01:K0:Ac30ifQIodk=:cb2QQN4Edb+6oOWXxbZqTD 1AjDwJkpST/PYHqVlH2PCu9r3HE/f8Az6hkaLY6ZMK+jXVpbIqgtFqMdtUrrGnb/Ve7Mn/FOx i9ave0jL16mbpQpt2OiJztq9pg/fSmrhj9Ggo5vDjCxSZMnvuSqwcbYW1ivRkkGAMmXzq5G/B NXRtdjRglGMixmbF6QDhX+GjdudAFuJuUbjuqy5AzrCtG3bdf+5qYm6lwR6kTEK+X7zg93+S0 s+tCDnGreiSPoit14s4GGAaU3rdymkIMgAz00WkVEwXLVqJpGOdomEJsP6vtFalgcIvZaFO0F zsXC+Vjg/aVf8KEkLxQbwQs2DZF78wcJ9tPSXP4itK4YWyMoeOOVHa0w6KPtV/kYh7wyhOt4R yImfU8tKfD/F+rCwJyL4nB5unp3LUPmu+y51ntjNgLscKwMEbrlPr8wLnxfui9sHm7zVWpbVL R3b0ftiMWjznxHXQXpkZcKYVYohSRvvx73SmHyQ3K9Z2sARtDf50fnLFelKpbDr5a3+8PQrnC 1oKVqU1SXxvMdGb6g3my6eQojLrp2KYPBLByVSM3BUquYWq5IZ7u/97mHXd0b3S2w2fRUxHkE ZhYURKNxGobhyFSW+diFQYU/FKmbmUVI/0KQkoatRTXmlh2WTtGt91iRaHsz0/HrVi3Fo3RlU RK/unYf6jIVleYGLrtUMuG89rvm5A7Z72LKMK2pC3aGNUK24rjti1YT0SUhHgjUCyNd6yAFJz u3qDAnVPkjL4vIHMb0d03r2/cdf5ibqz65Fw4Q== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.131 Subject: [Qemu-devel] [PATCH for 2.13 05/19] linux-user: move sparc/sparc64 cpu loop to sparc directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to sparc/cpu_loop.c. Include sparc/cpu_loop.c in sparc64/cpu_loop.c to avoid to duplicate code. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- linux-user/main.c | 288 +-------------------------------------= ---- linux-user/sparc/cpu_loop.c | 280 ++++++++++++++++++++++++++++++++++++++= ++ linux-user/sparc64/cpu_loop.c | 8 +- 3 files changed, 282 insertions(+), 294 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index f8ea0c8b96..349dcd6a20 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -149,281 +149,6 @@ void fork_end(int child) } } =20 -#ifdef TARGET_SPARC -#define SPARC64_STACK_BIAS 2047 - -//#define DEBUG_WIN - -/* WARNING: dealing with register windows _is_ complicated. More info - can be found at http://www.sics.se/~psm/sparcstack.html */ -static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) -{ - index =3D (index + cwp * 16) % (16 * env->nwindows); - /* wrap handling : if cwp is on the last window, then we use the - registers 'after' the end */ - if (index < 8 && env->cwp =3D=3D env->nwindows - 1) - index +=3D 16 * env->nwindows; - return index; -} - -/* save the register window 'cwp1' */ -static inline void save_window_offset(CPUSPARCState *env, int cwp1) -{ - unsigned int i; - abi_ulong sp_ptr; - - sp_ptr =3D env->regbase[get_reg_index(env, cwp1, 6)]; -#ifdef TARGET_SPARC64 - if (sp_ptr & 3) - sp_ptr +=3D SPARC64_STACK_BIAS; -#endif -#if defined(DEBUG_WIN) - printf("win_overflow: sp_ptr=3D0x" TARGET_ABI_FMT_lx " save_cwp=3D%d\n= ", - sp_ptr, cwp1); -#endif - for(i =3D 0; i < 16; i++) { - /* FIXME - what to do if put_user() fails? */ - put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr= ); - sp_ptr +=3D sizeof(abi_ulong); - } -} - -static void save_window(CPUSPARCState *env) -{ -#ifndef TARGET_SPARC64 - unsigned int new_wim; - new_wim =3D ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & - ((1LL << env->nwindows) - 1); - save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); - env->wim =3D new_wim; -#else - save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); - env->cansave++; - env->canrestore--; -#endif -} - -static void restore_window(CPUSPARCState *env) -{ -#ifndef TARGET_SPARC64 - unsigned int new_wim; -#endif - unsigned int i, cwp1; - abi_ulong sp_ptr; - -#ifndef TARGET_SPARC64 - new_wim =3D ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & - ((1LL << env->nwindows) - 1); -#endif - - /* restore the invalid window */ - cwp1 =3D cpu_cwp_inc(env, env->cwp + 1); - sp_ptr =3D env->regbase[get_reg_index(env, cwp1, 6)]; -#ifdef TARGET_SPARC64 - if (sp_ptr & 3) - sp_ptr +=3D SPARC64_STACK_BIAS; -#endif -#if defined(DEBUG_WIN) - printf("win_underflow: sp_ptr=3D0x" TARGET_ABI_FMT_lx " load_cwp=3D%d\= n", - sp_ptr, cwp1); -#endif - for(i =3D 0; i < 16; i++) { - /* FIXME - what to do if get_user() fails? */ - get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr= ); - sp_ptr +=3D sizeof(abi_ulong); - } -#ifdef TARGET_SPARC64 - env->canrestore++; - if (env->cleanwin < env->nwindows - 1) - env->cleanwin++; - env->cansave--; -#else - env->wim =3D new_wim; -#endif -} - -static void flush_windows(CPUSPARCState *env) -{ - int offset, cwp1; - - offset =3D 1; - for(;;) { - /* if restore would invoke restore_window(), then we can stop */ - cwp1 =3D cpu_cwp_inc(env, env->cwp + offset); -#ifndef TARGET_SPARC64 - if (env->wim & (1 << cwp1)) - break; -#else - if (env->canrestore =3D=3D 0) - break; - env->cansave++; - env->canrestore--; -#endif - save_window_offset(env, cwp1); - offset++; - } - cwp1 =3D cpu_cwp_inc(env, env->cwp + 1); -#ifndef TARGET_SPARC64 - /* set wim so that restore will reload the registers */ - env->wim =3D 1 << cwp1; -#endif -#if defined(DEBUG_WIN) - printf("flush_windows: nb=3D%d\n", offset - 1); -#endif -} - -void cpu_loop (CPUSPARCState *env) -{ - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); - int trapnr; - abi_long ret; - target_siginfo_t info; - - while (1) { - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - /* Compute PSR before exposing state. */ - if (env->cc_op !=3D CC_OP_FLAGS) { - cpu_get_psr(env); - } - - switch (trapnr) { -#ifndef TARGET_SPARC64 - case 0x88: - case 0x90: -#else - case 0x110: - case 0x16d: -#endif - ret =3D do_syscall (env, env->gregs[1], - env->regwptr[0], env->regwptr[1], - env->regwptr[2], env->regwptr[3], - env->regwptr[4], env->regwptr[5], - 0, 0); - if (ret =3D=3D -TARGET_ERESTARTSYS || ret =3D=3D -TARGET_QEMU_= ESIGRETURN) { - break; - } - if ((abi_ulong)ret >=3D (abi_ulong)(-515)) { -#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) - env->xcc |=3D PSR_CARRY; -#else - env->psr |=3D PSR_CARRY; -#endif - ret =3D -ret; - } else { -#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) - env->xcc &=3D ~PSR_CARRY; -#else - env->psr &=3D ~PSR_CARRY; -#endif - } - env->regwptr[0] =3D ret; - /* next instruction */ - env->pc =3D env->npc; - env->npc =3D env->npc + 4; - break; - case 0x83: /* flush windows */ -#ifdef TARGET_ABI32 - case 0x103: -#endif - flush_windows(env); - /* next instruction */ - env->pc =3D env->npc; - env->npc =3D env->npc + 4; - break; -#ifndef TARGET_SPARC64 - case TT_WIN_OVF: /* window overflow */ - save_window(env); - break; - case TT_WIN_UNF: /* window underflow */ - restore_window(env); - break; - case TT_TFAULT: - case TT_DFAULT: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->mmuregs[4]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; -#else - case TT_SPILL: /* window overflow */ - save_window(env); - break; - case TT_FILL: /* window underflow */ - restore_window(env); - break; - case TT_TFAULT: - case TT_DFAULT: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - if (trapnr =3D=3D TT_DFAULT) - info._sifields._sigfault._addr =3D env->dmmu.mmuregs[4= ]; - else - info._sifields._sigfault._addr =3D cpu_tsptr(env)->tpc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; -#ifndef TARGET_ABI32 - case 0x16e: - flush_windows(env); - sparc64_get_context(env); - break; - case 0x16f: - flush_windows(env); - sparc64_set_context(env); - break; -#endif -#endif - case EXCP_INTERRUPT: - /* just indicate that signals should be handled asap */ - break; - case TT_ILL_INSN: - { - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D TARGET_ILL_ILLOPC; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; - case EXCP_DEBUG: - { - int sig; - - sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (sig) - { - info.si_signo =3D sig; - info.si_errno =3D 0; - info.si_code =3D TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - } - break; - case EXCP_ATOMIC: - cpu_exec_step_atomic(cs); - break; - default: - printf ("Unhandled trap: 0x%x\n", trapnr); - cpu_dump_state(cs, stderr, fprintf, 0); - exit(EXIT_FAILURE); - } - process_pending_signals (env); - } -} - -#endif - #ifdef TARGET_PPC static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env) { @@ -3999,18 +3724,7 @@ int main(int argc, char **argv, char **envp) =20 target_cpu_copy_regs(env, regs); =20 -#if defined(TARGET_SPARC) - { - int i; - env->pc =3D regs->pc; - env->npc =3D regs->npc; - env->y =3D regs->y; - for(i =3D 0; i < 8; i++) - env->gregs[i] =3D regs->u_regs[i]; - for(i =3D 0; i < 8; i++) - env->regwptr[i] =3D regs->u_regs[i + 8]; - } -#elif defined(TARGET_PPC) +#if defined(TARGET_PPC) { int i; =20 diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index b7700a5561..7c4796ca23 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -21,6 +21,286 @@ #include "qemu.h" #include "cpu_loop-common.h" =20 +#define SPARC64_STACK_BIAS 2047 + +//#define DEBUG_WIN + +/* WARNING: dealing with register windows _is_ complicated. More info + can be found at http://www.sics.se/~psm/sparcstack.html */ +static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) +{ + index =3D (index + cwp * 16) % (16 * env->nwindows); + /* wrap handling : if cwp is on the last window, then we use the + registers 'after' the end */ + if (index < 8 && env->cwp =3D=3D env->nwindows - 1) + index +=3D 16 * env->nwindows; + return index; +} + +/* save the register window 'cwp1' */ +static inline void save_window_offset(CPUSPARCState *env, int cwp1) +{ + unsigned int i; + abi_ulong sp_ptr; + + sp_ptr =3D env->regbase[get_reg_index(env, cwp1, 6)]; +#ifdef TARGET_SPARC64 + if (sp_ptr & 3) + sp_ptr +=3D SPARC64_STACK_BIAS; +#endif +#if defined(DEBUG_WIN) + printf("win_overflow: sp_ptr=3D0x" TARGET_ABI_FMT_lx " save_cwp=3D%d\n= ", + sp_ptr, cwp1); +#endif + for(i =3D 0; i < 16; i++) { + /* FIXME - what to do if put_user() fails? */ + put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr= ); + sp_ptr +=3D sizeof(abi_ulong); + } +} + +static void save_window(CPUSPARCState *env) +{ +#ifndef TARGET_SPARC64 + unsigned int new_wim; + new_wim =3D ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & + ((1LL << env->nwindows) - 1); + save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); + env->wim =3D new_wim; +#else + save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); + env->cansave++; + env->canrestore--; +#endif +} + +static void restore_window(CPUSPARCState *env) +{ +#ifndef TARGET_SPARC64 + unsigned int new_wim; +#endif + unsigned int i, cwp1; + abi_ulong sp_ptr; + +#ifndef TARGET_SPARC64 + new_wim =3D ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & + ((1LL << env->nwindows) - 1); +#endif + + /* restore the invalid window */ + cwp1 =3D cpu_cwp_inc(env, env->cwp + 1); + sp_ptr =3D env->regbase[get_reg_index(env, cwp1, 6)]; +#ifdef TARGET_SPARC64 + if (sp_ptr & 3) + sp_ptr +=3D SPARC64_STACK_BIAS; +#endif +#if defined(DEBUG_WIN) + printf("win_underflow: sp_ptr=3D0x" TARGET_ABI_FMT_lx " load_cwp=3D%d\= n", + sp_ptr, cwp1); +#endif + for(i =3D 0; i < 16; i++) { + /* FIXME - what to do if get_user() fails? */ + get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr= ); + sp_ptr +=3D sizeof(abi_ulong); + } +#ifdef TARGET_SPARC64 + env->canrestore++; + if (env->cleanwin < env->nwindows - 1) + env->cleanwin++; + env->cansave--; +#else + env->wim =3D new_wim; +#endif +} + +static void flush_windows(CPUSPARCState *env) +{ + int offset, cwp1; + + offset =3D 1; + for(;;) { + /* if restore would invoke restore_window(), then we can stop */ + cwp1 =3D cpu_cwp_inc(env, env->cwp + offset); +#ifndef TARGET_SPARC64 + if (env->wim & (1 << cwp1)) + break; +#else + if (env->canrestore =3D=3D 0) + break; + env->cansave++; + env->canrestore--; +#endif + save_window_offset(env, cwp1); + offset++; + } + cwp1 =3D cpu_cwp_inc(env, env->cwp + 1); +#ifndef TARGET_SPARC64 + /* set wim so that restore will reload the registers */ + env->wim =3D 1 << cwp1; +#endif +#if defined(DEBUG_WIN) + printf("flush_windows: nb=3D%d\n", offset - 1); +#endif +} + +void cpu_loop (CPUSPARCState *env) +{ + CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + int trapnr; + abi_long ret; + target_siginfo_t info; + + while (1) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + /* Compute PSR before exposing state. */ + if (env->cc_op !=3D CC_OP_FLAGS) { + cpu_get_psr(env); + } + + switch (trapnr) { +#ifndef TARGET_SPARC64 + case 0x88: + case 0x90: +#else + case 0x110: + case 0x16d: +#endif + ret =3D do_syscall (env, env->gregs[1], + env->regwptr[0], env->regwptr[1], + env->regwptr[2], env->regwptr[3], + env->regwptr[4], env->regwptr[5], + 0, 0); + if (ret =3D=3D -TARGET_ERESTARTSYS || ret =3D=3D -TARGET_QEMU_= ESIGRETURN) { + break; + } + if ((abi_ulong)ret >=3D (abi_ulong)(-515)) { +#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) + env->xcc |=3D PSR_CARRY; +#else + env->psr |=3D PSR_CARRY; +#endif + ret =3D -ret; + } else { +#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) + env->xcc &=3D ~PSR_CARRY; +#else + env->psr &=3D ~PSR_CARRY; +#endif + } + env->regwptr[0] =3D ret; + /* next instruction */ + env->pc =3D env->npc; + env->npc =3D env->npc + 4; + break; + case 0x83: /* flush windows */ +#ifdef TARGET_ABI32 + case 0x103: +#endif + flush_windows(env); + /* next instruction */ + env->pc =3D env->npc; + env->npc =3D env->npc + 4; + break; +#ifndef TARGET_SPARC64 + case TT_WIN_OVF: /* window overflow */ + save_window(env); + break; + case TT_WIN_UNF: /* window underflow */ + restore_window(env); + break; + case TT_TFAULT: + case TT_DFAULT: + { + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + /* XXX: check env->error_code */ + info.si_code =3D TARGET_SEGV_MAPERR; + info._sifields._sigfault._addr =3D env->mmuregs[4]; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + break; +#else + case TT_SPILL: /* window overflow */ + save_window(env); + break; + case TT_FILL: /* window underflow */ + restore_window(env); + break; + case TT_TFAULT: + case TT_DFAULT: + { + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + /* XXX: check env->error_code */ + info.si_code =3D TARGET_SEGV_MAPERR; + if (trapnr =3D=3D TT_DFAULT) + info._sifields._sigfault._addr =3D env->dmmu.mmuregs[4= ]; + else + info._sifields._sigfault._addr =3D cpu_tsptr(env)->tpc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + break; +#ifndef TARGET_ABI32 + case 0x16e: + flush_windows(env); + sparc64_get_context(env); + break; + case 0x16f: + flush_windows(env); + sparc64_set_context(env); + break; +#endif +#endif + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case TT_ILL_INSN: + { + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D TARGET_ILL_ILLOPC; + info._sifields._sigfault._addr =3D env->pc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + break; + case EXCP_DEBUG: + { + int sig; + + sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); + if (sig) + { + info.si_signo =3D sig; + info.si_errno =3D 0; + info.si_code =3D TARGET_TRAP_BRKPT; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + } + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + default: + printf ("Unhandled trap: 0x%x\n", trapnr); + cpu_dump_state(cs, stderr, fprintf, 0); + exit(EXIT_FAILURE); + } + process_pending_signals (env); + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + int i; + env->pc =3D regs->pc; + env->npc =3D regs->npc; + env->y =3D regs->y; + for(i =3D 0; i < 8; i++) + env->gregs[i] =3D regs->u_regs[i]; + for(i =3D 0; i < 8; i++) + env->regwptr[i] =3D regs->u_regs[i + 8]; } diff --git a/linux-user/sparc64/cpu_loop.c b/linux-user/sparc64/cpu_loop.c index b7700a5561..4fd44e1b1e 100644 --- a/linux-user/sparc64/cpu_loop.c +++ b/linux-user/sparc64/cpu_loop.c @@ -17,10 +17,4 @@ * along with this program; if not, see . */ =20 -#include "qemu/osdep.h" -#include "qemu.h" -#include "cpu_loop-common.h" - -void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) -{ -} +#include "../sparc/cpu_loop.c" --=20 2.14.3 From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522091951425429.9376313753537; Mon, 26 Mar 2018 12:19:11 -0700 (PDT) Received: from localhost ([::1]:58647 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0XeA-0004rI-Cx for importer@patchew.org; Mon, 26 Mar 2018 15:19:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58497) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xbo-0003KK-Pl for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0Xbk-0001YA-KU for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:44 -0400 Received: from mout.kundenserver.de ([212.227.126.135]:53081) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0Xbk-0001X3-26; Mon, 26 Mar 2018 15:16:40 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0LqrfL-1eNN2Q1DUZ-00eZpS; Mon, 26 Mar 2018 21:16:26 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:15:50 +0200 Message-Id: <20180326191603.10217-7-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:zRrv1fmBy41hg7nnWt4YrA1a9Cj/wZ0sxR5a8PATYHQRSo+AN6X Wnvw7LkMOqdOb+e94eNQznwCPWY6AYB0R/Kixc3//aweA9f5EWU1I0i8/D5qdSgO8wn8chq 0qSnRBhger4j/SLJpF7omysR82k7M5jmkB1MpiSi/+t+IggOWVKHdEdNNCq1gNc+kH6UKWt +tZdksy1jJ96GIUwIjIxA== X-UI-Out-Filterresults: notjunk:1;V01:K0:8uSEl7jsUcA=:rzC1DArJbzxL2Mdap2GSB6 3oB7vE6ATn8joBbZoNPXVdSaEzWH8305MG4ZLf4POZhAuAHi+Ap7aUn6rpweDKhjy6ZX9EVrk t0PdbmijJxzZNzl2qMXeF08RcGpvCE4sp/nrIh97/cxfPBr5zkgrY1VrI/RPM29z/dHaTNC0S bvBWAeoV2ks0rSvzfLI4oeVi6XU2ZtJ2+BtkO6TLrkY/g/h9ziF4HEPpan5sEuqTgk8oCxoCa nyFvVbKju7AC7KRuGMVRhX677gmNwNAXgJ7WB+31B01XEkO83++TS/DF49odVyMdHcEBmLVY+ OGKlrj70FQiELT59am1pwJEW/2p1SwxSz1vmX4okwMXHTWNSPTJtCsiF71irlJunsRbNWBpAT 8nhpwEg/csVMp8ClU719++RZ5qhFKIDCt5zAy+dSTVSCs4y/3LfM9rLP05U+6CYzWKjFmopNv mxXKH72ED49BLdYec2kdg6gubDvqxIKrwvP+UfRsNrB65jPBHWKAiemL6J0o9CeLakk/YMHN3 CGYxJkNBEi9bjb6l5mFqor/N3lnHy8NWhn2G5TAWjz0qwNza92cVdtRyKl2WDMnVfGQewf0zr T2OQ18kpr1ewK4GWdNAqXv03N32nQ3NKgW5F0QqL+pSemzMXstxpKrNAhJ+pACgzXJ66/0aGg 5V0/6u+cOEdjVvccr7E4nEVqZPqHOu8pBizY49Ukimuplv3pvd844ZazHGtZAN0VQ8XI4XaiD bLbPSVTmWOToCi80NCDACSaQqb5sFRa+ClducA== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.135 Subject: [Qemu-devel] [PATCH for 2.13 06/19] linux-user: move ppc/ppc64 cpu loop to ppc directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to ppc/cpu_loop.c. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- linux-user/main.c | 560 +-----------------------------------------= ---- linux-user/ppc/cpu_loop.c | 553 ++++++++++++++++++++++++++++++++++++++++++= +++ 2 files changed, 554 insertions(+), 559 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 349dcd6a20..b5d0513b44 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -149,547 +149,6 @@ void fork_end(int child) } } =20 -#ifdef TARGET_PPC -static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env) -{ - return cpu_get_host_ticks(); -} - -uint64_t cpu_ppc_load_tbl(CPUPPCState *env) -{ - return cpu_ppc_get_tb(env); -} - -uint32_t cpu_ppc_load_tbu(CPUPPCState *env) -{ - return cpu_ppc_get_tb(env) >> 32; -} - -uint64_t cpu_ppc_load_atbl(CPUPPCState *env) -{ - return cpu_ppc_get_tb(env); -} - -uint32_t cpu_ppc_load_atbu(CPUPPCState *env) -{ - return cpu_ppc_get_tb(env) >> 32; -} - -uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env) -__attribute__ (( alias ("cpu_ppc_load_tbu") )); - -uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env) -{ - return cpu_ppc_load_tbl(env) & 0x3FFFFF80; -} - -/* XXX: to be fixed */ -int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) -{ - return -1; -} - -int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) -{ - return -1; -} - -static int do_store_exclusive(CPUPPCState *env) -{ - target_ulong addr; - target_ulong page_addr; - target_ulong val, val2 __attribute__((unused)) =3D 0; - int flags; - int segv =3D 0; - - addr =3D env->reserve_ea; - page_addr =3D addr & TARGET_PAGE_MASK; - start_exclusive(); - mmap_lock(); - flags =3D page_get_flags(page_addr); - if ((flags & PAGE_READ) =3D=3D 0) { - segv =3D 1; - } else { - int reg =3D env->reserve_info & 0x1f; - int size =3D env->reserve_info >> 5; - int stored =3D 0; - - if (addr =3D=3D env->reserve_addr) { - switch (size) { - case 1: segv =3D get_user_u8(val, addr); break; - case 2: segv =3D get_user_u16(val, addr); break; - case 4: segv =3D get_user_u32(val, addr); break; -#if defined(TARGET_PPC64) - case 8: segv =3D get_user_u64(val, addr); break; - case 16: { - segv =3D get_user_u64(val, addr); - if (!segv) { - segv =3D get_user_u64(val2, addr + 8); - } - break; - } -#endif - default: abort(); - } - if (!segv && val =3D=3D env->reserve_val) { - val =3D env->gpr[reg]; - switch (size) { - case 1: segv =3D put_user_u8(val, addr); break; - case 2: segv =3D put_user_u16(val, addr); break; - case 4: segv =3D put_user_u32(val, addr); break; -#if defined(TARGET_PPC64) - case 8: segv =3D put_user_u64(val, addr); break; - case 16: { - if (val2 =3D=3D env->reserve_val2) { - if (msr_le) { - val2 =3D val; - val =3D env->gpr[reg+1]; - } else { - val2 =3D env->gpr[reg+1]; - } - segv =3D put_user_u64(val, addr); - if (!segv) { - segv =3D put_user_u64(val2, addr + 8); - } - } - break; - } -#endif - default: abort(); - } - if (!segv) { - stored =3D 1; - } - } - } - env->crf[0] =3D (stored << 1) | xer_so; - env->reserve_addr =3D (target_ulong)-1; - } - if (!segv) { - env->nip +=3D 4; - } - mmap_unlock(); - end_exclusive(); - return segv; -} - -void cpu_loop(CPUPPCState *env) -{ - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); - target_siginfo_t info; - int trapnr; - target_ulong ret; - - for(;;) { - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - switch(trapnr) { - case POWERPC_EXCP_NONE: - /* Just go on */ - break; - case POWERPC_EXCP_CRITICAL: /* Critical input = */ - cpu_abort(cs, "Critical interrupt while in user mode. " - "Aborting\n"); - break; - case POWERPC_EXCP_MCHECK: /* Machine check exception = */ - cpu_abort(cs, "Machine check exception while in user mode. " - "Aborting\n"); - break; - case POWERPC_EXCP_DSI: /* Data storage exception = */ - /* XXX: check this. Seems bugged */ - switch (env->error_code & 0xFF000000) { - case 0x40000000: - case 0x42000000: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_MAPERR; - break; - case 0x04000000: - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D TARGET_ILL_ILLADR; - break; - case 0x08000000: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_ACCERR; - break; - default: - /* Let's send a regular segfault... */ - EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", - env->error_code); - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_MAPERR; - break; - } - info._sifields._sigfault._addr =3D env->spr[SPR_DAR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case POWERPC_EXCP_ISI: /* Instruction storage exception = */ - /* XXX: check this */ - switch (env->error_code & 0xFF000000) { - case 0x40000000: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_MAPERR; - break; - case 0x10000000: - case 0x08000000: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_ACCERR; - break; - default: - /* Let's send a regular segfault... */ - EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", - env->error_code); - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_MAPERR; - break; - } - info._sifields._sigfault._addr =3D env->nip - 4; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case POWERPC_EXCP_EXTERNAL: /* External input = */ - cpu_abort(cs, "External interrupt while in user mode. " - "Aborting\n"); - break; - case POWERPC_EXCP_ALIGN: /* Alignment exception = */ - /* XXX: check this */ - info.si_signo =3D TARGET_SIGBUS; - info.si_errno =3D 0; - info.si_code =3D TARGET_BUS_ADRALN; - info._sifields._sigfault._addr =3D env->nip; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case POWERPC_EXCP_PROGRAM: /* Program exception = */ - case POWERPC_EXCP_HV_EMU: /* HV emulation = */ - /* XXX: check this */ - switch (env->error_code & ~0xF) { - case POWERPC_EXCP_FP: - info.si_signo =3D TARGET_SIGFPE; - info.si_errno =3D 0; - switch (env->error_code & 0xF) { - case POWERPC_EXCP_FP_OX: - info.si_code =3D TARGET_FPE_FLTOVF; - break; - case POWERPC_EXCP_FP_UX: - info.si_code =3D TARGET_FPE_FLTUND; - break; - case POWERPC_EXCP_FP_ZX: - case POWERPC_EXCP_FP_VXZDZ: - info.si_code =3D TARGET_FPE_FLTDIV; - break; - case POWERPC_EXCP_FP_XX: - info.si_code =3D TARGET_FPE_FLTRES; - break; - case POWERPC_EXCP_FP_VXSOFT: - info.si_code =3D TARGET_FPE_FLTINV; - break; - case POWERPC_EXCP_FP_VXSNAN: - case POWERPC_EXCP_FP_VXISI: - case POWERPC_EXCP_FP_VXIDI: - case POWERPC_EXCP_FP_VXIMZ: - case POWERPC_EXCP_FP_VXVC: - case POWERPC_EXCP_FP_VXSQRT: - case POWERPC_EXCP_FP_VXCVI: - info.si_code =3D TARGET_FPE_FLTSUB; - break; - default: - EXCP_DUMP(env, "Unknown floating point exception (%02x= )\n", - env->error_code); - break; - } - break; - case POWERPC_EXCP_INVAL: - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - switch (env->error_code & 0xF) { - case POWERPC_EXCP_INVAL_INVAL: - info.si_code =3D TARGET_ILL_ILLOPC; - break; - case POWERPC_EXCP_INVAL_LSWX: - info.si_code =3D TARGET_ILL_ILLOPN; - break; - case POWERPC_EXCP_INVAL_SPR: - info.si_code =3D TARGET_ILL_PRVREG; - break; - case POWERPC_EXCP_INVAL_FP: - info.si_code =3D TARGET_ILL_COPROC; - break; - default: - EXCP_DUMP(env, "Unknown invalid operation (%02x)\n", - env->error_code & 0xF); - info.si_code =3D TARGET_ILL_ILLADR; - break; - } - break; - case POWERPC_EXCP_PRIV: - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - switch (env->error_code & 0xF) { - case POWERPC_EXCP_PRIV_OPC: - info.si_code =3D TARGET_ILL_PRVOPC; - break; - case POWERPC_EXCP_PRIV_REG: - info.si_code =3D TARGET_ILL_PRVREG; - break; - default: - EXCP_DUMP(env, "Unknown privilege violation (%02x)\n", - env->error_code & 0xF); - info.si_code =3D TARGET_ILL_PRVOPC; - break; - } - break; - case POWERPC_EXCP_TRAP: - cpu_abort(cs, "Tried to call a TRAP\n"); - break; - default: - /* Should not happen ! */ - cpu_abort(cs, "Unknown program exception (%02x)\n", - env->error_code); - break; - } - info._sifields._sigfault._addr =3D env->nip; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case POWERPC_EXCP_FPU: /* Floating-point unavailable exceptio= n */ - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D TARGET_ILL_COPROC; - info._sifields._sigfault._addr =3D env->nip; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case POWERPC_EXCP_SYSCALL: /* System call exception = */ - cpu_abort(cs, "Syscall exception while in user mode. " - "Aborting\n"); - break; - case POWERPC_EXCP_APU: /* Auxiliary processor unavailable = */ - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D TARGET_ILL_COPROC; - info._sifields._sigfault._addr =3D env->nip; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case POWERPC_EXCP_DECR: /* Decrementer exception = */ - cpu_abort(cs, "Decrementer interrupt while in user mode. " - "Aborting\n"); - break; - case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt = */ - cpu_abort(cs, "Fix interval timer interrupt while in user mode= . " - "Aborting\n"); - break; - case POWERPC_EXCP_WDT: /* Watchdog timer interrupt = */ - cpu_abort(cs, "Watchdog timer interrupt while in user mode. " - "Aborting\n"); - break; - case POWERPC_EXCP_DTLB: /* Data TLB error = */ - cpu_abort(cs, "Data TLB exception while in user mode. " - "Aborting\n"); - break; - case POWERPC_EXCP_ITLB: /* Instruction TLB error = */ - cpu_abort(cs, "Instruction TLB exception while in user mode. " - "Aborting\n"); - break; - case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail= . */ - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D TARGET_ILL_COPROC; - info._sifields._sigfault._addr =3D env->nip; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ = */ - cpu_abort(cs, "Embedded floating-point data IRQ not handled\n"= ); - break; - case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ = */ - cpu_abort(cs, "Embedded floating-point round IRQ not handled\n= "); - break; - case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ = */ - cpu_abort(cs, "Performance monitor exception not handled\n"); - break; - case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt = */ - cpu_abort(cs, "Doorbell interrupt while in user mode. " - "Aborting\n"); - break; - case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrup= t */ - cpu_abort(cs, "Doorbell critical interrupt while in user mode.= " - "Aborting\n"); - break; - case POWERPC_EXCP_RESET: /* System reset exception = */ - cpu_abort(cs, "Reset interrupt while in user mode. " - "Aborting\n"); - break; - case POWERPC_EXCP_DSEG: /* Data segment exception = */ - cpu_abort(cs, "Data segment exception while in user mode. " - "Aborting\n"); - break; - case POWERPC_EXCP_ISEG: /* Instruction segment exception = */ - cpu_abort(cs, "Instruction segment exception " - "while in user mode. Aborting\n"); - break; - /* PowerPC 64 with hypervisor mode support */ - case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception = */ - cpu_abort(cs, "Hypervisor decrementer interrupt " - "while in user mode. Aborting\n"); - break; - case POWERPC_EXCP_TRACE: /* Trace exception = */ - /* Nothing to do: - * we use this exception to emulate step-by-step execution mod= e. - */ - break; - /* PowerPC 64 with hypervisor mode support */ - case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception = */ - cpu_abort(cs, "Hypervisor data storage exception " - "while in user mode. Aborting\n"); - break; - case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp= */ - cpu_abort(cs, "Hypervisor instruction storage exception " - "while in user mode. Aborting\n"); - break; - case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception = */ - cpu_abort(cs, "Hypervisor data segment exception " - "while in user mode. Aborting\n"); - break; - case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp= */ - cpu_abort(cs, "Hypervisor instruction segment exception " - "while in user mode. Aborting\n"); - break; - case POWERPC_EXCP_VPU: /* Vector unavailable exception = */ - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D TARGET_ILL_COPROC; - info._sifields._sigfault._addr =3D env->nip; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ = */ - cpu_abort(cs, "Programmable interval timer interrupt " - "while in user mode. Aborting\n"); - break; - case POWERPC_EXCP_IO: /* IO error exception = */ - cpu_abort(cs, "IO error exception while in user mode. " - "Aborting\n"); - break; - case POWERPC_EXCP_RUNM: /* Run mode exception = */ - cpu_abort(cs, "Run mode exception while in user mode. " - "Aborting\n"); - break; - case POWERPC_EXCP_EMUL: /* Emulation trap exception = */ - cpu_abort(cs, "Emulation trap exception not handled\n"); - break; - case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error = */ - cpu_abort(cs, "Instruction fetch TLB exception " - "while in user-mode. Aborting"); - break; - case POWERPC_EXCP_DLTLB: /* Data load TLB miss = */ - cpu_abort(cs, "Data load TLB exception while in user-mode. " - "Aborting"); - break; - case POWERPC_EXCP_DSTLB: /* Data store TLB miss = */ - cpu_abort(cs, "Data store TLB exception while in user-mode. " - "Aborting"); - break; - case POWERPC_EXCP_FPA: /* Floating-point assist exception = */ - cpu_abort(cs, "Floating-point assist exception not handled\n"); - break; - case POWERPC_EXCP_IABR: /* Instruction address breakpoint = */ - cpu_abort(cs, "Instruction address breakpoint exception " - "not handled\n"); - break; - case POWERPC_EXCP_SMI: /* System management interrupt = */ - cpu_abort(cs, "System management interrupt while in user mode.= " - "Aborting\n"); - break; - case POWERPC_EXCP_THERM: /* Thermal interrupt = */ - cpu_abort(cs, "Thermal interrupt interrupt while in user mode.= " - "Aborting\n"); - break; - case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ = */ - cpu_abort(cs, "Performance monitor exception not handled\n"); - break; - case POWERPC_EXCP_VPUA: /* Vector assist exception = */ - cpu_abort(cs, "Vector assist exception not handled\n"); - break; - case POWERPC_EXCP_SOFTP: /* Soft patch exception = */ - cpu_abort(cs, "Soft patch exception not handled\n"); - break; - case POWERPC_EXCP_MAINT: /* Maintenance exception = */ - cpu_abort(cs, "Maintenance exception while in user mode. " - "Aborting\n"); - break; - case POWERPC_EXCP_STOP: /* stop translation = */ - /* We did invalidate the instruction cache. Go on */ - break; - case POWERPC_EXCP_BRANCH: /* branch instruction: = */ - /* We just stopped because of a branch. Go on */ - break; - case POWERPC_EXCP_SYSCALL_USER: - /* system call in user-mode emulation */ - /* WARNING: - * PPC ABI uses overflow flag in cr0 to signal an error - * in syscalls. - */ - env->crf[0] &=3D ~0x1; - env->nip +=3D 4; - ret =3D do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], - env->gpr[5], env->gpr[6], env->gpr[7], - env->gpr[8], 0, 0); - if (ret =3D=3D -TARGET_ERESTARTSYS) { - env->nip -=3D 4; - break; - } - if (ret =3D=3D (target_ulong)(-TARGET_QEMU_ESIGRETURN)) { - /* Returning from a successful sigreturn syscall. - Avoid corrupting register state. */ - break; - } - if (ret > (target_ulong)(-515)) { - env->crf[0] |=3D 0x1; - ret =3D -ret; - } - env->gpr[3] =3D ret; - break; - case POWERPC_EXCP_STCX: - if (do_store_exclusive(env)) { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->nip; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; - case EXCP_DEBUG: - { - int sig; - - sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (sig) { - info.si_signo =3D sig; - info.si_errno =3D 0; - info.si_code =3D TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - } - break; - case EXCP_INTERRUPT: - /* just indicate that signals should be handled asap */ - break; - case EXCP_ATOMIC: - cpu_exec_step_atomic(cs); - break; - default: - cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr); - break; - } - process_pending_signals(env); - } -} -#endif - #ifdef TARGET_MIPS =20 # ifdef TARGET_ABI_MIPSO32 @@ -3724,24 +3183,7 @@ int main(int argc, char **argv, char **envp) =20 target_cpu_copy_regs(env, regs); =20 -#if defined(TARGET_PPC) - { - int i; - -#if defined(TARGET_PPC64) - int flag =3D (env->insns_flags2 & PPC2_BOOKE206) ? MSR_CM : MSR_SF; -#if defined(TARGET_ABI32) - env->msr &=3D ~((target_ulong)1 << flag); -#else - env->msr |=3D (target_ulong)1 << flag; -#endif -#endif - env->nip =3D regs->nip; - for(i =3D 0; i < 32; i++) { - env->gpr[i] =3D regs->gpr[i]; - } - } -#elif defined(TARGET_M68K) +#if defined(TARGET_M68K) { env->pc =3D regs->pc; env->dregs[0] =3D regs->d0; diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index b7700a5561..2fb516cb00 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -21,6 +21,559 @@ #include "qemu.h" #include "cpu_loop-common.h" =20 +static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env) +{ + return cpu_get_host_ticks(); +} + +uint64_t cpu_ppc_load_tbl(CPUPPCState *env) +{ + return cpu_ppc_get_tb(env); +} + +uint32_t cpu_ppc_load_tbu(CPUPPCState *env) +{ + return cpu_ppc_get_tb(env) >> 32; +} + +uint64_t cpu_ppc_load_atbl(CPUPPCState *env) +{ + return cpu_ppc_get_tb(env); +} + +uint32_t cpu_ppc_load_atbu(CPUPPCState *env) +{ + return cpu_ppc_get_tb(env) >> 32; +} + +uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env) +__attribute__ (( alias ("cpu_ppc_load_tbu") )); + +uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env) +{ + return cpu_ppc_load_tbl(env) & 0x3FFFFF80; +} + +/* XXX: to be fixed */ +int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) +{ + return -1; +} + +int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) +{ + return -1; +} + +static int do_store_exclusive(CPUPPCState *env) +{ + target_ulong addr; + target_ulong page_addr; + target_ulong val, val2 __attribute__((unused)) =3D 0; + int flags; + int segv =3D 0; + + addr =3D env->reserve_ea; + page_addr =3D addr & TARGET_PAGE_MASK; + start_exclusive(); + mmap_lock(); + flags =3D page_get_flags(page_addr); + if ((flags & PAGE_READ) =3D=3D 0) { + segv =3D 1; + } else { + int reg =3D env->reserve_info & 0x1f; + int size =3D env->reserve_info >> 5; + int stored =3D 0; + + if (addr =3D=3D env->reserve_addr) { + switch (size) { + case 1: segv =3D get_user_u8(val, addr); break; + case 2: segv =3D get_user_u16(val, addr); break; + case 4: segv =3D get_user_u32(val, addr); break; +#if defined(TARGET_PPC64) + case 8: segv =3D get_user_u64(val, addr); break; + case 16: { + segv =3D get_user_u64(val, addr); + if (!segv) { + segv =3D get_user_u64(val2, addr + 8); + } + break; + } +#endif + default: abort(); + } + if (!segv && val =3D=3D env->reserve_val) { + val =3D env->gpr[reg]; + switch (size) { + case 1: segv =3D put_user_u8(val, addr); break; + case 2: segv =3D put_user_u16(val, addr); break; + case 4: segv =3D put_user_u32(val, addr); break; +#if defined(TARGET_PPC64) + case 8: segv =3D put_user_u64(val, addr); break; + case 16: { + if (val2 =3D=3D env->reserve_val2) { + if (msr_le) { + val2 =3D val; + val =3D env->gpr[reg+1]; + } else { + val2 =3D env->gpr[reg+1]; + } + segv =3D put_user_u64(val, addr); + if (!segv) { + segv =3D put_user_u64(val2, addr + 8); + } + } + break; + } +#endif + default: abort(); + } + if (!segv) { + stored =3D 1; + } + } + } + env->crf[0] =3D (stored << 1) | xer_so; + env->reserve_addr =3D (target_ulong)-1; + } + if (!segv) { + env->nip +=3D 4; + } + mmap_unlock(); + end_exclusive(); + return segv; +} + +void cpu_loop(CPUPPCState *env) +{ + CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + target_siginfo_t info; + int trapnr; + target_ulong ret; + + for(;;) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch(trapnr) { + case POWERPC_EXCP_NONE: + /* Just go on */ + break; + case POWERPC_EXCP_CRITICAL: /* Critical input = */ + cpu_abort(cs, "Critical interrupt while in user mode. " + "Aborting\n"); + break; + case POWERPC_EXCP_MCHECK: /* Machine check exception = */ + cpu_abort(cs, "Machine check exception while in user mode. " + "Aborting\n"); + break; + case POWERPC_EXCP_DSI: /* Data storage exception = */ + /* XXX: check this. Seems bugged */ + switch (env->error_code & 0xFF000000) { + case 0x40000000: + case 0x42000000: + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info.si_code =3D TARGET_SEGV_MAPERR; + break; + case 0x04000000: + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D TARGET_ILL_ILLADR; + break; + case 0x08000000: + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info.si_code =3D TARGET_SEGV_ACCERR; + break; + default: + /* Let's send a regular segfault... */ + EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", + env->error_code); + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info.si_code =3D TARGET_SEGV_MAPERR; + break; + } + info._sifields._sigfault._addr =3D env->spr[SPR_DAR]; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case POWERPC_EXCP_ISI: /* Instruction storage exception = */ + /* XXX: check this */ + switch (env->error_code & 0xFF000000) { + case 0x40000000: + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info.si_code =3D TARGET_SEGV_MAPERR; + break; + case 0x10000000: + case 0x08000000: + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info.si_code =3D TARGET_SEGV_ACCERR; + break; + default: + /* Let's send a regular segfault... */ + EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", + env->error_code); + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info.si_code =3D TARGET_SEGV_MAPERR; + break; + } + info._sifields._sigfault._addr =3D env->nip - 4; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case POWERPC_EXCP_EXTERNAL: /* External input = */ + cpu_abort(cs, "External interrupt while in user mode. " + "Aborting\n"); + break; + case POWERPC_EXCP_ALIGN: /* Alignment exception = */ + /* XXX: check this */ + info.si_signo =3D TARGET_SIGBUS; + info.si_errno =3D 0; + info.si_code =3D TARGET_BUS_ADRALN; + info._sifields._sigfault._addr =3D env->nip; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case POWERPC_EXCP_PROGRAM: /* Program exception = */ + case POWERPC_EXCP_HV_EMU: /* HV emulation = */ + /* XXX: check this */ + switch (env->error_code & ~0xF) { + case POWERPC_EXCP_FP: + info.si_signo =3D TARGET_SIGFPE; + info.si_errno =3D 0; + switch (env->error_code & 0xF) { + case POWERPC_EXCP_FP_OX: + info.si_code =3D TARGET_FPE_FLTOVF; + break; + case POWERPC_EXCP_FP_UX: + info.si_code =3D TARGET_FPE_FLTUND; + break; + case POWERPC_EXCP_FP_ZX: + case POWERPC_EXCP_FP_VXZDZ: + info.si_code =3D TARGET_FPE_FLTDIV; + break; + case POWERPC_EXCP_FP_XX: + info.si_code =3D TARGET_FPE_FLTRES; + break; + case POWERPC_EXCP_FP_VXSOFT: + info.si_code =3D TARGET_FPE_FLTINV; + break; + case POWERPC_EXCP_FP_VXSNAN: + case POWERPC_EXCP_FP_VXISI: + case POWERPC_EXCP_FP_VXIDI: + case POWERPC_EXCP_FP_VXIMZ: + case POWERPC_EXCP_FP_VXVC: + case POWERPC_EXCP_FP_VXSQRT: + case POWERPC_EXCP_FP_VXCVI: + info.si_code =3D TARGET_FPE_FLTSUB; + break; + default: + EXCP_DUMP(env, "Unknown floating point exception (%02x= )\n", + env->error_code); + break; + } + break; + case POWERPC_EXCP_INVAL: + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + switch (env->error_code & 0xF) { + case POWERPC_EXCP_INVAL_INVAL: + info.si_code =3D TARGET_ILL_ILLOPC; + break; + case POWERPC_EXCP_INVAL_LSWX: + info.si_code =3D TARGET_ILL_ILLOPN; + break; + case POWERPC_EXCP_INVAL_SPR: + info.si_code =3D TARGET_ILL_PRVREG; + break; + case POWERPC_EXCP_INVAL_FP: + info.si_code =3D TARGET_ILL_COPROC; + break; + default: + EXCP_DUMP(env, "Unknown invalid operation (%02x)\n", + env->error_code & 0xF); + info.si_code =3D TARGET_ILL_ILLADR; + break; + } + break; + case POWERPC_EXCP_PRIV: + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + switch (env->error_code & 0xF) { + case POWERPC_EXCP_PRIV_OPC: + info.si_code =3D TARGET_ILL_PRVOPC; + break; + case POWERPC_EXCP_PRIV_REG: + info.si_code =3D TARGET_ILL_PRVREG; + break; + default: + EXCP_DUMP(env, "Unknown privilege violation (%02x)\n", + env->error_code & 0xF); + info.si_code =3D TARGET_ILL_PRVOPC; + break; + } + break; + case POWERPC_EXCP_TRAP: + cpu_abort(cs, "Tried to call a TRAP\n"); + break; + default: + /* Should not happen ! */ + cpu_abort(cs, "Unknown program exception (%02x)\n", + env->error_code); + break; + } + info._sifields._sigfault._addr =3D env->nip; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case POWERPC_EXCP_FPU: /* Floating-point unavailable exceptio= n */ + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D TARGET_ILL_COPROC; + info._sifields._sigfault._addr =3D env->nip; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case POWERPC_EXCP_SYSCALL: /* System call exception = */ + cpu_abort(cs, "Syscall exception while in user mode. " + "Aborting\n"); + break; + case POWERPC_EXCP_APU: /* Auxiliary processor unavailable = */ + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D TARGET_ILL_COPROC; + info._sifields._sigfault._addr =3D env->nip; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case POWERPC_EXCP_DECR: /* Decrementer exception = */ + cpu_abort(cs, "Decrementer interrupt while in user mode. " + "Aborting\n"); + break; + case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt = */ + cpu_abort(cs, "Fix interval timer interrupt while in user mode= . " + "Aborting\n"); + break; + case POWERPC_EXCP_WDT: /* Watchdog timer interrupt = */ + cpu_abort(cs, "Watchdog timer interrupt while in user mode. " + "Aborting\n"); + break; + case POWERPC_EXCP_DTLB: /* Data TLB error = */ + cpu_abort(cs, "Data TLB exception while in user mode. " + "Aborting\n"); + break; + case POWERPC_EXCP_ITLB: /* Instruction TLB error = */ + cpu_abort(cs, "Instruction TLB exception while in user mode. " + "Aborting\n"); + break; + case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail= . */ + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D TARGET_ILL_COPROC; + info._sifields._sigfault._addr =3D env->nip; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ = */ + cpu_abort(cs, "Embedded floating-point data IRQ not handled\n"= ); + break; + case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ = */ + cpu_abort(cs, "Embedded floating-point round IRQ not handled\n= "); + break; + case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ = */ + cpu_abort(cs, "Performance monitor exception not handled\n"); + break; + case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt = */ + cpu_abort(cs, "Doorbell interrupt while in user mode. " + "Aborting\n"); + break; + case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrup= t */ + cpu_abort(cs, "Doorbell critical interrupt while in user mode.= " + "Aborting\n"); + break; + case POWERPC_EXCP_RESET: /* System reset exception = */ + cpu_abort(cs, "Reset interrupt while in user mode. " + "Aborting\n"); + break; + case POWERPC_EXCP_DSEG: /* Data segment exception = */ + cpu_abort(cs, "Data segment exception while in user mode. " + "Aborting\n"); + break; + case POWERPC_EXCP_ISEG: /* Instruction segment exception = */ + cpu_abort(cs, "Instruction segment exception " + "while in user mode. Aborting\n"); + break; + /* PowerPC 64 with hypervisor mode support */ + case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception = */ + cpu_abort(cs, "Hypervisor decrementer interrupt " + "while in user mode. Aborting\n"); + break; + case POWERPC_EXCP_TRACE: /* Trace exception = */ + /* Nothing to do: + * we use this exception to emulate step-by-step execution mod= e. + */ + break; + /* PowerPC 64 with hypervisor mode support */ + case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception = */ + cpu_abort(cs, "Hypervisor data storage exception " + "while in user mode. Aborting\n"); + break; + case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp= */ + cpu_abort(cs, "Hypervisor instruction storage exception " + "while in user mode. Aborting\n"); + break; + case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception = */ + cpu_abort(cs, "Hypervisor data segment exception " + "while in user mode. Aborting\n"); + break; + case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp= */ + cpu_abort(cs, "Hypervisor instruction segment exception " + "while in user mode. Aborting\n"); + break; + case POWERPC_EXCP_VPU: /* Vector unavailable exception = */ + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D TARGET_ILL_COPROC; + info._sifields._sigfault._addr =3D env->nip; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ = */ + cpu_abort(cs, "Programmable interval timer interrupt " + "while in user mode. Aborting\n"); + break; + case POWERPC_EXCP_IO: /* IO error exception = */ + cpu_abort(cs, "IO error exception while in user mode. " + "Aborting\n"); + break; + case POWERPC_EXCP_RUNM: /* Run mode exception = */ + cpu_abort(cs, "Run mode exception while in user mode. " + "Aborting\n"); + break; + case POWERPC_EXCP_EMUL: /* Emulation trap exception = */ + cpu_abort(cs, "Emulation trap exception not handled\n"); + break; + case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error = */ + cpu_abort(cs, "Instruction fetch TLB exception " + "while in user-mode. Aborting"); + break; + case POWERPC_EXCP_DLTLB: /* Data load TLB miss = */ + cpu_abort(cs, "Data load TLB exception while in user-mode. " + "Aborting"); + break; + case POWERPC_EXCP_DSTLB: /* Data store TLB miss = */ + cpu_abort(cs, "Data store TLB exception while in user-mode. " + "Aborting"); + break; + case POWERPC_EXCP_FPA: /* Floating-point assist exception = */ + cpu_abort(cs, "Floating-point assist exception not handled\n"); + break; + case POWERPC_EXCP_IABR: /* Instruction address breakpoint = */ + cpu_abort(cs, "Instruction address breakpoint exception " + "not handled\n"); + break; + case POWERPC_EXCP_SMI: /* System management interrupt = */ + cpu_abort(cs, "System management interrupt while in user mode.= " + "Aborting\n"); + break; + case POWERPC_EXCP_THERM: /* Thermal interrupt = */ + cpu_abort(cs, "Thermal interrupt interrupt while in user mode.= " + "Aborting\n"); + break; + case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ = */ + cpu_abort(cs, "Performance monitor exception not handled\n"); + break; + case POWERPC_EXCP_VPUA: /* Vector assist exception = */ + cpu_abort(cs, "Vector assist exception not handled\n"); + break; + case POWERPC_EXCP_SOFTP: /* Soft patch exception = */ + cpu_abort(cs, "Soft patch exception not handled\n"); + break; + case POWERPC_EXCP_MAINT: /* Maintenance exception = */ + cpu_abort(cs, "Maintenance exception while in user mode. " + "Aborting\n"); + break; + case POWERPC_EXCP_STOP: /* stop translation = */ + /* We did invalidate the instruction cache. Go on */ + break; + case POWERPC_EXCP_BRANCH: /* branch instruction: = */ + /* We just stopped because of a branch. Go on */ + break; + case POWERPC_EXCP_SYSCALL_USER: + /* system call in user-mode emulation */ + /* WARNING: + * PPC ABI uses overflow flag in cr0 to signal an error + * in syscalls. + */ + env->crf[0] &=3D ~0x1; + env->nip +=3D 4; + ret =3D do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], + env->gpr[5], env->gpr[6], env->gpr[7], + env->gpr[8], 0, 0); + if (ret =3D=3D -TARGET_ERESTARTSYS) { + env->nip -=3D 4; + break; + } + if (ret =3D=3D (target_ulong)(-TARGET_QEMU_ESIGRETURN)) { + /* Returning from a successful sigreturn syscall. + Avoid corrupting register state. */ + break; + } + if (ret > (target_ulong)(-515)) { + env->crf[0] |=3D 0x1; + ret =3D -ret; + } + env->gpr[3] =3D ret; + break; + case POWERPC_EXCP_STCX: + if (do_store_exclusive(env)) { + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info.si_code =3D TARGET_SEGV_MAPERR; + info._sifields._sigfault._addr =3D env->nip; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + break; + case EXCP_DEBUG: + { + int sig; + + sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); + if (sig) { + info.si_signo =3D sig; + info.si_errno =3D 0; + info.si_code =3D TARGET_TRAP_BRKPT; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + } + break; + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + default: + cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr); + break; + } + process_pending_signals(env); + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + int i; + +#if defined(TARGET_PPC64) + int flag =3D (env->insns_flags2 & PPC2_BOOKE206) ? MSR_CM : MSR_SF; +#if defined(TARGET_ABI32) + env->msr &=3D ~((target_ulong)1 << flag); +#else + env->msr |=3D (target_ulong)1 << flag; +#endif +#endif + env->nip =3D regs->nip; + for(i =3D 0; i < 32; i++) { + env->gpr[i] =3D regs->gpr[i]; + } } --=20 2.14.3 From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522092759803632.7035030971233; Mon, 26 Mar 2018 12:32:39 -0700 (PDT) Received: from localhost ([::1]:58752 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0XrC-0000fV-PZ for importer@patchew.org; Mon, 26 Mar 2018 15:32:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58958) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0XcN-0003pK-7I for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:17:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0XcI-0001r3-U5 for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:17:19 -0400 Received: from mout.kundenserver.de ([212.227.126.133]:41837) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0Xc9-0001nW-4u; Mon, 26 Mar 2018 15:17:05 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MYpHi-1f5TJZ3Dow-00VT6p; Mon, 26 Mar 2018 21:16:29 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:15:51 +0200 Message-Id: <20180326191603.10217-8-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:JZUX9flGgZip+oLc+PffIiph15zWrtIpMH0b1makbnIHBM2/Ev8 xkqvDKeHDVluRiW6irrnPbqPdPlvlvFIxqATSptIltGd4QOxQohb74rIkFd0G6Vz6E4VMLr s9DN45SBPAoSWVuIsSZ/QpNCuatKlZTexA+YwOoIwUB3yQH3JhXVNOyHzJ71RWeoFPtR8sj kCMCrPpBeNILxUzaVr3LA== X-UI-Out-Filterresults: notjunk:1;V01:K0:XsIca5sCmfA=:VjYV6LgudApoThiZ1wGrW6 8XFtGvLhwbuMOGSrZyMr8kLneGfZK+IebTPttlZ8pc/0z1i40Ob+wR70Gv0FZGiyuGZ5v0qbR eE0TZE0sarMmrxXrS9gvdF3+aar+M9JM3lpKCyccIFCJCoJ5/gLkT0+Ez5JIJNqd3MHcatsDR I8gtM8uRscGRDwZEkPDs+FjDwqGVMndr3nGWASa5seNdMO8dAzqIHSUCyJ781QE4AC4G3s5Fd xucODeDMgNOMSwq65VE0Vo6Tgz/iw7Q7OZH3U676Rk44BNruTQ4f5JBXs5hg6I5T3K6+JTMvF IXUb9JZAX269oAs+UMopJ6KXgkV9fCScTEe80Qf5z78WCQkWeKtipbvwBUFNNKgIdSeUCgfRf T745wTD0LS1lrAypMnBcHYxvMogzMe/IybVGdV4uzZBent2KH/FxjpFPPldpsQLunbRYHlrLx nL3OY+OIc9ZW8jt9IajMsnOxjEcsu8B+IsLFwZaDXllLvCV2sH1a+Ohx3+5nhgtc30XOtzCjq v6EYs9vDyKLrXUiLSdeUz0tSyIItV8+S4maapxi6yP5Q3IWOIWddp7kRlXhBwiGU3mHyrIClh IHn+HVEkr1ZFHXKdQ/1XkuzzjnJlVhx2NwGp00IfdAn9vcaihLLAmtL3YXpUfkL2SPHiz17ml L6sW0dFcq56613FKspuMRQkcvY4wIDf/3NrxbSFqUxm5tbAgyt3PPz1HucvLT679AYpZIFv3U Fu4HgaccMPnx1uOLmHflWzS8rLhBnS9YAOtQUA== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.133 Subject: [Qemu-devel] [PATCH for 2.13 07/19] linux-user: move mips/mips64 cpu loop to mips directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to mips/cpu_loop.c. Include mips/cpu_loop.c in mips64/cpu_loop.c to avoid to duplicate code. Signed-off-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- linux-user/main.c | 725 ---------------------------------------= ---- linux-user/mips/cpu_loop.c | 723 +++++++++++++++++++++++++++++++++++++++= +++ linux-user/mips64/cpu_loop.c | 8 +- 3 files changed, 724 insertions(+), 732 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index b5d0513b44..490733a3fb 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -149,705 +149,6 @@ void fork_end(int child) } } =20 -#ifdef TARGET_MIPS - -# ifdef TARGET_ABI_MIPSO32 -# define MIPS_SYS(name, args) args, -static const uint8_t mips_syscall_args[] =3D { - MIPS_SYS(sys_syscall , 8) /* 4000 */ - MIPS_SYS(sys_exit , 1) - MIPS_SYS(sys_fork , 0) - MIPS_SYS(sys_read , 3) - MIPS_SYS(sys_write , 3) - MIPS_SYS(sys_open , 3) /* 4005 */ - MIPS_SYS(sys_close , 1) - MIPS_SYS(sys_waitpid , 3) - MIPS_SYS(sys_creat , 2) - MIPS_SYS(sys_link , 2) - MIPS_SYS(sys_unlink , 1) /* 4010 */ - MIPS_SYS(sys_execve , 0) - MIPS_SYS(sys_chdir , 1) - MIPS_SYS(sys_time , 1) - MIPS_SYS(sys_mknod , 3) - MIPS_SYS(sys_chmod , 2) /* 4015 */ - MIPS_SYS(sys_lchown , 3) - MIPS_SYS(sys_ni_syscall , 0) - MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */ - MIPS_SYS(sys_lseek , 3) - MIPS_SYS(sys_getpid , 0) /* 4020 */ - MIPS_SYS(sys_mount , 5) - MIPS_SYS(sys_umount , 1) - MIPS_SYS(sys_setuid , 1) - MIPS_SYS(sys_getuid , 0) - MIPS_SYS(sys_stime , 1) /* 4025 */ - MIPS_SYS(sys_ptrace , 4) - MIPS_SYS(sys_alarm , 1) - MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */ - MIPS_SYS(sys_pause , 0) - MIPS_SYS(sys_utime , 2) /* 4030 */ - MIPS_SYS(sys_ni_syscall , 0) - MIPS_SYS(sys_ni_syscall , 0) - MIPS_SYS(sys_access , 2) - MIPS_SYS(sys_nice , 1) - MIPS_SYS(sys_ni_syscall , 0) /* 4035 */ - MIPS_SYS(sys_sync , 0) - MIPS_SYS(sys_kill , 2) - MIPS_SYS(sys_rename , 2) - MIPS_SYS(sys_mkdir , 2) - MIPS_SYS(sys_rmdir , 1) /* 4040 */ - MIPS_SYS(sys_dup , 1) - MIPS_SYS(sys_pipe , 0) - MIPS_SYS(sys_times , 1) - MIPS_SYS(sys_ni_syscall , 0) - MIPS_SYS(sys_brk , 1) /* 4045 */ - MIPS_SYS(sys_setgid , 1) - MIPS_SYS(sys_getgid , 0) - MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */ - MIPS_SYS(sys_geteuid , 0) - MIPS_SYS(sys_getegid , 0) /* 4050 */ - MIPS_SYS(sys_acct , 0) - MIPS_SYS(sys_umount2 , 2) - MIPS_SYS(sys_ni_syscall , 0) - MIPS_SYS(sys_ioctl , 3) - MIPS_SYS(sys_fcntl , 3) /* 4055 */ - MIPS_SYS(sys_ni_syscall , 2) - MIPS_SYS(sys_setpgid , 2) - MIPS_SYS(sys_ni_syscall , 0) - MIPS_SYS(sys_olduname , 1) - MIPS_SYS(sys_umask , 1) /* 4060 */ - MIPS_SYS(sys_chroot , 1) - MIPS_SYS(sys_ustat , 2) - MIPS_SYS(sys_dup2 , 2) - MIPS_SYS(sys_getppid , 0) - MIPS_SYS(sys_getpgrp , 0) /* 4065 */ - MIPS_SYS(sys_setsid , 0) - MIPS_SYS(sys_sigaction , 3) - MIPS_SYS(sys_sgetmask , 0) - MIPS_SYS(sys_ssetmask , 1) - MIPS_SYS(sys_setreuid , 2) /* 4070 */ - MIPS_SYS(sys_setregid , 2) - MIPS_SYS(sys_sigsuspend , 0) - MIPS_SYS(sys_sigpending , 1) - MIPS_SYS(sys_sethostname , 2) - MIPS_SYS(sys_setrlimit , 2) /* 4075 */ - MIPS_SYS(sys_getrlimit , 2) - MIPS_SYS(sys_getrusage , 2) - MIPS_SYS(sys_gettimeofday, 2) - MIPS_SYS(sys_settimeofday, 2) - MIPS_SYS(sys_getgroups , 2) /* 4080 */ - MIPS_SYS(sys_setgroups , 2) - MIPS_SYS(sys_ni_syscall , 0) /* old_select */ - MIPS_SYS(sys_symlink , 2) - MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */ - MIPS_SYS(sys_readlink , 3) /* 4085 */ - MIPS_SYS(sys_uselib , 1) - MIPS_SYS(sys_swapon , 2) - MIPS_SYS(sys_reboot , 3) - MIPS_SYS(old_readdir , 3) - MIPS_SYS(old_mmap , 6) /* 4090 */ - MIPS_SYS(sys_munmap , 2) - MIPS_SYS(sys_truncate , 2) - MIPS_SYS(sys_ftruncate , 2) - MIPS_SYS(sys_fchmod , 2) - MIPS_SYS(sys_fchown , 3) /* 4095 */ - MIPS_SYS(sys_getpriority , 2) - MIPS_SYS(sys_setpriority , 3) - MIPS_SYS(sys_ni_syscall , 0) - MIPS_SYS(sys_statfs , 2) - MIPS_SYS(sys_fstatfs , 2) /* 4100 */ - MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */ - MIPS_SYS(sys_socketcall , 2) - MIPS_SYS(sys_syslog , 3) - MIPS_SYS(sys_setitimer , 3) - MIPS_SYS(sys_getitimer , 2) /* 4105 */ - MIPS_SYS(sys_newstat , 2) - MIPS_SYS(sys_newlstat , 2) - MIPS_SYS(sys_newfstat , 2) - MIPS_SYS(sys_uname , 1) - MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */ - MIPS_SYS(sys_vhangup , 0) - MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */ - MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */ - MIPS_SYS(sys_wait4 , 4) - MIPS_SYS(sys_swapoff , 1) /* 4115 */ - MIPS_SYS(sys_sysinfo , 1) - MIPS_SYS(sys_ipc , 6) - MIPS_SYS(sys_fsync , 1) - MIPS_SYS(sys_sigreturn , 0) - MIPS_SYS(sys_clone , 6) /* 4120 */ - MIPS_SYS(sys_setdomainname, 2) - MIPS_SYS(sys_newuname , 1) - MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */ - MIPS_SYS(sys_adjtimex , 1) - MIPS_SYS(sys_mprotect , 3) /* 4125 */ - MIPS_SYS(sys_sigprocmask , 3) - MIPS_SYS(sys_ni_syscall , 0) /* was create_module */ - MIPS_SYS(sys_init_module , 5) - MIPS_SYS(sys_delete_module, 1) - MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */ - MIPS_SYS(sys_quotactl , 0) - MIPS_SYS(sys_getpgid , 1) - MIPS_SYS(sys_fchdir , 1) - MIPS_SYS(sys_bdflush , 2) - MIPS_SYS(sys_sysfs , 3) /* 4135 */ - MIPS_SYS(sys_personality , 1) - MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */ - MIPS_SYS(sys_setfsuid , 1) - MIPS_SYS(sys_setfsgid , 1) - MIPS_SYS(sys_llseek , 5) /* 4140 */ - MIPS_SYS(sys_getdents , 3) - MIPS_SYS(sys_select , 5) - MIPS_SYS(sys_flock , 2) - MIPS_SYS(sys_msync , 3) - MIPS_SYS(sys_readv , 3) /* 4145 */ - MIPS_SYS(sys_writev , 3) - MIPS_SYS(sys_cacheflush , 3) - MIPS_SYS(sys_cachectl , 3) - MIPS_SYS(sys_sysmips , 4) - MIPS_SYS(sys_ni_syscall , 0) /* 4150 */ - MIPS_SYS(sys_getsid , 1) - MIPS_SYS(sys_fdatasync , 0) - MIPS_SYS(sys_sysctl , 1) - MIPS_SYS(sys_mlock , 2) - MIPS_SYS(sys_munlock , 2) /* 4155 */ - MIPS_SYS(sys_mlockall , 1) - MIPS_SYS(sys_munlockall , 0) - MIPS_SYS(sys_sched_setparam, 2) - MIPS_SYS(sys_sched_getparam, 2) - MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */ - MIPS_SYS(sys_sched_getscheduler, 1) - MIPS_SYS(sys_sched_yield , 0) - MIPS_SYS(sys_sched_get_priority_max, 1) - MIPS_SYS(sys_sched_get_priority_min, 1) - MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */ - MIPS_SYS(sys_nanosleep, 2) - MIPS_SYS(sys_mremap , 5) - MIPS_SYS(sys_accept , 3) - MIPS_SYS(sys_bind , 3) - MIPS_SYS(sys_connect , 3) /* 4170 */ - MIPS_SYS(sys_getpeername , 3) - MIPS_SYS(sys_getsockname , 3) - MIPS_SYS(sys_getsockopt , 5) - MIPS_SYS(sys_listen , 2) - MIPS_SYS(sys_recv , 4) /* 4175 */ - MIPS_SYS(sys_recvfrom , 6) - MIPS_SYS(sys_recvmsg , 3) - MIPS_SYS(sys_send , 4) - MIPS_SYS(sys_sendmsg , 3) - MIPS_SYS(sys_sendto , 6) /* 4180 */ - MIPS_SYS(sys_setsockopt , 5) - MIPS_SYS(sys_shutdown , 2) - MIPS_SYS(sys_socket , 3) - MIPS_SYS(sys_socketpair , 4) - MIPS_SYS(sys_setresuid , 3) /* 4185 */ - MIPS_SYS(sys_getresuid , 3) - MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */ - MIPS_SYS(sys_poll , 3) - MIPS_SYS(sys_nfsservctl , 3) - MIPS_SYS(sys_setresgid , 3) /* 4190 */ - MIPS_SYS(sys_getresgid , 3) - MIPS_SYS(sys_prctl , 5) - MIPS_SYS(sys_rt_sigreturn, 0) - MIPS_SYS(sys_rt_sigaction, 4) - MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */ - MIPS_SYS(sys_rt_sigpending, 2) - MIPS_SYS(sys_rt_sigtimedwait, 4) - MIPS_SYS(sys_rt_sigqueueinfo, 3) - MIPS_SYS(sys_rt_sigsuspend, 0) - MIPS_SYS(sys_pread64 , 6) /* 4200 */ - MIPS_SYS(sys_pwrite64 , 6) - MIPS_SYS(sys_chown , 3) - MIPS_SYS(sys_getcwd , 2) - MIPS_SYS(sys_capget , 2) - MIPS_SYS(sys_capset , 2) /* 4205 */ - MIPS_SYS(sys_sigaltstack , 2) - MIPS_SYS(sys_sendfile , 4) - MIPS_SYS(sys_ni_syscall , 0) - MIPS_SYS(sys_ni_syscall , 0) - MIPS_SYS(sys_mmap2 , 6) /* 4210 */ - MIPS_SYS(sys_truncate64 , 4) - MIPS_SYS(sys_ftruncate64 , 4) - MIPS_SYS(sys_stat64 , 2) - MIPS_SYS(sys_lstat64 , 2) - MIPS_SYS(sys_fstat64 , 2) /* 4215 */ - MIPS_SYS(sys_pivot_root , 2) - MIPS_SYS(sys_mincore , 3) - MIPS_SYS(sys_madvise , 3) - MIPS_SYS(sys_getdents64 , 3) - MIPS_SYS(sys_fcntl64 , 3) /* 4220 */ - MIPS_SYS(sys_ni_syscall , 0) - MIPS_SYS(sys_gettid , 0) - MIPS_SYS(sys_readahead , 5) - MIPS_SYS(sys_setxattr , 5) - MIPS_SYS(sys_lsetxattr , 5) /* 4225 */ - MIPS_SYS(sys_fsetxattr , 5) - MIPS_SYS(sys_getxattr , 4) - MIPS_SYS(sys_lgetxattr , 4) - MIPS_SYS(sys_fgetxattr , 4) - MIPS_SYS(sys_listxattr , 3) /* 4230 */ - MIPS_SYS(sys_llistxattr , 3) - MIPS_SYS(sys_flistxattr , 3) - MIPS_SYS(sys_removexattr , 2) - MIPS_SYS(sys_lremovexattr, 2) - MIPS_SYS(sys_fremovexattr, 2) /* 4235 */ - MIPS_SYS(sys_tkill , 2) - MIPS_SYS(sys_sendfile64 , 5) - MIPS_SYS(sys_futex , 6) - MIPS_SYS(sys_sched_setaffinity, 3) - MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */ - MIPS_SYS(sys_io_setup , 2) - MIPS_SYS(sys_io_destroy , 1) - MIPS_SYS(sys_io_getevents, 5) - MIPS_SYS(sys_io_submit , 3) - MIPS_SYS(sys_io_cancel , 3) /* 4245 */ - MIPS_SYS(sys_exit_group , 1) - MIPS_SYS(sys_lookup_dcookie, 3) - MIPS_SYS(sys_epoll_create, 1) - MIPS_SYS(sys_epoll_ctl , 4) - MIPS_SYS(sys_epoll_wait , 3) /* 4250 */ - MIPS_SYS(sys_remap_file_pages, 5) - MIPS_SYS(sys_set_tid_address, 1) - MIPS_SYS(sys_restart_syscall, 0) - MIPS_SYS(sys_fadvise64_64, 7) - MIPS_SYS(sys_statfs64 , 3) /* 4255 */ - MIPS_SYS(sys_fstatfs64 , 2) - MIPS_SYS(sys_timer_create, 3) - MIPS_SYS(sys_timer_settime, 4) - MIPS_SYS(sys_timer_gettime, 2) - MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */ - MIPS_SYS(sys_timer_delete, 1) - MIPS_SYS(sys_clock_settime, 2) - MIPS_SYS(sys_clock_gettime, 2) - MIPS_SYS(sys_clock_getres, 2) - MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */ - MIPS_SYS(sys_tgkill , 3) - MIPS_SYS(sys_utimes , 2) - MIPS_SYS(sys_mbind , 4) - MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */ - MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */ - MIPS_SYS(sys_mq_open , 4) - MIPS_SYS(sys_mq_unlink , 1) - MIPS_SYS(sys_mq_timedsend, 5) - MIPS_SYS(sys_mq_timedreceive, 5) - MIPS_SYS(sys_mq_notify , 2) /* 4275 */ - MIPS_SYS(sys_mq_getsetattr, 3) - MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */ - MIPS_SYS(sys_waitid , 4) - MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */ - MIPS_SYS(sys_add_key , 5) - MIPS_SYS(sys_request_key, 4) - MIPS_SYS(sys_keyctl , 5) - MIPS_SYS(sys_set_thread_area, 1) - MIPS_SYS(sys_inotify_init, 0) - MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */ - MIPS_SYS(sys_inotify_rm_watch, 2) - MIPS_SYS(sys_migrate_pages, 4) - MIPS_SYS(sys_openat, 4) - MIPS_SYS(sys_mkdirat, 3) - MIPS_SYS(sys_mknodat, 4) /* 4290 */ - MIPS_SYS(sys_fchownat, 5) - MIPS_SYS(sys_futimesat, 3) - MIPS_SYS(sys_fstatat64, 4) - MIPS_SYS(sys_unlinkat, 3) - MIPS_SYS(sys_renameat, 4) /* 4295 */ - MIPS_SYS(sys_linkat, 5) - MIPS_SYS(sys_symlinkat, 3) - MIPS_SYS(sys_readlinkat, 4) - MIPS_SYS(sys_fchmodat, 3) - MIPS_SYS(sys_faccessat, 3) /* 4300 */ - MIPS_SYS(sys_pselect6, 6) - MIPS_SYS(sys_ppoll, 5) - MIPS_SYS(sys_unshare, 1) - MIPS_SYS(sys_splice, 6) - MIPS_SYS(sys_sync_file_range, 7) /* 4305 */ - MIPS_SYS(sys_tee, 4) - MIPS_SYS(sys_vmsplice, 4) - MIPS_SYS(sys_move_pages, 6) - MIPS_SYS(sys_set_robust_list, 2) - MIPS_SYS(sys_get_robust_list, 3) /* 4310 */ - MIPS_SYS(sys_kexec_load, 4) - MIPS_SYS(sys_getcpu, 3) - MIPS_SYS(sys_epoll_pwait, 6) - MIPS_SYS(sys_ioprio_set, 3) - MIPS_SYS(sys_ioprio_get, 2) - MIPS_SYS(sys_utimensat, 4) - MIPS_SYS(sys_signalfd, 3) - MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */ - MIPS_SYS(sys_eventfd, 1) - MIPS_SYS(sys_fallocate, 6) /* 4320 */ - MIPS_SYS(sys_timerfd_create, 2) - MIPS_SYS(sys_timerfd_gettime, 2) - MIPS_SYS(sys_timerfd_settime, 4) - MIPS_SYS(sys_signalfd4, 4) - MIPS_SYS(sys_eventfd2, 2) /* 4325 */ - MIPS_SYS(sys_epoll_create1, 1) - MIPS_SYS(sys_dup3, 3) - MIPS_SYS(sys_pipe2, 2) - MIPS_SYS(sys_inotify_init1, 1) - MIPS_SYS(sys_preadv, 5) /* 4330 */ - MIPS_SYS(sys_pwritev, 5) - MIPS_SYS(sys_rt_tgsigqueueinfo, 4) - MIPS_SYS(sys_perf_event_open, 5) - MIPS_SYS(sys_accept4, 4) - MIPS_SYS(sys_recvmmsg, 5) /* 4335 */ - MIPS_SYS(sys_fanotify_init, 2) - MIPS_SYS(sys_fanotify_mark, 6) - MIPS_SYS(sys_prlimit64, 4) - MIPS_SYS(sys_name_to_handle_at, 5) - MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */ - MIPS_SYS(sys_clock_adjtime, 2) - MIPS_SYS(sys_syncfs, 1) - MIPS_SYS(sys_sendmmsg, 4) - MIPS_SYS(sys_setns, 2) - MIPS_SYS(sys_process_vm_readv, 6) /* 345 */ - MIPS_SYS(sys_process_vm_writev, 6) - MIPS_SYS(sys_kcmp, 5) - MIPS_SYS(sys_finit_module, 3) - MIPS_SYS(sys_sched_setattr, 2) - MIPS_SYS(sys_sched_getattr, 3) /* 350 */ - MIPS_SYS(sys_renameat2, 5) - MIPS_SYS(sys_seccomp, 3) - MIPS_SYS(sys_getrandom, 3) - MIPS_SYS(sys_memfd_create, 2) - MIPS_SYS(sys_bpf, 3) /* 355 */ - MIPS_SYS(sys_execveat, 5) - MIPS_SYS(sys_userfaultfd, 1) - MIPS_SYS(sys_membarrier, 2) - MIPS_SYS(sys_mlock2, 3) - MIPS_SYS(sys_copy_file_range, 6) /* 360 */ - MIPS_SYS(sys_preadv2, 6) - MIPS_SYS(sys_pwritev2, 6) -}; -# undef MIPS_SYS -# endif /* O32 */ - -static int do_store_exclusive(CPUMIPSState *env) -{ - target_ulong addr; - target_ulong page_addr; - target_ulong val; - int flags; - int segv =3D 0; - int reg; - int d; - - addr =3D env->lladdr; - page_addr =3D addr & TARGET_PAGE_MASK; - start_exclusive(); - mmap_lock(); - flags =3D page_get_flags(page_addr); - if ((flags & PAGE_READ) =3D=3D 0) { - segv =3D 1; - } else { - reg =3D env->llreg & 0x1f; - d =3D (env->llreg & 0x20) !=3D 0; - if (d) { - segv =3D get_user_s64(val, addr); - } else { - segv =3D get_user_s32(val, addr); - } - if (!segv) { - if (val !=3D env->llval) { - env->active_tc.gpr[reg] =3D 0; - } else { - if (d) { - segv =3D put_user_u64(env->llnewval, addr); - } else { - segv =3D put_user_u32(env->llnewval, addr); - } - if (!segv) { - env->active_tc.gpr[reg] =3D 1; - } - } - } - } - env->lladdr =3D -1; - if (!segv) { - env->active_tc.PC +=3D 4; - } - mmap_unlock(); - end_exclusive(); - return segv; -} - -/* Break codes */ -enum { - BRK_OVERFLOW =3D 6, - BRK_DIVZERO =3D 7 -}; - -static int do_break(CPUMIPSState *env, target_siginfo_t *info, - unsigned int code) -{ - int ret =3D -1; - - switch (code) { - case BRK_OVERFLOW: - case BRK_DIVZERO: - info->si_signo =3D TARGET_SIGFPE; - info->si_errno =3D 0; - info->si_code =3D (code =3D=3D BRK_OVERFLOW) ? FPE_INTOVF : FPE_IN= TDIV; - queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info); - ret =3D 0; - break; - default: - info->si_signo =3D TARGET_SIGTRAP; - info->si_errno =3D 0; - queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info); - ret =3D 0; - break; - } - - return ret; -} - -void cpu_loop(CPUMIPSState *env) -{ - CPUState *cs =3D CPU(mips_env_get_cpu(env)); - target_siginfo_t info; - int trapnr; - abi_long ret; -# ifdef TARGET_ABI_MIPSO32 - unsigned int syscall_num; -# endif - - for(;;) { - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - switch(trapnr) { - case EXCP_SYSCALL: - env->active_tc.PC +=3D 4; -# ifdef TARGET_ABI_MIPSO32 - syscall_num =3D env->active_tc.gpr[2] - 4000; - if (syscall_num >=3D sizeof(mips_syscall_args)) { - ret =3D -TARGET_ENOSYS; - } else { - int nb_args; - abi_ulong sp_reg; - abi_ulong arg5 =3D 0, arg6 =3D 0, arg7 =3D 0, arg8 =3D 0; - - nb_args =3D mips_syscall_args[syscall_num]; - sp_reg =3D env->active_tc.gpr[29]; - switch (nb_args) { - /* these arguments are taken from the stack */ - case 8: - if ((ret =3D get_user_ual(arg8, sp_reg + 28)) !=3D 0) { - goto done_syscall; - } - case 7: - if ((ret =3D get_user_ual(arg7, sp_reg + 24)) !=3D 0) { - goto done_syscall; - } - case 6: - if ((ret =3D get_user_ual(arg6, sp_reg + 20)) !=3D 0) { - goto done_syscall; - } - case 5: - if ((ret =3D get_user_ual(arg5, sp_reg + 16)) !=3D 0) { - goto done_syscall; - } - default: - break; - } - ret =3D do_syscall(env, env->active_tc.gpr[2], - env->active_tc.gpr[4], - env->active_tc.gpr[5], - env->active_tc.gpr[6], - env->active_tc.gpr[7], - arg5, arg6, arg7, arg8); - } -done_syscall: -# else - ret =3D do_syscall(env, env->active_tc.gpr[2], - env->active_tc.gpr[4], env->active_tc.gpr[5], - env->active_tc.gpr[6], env->active_tc.gpr[7], - env->active_tc.gpr[8], env->active_tc.gpr[9], - env->active_tc.gpr[10], env->active_tc.gpr[11= ]); -# endif /* O32 */ - if (ret =3D=3D -TARGET_ERESTARTSYS) { - env->active_tc.PC -=3D 4; - break; - } - if (ret =3D=3D -TARGET_QEMU_ESIGRETURN) { - /* Returning from a successful sigreturn syscall. - Avoid clobbering register state. */ - break; - } - if ((abi_ulong)ret >=3D (abi_ulong)-1133) { - env->active_tc.gpr[7] =3D 1; /* error flag */ - ret =3D -ret; - } else { - env->active_tc.gpr[7] =3D 0; /* error flag */ - } - env->active_tc.gpr[2] =3D ret; - break; - case EXCP_TLBL: - case EXCP_TLBS: - case EXCP_AdEL: - case EXCP_AdES: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->CP0_BadVAddr; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_CpU: - case EXCP_RI: - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D 0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_INTERRUPT: - /* just indicate that signals should be handled asap */ - break; - case EXCP_DEBUG: - { - int sig; - - sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (sig) - { - info.si_signo =3D sig; - info.si_errno =3D 0; - info.si_code =3D TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - } - break; - case EXCP_SC: - if (do_store_exclusive(env)) { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->active_tc.PC; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; - case EXCP_DSPDIS: - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D TARGET_ILL_ILLOPC; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - /* The code below was inspired by the MIPS Linux kernel trap - * handling code in arch/mips/kernel/traps.c. - */ - case EXCP_BREAK: - { - abi_ulong trap_instr; - unsigned int code; - - if (env->hflags & MIPS_HFLAG_M16) { - if (env->insn_flags & ASE_MICROMIPS) { - /* microMIPS mode */ - ret =3D get_user_u16(trap_instr, env->active_tc.PC= ); - if (ret !=3D 0) { - goto error; - } - - if ((trap_instr >> 10) =3D=3D 0x11) { - /* 16-bit instruction */ - code =3D trap_instr & 0xf; - } else { - /* 32-bit instruction */ - abi_ulong instr_lo; - - ret =3D get_user_u16(instr_lo, - env->active_tc.PC + 2); - if (ret !=3D 0) { - goto error; - } - trap_instr =3D (trap_instr << 16) | instr_lo; - code =3D ((trap_instr >> 6) & ((1 << 20) - 1)); - /* Unfortunately, microMIPS also suffers from - the old assembler bug... */ - if (code >=3D (1 << 10)) { - code >>=3D 10; - } - } - } else { - /* MIPS16e mode */ - ret =3D get_user_u16(trap_instr, env->active_tc.PC= ); - if (ret !=3D 0) { - goto error; - } - code =3D (trap_instr >> 6) & 0x3f; - } - } else { - ret =3D get_user_u32(trap_instr, env->active_tc.PC); - if (ret !=3D 0) { - goto error; - } - - /* As described in the original Linux kernel code, the - * below checks on 'code' are to work around an old - * assembly bug. - */ - code =3D ((trap_instr >> 6) & ((1 << 20) - 1)); - if (code >=3D (1 << 10)) { - code >>=3D 10; - } - } - - if (do_break(env, &info, code) !=3D 0) { - goto error; - } - } - break; - case EXCP_TRAP: - { - abi_ulong trap_instr; - unsigned int code =3D 0; - - if (env->hflags & MIPS_HFLAG_M16) { - /* microMIPS mode */ - abi_ulong instr[2]; - - ret =3D get_user_u16(instr[0], env->active_tc.PC) || - get_user_u16(instr[1], env->active_tc.PC + 2); - - trap_instr =3D (instr[0] << 16) | instr[1]; - } else { - ret =3D get_user_u32(trap_instr, env->active_tc.PC); - } - - if (ret !=3D 0) { - goto error; - } - - /* The immediate versions don't provide a code. */ - if (!(trap_instr & 0xFC000000)) { - if (env->hflags & MIPS_HFLAG_M16) { - /* microMIPS mode */ - code =3D ((trap_instr >> 12) & ((1 << 4) - 1)); - } else { - code =3D ((trap_instr >> 6) & ((1 << 10) - 1)); - } - } - - if (do_break(env, &info, code) !=3D 0) { - goto error; - } - } - break; - case EXCP_ATOMIC: - cpu_exec_step_atomic(cs); - break; - default: -error: - EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\= n", trapnr); - abort(); - } - process_pending_signals(env); - } -} -#endif - #ifdef TARGET_NIOS2 =20 void cpu_loop(CPUNios2State *env) @@ -3241,32 +2542,6 @@ int main(int argc, char **argv, char **envp) env->regs[31] =3D regs->r31; =20 env->sregs[SR_PC] =3D regs->pc; } -#elif defined(TARGET_MIPS) - { - int i; - - for(i =3D 0; i < 32; i++) { - env->active_tc.gpr[i] =3D regs->regs[i]; - } - env->active_tc.PC =3D regs->cp0_epc & ~(target_ulong)1; - if (regs->cp0_epc & 1) { - env->hflags |=3D MIPS_HFLAG_M16; - } - if (((info->elf_flags & EF_MIPS_NAN2008) !=3D 0) !=3D - ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) !=3D 0)) { - if ((env->active_fpu.fcr31_rw_bitmask & - (1 << FCR31_NAN2008)) =3D=3D 0) { - fprintf(stderr, "ELF binary's NaN mode not supported by CP= U\n"); - exit(1); - } - if ((info->elf_flags & EF_MIPS_NAN2008) !=3D 0) { - env->active_fpu.fcr31 |=3D (1 << FCR31_NAN2008); - } else { - env->active_fpu.fcr31 &=3D ~(1 << FCR31_NAN2008); - } - restore_snan_bit_mode(env); - } - } #elif defined(TARGET_NIOS2) { env->regs[0] =3D 0; diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index b7700a5561..51bdb647dd 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -20,7 +20,730 @@ #include "qemu/osdep.h" #include "qemu.h" #include "cpu_loop-common.h" +#include "elf.h" + +# ifdef TARGET_ABI_MIPSO32 +# define MIPS_SYS(name, args) args, +static const uint8_t mips_syscall_args[] =3D { + MIPS_SYS(sys_syscall , 8) /* 4000 */ + MIPS_SYS(sys_exit , 1) + MIPS_SYS(sys_fork , 0) + MIPS_SYS(sys_read , 3) + MIPS_SYS(sys_write , 3) + MIPS_SYS(sys_open , 3) /* 4005 */ + MIPS_SYS(sys_close , 1) + MIPS_SYS(sys_waitpid , 3) + MIPS_SYS(sys_creat , 2) + MIPS_SYS(sys_link , 2) + MIPS_SYS(sys_unlink , 1) /* 4010 */ + MIPS_SYS(sys_execve , 0) + MIPS_SYS(sys_chdir , 1) + MIPS_SYS(sys_time , 1) + MIPS_SYS(sys_mknod , 3) + MIPS_SYS(sys_chmod , 2) /* 4015 */ + MIPS_SYS(sys_lchown , 3) + MIPS_SYS(sys_ni_syscall , 0) + MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */ + MIPS_SYS(sys_lseek , 3) + MIPS_SYS(sys_getpid , 0) /* 4020 */ + MIPS_SYS(sys_mount , 5) + MIPS_SYS(sys_umount , 1) + MIPS_SYS(sys_setuid , 1) + MIPS_SYS(sys_getuid , 0) + MIPS_SYS(sys_stime , 1) /* 4025 */ + MIPS_SYS(sys_ptrace , 4) + MIPS_SYS(sys_alarm , 1) + MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */ + MIPS_SYS(sys_pause , 0) + MIPS_SYS(sys_utime , 2) /* 4030 */ + MIPS_SYS(sys_ni_syscall , 0) + MIPS_SYS(sys_ni_syscall , 0) + MIPS_SYS(sys_access , 2) + MIPS_SYS(sys_nice , 1) + MIPS_SYS(sys_ni_syscall , 0) /* 4035 */ + MIPS_SYS(sys_sync , 0) + MIPS_SYS(sys_kill , 2) + MIPS_SYS(sys_rename , 2) + MIPS_SYS(sys_mkdir , 2) + MIPS_SYS(sys_rmdir , 1) /* 4040 */ + MIPS_SYS(sys_dup , 1) + MIPS_SYS(sys_pipe , 0) + MIPS_SYS(sys_times , 1) + MIPS_SYS(sys_ni_syscall , 0) + MIPS_SYS(sys_brk , 1) /* 4045 */ + MIPS_SYS(sys_setgid , 1) + MIPS_SYS(sys_getgid , 0) + MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */ + MIPS_SYS(sys_geteuid , 0) + MIPS_SYS(sys_getegid , 0) /* 4050 */ + MIPS_SYS(sys_acct , 0) + MIPS_SYS(sys_umount2 , 2) + MIPS_SYS(sys_ni_syscall , 0) + MIPS_SYS(sys_ioctl , 3) + MIPS_SYS(sys_fcntl , 3) /* 4055 */ + MIPS_SYS(sys_ni_syscall , 2) + MIPS_SYS(sys_setpgid , 2) + MIPS_SYS(sys_ni_syscall , 0) + MIPS_SYS(sys_olduname , 1) + MIPS_SYS(sys_umask , 1) /* 4060 */ + MIPS_SYS(sys_chroot , 1) + MIPS_SYS(sys_ustat , 2) + MIPS_SYS(sys_dup2 , 2) + MIPS_SYS(sys_getppid , 0) + MIPS_SYS(sys_getpgrp , 0) /* 4065 */ + MIPS_SYS(sys_setsid , 0) + MIPS_SYS(sys_sigaction , 3) + MIPS_SYS(sys_sgetmask , 0) + MIPS_SYS(sys_ssetmask , 1) + MIPS_SYS(sys_setreuid , 2) /* 4070 */ + MIPS_SYS(sys_setregid , 2) + MIPS_SYS(sys_sigsuspend , 0) + MIPS_SYS(sys_sigpending , 1) + MIPS_SYS(sys_sethostname , 2) + MIPS_SYS(sys_setrlimit , 2) /* 4075 */ + MIPS_SYS(sys_getrlimit , 2) + MIPS_SYS(sys_getrusage , 2) + MIPS_SYS(sys_gettimeofday, 2) + MIPS_SYS(sys_settimeofday, 2) + MIPS_SYS(sys_getgroups , 2) /* 4080 */ + MIPS_SYS(sys_setgroups , 2) + MIPS_SYS(sys_ni_syscall , 0) /* old_select */ + MIPS_SYS(sys_symlink , 2) + MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */ + MIPS_SYS(sys_readlink , 3) /* 4085 */ + MIPS_SYS(sys_uselib , 1) + MIPS_SYS(sys_swapon , 2) + MIPS_SYS(sys_reboot , 3) + MIPS_SYS(old_readdir , 3) + MIPS_SYS(old_mmap , 6) /* 4090 */ + MIPS_SYS(sys_munmap , 2) + MIPS_SYS(sys_truncate , 2) + MIPS_SYS(sys_ftruncate , 2) + MIPS_SYS(sys_fchmod , 2) + MIPS_SYS(sys_fchown , 3) /* 4095 */ + MIPS_SYS(sys_getpriority , 2) + MIPS_SYS(sys_setpriority , 3) + MIPS_SYS(sys_ni_syscall , 0) + MIPS_SYS(sys_statfs , 2) + MIPS_SYS(sys_fstatfs , 2) /* 4100 */ + MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */ + MIPS_SYS(sys_socketcall , 2) + MIPS_SYS(sys_syslog , 3) + MIPS_SYS(sys_setitimer , 3) + MIPS_SYS(sys_getitimer , 2) /* 4105 */ + MIPS_SYS(sys_newstat , 2) + MIPS_SYS(sys_newlstat , 2) + MIPS_SYS(sys_newfstat , 2) + MIPS_SYS(sys_uname , 1) + MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */ + MIPS_SYS(sys_vhangup , 0) + MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */ + MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */ + MIPS_SYS(sys_wait4 , 4) + MIPS_SYS(sys_swapoff , 1) /* 4115 */ + MIPS_SYS(sys_sysinfo , 1) + MIPS_SYS(sys_ipc , 6) + MIPS_SYS(sys_fsync , 1) + MIPS_SYS(sys_sigreturn , 0) + MIPS_SYS(sys_clone , 6) /* 4120 */ + MIPS_SYS(sys_setdomainname, 2) + MIPS_SYS(sys_newuname , 1) + MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */ + MIPS_SYS(sys_adjtimex , 1) + MIPS_SYS(sys_mprotect , 3) /* 4125 */ + MIPS_SYS(sys_sigprocmask , 3) + MIPS_SYS(sys_ni_syscall , 0) /* was create_module */ + MIPS_SYS(sys_init_module , 5) + MIPS_SYS(sys_delete_module, 1) + MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */ + MIPS_SYS(sys_quotactl , 0) + MIPS_SYS(sys_getpgid , 1) + MIPS_SYS(sys_fchdir , 1) + MIPS_SYS(sys_bdflush , 2) + MIPS_SYS(sys_sysfs , 3) /* 4135 */ + MIPS_SYS(sys_personality , 1) + MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */ + MIPS_SYS(sys_setfsuid , 1) + MIPS_SYS(sys_setfsgid , 1) + MIPS_SYS(sys_llseek , 5) /* 4140 */ + MIPS_SYS(sys_getdents , 3) + MIPS_SYS(sys_select , 5) + MIPS_SYS(sys_flock , 2) + MIPS_SYS(sys_msync , 3) + MIPS_SYS(sys_readv , 3) /* 4145 */ + MIPS_SYS(sys_writev , 3) + MIPS_SYS(sys_cacheflush , 3) + MIPS_SYS(sys_cachectl , 3) + MIPS_SYS(sys_sysmips , 4) + MIPS_SYS(sys_ni_syscall , 0) /* 4150 */ + MIPS_SYS(sys_getsid , 1) + MIPS_SYS(sys_fdatasync , 0) + MIPS_SYS(sys_sysctl , 1) + MIPS_SYS(sys_mlock , 2) + MIPS_SYS(sys_munlock , 2) /* 4155 */ + MIPS_SYS(sys_mlockall , 1) + MIPS_SYS(sys_munlockall , 0) + MIPS_SYS(sys_sched_setparam, 2) + MIPS_SYS(sys_sched_getparam, 2) + MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */ + MIPS_SYS(sys_sched_getscheduler, 1) + MIPS_SYS(sys_sched_yield , 0) + MIPS_SYS(sys_sched_get_priority_max, 1) + MIPS_SYS(sys_sched_get_priority_min, 1) + MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */ + MIPS_SYS(sys_nanosleep, 2) + MIPS_SYS(sys_mremap , 5) + MIPS_SYS(sys_accept , 3) + MIPS_SYS(sys_bind , 3) + MIPS_SYS(sys_connect , 3) /* 4170 */ + MIPS_SYS(sys_getpeername , 3) + MIPS_SYS(sys_getsockname , 3) + MIPS_SYS(sys_getsockopt , 5) + MIPS_SYS(sys_listen , 2) + MIPS_SYS(sys_recv , 4) /* 4175 */ + MIPS_SYS(sys_recvfrom , 6) + MIPS_SYS(sys_recvmsg , 3) + MIPS_SYS(sys_send , 4) + MIPS_SYS(sys_sendmsg , 3) + MIPS_SYS(sys_sendto , 6) /* 4180 */ + MIPS_SYS(sys_setsockopt , 5) + MIPS_SYS(sys_shutdown , 2) + MIPS_SYS(sys_socket , 3) + MIPS_SYS(sys_socketpair , 4) + MIPS_SYS(sys_setresuid , 3) /* 4185 */ + MIPS_SYS(sys_getresuid , 3) + MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */ + MIPS_SYS(sys_poll , 3) + MIPS_SYS(sys_nfsservctl , 3) + MIPS_SYS(sys_setresgid , 3) /* 4190 */ + MIPS_SYS(sys_getresgid , 3) + MIPS_SYS(sys_prctl , 5) + MIPS_SYS(sys_rt_sigreturn, 0) + MIPS_SYS(sys_rt_sigaction, 4) + MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */ + MIPS_SYS(sys_rt_sigpending, 2) + MIPS_SYS(sys_rt_sigtimedwait, 4) + MIPS_SYS(sys_rt_sigqueueinfo, 3) + MIPS_SYS(sys_rt_sigsuspend, 0) + MIPS_SYS(sys_pread64 , 6) /* 4200 */ + MIPS_SYS(sys_pwrite64 , 6) + MIPS_SYS(sys_chown , 3) + MIPS_SYS(sys_getcwd , 2) + MIPS_SYS(sys_capget , 2) + MIPS_SYS(sys_capset , 2) /* 4205 */ + MIPS_SYS(sys_sigaltstack , 2) + MIPS_SYS(sys_sendfile , 4) + MIPS_SYS(sys_ni_syscall , 0) + MIPS_SYS(sys_ni_syscall , 0) + MIPS_SYS(sys_mmap2 , 6) /* 4210 */ + MIPS_SYS(sys_truncate64 , 4) + MIPS_SYS(sys_ftruncate64 , 4) + MIPS_SYS(sys_stat64 , 2) + MIPS_SYS(sys_lstat64 , 2) + MIPS_SYS(sys_fstat64 , 2) /* 4215 */ + MIPS_SYS(sys_pivot_root , 2) + MIPS_SYS(sys_mincore , 3) + MIPS_SYS(sys_madvise , 3) + MIPS_SYS(sys_getdents64 , 3) + MIPS_SYS(sys_fcntl64 , 3) /* 4220 */ + MIPS_SYS(sys_ni_syscall , 0) + MIPS_SYS(sys_gettid , 0) + MIPS_SYS(sys_readahead , 5) + MIPS_SYS(sys_setxattr , 5) + MIPS_SYS(sys_lsetxattr , 5) /* 4225 */ + MIPS_SYS(sys_fsetxattr , 5) + MIPS_SYS(sys_getxattr , 4) + MIPS_SYS(sys_lgetxattr , 4) + MIPS_SYS(sys_fgetxattr , 4) + MIPS_SYS(sys_listxattr , 3) /* 4230 */ + MIPS_SYS(sys_llistxattr , 3) + MIPS_SYS(sys_flistxattr , 3) + MIPS_SYS(sys_removexattr , 2) + MIPS_SYS(sys_lremovexattr, 2) + MIPS_SYS(sys_fremovexattr, 2) /* 4235 */ + MIPS_SYS(sys_tkill , 2) + MIPS_SYS(sys_sendfile64 , 5) + MIPS_SYS(sys_futex , 6) + MIPS_SYS(sys_sched_setaffinity, 3) + MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */ + MIPS_SYS(sys_io_setup , 2) + MIPS_SYS(sys_io_destroy , 1) + MIPS_SYS(sys_io_getevents, 5) + MIPS_SYS(sys_io_submit , 3) + MIPS_SYS(sys_io_cancel , 3) /* 4245 */ + MIPS_SYS(sys_exit_group , 1) + MIPS_SYS(sys_lookup_dcookie, 3) + MIPS_SYS(sys_epoll_create, 1) + MIPS_SYS(sys_epoll_ctl , 4) + MIPS_SYS(sys_epoll_wait , 3) /* 4250 */ + MIPS_SYS(sys_remap_file_pages, 5) + MIPS_SYS(sys_set_tid_address, 1) + MIPS_SYS(sys_restart_syscall, 0) + MIPS_SYS(sys_fadvise64_64, 7) + MIPS_SYS(sys_statfs64 , 3) /* 4255 */ + MIPS_SYS(sys_fstatfs64 , 2) + MIPS_SYS(sys_timer_create, 3) + MIPS_SYS(sys_timer_settime, 4) + MIPS_SYS(sys_timer_gettime, 2) + MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */ + MIPS_SYS(sys_timer_delete, 1) + MIPS_SYS(sys_clock_settime, 2) + MIPS_SYS(sys_clock_gettime, 2) + MIPS_SYS(sys_clock_getres, 2) + MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */ + MIPS_SYS(sys_tgkill , 3) + MIPS_SYS(sys_utimes , 2) + MIPS_SYS(sys_mbind , 4) + MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */ + MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */ + MIPS_SYS(sys_mq_open , 4) + MIPS_SYS(sys_mq_unlink , 1) + MIPS_SYS(sys_mq_timedsend, 5) + MIPS_SYS(sys_mq_timedreceive, 5) + MIPS_SYS(sys_mq_notify , 2) /* 4275 */ + MIPS_SYS(sys_mq_getsetattr, 3) + MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */ + MIPS_SYS(sys_waitid , 4) + MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */ + MIPS_SYS(sys_add_key , 5) + MIPS_SYS(sys_request_key, 4) + MIPS_SYS(sys_keyctl , 5) + MIPS_SYS(sys_set_thread_area, 1) + MIPS_SYS(sys_inotify_init, 0) + MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */ + MIPS_SYS(sys_inotify_rm_watch, 2) + MIPS_SYS(sys_migrate_pages, 4) + MIPS_SYS(sys_openat, 4) + MIPS_SYS(sys_mkdirat, 3) + MIPS_SYS(sys_mknodat, 4) /* 4290 */ + MIPS_SYS(sys_fchownat, 5) + MIPS_SYS(sys_futimesat, 3) + MIPS_SYS(sys_fstatat64, 4) + MIPS_SYS(sys_unlinkat, 3) + MIPS_SYS(sys_renameat, 4) /* 4295 */ + MIPS_SYS(sys_linkat, 5) + MIPS_SYS(sys_symlinkat, 3) + MIPS_SYS(sys_readlinkat, 4) + MIPS_SYS(sys_fchmodat, 3) + MIPS_SYS(sys_faccessat, 3) /* 4300 */ + MIPS_SYS(sys_pselect6, 6) + MIPS_SYS(sys_ppoll, 5) + MIPS_SYS(sys_unshare, 1) + MIPS_SYS(sys_splice, 6) + MIPS_SYS(sys_sync_file_range, 7) /* 4305 */ + MIPS_SYS(sys_tee, 4) + MIPS_SYS(sys_vmsplice, 4) + MIPS_SYS(sys_move_pages, 6) + MIPS_SYS(sys_set_robust_list, 2) + MIPS_SYS(sys_get_robust_list, 3) /* 4310 */ + MIPS_SYS(sys_kexec_load, 4) + MIPS_SYS(sys_getcpu, 3) + MIPS_SYS(sys_epoll_pwait, 6) + MIPS_SYS(sys_ioprio_set, 3) + MIPS_SYS(sys_ioprio_get, 2) + MIPS_SYS(sys_utimensat, 4) + MIPS_SYS(sys_signalfd, 3) + MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */ + MIPS_SYS(sys_eventfd, 1) + MIPS_SYS(sys_fallocate, 6) /* 4320 */ + MIPS_SYS(sys_timerfd_create, 2) + MIPS_SYS(sys_timerfd_gettime, 2) + MIPS_SYS(sys_timerfd_settime, 4) + MIPS_SYS(sys_signalfd4, 4) + MIPS_SYS(sys_eventfd2, 2) /* 4325 */ + MIPS_SYS(sys_epoll_create1, 1) + MIPS_SYS(sys_dup3, 3) + MIPS_SYS(sys_pipe2, 2) + MIPS_SYS(sys_inotify_init1, 1) + MIPS_SYS(sys_preadv, 5) /* 4330 */ + MIPS_SYS(sys_pwritev, 5) + MIPS_SYS(sys_rt_tgsigqueueinfo, 4) + MIPS_SYS(sys_perf_event_open, 5) + MIPS_SYS(sys_accept4, 4) + MIPS_SYS(sys_recvmmsg, 5) /* 4335 */ + MIPS_SYS(sys_fanotify_init, 2) + MIPS_SYS(sys_fanotify_mark, 6) + MIPS_SYS(sys_prlimit64, 4) + MIPS_SYS(sys_name_to_handle_at, 5) + MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */ + MIPS_SYS(sys_clock_adjtime, 2) + MIPS_SYS(sys_syncfs, 1) + MIPS_SYS(sys_sendmmsg, 4) + MIPS_SYS(sys_setns, 2) + MIPS_SYS(sys_process_vm_readv, 6) /* 345 */ + MIPS_SYS(sys_process_vm_writev, 6) + MIPS_SYS(sys_kcmp, 5) + MIPS_SYS(sys_finit_module, 3) + MIPS_SYS(sys_sched_setattr, 2) + MIPS_SYS(sys_sched_getattr, 3) /* 350 */ + MIPS_SYS(sys_renameat2, 5) + MIPS_SYS(sys_seccomp, 3) + MIPS_SYS(sys_getrandom, 3) + MIPS_SYS(sys_memfd_create, 2) + MIPS_SYS(sys_bpf, 3) /* 355 */ + MIPS_SYS(sys_execveat, 5) + MIPS_SYS(sys_userfaultfd, 1) + MIPS_SYS(sys_membarrier, 2) + MIPS_SYS(sys_mlock2, 3) + MIPS_SYS(sys_copy_file_range, 6) /* 360 */ + MIPS_SYS(sys_preadv2, 6) + MIPS_SYS(sys_pwritev2, 6) +}; +# undef MIPS_SYS +# endif /* O32 */ + +static int do_store_exclusive(CPUMIPSState *env) +{ + target_ulong addr; + target_ulong page_addr; + target_ulong val; + int flags; + int segv =3D 0; + int reg; + int d; + + addr =3D env->lladdr; + page_addr =3D addr & TARGET_PAGE_MASK; + start_exclusive(); + mmap_lock(); + flags =3D page_get_flags(page_addr); + if ((flags & PAGE_READ) =3D=3D 0) { + segv =3D 1; + } else { + reg =3D env->llreg & 0x1f; + d =3D (env->llreg & 0x20) !=3D 0; + if (d) { + segv =3D get_user_s64(val, addr); + } else { + segv =3D get_user_s32(val, addr); + } + if (!segv) { + if (val !=3D env->llval) { + env->active_tc.gpr[reg] =3D 0; + } else { + if (d) { + segv =3D put_user_u64(env->llnewval, addr); + } else { + segv =3D put_user_u32(env->llnewval, addr); + } + if (!segv) { + env->active_tc.gpr[reg] =3D 1; + } + } + } + } + env->lladdr =3D -1; + if (!segv) { + env->active_tc.PC +=3D 4; + } + mmap_unlock(); + end_exclusive(); + return segv; +} + +/* Break codes */ +enum { + BRK_OVERFLOW =3D 6, + BRK_DIVZERO =3D 7 +}; + +static int do_break(CPUMIPSState *env, target_siginfo_t *info, + unsigned int code) +{ + int ret =3D -1; + + switch (code) { + case BRK_OVERFLOW: + case BRK_DIVZERO: + info->si_signo =3D TARGET_SIGFPE; + info->si_errno =3D 0; + info->si_code =3D (code =3D=3D BRK_OVERFLOW) ? FPE_INTOVF : FPE_IN= TDIV; + queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info); + ret =3D 0; + break; + default: + info->si_signo =3D TARGET_SIGTRAP; + info->si_errno =3D 0; + queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info); + ret =3D 0; + break; + } + + return ret; +} + +void cpu_loop(CPUMIPSState *env) +{ + CPUState *cs =3D CPU(mips_env_get_cpu(env)); + target_siginfo_t info; + int trapnr; + abi_long ret; +# ifdef TARGET_ABI_MIPSO32 + unsigned int syscall_num; +# endif + + for(;;) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch(trapnr) { + case EXCP_SYSCALL: + env->active_tc.PC +=3D 4; +# ifdef TARGET_ABI_MIPSO32 + syscall_num =3D env->active_tc.gpr[2] - 4000; + if (syscall_num >=3D sizeof(mips_syscall_args)) { + ret =3D -TARGET_ENOSYS; + } else { + int nb_args; + abi_ulong sp_reg; + abi_ulong arg5 =3D 0, arg6 =3D 0, arg7 =3D 0, arg8 =3D 0; + + nb_args =3D mips_syscall_args[syscall_num]; + sp_reg =3D env->active_tc.gpr[29]; + switch (nb_args) { + /* these arguments are taken from the stack */ + case 8: + if ((ret =3D get_user_ual(arg8, sp_reg + 28)) !=3D 0) { + goto done_syscall; + } + case 7: + if ((ret =3D get_user_ual(arg7, sp_reg + 24)) !=3D 0) { + goto done_syscall; + } + case 6: + if ((ret =3D get_user_ual(arg6, sp_reg + 20)) !=3D 0) { + goto done_syscall; + } + case 5: + if ((ret =3D get_user_ual(arg5, sp_reg + 16)) !=3D 0) { + goto done_syscall; + } + default: + break; + } + ret =3D do_syscall(env, env->active_tc.gpr[2], + env->active_tc.gpr[4], + env->active_tc.gpr[5], + env->active_tc.gpr[6], + env->active_tc.gpr[7], + arg5, arg6, arg7, arg8); + } +done_syscall: +# else + ret =3D do_syscall(env, env->active_tc.gpr[2], + env->active_tc.gpr[4], env->active_tc.gpr[5], + env->active_tc.gpr[6], env->active_tc.gpr[7], + env->active_tc.gpr[8], env->active_tc.gpr[9], + env->active_tc.gpr[10], env->active_tc.gpr[11= ]); +# endif /* O32 */ + if (ret =3D=3D -TARGET_ERESTARTSYS) { + env->active_tc.PC -=3D 4; + break; + } + if (ret =3D=3D -TARGET_QEMU_ESIGRETURN) { + /* Returning from a successful sigreturn syscall. + Avoid clobbering register state. */ + break; + } + if ((abi_ulong)ret >=3D (abi_ulong)-1133) { + env->active_tc.gpr[7] =3D 1; /* error flag */ + ret =3D -ret; + } else { + env->active_tc.gpr[7] =3D 0; /* error flag */ + } + env->active_tc.gpr[2] =3D ret; + break; + case EXCP_TLBL: + case EXCP_TLBS: + case EXCP_AdEL: + case EXCP_AdES: + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + /* XXX: check env->error_code */ + info.si_code =3D TARGET_SEGV_MAPERR; + info._sifields._sigfault._addr =3D env->CP0_BadVAddr; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_CpU: + case EXCP_RI: + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D 0; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case EXCP_DEBUG: + { + int sig; + + sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); + if (sig) + { + info.si_signo =3D sig; + info.si_errno =3D 0; + info.si_code =3D TARGET_TRAP_BRKPT; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + } + break; + case EXCP_SC: + if (do_store_exclusive(env)) { + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info.si_code =3D TARGET_SEGV_MAPERR; + info._sifields._sigfault._addr =3D env->active_tc.PC; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + break; + case EXCP_DSPDIS: + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D TARGET_ILL_ILLOPC; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + /* The code below was inspired by the MIPS Linux kernel trap + * handling code in arch/mips/kernel/traps.c. + */ + case EXCP_BREAK: + { + abi_ulong trap_instr; + unsigned int code; + + if (env->hflags & MIPS_HFLAG_M16) { + if (env->insn_flags & ASE_MICROMIPS) { + /* microMIPS mode */ + ret =3D get_user_u16(trap_instr, env->active_tc.PC= ); + if (ret !=3D 0) { + goto error; + } + + if ((trap_instr >> 10) =3D=3D 0x11) { + /* 16-bit instruction */ + code =3D trap_instr & 0xf; + } else { + /* 32-bit instruction */ + abi_ulong instr_lo; + + ret =3D get_user_u16(instr_lo, + env->active_tc.PC + 2); + if (ret !=3D 0) { + goto error; + } + trap_instr =3D (trap_instr << 16) | instr_lo; + code =3D ((trap_instr >> 6) & ((1 << 20) - 1)); + /* Unfortunately, microMIPS also suffers from + the old assembler bug... */ + if (code >=3D (1 << 10)) { + code >>=3D 10; + } + } + } else { + /* MIPS16e mode */ + ret =3D get_user_u16(trap_instr, env->active_tc.PC= ); + if (ret !=3D 0) { + goto error; + } + code =3D (trap_instr >> 6) & 0x3f; + } + } else { + ret =3D get_user_u32(trap_instr, env->active_tc.PC); + if (ret !=3D 0) { + goto error; + } + + /* As described in the original Linux kernel code, the + * below checks on 'code' are to work around an old + * assembly bug. + */ + code =3D ((trap_instr >> 6) & ((1 << 20) - 1)); + if (code >=3D (1 << 10)) { + code >>=3D 10; + } + } + + if (do_break(env, &info, code) !=3D 0) { + goto error; + } + } + break; + case EXCP_TRAP: + { + abi_ulong trap_instr; + unsigned int code =3D 0; + + if (env->hflags & MIPS_HFLAG_M16) { + /* microMIPS mode */ + abi_ulong instr[2]; + + ret =3D get_user_u16(instr[0], env->active_tc.PC) || + get_user_u16(instr[1], env->active_tc.PC + 2); + + trap_instr =3D (instr[0] << 16) | instr[1]; + } else { + ret =3D get_user_u32(trap_instr, env->active_tc.PC); + } + + if (ret !=3D 0) { + goto error; + } + + /* The immediate versions don't provide a code. */ + if (!(trap_instr & 0xFC000000)) { + if (env->hflags & MIPS_HFLAG_M16) { + /* microMIPS mode */ + code =3D ((trap_instr >> 12) & ((1 << 4) - 1)); + } else { + code =3D ((trap_instr >> 6) & ((1 << 10) - 1)); + } + } + + if (do_break(env, &info, code) !=3D 0) { + goto error; + } + } + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + default: +error: + EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\= n", trapnr); + abort(); + } + process_pending_signals(env); + } +} =20 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + CPUState *cpu =3D ENV_GET_CPU(env); + TaskState *ts =3D cpu->opaque; + struct image_info *info =3D ts->info; + int i; + + for(i =3D 0; i < 32; i++) { + env->active_tc.gpr[i] =3D regs->regs[i]; + } + env->active_tc.PC =3D regs->cp0_epc & ~(target_ulong)1; + if (regs->cp0_epc & 1) { + env->hflags |=3D MIPS_HFLAG_M16; + } + if (((info->elf_flags & EF_MIPS_NAN2008) !=3D 0) !=3D + ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) !=3D 0)) { + if ((env->active_fpu.fcr31_rw_bitmask & + (1 << FCR31_NAN2008)) =3D=3D 0) { + fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n"= ); + exit(1); + } + if ((info->elf_flags & EF_MIPS_NAN2008) !=3D 0) { + env->active_fpu.fcr31 |=3D (1 << FCR31_NAN2008); + } else { + env->active_fpu.fcr31 &=3D ~(1 << FCR31_NAN2008); + } + restore_snan_bit_mode(env); + } } diff --git a/linux-user/mips64/cpu_loop.c b/linux-user/mips64/cpu_loop.c index b7700a5561..858bc5be78 100644 --- a/linux-user/mips64/cpu_loop.c +++ b/linux-user/mips64/cpu_loop.c @@ -17,10 +17,4 @@ * along with this program; if not, see . */ =20 -#include "qemu/osdep.h" -#include "qemu.h" -#include "cpu_loop-common.h" - -void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) -{ -} +#include "../mips/cpu_loop.c" --=20 2.14.3 From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522092109083971.1628858554004; Mon, 26 Mar 2018 12:21:49 -0700 (PDT) Received: from localhost ([::1]:58669 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xgi-0007Y1-4G for importer@patchew.org; Mon, 26 Mar 2018 15:21:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58577) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xbt-0003OV-96 for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0Xbr-0001eP-LE for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:49 -0400 Received: from mout.kundenserver.de ([212.227.126.131]:45713) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0Xbr-0001dq-AP; Mon, 26 Mar 2018 15:16:47 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MYpHi-1f5TJf3QTS-00VT6p; Mon, 26 Mar 2018 21:16:30 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:15:52 +0200 Message-Id: <20180326191603.10217-9-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:TwcBidXyKCqiS/lnVRA25MaUtjJ2WvQu1vt/IseI7N+/AeM7Y7c IVTJAQqLvXf7PQSSWM3ZCC4E1pMjofXKYYpietOwFJ6XZTW5PK+pQufPw/2oozrWySx8yjo 8yba5dIfVkqVYJF63UJx0EJWupULryR0w4YkpYZfDEBCcu2CKvWMS1F/zKwfahqb8J24lMW Foz0jRXDR2hlcuxI3DP7Q== X-UI-Out-Filterresults: notjunk:1;V01:K0:v6/NCo3/qzY=:JUtd2OHuKgmaaj7sv/EI+H ExMrYrjl2i7iaMlcSM04c1MhEih9c8DpUCRqChj6VInid3Cisa1O7Bs7a8BWkSFs/i50ImzDA pRvC5lnZcG68nC+5gaBfglt1ekxQJowNd8vQ9T1vL9TvVyo4Y5VXy+7sHpDpC8oxlAxepTPdI l4AHumPy/so3g6Q71+wOnSEJcSc83PsdcXGmUUrANes+JC6BZCu9mqL2ccdscXN/YF1UvGnbW 28eJPtlTg0LLS9qv2pnXw2MRTiz/zsC+z7z86LuwUAjhuuFKyisQZyMAVHY8CJSLvIZEyioOn +SamI5npio4evNJeR3v8bOQhFZWAGQ6/hHBaqA25SS0RtTaq2QCnPxQXowBsiRLswQKYjcMEH 3GeybQ+jCCiRIZcJ8l5U13N3HuHPfxyMj2x8QmtXTElJUkNjQfgwAQI+HDVjmd4W+sy4GHXo5 5bFeGSJtfegOz2llg+8CiYIvSIz9wxZhR5VnFoqXoxiCAN3Pzzk/iF8dPTkkNh/bNjder4HSx 3mLxkroSMZIRsNzFibVQYnXszTNDrtxsVocuwS6Mh2W1urVOWlKDnLwZ1t+wqzRvJyplKJZ5G u2GaI3NUo42IQZQrG44FtEYGkK+/EApkNh9FKo2DsbM/foMERZshbE/7b/5HqO6bKKE4pZTsQ iYPxwFFFo1CxCGz2jEMSmmWecg4MCSAgKb4/RbmoGMdxRSfPBBO8cYFsgG8O1XPQ+Qh6MtHiL 4KJNQxeiO3tdBTaEEt6h7qPQcfDSPMbKCKi4pw== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.131 Subject: [Qemu-devel] [PATCH for 2.13 08/19] linux-user: move nios2 cpu loop to nios2 directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to nios2/cpu_loop.c. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- linux-user/main.c | 133 ----------------------------------------= ---- linux-user/nios2/cpu_loop.c | 126 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 126 insertions(+), 133 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 490733a3fb..6ee474e5c2 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -149,109 +149,6 @@ void fork_end(int child) } } =20 -#ifdef TARGET_NIOS2 - -void cpu_loop(CPUNios2State *env) -{ - CPUState *cs =3D ENV_GET_CPU(env); - Nios2CPU *cpu =3D NIOS2_CPU(cs); - target_siginfo_t info; - int trapnr, gdbsig, ret; - - for (;;) { - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - gdbsig =3D 0; - - switch (trapnr) { - case EXCP_INTERRUPT: - /* just indicate that signals should be handled asap */ - break; - case EXCP_TRAP: - if (env->regs[R_AT] =3D=3D 0) { - abi_long ret; - qemu_log_mask(CPU_LOG_INT, "\nSyscall\n"); - - ret =3D do_syscall(env, env->regs[2], - env->regs[4], env->regs[5], env->regs[6], - env->regs[7], env->regs[8], env->regs[9], - 0, 0); - - if (env->regs[2] =3D=3D 0) { /* FIXME: syscall 0 workar= ound */ - ret =3D 0; - } - - env->regs[2] =3D abs(ret); - /* Return value is 0..4096 */ - env->regs[7] =3D (ret > 0xfffffffffffff000ULL); - env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; - env->regs[CR_STATUS] &=3D ~0x3; - env->regs[R_EA] =3D env->regs[R_PC] + 4; - env->regs[R_PC] +=3D 4; - break; - } else { - qemu_log_mask(CPU_LOG_INT, "\nTrap\n"); - - env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; - env->regs[CR_STATUS] &=3D ~0x3; - env->regs[R_EA] =3D env->regs[R_PC] + 4; - env->regs[R_PC] =3D cpu->exception_addr; - - gdbsig =3D TARGET_SIGTRAP; - break; - } - case 0xaa: - switch (env->regs[R_PC]) { - /*case 0x1000:*/ /* TODO:__kuser_helper_version */ - case 0x1004: /* __kuser_cmpxchg */ - start_exclusive(); - if (env->regs[4] & 0x3) { - goto kuser_fail; - } - ret =3D get_user_u32(env->regs[2], env->regs[4]); - if (ret) { - end_exclusive(); - goto kuser_fail; - } - env->regs[2] -=3D env->regs[5]; - if (env->regs[2] =3D=3D 0) { - put_user_u32(env->regs[6], env->regs[4]); - } - end_exclusive(); - env->regs[R_PC] =3D env->regs[R_RA]; - break; - /*case 0x1040:*/ /* TODO:__kuser_sigtramp */ - default: - ; -kuser_fail: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* TODO: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->regs[R_PC]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; - default: - EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting= \n", - trapnr); - gdbsig =3D TARGET_SIGILL; - break; - } - if (gdbsig) { - gdb_handlesig(cs, gdbsig); - if (gdbsig !=3D TARGET_SIGTRAP) { - exit(EXIT_FAILURE); - } - } - - process_pending_signals(env); - } -} - -#endif /* TARGET_NIOS2 */ - #ifdef TARGET_OPENRISC =20 void cpu_loop(CPUOpenRISCState *env) @@ -2542,36 +2439,6 @@ int main(int argc, char **argv, char **envp) env->regs[31] =3D regs->r31; =20 env->sregs[SR_PC] =3D regs->pc; } -#elif defined(TARGET_NIOS2) - { - env->regs[0] =3D 0; - env->regs[1] =3D regs->r1; - env->regs[2] =3D regs->r2; - env->regs[3] =3D regs->r3; - env->regs[4] =3D regs->r4; - env->regs[5] =3D regs->r5; - env->regs[6] =3D regs->r6; - env->regs[7] =3D regs->r7; - env->regs[8] =3D regs->r8; - env->regs[9] =3D regs->r9; - env->regs[10] =3D regs->r10; - env->regs[11] =3D regs->r11; - env->regs[12] =3D regs->r12; - env->regs[13] =3D regs->r13; - env->regs[14] =3D regs->r14; - env->regs[15] =3D regs->r15; - /* TODO: unsigned long orig_r2; */ - env->regs[R_RA] =3D regs->ra; - env->regs[R_FP] =3D regs->fp; - env->regs[R_SP] =3D regs->sp; - env->regs[R_GP] =3D regs->gp; - env->regs[CR_ESTATUS] =3D regs->estatus; - env->regs[R_EA] =3D regs->ea; - /* TODO: unsigned long orig_r7; */ - - /* Emulate eret when starting thread. */ - env->regs[R_PC] =3D regs->ea; - } #elif defined(TARGET_OPENRISC) { int i; diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index b7700a5561..dac7a06181 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -21,6 +21,132 @@ #include "qemu.h" #include "cpu_loop-common.h" =20 +void cpu_loop(CPUNios2State *env) +{ + CPUState *cs =3D ENV_GET_CPU(env); + Nios2CPU *cpu =3D NIOS2_CPU(cs); + target_siginfo_t info; + int trapnr, gdbsig, ret; + + for (;;) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + gdbsig =3D 0; + + switch (trapnr) { + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case EXCP_TRAP: + if (env->regs[R_AT] =3D=3D 0) { + abi_long ret; + qemu_log_mask(CPU_LOG_INT, "\nSyscall\n"); + + ret =3D do_syscall(env, env->regs[2], + env->regs[4], env->regs[5], env->regs[6], + env->regs[7], env->regs[8], env->regs[9], + 0, 0); + + if (env->regs[2] =3D=3D 0) { /* FIXME: syscall 0 workar= ound */ + ret =3D 0; + } + + env->regs[2] =3D abs(ret); + /* Return value is 0..4096 */ + env->regs[7] =3D (ret > 0xfffffffffffff000ULL); + env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; + env->regs[CR_STATUS] &=3D ~0x3; + env->regs[R_EA] =3D env->regs[R_PC] + 4; + env->regs[R_PC] +=3D 4; + break; + } else { + qemu_log_mask(CPU_LOG_INT, "\nTrap\n"); + + env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; + env->regs[CR_STATUS] &=3D ~0x3; + env->regs[R_EA] =3D env->regs[R_PC] + 4; + env->regs[R_PC] =3D cpu->exception_addr; + + gdbsig =3D TARGET_SIGTRAP; + break; + } + case 0xaa: + switch (env->regs[R_PC]) { + /*case 0x1000:*/ /* TODO:__kuser_helper_version */ + case 0x1004: /* __kuser_cmpxchg */ + start_exclusive(); + if (env->regs[4] & 0x3) { + goto kuser_fail; + } + ret =3D get_user_u32(env->regs[2], env->regs[4]); + if (ret) { + end_exclusive(); + goto kuser_fail; + } + env->regs[2] -=3D env->regs[5]; + if (env->regs[2] =3D=3D 0) { + put_user_u32(env->regs[6], env->regs[4]); + } + end_exclusive(); + env->regs[R_PC] =3D env->regs[R_RA]; + break; + /*case 0x1040:*/ /* TODO:__kuser_sigtramp */ + default: + ; +kuser_fail: + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + /* TODO: check env->error_code */ + info.si_code =3D TARGET_SEGV_MAPERR; + info._sifields._sigfault._addr =3D env->regs[R_PC]; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + break; + default: + EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting= \n", + trapnr); + gdbsig =3D TARGET_SIGILL; + break; + } + if (gdbsig) { + gdb_handlesig(cs, gdbsig); + if (gdbsig !=3D TARGET_SIGTRAP) { + exit(EXIT_FAILURE); + } + } + + process_pending_signals(env); + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + env->regs[0] =3D 0; + env->regs[1] =3D regs->r1; + env->regs[2] =3D regs->r2; + env->regs[3] =3D regs->r3; + env->regs[4] =3D regs->r4; + env->regs[5] =3D regs->r5; + env->regs[6] =3D regs->r6; + env->regs[7] =3D regs->r7; + env->regs[8] =3D regs->r8; + env->regs[9] =3D regs->r9; + env->regs[10] =3D regs->r10; + env->regs[11] =3D regs->r11; + env->regs[12] =3D regs->r12; + env->regs[13] =3D regs->r13; + env->regs[14] =3D regs->r14; + env->regs[15] =3D regs->r15; + /* TODO: unsigned long orig_r2; */ + env->regs[R_RA] =3D regs->ra; + env->regs[R_FP] =3D regs->fp; + env->regs[R_SP] =3D regs->sp; + env->regs[R_GP] =3D regs->gp; + env->regs[CR_ESTATUS] =3D regs->estatus; + env->regs[R_EA] =3D regs->ea; + /* TODO: unsigned long orig_r7; */ + + /* Emulate eret when starting thread. */ + env->regs[R_PC] =3D regs->ea; } --=20 2.14.3 From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152209194486060.61520310823505; Mon, 26 Mar 2018 12:19:04 -0700 (PDT) Received: from localhost ([::1]:58646 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xdz-0004j7-H9 for importer@patchew.org; Mon, 26 Mar 2018 15:18:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58525) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xbq-0003MH-Pu for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0Xbp-0001dE-Cd for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:46 -0400 Received: from mout.kundenserver.de ([212.227.126.131]:52229) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0Xbp-0001cA-2d; Mon, 26 Mar 2018 15:16:45 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MMtZ5-1evKoC1SBD-008YOs; Mon, 26 Mar 2018 21:16:31 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:15:53 +0200 Message-Id: <20180326191603.10217-10-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:eNbSgqBSsm/rnBuHcQXuBjTTEuu1/pKhzb77SgbJEGJzyjQ/Umt FPNVas7r9m3WV2kCYxqHdn0TC4KLxJO24c/Y+LobFsBmAruAb7xl4Qhgh4X1Sv5BRdq4f7o AHSPaI19HLfMRywgFTRgsXHYxNg3JtJVP+M+9DHLAJOjbl+MyCIBwtGBeufexXVYIGnrxfq 2c3yjliMOJIhWs9cPoTgg== X-UI-Out-Filterresults: notjunk:1;V01:K0:14QCD/wmP90=:zMqHVFJnCxQlKeoPCnB8V9 d4/p0qwzlw8SvUbcJE5EvjZiczKkjUNH2bkA/FexBGFiYy5sqfhKnS0wiTlHobaeCMwnCE0W/ Y+VAuN9y7QuOHX87uTBzGJOzaoguJ0xEylRBt8EDcCIuwRzDf8oBUNsM6MHvwOsjAiL56sxWp exY5RJkji7BganjYzdslv6JegicqQjeFWScoqRXrH+hL9I7z+pgC5gDKr3+7tWAZhDD+QtsiW uGfZ+zvrBDyzndLKwraJmNcSaWS0Leo5eWxcRsxHWclhMLcD5VuIBYDHyDviU4rrmFjtKou4S eiN7HtkQSrkdOqsjOGeB/MplDhu4s8nkg9blw8MuXJDuovBoOOKWu/YrG5pPoICCdcJfgB6Jt /j4q0kiIQ/siFbhRh1FVqPqnzC0Qqu73t4mMtca/1wdHkElrRcR9mZHsQYijs50sRwQXfIY1S IVXit309MLcY3sicj4bWIUpIDWcjYlUjbJZYjeCGbfeMFbM7ulTzekLcCqdi2h+RgSWRj5dz2 By87Ry4A1pipd+BkYXpw9yNeoCxSqxjulr5PnJgMQx9EdqP57lcwX4twDsY+gPjfBB+Si95d4 vkVbo5z1to60OIoID9EyaKlwmmGMd+wTxXNaedpaZyMCeGQIEnn/18jPcz8h01r5mhmX+NpG3 06SbUv73bxQBjeeCJxbXDizygFrov/dzTB3pYxG4Z+o2OVq7nq+fSE+2+gO+sqi0an0LY80Es NgbPzOhgRFS2miydTpm2qm45plRQ5FIBh7Jz3w== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.131 Subject: [Qemu-devel] [PATCH for 2.13 09/19] linux-user: move openrisc cpu loop to openrisc directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to openrisc/cpu_loop.c. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- linux-user/main.c | 96 --------------------------------------= ---- linux-user/openrisc/cpu_loop.c | 89 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+), 96 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 6ee474e5c2..8530dbfdf1 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -149,92 +149,6 @@ void fork_end(int child) } } =20 -#ifdef TARGET_OPENRISC - -void cpu_loop(CPUOpenRISCState *env) -{ - CPUState *cs =3D CPU(openrisc_env_get_cpu(env)); - int trapnr; - abi_long ret; - target_siginfo_t info; - - for (;;) { - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - switch (trapnr) { - case EXCP_SYSCALL: - env->pc +=3D 4; /* 0xc00; */ - ret =3D do_syscall(env, - cpu_get_gpr(env, 11), /* return value */ - cpu_get_gpr(env, 3), /* r3 - r7 are params */ - cpu_get_gpr(env, 4), - cpu_get_gpr(env, 5), - cpu_get_gpr(env, 6), - cpu_get_gpr(env, 7), - cpu_get_gpr(env, 8), 0, 0); - if (ret =3D=3D -TARGET_ERESTARTSYS) { - env->pc -=3D 4; - } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { - cpu_set_gpr(env, 11, ret); - } - break; - case EXCP_DPF: - case EXCP_IPF: - case EXCP_RANGE: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_ALIGN: - info.si_signo =3D TARGET_SIGBUS; - info.si_errno =3D 0; - info.si_code =3D TARGET_BUS_ADRALN; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_ILLEGAL: - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D TARGET_ILL_ILLOPC; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_FPE: - info.si_signo =3D TARGET_SIGFPE; - info.si_errno =3D 0; - info.si_code =3D 0; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_INTERRUPT: - /* We processed the pending cpu work above. */ - break; - case EXCP_DEBUG: - trapnr =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (trapnr) { - info.si_signo =3D trapnr; - info.si_errno =3D 0; - info.si_code =3D TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; - case EXCP_ATOMIC: - cpu_exec_step_atomic(cs); - break; - default: - g_assert_not_reached(); - } - process_pending_signals(env); - } -} - -#endif /* TARGET_OPENRISC */ - #ifdef TARGET_SH4 void cpu_loop(CPUSH4State *env) { @@ -2439,16 +2353,6 @@ int main(int argc, char **argv, char **envp) env->regs[31] =3D regs->r31; =20 env->sregs[SR_PC] =3D regs->pc; } -#elif defined(TARGET_OPENRISC) - { - int i; - - for (i =3D 0; i < 32; i++) { - cpu_set_gpr(env, i, regs->gpr[i]); - } - env->pc =3D regs->pc; - cpu_set_sr(env, regs->sr); - } #elif defined(TARGET_RISCV) { env->pc =3D regs->sepc; diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index b7700a5561..6c6ea871e1 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -21,6 +21,95 @@ #include "qemu.h" #include "cpu_loop-common.h" =20 +void cpu_loop(CPUOpenRISCState *env) +{ + CPUState *cs =3D CPU(openrisc_env_get_cpu(env)); + int trapnr; + abi_long ret; + target_siginfo_t info; + + for (;;) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch (trapnr) { + case EXCP_SYSCALL: + env->pc +=3D 4; /* 0xc00; */ + ret =3D do_syscall(env, + cpu_get_gpr(env, 11), /* return value */ + cpu_get_gpr(env, 3), /* r3 - r7 are params */ + cpu_get_gpr(env, 4), + cpu_get_gpr(env, 5), + cpu_get_gpr(env, 6), + cpu_get_gpr(env, 7), + cpu_get_gpr(env, 8), 0, 0); + if (ret =3D=3D -TARGET_ERESTARTSYS) { + env->pc -=3D 4; + } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { + cpu_set_gpr(env, 11, ret); + } + break; + case EXCP_DPF: + case EXCP_IPF: + case EXCP_RANGE: + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info.si_code =3D TARGET_SEGV_MAPERR; + info._sifields._sigfault._addr =3D env->pc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_ALIGN: + info.si_signo =3D TARGET_SIGBUS; + info.si_errno =3D 0; + info.si_code =3D TARGET_BUS_ADRALN; + info._sifields._sigfault._addr =3D env->pc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_ILLEGAL: + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D TARGET_ILL_ILLOPC; + info._sifields._sigfault._addr =3D env->pc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_FPE: + info.si_signo =3D TARGET_SIGFPE; + info.si_errno =3D 0; + info.si_code =3D 0; + info._sifields._sigfault._addr =3D env->pc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_INTERRUPT: + /* We processed the pending cpu work above. */ + break; + case EXCP_DEBUG: + trapnr =3D gdb_handlesig(cs, TARGET_SIGTRAP); + if (trapnr) { + info.si_signo =3D trapnr; + info.si_errno =3D 0; + info.si_code =3D TARGET_TRAP_BRKPT; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + default: + g_assert_not_reached(); + } + process_pending_signals(env); + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + int i; + + for (i =3D 0; i < 32; i++) { + cpu_set_gpr(env, i, regs->gpr[i]); + } + env->pc =3D regs->pc; + cpu_set_sr(env, regs->sr); } --=20 2.14.3 From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522092280197779.4023287929821; Mon, 26 Mar 2018 12:24:40 -0700 (PDT) Received: from localhost ([::1]:58687 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0XjL-0001pU-Db for importer@patchew.org; Mon, 26 Mar 2018 15:24:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58588) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xbu-0003PQ-B4 for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0Xbq-0001dh-8O for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:50 -0400 Received: from mout.kundenserver.de ([212.227.126.130]:37011) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0Xbp-0001d0-V5; Mon, 26 Mar 2018 15:16:46 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0LcaSx-1eK5G33EMp-00k69W; Mon, 26 Mar 2018 21:16:33 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:15:54 +0200 Message-Id: <20180326191603.10217-11-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:41D/oTyIwg92KGMKnoVj18QgvZFuauy9OqHHFaGwROnSyTRsDVv lZNeCk9EHNTE1WjW7QGX6xwFqSNV+UZUVex6AHJ0Yn2srd7mMBi0mSMDYTU4UUs8+AYpQNf E3RkOxltO7180pyreNvJwfUfBzr4aKw0y5dWGCkmRpbF6Cn0CFLUWqGnEe+/siCtkP493qv JgpKlyIQ4iaBhY3euGSBw== X-UI-Out-Filterresults: notjunk:1;V01:K0:1yycTwYWfos=:RJJe8T0Bx7jXHTQ8gCBbWD dJOeBU5vALhonj/JiTsSbJd3pfBbrUsOSZrUoB4cGZveMWB/oIWLsSHEsgUC8kvhAUheSr9ld LYbvsoTf578/j2HZxwds2TtC9R2VeS2dS8+Xz9ua7UuAB0m38tAaXpH3FqU7Ste3PXaogENRe Za4qi+t3UOtywa0eLxEAkka1oF7/EBtRs4iIEVtubinOZlRjep8IVDUEXR80GxfEN3zRQ+gtK rQxn7l0nO/RFWXqt3gmNR7YunMFQd3cQYNonGlcCkA+3vzl4w8lFzjWRwcPdL81qks20s06+9 l9nqW32kFpG++B29u3YCKWktwD6Hj3EsAeeQ/uAvXS0pbAHQZZI0MnIzU9DRJAyVqbw3RlmwH XswZd9KcrfI0Fw1vnsaWxrD3WbBoaPto4j+sQ25UlTFiDqrrkb25yHwecUDivd8DueCB8pVZY 56DJHLuq2ZUambdQBq+8K5nMUE2anRWZxaMltOkH3LSFg7vb7jo3Lqm9nXoOC38X6jAHRTBIU /2BLb2cyKbDSOdkP7V0cPRsvBDZW07kMJoC52o5vSlX/aV9zQ1aS1XpTNp+6em77Z61/LA3RP 5+nrn578AMAGVRa1iE+pxeiPW3tupiX1L4WP0KdF/NDLR9aFUhvnPMxYgY8lNavUU5dc3nR7O T+DSaUT+6RlnDDssFpX3BAT4H16w431PUHVN2cFUWQhWX9zbVKeRt/HCRYpc4t/wt9m9jmsLj SlbLtolkQ9DcRVog5l3x8utKstbZoNr5qrMQWQ== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.130 Subject: [Qemu-devel] [PATCH for 2.13 10/19] linux-user: move sh4 cpu loop to sh4 directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to sh4/cpu_loop.c. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- linux-user/main.c | 90 -------------------------------------------= ---- linux-user/sh4/cpu_loop.c | 85 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 85 insertions(+), 90 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 8530dbfdf1..211148858e 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -149,87 +149,6 @@ void fork_end(int child) } } =20 -#ifdef TARGET_SH4 -void cpu_loop(CPUSH4State *env) -{ - CPUState *cs =3D CPU(sh_env_get_cpu(env)); - int trapnr, ret; - target_siginfo_t info; - - while (1) { - bool arch_interrupt =3D true; - - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - switch (trapnr) { - case 0x160: - env->pc +=3D 2; - ret =3D do_syscall(env, - env->gregs[3], - env->gregs[4], - env->gregs[5], - env->gregs[6], - env->gregs[7], - env->gregs[0], - env->gregs[1], - 0, 0); - if (ret =3D=3D -TARGET_ERESTARTSYS) { - env->pc -=3D 2; - } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { - env->gregs[0] =3D ret; - } - break; - case EXCP_INTERRUPT: - /* just indicate that signals should be handled asap */ - break; - case EXCP_DEBUG: - { - int sig; - - sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (sig) { - info.si_signo =3D sig; - info.si_errno =3D 0; - info.si_code =3D TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } else { - arch_interrupt =3D false; - } - } - break; - case 0xa0: - case 0xc0: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->tea; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_ATOMIC: - cpu_exec_step_atomic(cs); - arch_interrupt =3D false; - break; - default: - printf ("Unhandled trap: 0x%x\n", trapnr); - cpu_dump_state(cs, stderr, fprintf, 0); - exit(EXIT_FAILURE); - } - process_pending_signals (env); - - /* Most of the traps imply an exception or interrupt, which - implies an REI instruction has been executed. Which means - that LDST (aka LOK_ADDR) should be cleared. But there are - a few exceptions for traps internal to QEMU. */ - if (arch_interrupt) { - env->lock_addr =3D -1; - } - } -} -#endif - #ifdef TARGET_CRIS void cpu_loop(CPUCRISState *env) { @@ -2358,15 +2277,6 @@ int main(int argc, char **argv, char **envp) env->pc =3D regs->sepc; env->gpr[xSP] =3D regs->sp; } -#elif defined(TARGET_SH4) - { - int i; - - for(i =3D 0; i < 16; i++) { - env->gregs[i] =3D regs->regs[i]; - } - env->pc =3D regs->pc; - } #elif defined(TARGET_ALPHA) { int i; diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c index b7700a5561..3f0b9320e7 100644 --- a/linux-user/sh4/cpu_loop.c +++ b/linux-user/sh4/cpu_loop.c @@ -21,6 +21,91 @@ #include "qemu.h" #include "cpu_loop-common.h" =20 +void cpu_loop(CPUSH4State *env) +{ + CPUState *cs =3D CPU(sh_env_get_cpu(env)); + int trapnr, ret; + target_siginfo_t info; + + while (1) { + bool arch_interrupt =3D true; + + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch (trapnr) { + case 0x160: + env->pc +=3D 2; + ret =3D do_syscall(env, + env->gregs[3], + env->gregs[4], + env->gregs[5], + env->gregs[6], + env->gregs[7], + env->gregs[0], + env->gregs[1], + 0, 0); + if (ret =3D=3D -TARGET_ERESTARTSYS) { + env->pc -=3D 2; + } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { + env->gregs[0] =3D ret; + } + break; + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case EXCP_DEBUG: + { + int sig; + + sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); + if (sig) { + info.si_signo =3D sig; + info.si_errno =3D 0; + info.si_code =3D TARGET_TRAP_BRKPT; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } else { + arch_interrupt =3D false; + } + } + break; + case 0xa0: + case 0xc0: + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info.si_code =3D TARGET_SEGV_MAPERR; + info._sifields._sigfault._addr =3D env->tea; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + arch_interrupt =3D false; + break; + default: + printf ("Unhandled trap: 0x%x\n", trapnr); + cpu_dump_state(cs, stderr, fprintf, 0); + exit(EXIT_FAILURE); + } + process_pending_signals (env); + + /* Most of the traps imply an exception or interrupt, which + implies an REI instruction has been executed. Which means + that LDST (aka LOK_ADDR) should be cleared. But there are + a few exceptions for traps internal to QEMU. */ + if (arch_interrupt) { + env->lock_addr =3D -1; + } + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + int i; + + for(i =3D 0; i < 16; i++) { + env->gregs[i] =3D regs->regs[i]; + } + env->pc =3D regs->pc; } --=20 2.14.3 From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522092221780890.0301086421708; Mon, 26 Mar 2018 12:23:41 -0700 (PDT) Received: from localhost ([::1]:58685 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0XiW-0000mh-Ne for importer@patchew.org; Mon, 26 Mar 2018 15:23:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58659) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xby-0003TP-QD for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0Xbx-0001hA-HB for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:54 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:53033) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0Xbx-0001gm-7R; Mon, 26 Mar 2018 15:16:53 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0LfcCc-1eCgrj2wWY-00pLTf; Mon, 26 Mar 2018 21:16:34 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:15:55 +0200 Message-Id: <20180326191603.10217-12-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:m/S6NORjmjDvTV28y6dFeqrwry5YprNKAA2zb35tKdTIP6ND3SL ftt/1HZnTNNcIZDc2cvVWMEW+ZzwESBWzwZWwmsoYflUtnC6ku8rN7L118VEXTpTBbsMi36 XI2sOiiQrffds3U9822bxL5Iw3p/Xh26O/ZPIHADfKlE6sJ1p60JWhr7nZyKQxSviecXIjy S28eCZjug2L3hJkM/oOrA== X-UI-Out-Filterresults: notjunk:1;V01:K0:/CNchzKJx6s=:4vgClGB8dB2giyyQ9ARkJA SsJUJ4S8RjV1r9Q1CWY3v8CIiqZgi4rIFNw7fngmhrL5ZQiqkwDcpBP8q0Z9UFlz/IqzPaI7t beY1Wn3/C3ZuZ8iLj+W4pW7Nit7OsLvczUDcwX744g7ut+kJ7Loq9xOonQbknghp8SMFYIcRO R/Y0Qtvy5OJVchc7p2PPCZe3hzPemTqmSxG06IlRydT2QUsRXQsnCT1Wwi9BvT5kWn10ptB6w 9wMNpWuayoGbcyJdqCLwVKjdj3eURQ41B6Ks0NS7XEAxgJuF3wksrEN1kC7RgG/cObwwV9xq1 A3a0z2WYO2f5XVPVqSYPK18DWV6N4nWwFAxtRlBAlTAVUncfHBdz6/pKj/tBm/IrPl+U62FcU Xi9xq+W+6necRATBqrJRPI0EOvqgrkljQhJN4xDAG2DnsiAEiCdzFIA1vMQEFmZJUq+eoaBvN pGlUz476EdztVSQ9KbUspW3STa3cdZDcUPoFn34oFyi092eGzMztAe/hUgAHW0wnen2f3mpNg 245q11vZdnPaCepXroMSiuSnQvgMQcHQR/bK9bG+1Sq3i9K7HxhyQBueVtDfuzOvfBm2K8Rf/ /RYtyQvTEbGM1Uta5cqbENlQtFMOI99G0Q5vN+Z5T3VKa3vc2a+LUZgh46bJfVec4krxkr+5K BW9P1YRV82dpmxSj6fHAg36Ysh+JBSMyUqxEUOeKIJVxTTQ1taE/JzfJ16p0M/hcVXYRZEzCH iyDaLmPNfmXYr7WVkUYMY6b/4yQEYiGAcXM+OQ== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PATCH for 2.13 11/19] linux-user: move cris cpu loop to cris directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to cris/cpu_loop.c. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- linux-user/cris/cpu_loop.c | 89 ++++++++++++++++++++++++++++++++++++++++++= +++ linux-user/main.c | 90 ------------------------------------------= ---- 2 files changed, 89 insertions(+), 90 deletions(-) diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c index b7700a5561..96406e5c97 100644 --- a/linux-user/cris/cpu_loop.c +++ b/linux-user/cris/cpu_loop.c @@ -21,6 +21,95 @@ #include "qemu.h" #include "cpu_loop-common.h" =20 +void cpu_loop(CPUCRISState *env) +{ + CPUState *cs =3D CPU(cris_env_get_cpu(env)); + int trapnr, ret; + target_siginfo_t info; + =20 + while (1) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch (trapnr) { + case 0xaa: + { + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + /* XXX: check env->error_code */ + info.si_code =3D TARGET_SEGV_MAPERR; + info._sifields._sigfault._addr =3D env->pregs[PR_EDA]; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + break; + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case EXCP_BREAK: + ret =3D do_syscall(env,=20 + env->regs[9],=20 + env->regs[10],=20 + env->regs[11],=20 + env->regs[12],=20 + env->regs[13],=20 + env->pregs[7],=20 + env->pregs[11], + 0, 0); + if (ret =3D=3D -TARGET_ERESTARTSYS) { + env->pc -=3D 2; + } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { + env->regs[10] =3D ret; + } + break; + case EXCP_DEBUG: + { + int sig; + + sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); + if (sig) + { + info.si_signo =3D sig; + info.si_errno =3D 0; + info.si_code =3D TARGET_TRAP_BRKPT; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + } + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + default: + printf ("Unhandled trap: 0x%x\n", trapnr); + cpu_dump_state(cs, stderr, fprintf, 0); + exit(EXIT_FAILURE); + } + process_pending_signals (env); + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + CPUState *cpu =3D ENV_GET_CPU(env); + TaskState *ts =3D cpu->opaque; + struct image_info *info =3D ts->info; + + env->regs[0] =3D regs->r0; + env->regs[1] =3D regs->r1; + env->regs[2] =3D regs->r2; + env->regs[3] =3D regs->r3; + env->regs[4] =3D regs->r4; + env->regs[5] =3D regs->r5; + env->regs[6] =3D regs->r6; + env->regs[7] =3D regs->r7; + env->regs[8] =3D regs->r8; + env->regs[9] =3D regs->r9; + env->regs[10] =3D regs->r10; + env->regs[11] =3D regs->r11; + env->regs[12] =3D regs->r12; + env->regs[13] =3D regs->r13; + env->regs[14] =3D info->start_stack; + env->regs[15] =3D regs->acr; + env->pc =3D regs->erp; } diff --git a/linux-user/main.c b/linux-user/main.c index 211148858e..560e4a5b6a 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -149,76 +149,6 @@ void fork_end(int child) } } =20 -#ifdef TARGET_CRIS -void cpu_loop(CPUCRISState *env) -{ - CPUState *cs =3D CPU(cris_env_get_cpu(env)); - int trapnr, ret; - target_siginfo_t info; - =20 - while (1) { - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - switch (trapnr) { - case 0xaa: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->pregs[PR_EDA]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; - case EXCP_INTERRUPT: - /* just indicate that signals should be handled asap */ - break; - case EXCP_BREAK: - ret =3D do_syscall(env,=20 - env->regs[9],=20 - env->regs[10],=20 - env->regs[11],=20 - env->regs[12],=20 - env->regs[13],=20 - env->pregs[7],=20 - env->pregs[11], - 0, 0); - if (ret =3D=3D -TARGET_ERESTARTSYS) { - env->pc -=3D 2; - } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { - env->regs[10] =3D ret; - } - break; - case EXCP_DEBUG: - { - int sig; - - sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (sig) - { - info.si_signo =3D sig; - info.si_errno =3D 0; - info.si_code =3D TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - } - break; - case EXCP_ATOMIC: - cpu_exec_step_atomic(cs); - break; - default: - printf ("Unhandled trap: 0x%x\n", trapnr); - cpu_dump_state(cs, stderr, fprintf, 0); - exit(EXIT_FAILURE); - } - process_pending_signals (env); - } -} -#endif - #ifdef TARGET_MICROBLAZE void cpu_loop(CPUMBState *env) { @@ -2287,26 +2217,6 @@ int main(int argc, char **argv, char **envp) env->ir[IR_SP] =3D regs->usp; env->pc =3D regs->pc; } -#elif defined(TARGET_CRIS) - { - env->regs[0] =3D regs->r0; - env->regs[1] =3D regs->r1; - env->regs[2] =3D regs->r2; - env->regs[3] =3D regs->r3; - env->regs[4] =3D regs->r4; - env->regs[5] =3D regs->r5; - env->regs[6] =3D regs->r6; - env->regs[7] =3D regs->r7; - env->regs[8] =3D regs->r8; - env->regs[9] =3D regs->r9; - env->regs[10] =3D regs->r10; - env->regs[11] =3D regs->r11; - env->regs[12] =3D regs->r12; - env->regs[13] =3D regs->r13; - env->regs[14] =3D info->start_stack; - env->regs[15] =3D regs->acr; =20 - env->pc =3D regs->erp; - } #elif defined(TARGET_S390X) { int i; --=20 2.14.3 From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522092622162354.41882507778587; Mon, 26 Mar 2018 12:30:22 -0700 (PDT) Received: from localhost ([::1]:58734 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xoz-0007LH-9h for importer@patchew.org; Mon, 26 Mar 2018 15:30:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58717) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xc0-0003W3-TA for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0Xby-0001hu-Lr for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:56 -0400 Received: from mout.kundenserver.de ([212.227.126.131]:50363) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0Xbr-0001e7-NR; Mon, 26 Mar 2018 15:16:48 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MgDvl-1fEVaJ3T89-00NSsu; Mon, 26 Mar 2018 21:16:35 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:15:56 +0200 Message-Id: <20180326191603.10217-13-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:WR7Y8Kbm+bqvi8rt4sIKUmRGkXv15EBsEYst0dvYOz7FHANKrSv O0poNlAz1UpkmVTIV7aLUXuipzYTV5P8DHOZGdY80e23WEiV9y4rZAVIZ7FiNi8pekRm9sY Di+6qSu84s2Qf7eEqkA9N/0T/AhO26FcTjteVcVkmxk94ifffl2c1A23HMSrLnQ/fKiGBX1 tT5BPVa3JVJj1h5DHpAiw== X-UI-Out-Filterresults: notjunk:1;V01:K0:tw9SYfL3lrY=:B3bJHUon2W3SQFeLUHWuAs ESR9/W06rUl8+Ra9DzMEuCk1lGCGx1vaOFnQViavLOFp/9mnqRbzuQkKbvEfHqKC/pPaSQ53H AIrFx/BghxqN/V5q6Ez0F2gNkKhVY2AFdx5ITr7ATs7olJY9ybvba4cfK+w1Piygg8n0MjLMX 7iKGtU9fkF7S/x7AUdTdHOvYdaU3rzNfKcO4JF0fAJY3gmdL7GD6SCAblffXa83HZ6YHnOl3E 8mMtWdpE8fpzZbtAgqcQbeilk5WSUTr+R5cb2uHvysxbIezaCBlliMTIpUT56xk+aQJgJc14p nIrx2dqCYYKX1CO62UNEIe04MJxbh2BdJAwMPTYBtHxNDGqymqGdau+nolIRASPJa2k9zc1uq f/sS+xT1FF0Yz0oVqsiPzmLDQ+Pd57s9+0Wl9GSedCuT9Sb9qefFl5kziSZ1jSgkKJcTEBFPm fMgGrl4ajPDfRieQP+Dd5D0Rp3+gz51RwnILqzHfXaKWWdd5ab5xsDlGS7VOEoTwsasfZCWch GLJlVSTuPArIC2+SiZGlxMCZlOXXgNBYS8qo1/bAbaPd84eOQaT5MCv71osEEywIJKa2DeT45 qjD+JNljtvYzqqUXFJquNNNygx2FQJyXwkYZBpigxgK5cvXNt/yXM4jzy70Ii2V/lDqh4mCSS nElA2LDssa/F9bqTudS6WZb3VL8f/lIEOdU8G/rmmNexaHn30QSmxMSRXkEx5SM2UZtvmmcrn VwjQmpk1dRcgIGnmPWQu7u+f1Q3xEkPErZctKQ== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.131 Subject: [Qemu-devel] [PATCH for 2.13 12/19] linux-user: move microblaze cpu loop to microblaze directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to microblaze/cpu_loop.c. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- linux-user/main.c | 155 -----------------------------------= ---- linux-user/microblaze/cpu_loop.c | 150 +++++++++++++++++++++++++++++++++++= ++ 2 files changed, 150 insertions(+), 155 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 560e4a5b6a..f8c35e7369 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -149,125 +149,6 @@ void fork_end(int child) } } =20 -#ifdef TARGET_MICROBLAZE -void cpu_loop(CPUMBState *env) -{ - CPUState *cs =3D CPU(mb_env_get_cpu(env)); - int trapnr, ret; - target_siginfo_t info; - =20 - while (1) { - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - switch (trapnr) { - case 0xaa: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D 0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; - case EXCP_INTERRUPT: - /* just indicate that signals should be handled asap */ - break; - case EXCP_BREAK: - /* Return address is 4 bytes after the call. */ - env->regs[14] +=3D 4; - env->sregs[SR_PC] =3D env->regs[14]; - ret =3D do_syscall(env,=20 - env->regs[12],=20 - env->regs[5],=20 - env->regs[6],=20 - env->regs[7],=20 - env->regs[8],=20 - env->regs[9],=20 - env->regs[10], - 0, 0); - if (ret =3D=3D -TARGET_ERESTARTSYS) { - /* Wind back to before the syscall. */ - env->sregs[SR_PC] -=3D 4; - } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { - env->regs[3] =3D ret; - } - /* All syscall exits result in guest r14 being equal to the - * PC we return to, because the kernel syscall exit "rtbd" does - * this. (This is true even for sigreturn(); note that r14 is - * not a userspace-usable register, as the kernel may clobber = it - * at any point.) - */ - env->regs[14] =3D env->sregs[SR_PC]; - break; - case EXCP_HW_EXCP: - env->regs[17] =3D env->sregs[SR_PC] + 4; - if (env->iflags & D_FLAG) { - env->sregs[SR_ESR] |=3D 1 << 12; - env->sregs[SR_PC] -=3D 4; - /* FIXME: if branch was immed, replay the imm as well. */ - } - - env->iflags &=3D ~(IMM_FLAG | D_FLAG); - - switch (env->sregs[SR_ESR] & 31) { - case ESR_EC_DIVZERO: - info.si_signo =3D TARGET_SIGFPE; - info.si_errno =3D 0; - info.si_code =3D TARGET_FPE_FLTDIV; - info._sifields._sigfault._addr =3D 0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case ESR_EC_FPU: - info.si_signo =3D TARGET_SIGFPE; - info.si_errno =3D 0; - if (env->sregs[SR_FSR] & FSR_IO) { - info.si_code =3D TARGET_FPE_FLTINV; - } - if (env->sregs[SR_FSR] & FSR_DZ) { - info.si_code =3D TARGET_FPE_FLTDIV; - } - info._sifields._sigfault._addr =3D 0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - default: - printf ("Unhandled hw-exception: 0x%x\n", - env->sregs[SR_ESR] & ESR_EC_MASK); - cpu_dump_state(cs, stderr, fprintf, 0); - exit(EXIT_FAILURE); - break; - } - break; - case EXCP_DEBUG: - { - int sig; - - sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (sig) - { - info.si_signo =3D sig; - info.si_errno =3D 0; - info.si_code =3D TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - } - break; - case EXCP_ATOMIC: - cpu_exec_step_atomic(cs); - break; - default: - printf ("Unhandled trap: 0x%x\n", trapnr); - cpu_dump_state(cs, stderr, fprintf, 0); - exit(EXIT_FAILURE); - } - process_pending_signals (env); - } -} -#endif - #ifdef TARGET_M68K =20 void cpu_loop(CPUM68KState *env) @@ -2166,42 +2047,6 @@ int main(int argc, char **argv, char **envp) env->sr =3D regs->sr; ts->sim_syscalls =3D 1; } -#elif defined(TARGET_MICROBLAZE) - { - env->regs[0] =3D regs->r0; - env->regs[1] =3D regs->r1; - env->regs[2] =3D regs->r2; - env->regs[3] =3D regs->r3; - env->regs[4] =3D regs->r4; - env->regs[5] =3D regs->r5; - env->regs[6] =3D regs->r6; - env->regs[7] =3D regs->r7; - env->regs[8] =3D regs->r8; - env->regs[9] =3D regs->r9; - env->regs[10] =3D regs->r10; - env->regs[11] =3D regs->r11; - env->regs[12] =3D regs->r12; - env->regs[13] =3D regs->r13; - env->regs[14] =3D regs->r14; - env->regs[15] =3D regs->r15; =20 - env->regs[16] =3D regs->r16; =20 - env->regs[17] =3D regs->r17; =20 - env->regs[18] =3D regs->r18; =20 - env->regs[19] =3D regs->r19; =20 - env->regs[20] =3D regs->r20; =20 - env->regs[21] =3D regs->r21; =20 - env->regs[22] =3D regs->r22; =20 - env->regs[23] =3D regs->r23; =20 - env->regs[24] =3D regs->r24; =20 - env->regs[25] =3D regs->r25; =20 - env->regs[26] =3D regs->r26; =20 - env->regs[27] =3D regs->r27; =20 - env->regs[28] =3D regs->r28; =20 - env->regs[29] =3D regs->r29; =20 - env->regs[30] =3D regs->r30; =20 - env->regs[31] =3D regs->r31; =20 - env->sregs[SR_PC] =3D regs->pc; - } #elif defined(TARGET_RISCV) { env->pc =3D regs->sepc; diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_l= oop.c index b7700a5561..650f82b066 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -21,6 +21,156 @@ #include "qemu.h" #include "cpu_loop-common.h" =20 +void cpu_loop(CPUMBState *env) +{ + CPUState *cs =3D CPU(mb_env_get_cpu(env)); + int trapnr, ret; + target_siginfo_t info; + =20 + while (1) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch (trapnr) { + case 0xaa: + { + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + /* XXX: check env->error_code */ + info.si_code =3D TARGET_SEGV_MAPERR; + info._sifields._sigfault._addr =3D 0; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + break; + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case EXCP_BREAK: + /* Return address is 4 bytes after the call. */ + env->regs[14] +=3D 4; + env->sregs[SR_PC] =3D env->regs[14]; + ret =3D do_syscall(env,=20 + env->regs[12],=20 + env->regs[5],=20 + env->regs[6],=20 + env->regs[7],=20 + env->regs[8],=20 + env->regs[9],=20 + env->regs[10], + 0, 0); + if (ret =3D=3D -TARGET_ERESTARTSYS) { + /* Wind back to before the syscall. */ + env->sregs[SR_PC] -=3D 4; + } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { + env->regs[3] =3D ret; + } + /* All syscall exits result in guest r14 being equal to the + * PC we return to, because the kernel syscall exit "rtbd" does + * this. (This is true even for sigreturn(); note that r14 is + * not a userspace-usable register, as the kernel may clobber = it + * at any point.) + */ + env->regs[14] =3D env->sregs[SR_PC]; + break; + case EXCP_HW_EXCP: + env->regs[17] =3D env->sregs[SR_PC] + 4; + if (env->iflags & D_FLAG) { + env->sregs[SR_ESR] |=3D 1 << 12; + env->sregs[SR_PC] -=3D 4; + /* FIXME: if branch was immed, replay the imm as well. */ + } + + env->iflags &=3D ~(IMM_FLAG | D_FLAG); + + switch (env->sregs[SR_ESR] & 31) { + case ESR_EC_DIVZERO: + info.si_signo =3D TARGET_SIGFPE; + info.si_errno =3D 0; + info.si_code =3D TARGET_FPE_FLTDIV; + info._sifields._sigfault._addr =3D 0; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case ESR_EC_FPU: + info.si_signo =3D TARGET_SIGFPE; + info.si_errno =3D 0; + if (env->sregs[SR_FSR] & FSR_IO) { + info.si_code =3D TARGET_FPE_FLTINV; + } + if (env->sregs[SR_FSR] & FSR_DZ) { + info.si_code =3D TARGET_FPE_FLTDIV; + } + info._sifields._sigfault._addr =3D 0; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + default: + printf ("Unhandled hw-exception: 0x%x\n", + env->sregs[SR_ESR] & ESR_EC_MASK); + cpu_dump_state(cs, stderr, fprintf, 0); + exit(EXIT_FAILURE); + break; + } + break; + case EXCP_DEBUG: + { + int sig; + + sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); + if (sig) + { + info.si_signo =3D sig; + info.si_errno =3D 0; + info.si_code =3D TARGET_TRAP_BRKPT; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + } + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + default: + printf ("Unhandled trap: 0x%x\n", trapnr); + cpu_dump_state(cs, stderr, fprintf, 0); + exit(EXIT_FAILURE); + } + process_pending_signals (env); + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + env->regs[0] =3D regs->r0; + env->regs[1] =3D regs->r1; + env->regs[2] =3D regs->r2; + env->regs[3] =3D regs->r3; + env->regs[4] =3D regs->r4; + env->regs[5] =3D regs->r5; + env->regs[6] =3D regs->r6; + env->regs[7] =3D regs->r7; + env->regs[8] =3D regs->r8; + env->regs[9] =3D regs->r9; + env->regs[10] =3D regs->r10; + env->regs[11] =3D regs->r11; + env->regs[12] =3D regs->r12; + env->regs[13] =3D regs->r13; + env->regs[14] =3D regs->r14; + env->regs[15] =3D regs->r15; + env->regs[16] =3D regs->r16; + env->regs[17] =3D regs->r17; + env->regs[18] =3D regs->r18; + env->regs[19] =3D regs->r19; + env->regs[20] =3D regs->r20; + env->regs[21] =3D regs->r21; + env->regs[22] =3D regs->r22; + env->regs[23] =3D regs->r23; + env->regs[24] =3D regs->r24; + env->regs[25] =3D regs->r25; + env->regs[26] =3D regs->r26; + env->regs[27] =3D regs->r27; + env->regs[28] =3D regs->r28; + env->regs[29] =3D regs->r29; + env->regs[30] =3D regs->r30; + env->regs[31] =3D regs->r31; + env->sregs[SR_PC] =3D regs->pc; } --=20 2.14.3 From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 26 Mar 2018 15:16:51 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MYpHi-1f5TJG1ETy-00VT6p; Mon, 26 Mar 2018 21:16:36 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:15:57 +0200 Message-Id: <20180326191603.10217-14-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:SwIQXW6KgTBGhTjemb3HGqKYoKD4xaSmLXFKsry9UnDeNnuegOv akUbPoaxWT0S+N0Nt6yyrvuZEdu/kT3LTXABLSQYfbPK77Q34DmBkhNZGhdYi1Xowskp428 d/Se5uxd4fu6RbkGJezfsAKipe+E11u2c5juMl6f+3azD8AhPoEB7/B+FV91kUpbnY33C3z bTxCIoyrPrFnDdInqh2xg== X-UI-Out-Filterresults: notjunk:1;V01:K0:H+eM0aELTdE=:NIBCnYWW0yOy/2Ppm08ski sCfiQXCPBTiURtcwppS2LpBNMk71vSr2SO+RJAc7KgRpW9T+VocxQBZA8JpQzfAWrIlvzuPoh I+0+jzDLtMTYDUI32FDv9f+dwLNKH8SXe/4aDqdo33HQDtUrUeNACdJr0hrdgPB6JIvhYtrt4 leTCmJ9i7r4sHaz0/7jSV0bWIYLhgVwHbf17Y2qJ6JtDv/vg7f5lD8CXT3EVY7XlTkgFggkCO nid6TTnQUb56vXuUq5pJ2v+wGFSrNUu0NWDmOiolHD9XuhkMHEmOBXAmvDxEv2kYPP/0wPSFK +28x9tdvkM/qcuXvlGLM8lAqqQw1sCJQkANA8s9mVKdaU1OX9bJCoybVy7Glk+jcc198ATPIO Fi9DEZ8MJm4q1+9PwiEmYYAASdWRc9GGPaHtd/KM71AmuXkHk5LOXpnxI/LZ/Sf23whV756hO weVXfqJ9dnw5poxZdT2JVxTN28cCE2XkCd4hdlb2ZnvwsF6DhngR3stKp4Be2+eQ4Ru1cWrEN NlISlUTFjdoBOwoq4mhJekZXKZ3N8fZ88JE7OLGzAR8D/yZy3Kus4uRz9uWTjhL6sloGboVn9 4ZQjPdlCeuoL4J91KIDCMvwv5INbmkwai9KTkDQAhyM+j9CteE1PIsXaXlylrU+rbLQiL/Zw1 jLTioI1sUAz5C1hmb8tCsPYmmRKgONYNGTBY6LEGOXoY8rxmCptpXM7ltTBDv3DYB+AEqLPjV DpGNvQGYCZamjgM/vjdZXPtpUkPfgg5VoejJPg== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PATCH for 2.13 13/19] linux-user: move m68k cpu loop to m68k directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to m68k/cpu_loop.c. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 144 +++++++++++++++++++++++++++++++++++++++++= ++ linux-user/main.c | 150 +----------------------------------------= ---- 2 files changed, 145 insertions(+), 149 deletions(-) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index b7700a5561..b4d3d8af3d 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -21,6 +21,150 @@ #include "qemu.h" #include "cpu_loop-common.h" =20 +void cpu_loop(CPUM68KState *env) +{ + CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + int trapnr; + unsigned int n; + target_siginfo_t info; + TaskState *ts =3D cs->opaque; + + for(;;) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch(trapnr) { + case EXCP_ILLEGAL: + { + if (ts->sim_syscalls) { + uint16_t nr; + get_user_u16(nr, env->pc + 2); + env->pc +=3D 4; + do_m68k_simcall(env, nr); + } else { + goto do_sigill; + } + } + break; + case EXCP_HALT_INSN: + /* Semihosing syscall. */ + env->pc +=3D 4; + do_m68k_semihosting(env, env->dregs[0]); + break; + case EXCP_LINEA: + case EXCP_LINEF: + case EXCP_UNSUPPORTED: + do_sigill: + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D TARGET_ILL_ILLOPN; + info._sifields._sigfault._addr =3D env->pc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_CHK: + info.si_signo =3D TARGET_SIGFPE; + info.si_errno =3D 0; + info.si_code =3D TARGET_FPE_INTOVF; + info._sifields._sigfault._addr =3D env->pc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_DIV0: + info.si_signo =3D TARGET_SIGFPE; + info.si_errno =3D 0; + info.si_code =3D TARGET_FPE_INTDIV; + info._sifields._sigfault._addr =3D env->pc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_TRAP0: + { + abi_long ret; + ts->sim_syscalls =3D 0; + n =3D env->dregs[0]; + env->pc +=3D 2; + ret =3D do_syscall(env, + n, + env->dregs[1], + env->dregs[2], + env->dregs[3], + env->dregs[4], + env->dregs[5], + env->aregs[0], + 0, 0); + if (ret =3D=3D -TARGET_ERESTARTSYS) { + env->pc -=3D 2; + } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { + env->dregs[0] =3D ret; + } + } + break; + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case EXCP_ACCESS: + { + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + /* XXX: check env->error_code */ + info.si_code =3D TARGET_SEGV_MAPERR; + info._sifields._sigfault._addr =3D env->mmu.ar; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + break; + case EXCP_DEBUG: + { + int sig; + + sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); + if (sig) + { + info.si_signo =3D sig; + info.si_errno =3D 0; + info.si_code =3D TARGET_TRAP_BRKPT; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + } + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + default: + EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\= n", trapnr); + abort(); + } + process_pending_signals(env); + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + CPUState *cpu =3D ENV_GET_CPU(env); + TaskState *ts =3D cpu->opaque; + struct image_info *info =3D ts->info; + + env->pc =3D regs->pc; + env->dregs[0] =3D regs->d0; + env->dregs[1] =3D regs->d1; + env->dregs[2] =3D regs->d2; + env->dregs[3] =3D regs->d3; + env->dregs[4] =3D regs->d4; + env->dregs[5] =3D regs->d5; + env->dregs[6] =3D regs->d6; + env->dregs[7] =3D regs->d7; + env->aregs[0] =3D regs->a0; + env->aregs[1] =3D regs->a1; + env->aregs[2] =3D regs->a2; + env->aregs[3] =3D regs->a3; + env->aregs[4] =3D regs->a4; + env->aregs[5] =3D regs->a5; + env->aregs[6] =3D regs->a6; + env->aregs[7] =3D regs->usp; + env->sr =3D regs->sr; + + ts->sim_syscalls =3D 1; + ts->stack_base =3D info->start_stack; + ts->heap_base =3D info->brk; + /* This will be filled in on the first SYS_HEAPINFO call. */ + ts->heap_limit =3D 0; } diff --git a/linux-user/main.c b/linux-user/main.c index f8c35e7369..2a9afb6659 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -149,125 +149,6 @@ void fork_end(int child) } } =20 -#ifdef TARGET_M68K - -void cpu_loop(CPUM68KState *env) -{ - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); - int trapnr; - unsigned int n; - target_siginfo_t info; - TaskState *ts =3D cs->opaque; - - for(;;) { - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - switch(trapnr) { - case EXCP_ILLEGAL: - { - if (ts->sim_syscalls) { - uint16_t nr; - get_user_u16(nr, env->pc + 2); - env->pc +=3D 4; - do_m68k_simcall(env, nr); - } else { - goto do_sigill; - } - } - break; - case EXCP_HALT_INSN: - /* Semihosing syscall. */ - env->pc +=3D 4; - do_m68k_semihosting(env, env->dregs[0]); - break; - case EXCP_LINEA: - case EXCP_LINEF: - case EXCP_UNSUPPORTED: - do_sigill: - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D TARGET_ILL_ILLOPN; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_CHK: - info.si_signo =3D TARGET_SIGFPE; - info.si_errno =3D 0; - info.si_code =3D TARGET_FPE_INTOVF; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_DIV0: - info.si_signo =3D TARGET_SIGFPE; - info.si_errno =3D 0; - info.si_code =3D TARGET_FPE_INTDIV; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_TRAP0: - { - abi_long ret; - ts->sim_syscalls =3D 0; - n =3D env->dregs[0]; - env->pc +=3D 2; - ret =3D do_syscall(env, - n, - env->dregs[1], - env->dregs[2], - env->dregs[3], - env->dregs[4], - env->dregs[5], - env->aregs[0], - 0, 0); - if (ret =3D=3D -TARGET_ERESTARTSYS) { - env->pc -=3D 2; - } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { - env->dregs[0] =3D ret; - } - } - break; - case EXCP_INTERRUPT: - /* just indicate that signals should be handled asap */ - break; - case EXCP_ACCESS: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->mmu.ar; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; - case EXCP_DEBUG: - { - int sig; - - sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (sig) - { - info.si_signo =3D sig; - info.si_errno =3D 0; - info.si_code =3D TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - } - break; - case EXCP_ATOMIC: - cpu_exec_step_atomic(cs); - break; - default: - EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\= n", trapnr); - abort(); - } - process_pending_signals(env); - } -} -#endif /* TARGET_M68K */ - #ifdef TARGET_ALPHA void cpu_loop(CPUAlphaState *env) { @@ -2025,29 +1906,7 @@ int main(int argc, char **argv, char **envp) =20 target_cpu_copy_regs(env, regs); =20 -#if defined(TARGET_M68K) - { - env->pc =3D regs->pc; - env->dregs[0] =3D regs->d0; - env->dregs[1] =3D regs->d1; - env->dregs[2] =3D regs->d2; - env->dregs[3] =3D regs->d3; - env->dregs[4] =3D regs->d4; - env->dregs[5] =3D regs->d5; - env->dregs[6] =3D regs->d6; - env->dregs[7] =3D regs->d7; - env->aregs[0] =3D regs->a0; - env->aregs[1] =3D regs->a1; - env->aregs[2] =3D regs->a2; - env->aregs[3] =3D regs->a3; - env->aregs[4] =3D regs->a4; - env->aregs[5] =3D regs->a5; - env->aregs[6] =3D regs->a6; - env->aregs[7] =3D regs->usp; - env->sr =3D regs->sr; - ts->sim_syscalls =3D 1; - } -#elif defined(TARGET_RISCV) +#if defined(TARGET_RISCV) { env->pc =3D regs->sepc; env->gpr[xSP] =3D regs->sp; @@ -2102,13 +1961,6 @@ int main(int argc, char **argv, char **envp) } #endif =20 -#if defined(TARGET_M68K) - ts->stack_base =3D info->start_stack; - ts->heap_base =3D info->brk; - /* This will be filled in on the first SYS_HEAPINFO call. */ - ts->heap_limit =3D 0; -#endif - if (gdbstub_port) { if (gdbserver_start(gdbstub_port) < 0) { fprintf(stderr, "qemu: could not open gdbserver on port %d\n", --=20 2.14.3 From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522092442490717.8538947382701; Mon, 26 Mar 2018 12:27:22 -0700 (PDT) Received: from localhost ([::1]:58709 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xm5-0004QI-Ez for importer@patchew.org; Mon, 26 Mar 2018 15:27:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58860) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xc8-0003fu-E5 for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:17:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0Xc4-0001lF-9g for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:17:04 -0400 Received: from mout.kundenserver.de ([212.227.126.130]:42969) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0Xbx-0001gv-Ea; Mon, 26 Mar 2018 15:16:53 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MJ1gb-1ey4dQ2Der-002U80; Mon, 26 Mar 2018 21:16:38 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:15:58 +0200 Message-Id: <20180326191603.10217-15-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:e9C003nSq8uZegxDFXdibujquQ8DO1kqJpJtLqXpWURY35nFNp3 Mo+dsO1Xj0PhT8908rVnhgZRVYtW2KeyQxkEfpfUKUM7GdxJ1tDPSu/bJUTOuQxWvWvA226 sde4k66frgHSdchIuqyThZFF2w0Kwmv0MTYe6GbsH1o4AoMeJpCD2UTHsKR0Ri3q6dSaR5T WIIhEO1WGDQHB75NUSlVw== X-UI-Out-Filterresults: notjunk:1;V01:K0:7PnOINglPO4=:SfrgnL3HoFavZRxj2j7Y3w e8oi8DWIwrBWq9SqRypCYZ53RiPLtdFMUgMNIWVxfdbOi2mx4BXrl9lCmX6m/PUefVS/GpEX2 X7Livtqfl6lcDZmnrSJ9Ct7WuYVkGNtoU8XvajqMLXun35IJBiv5Jt+hXetoFz0O/KeBcN4qh bSPwubBcOJF8Fw6uXdfWckei2DyC9yobV1SEC3sNS6um3KkL9S0mSvhBflLpcQUXqXScHuIdI a6gtVcUxeyuHkjwqu/Ygti0u2DYdURZvaTEkeqS0CB/ZWwlVPrmXGlQvUR58O5TcjjdT4vnXB bYioRtumLXDtI64mDCIRulQsSJI2jXhvLYsfawb4Pj2Z0zyB2Jq1K7UiBL0qdsQeL6WUGnOWQ grmxLQoiT7PGAqsDxj4FH68IniLx+ufZtv3ZXiOY2y7jL4PuIUSecj4RYRi8autp7pWb7slLy P6nDHp7mfgqvsv4LyuhNq8HRzpOHUTbnWX6pwS+8rQ2sFJ0bKmboh6Nr7GQu80fElQExj/QYi XxOyvHTeiTtnhxx+VeYVc6HZqnoiJPPC7C48Xzi72w3kJ4mlsLFdlqH2Cl20dw7h9zQGxR/58 xQhasyl1xYaTw8yKqGwyR58YnwrLhg7KEr3Lb3y3X5TGi73IQ2lDN6lrBrxAq4A1U+sO84p0C s/zjbnM+ga8W8IphxsUdpkkCJz1aRn3mV/6c1rL2RrD26MZMJ6dw83Ql79KAiCqc6VRP0HJWE lVlKlLJ61jdm+PLmGgX0OJD1g8Cc8+9/rjfVfg== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.130 Subject: [Qemu-devel] [PATCH for 2.13 14/19] linux-user: move alpha cpu loop to alpha directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to alpha/cpu_loop.c. Signed-off-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- linux-user/alpha/cpu_loop.c | 199 ++++++++++++++++++++++++++++++++++++++++= ++ linux-user/main.c | 204 ----------------------------------------= ---- 2 files changed, 199 insertions(+), 204 deletions(-) diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index b7700a5561..b87fcaea87 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -21,6 +21,205 @@ #include "qemu.h" #include "cpu_loop-common.h" =20 +void cpu_loop(CPUAlphaState *env) +{ + CPUState *cs =3D CPU(alpha_env_get_cpu(env)); + int trapnr; + target_siginfo_t info; + abi_long sysret; + + while (1) { + bool arch_interrupt =3D true; + + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch (trapnr) { + case EXCP_RESET: + fprintf(stderr, "Reset requested. Exit\n"); + exit(EXIT_FAILURE); + break; + case EXCP_MCHK: + fprintf(stderr, "Machine check exception. Exit\n"); + exit(EXIT_FAILURE); + break; + case EXCP_SMP_INTERRUPT: + case EXCP_CLK_INTERRUPT: + case EXCP_DEV_INTERRUPT: + fprintf(stderr, "External interrupt. Exit\n"); + exit(EXIT_FAILURE); + break; + case EXCP_MMFAULT: + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info.si_code =3D (page_get_flags(env->trap_arg0) & PAGE_VALID + ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); + info._sifields._sigfault._addr =3D env->trap_arg0; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_UNALIGN: + info.si_signo =3D TARGET_SIGBUS; + info.si_errno =3D 0; + info.si_code =3D TARGET_BUS_ADRALN; + info._sifields._sigfault._addr =3D env->trap_arg0; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_OPCDEC: + do_sigill: + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D TARGET_ILL_ILLOPC; + info._sifields._sigfault._addr =3D env->pc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_ARITH: + info.si_signo =3D TARGET_SIGFPE; + info.si_errno =3D 0; + info.si_code =3D TARGET_FPE_FLTINV; + info._sifields._sigfault._addr =3D env->pc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_FEN: + /* No-op. Linux simply re-enables the FPU. */ + break; + case EXCP_CALL_PAL: + switch (env->error_code) { + case 0x80: + /* BPT */ + info.si_signo =3D TARGET_SIGTRAP; + info.si_errno =3D 0; + info.si_code =3D TARGET_TRAP_BRKPT; + info._sifields._sigfault._addr =3D env->pc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case 0x81: + /* BUGCHK */ + info.si_signo =3D TARGET_SIGTRAP; + info.si_errno =3D 0; + info.si_code =3D 0; + info._sifields._sigfault._addr =3D env->pc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case 0x83: + /* CALLSYS */ + trapnr =3D env->ir[IR_V0]; + sysret =3D do_syscall(env, trapnr, + env->ir[IR_A0], env->ir[IR_A1], + env->ir[IR_A2], env->ir[IR_A3], + env->ir[IR_A4], env->ir[IR_A5], + 0, 0); + if (sysret =3D=3D -TARGET_ERESTARTSYS) { + env->pc -=3D 4; + break; + } + if (sysret =3D=3D -TARGET_QEMU_ESIGRETURN) { + break; + } + /* Syscall writes 0 to V0 to bypass error check, similar + to how this is handled internal to Linux kernel. + (Ab)use trapnr temporarily as boolean indicating error.= */ + trapnr =3D (env->ir[IR_V0] !=3D 0 && sysret < 0); + env->ir[IR_V0] =3D (trapnr ? -sysret : sysret); + env->ir[IR_A3] =3D trapnr; + break; + case 0x86: + /* IMB */ + /* ??? We can probably elide the code using page_unprotect + that is checking for self-modifying code. Instead we + could simply call tb_flush here. Until we work out the + changes required to turn off the extra write protection, + this can be a no-op. */ + break; + case 0x9E: + /* RDUNIQUE */ + /* Handled in the translator for usermode. */ + abort(); + case 0x9F: + /* WRUNIQUE */ + /* Handled in the translator for usermode. */ + abort(); + case 0xAA: + /* GENTRAP */ + info.si_signo =3D TARGET_SIGFPE; + switch (env->ir[IR_A0]) { + case TARGET_GEN_INTOVF: + info.si_code =3D TARGET_FPE_INTOVF; + break; + case TARGET_GEN_INTDIV: + info.si_code =3D TARGET_FPE_INTDIV; + break; + case TARGET_GEN_FLTOVF: + info.si_code =3D TARGET_FPE_FLTOVF; + break; + case TARGET_GEN_FLTUND: + info.si_code =3D TARGET_FPE_FLTUND; + break; + case TARGET_GEN_FLTINV: + info.si_code =3D TARGET_FPE_FLTINV; + break; + case TARGET_GEN_FLTINE: + info.si_code =3D TARGET_FPE_FLTRES; + break; + case TARGET_GEN_ROPRAND: + info.si_code =3D 0; + break; + default: + info.si_signo =3D TARGET_SIGTRAP; + info.si_code =3D 0; + break; + } + info.si_errno =3D 0; + info._sifields._sigfault._addr =3D env->pc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + default: + goto do_sigill; + } + break; + case EXCP_DEBUG: + info.si_signo =3D gdb_handlesig(cs, TARGET_SIGTRAP); + if (info.si_signo) { + info.si_errno =3D 0; + info.si_code =3D TARGET_TRAP_BRKPT; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } else { + arch_interrupt =3D false; + } + break; + case EXCP_INTERRUPT: + /* Just indicate that signals should be handled asap. */ + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + arch_interrupt =3D false; + break; + default: + printf ("Unhandled trap: 0x%x\n", trapnr); + cpu_dump_state(cs, stderr, fprintf, 0); + exit(EXIT_FAILURE); + } + process_pending_signals (env); + + /* Most of the traps imply a transition through PALcode, which + implies an REI instruction has been executed. Which means + that RX and LOCK_ADDR should be cleared. But there are a + few exceptions for traps internal to QEMU. */ + if (arch_interrupt) { + env->flags &=3D ~ENV_FLAG_RX_FLAG; + env->lock_addr =3D -1; + } + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + int i; + + for(i =3D 0; i < 28; i++) { + env->ir[i] =3D ((abi_ulong *)regs)[i]; + } + env->ir[IR_SP] =3D regs->usp; + env->pc =3D regs->pc; } diff --git a/linux-user/main.c b/linux-user/main.c index 2a9afb6659..a3c68dad36 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -149,200 +149,6 @@ void fork_end(int child) } } =20 -#ifdef TARGET_ALPHA -void cpu_loop(CPUAlphaState *env) -{ - CPUState *cs =3D CPU(alpha_env_get_cpu(env)); - int trapnr; - target_siginfo_t info; - abi_long sysret; - - while (1) { - bool arch_interrupt =3D true; - - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - switch (trapnr) { - case EXCP_RESET: - fprintf(stderr, "Reset requested. Exit\n"); - exit(EXIT_FAILURE); - break; - case EXCP_MCHK: - fprintf(stderr, "Machine check exception. Exit\n"); - exit(EXIT_FAILURE); - break; - case EXCP_SMP_INTERRUPT: - case EXCP_CLK_INTERRUPT: - case EXCP_DEV_INTERRUPT: - fprintf(stderr, "External interrupt. Exit\n"); - exit(EXIT_FAILURE); - break; - case EXCP_MMFAULT: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D (page_get_flags(env->trap_arg0) & PAGE_VALID - ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); - info._sifields._sigfault._addr =3D env->trap_arg0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_UNALIGN: - info.si_signo =3D TARGET_SIGBUS; - info.si_errno =3D 0; - info.si_code =3D TARGET_BUS_ADRALN; - info._sifields._sigfault._addr =3D env->trap_arg0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_OPCDEC: - do_sigill: - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D TARGET_ILL_ILLOPC; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_ARITH: - info.si_signo =3D TARGET_SIGFPE; - info.si_errno =3D 0; - info.si_code =3D TARGET_FPE_FLTINV; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_FEN: - /* No-op. Linux simply re-enables the FPU. */ - break; - case EXCP_CALL_PAL: - switch (env->error_code) { - case 0x80: - /* BPT */ - info.si_signo =3D TARGET_SIGTRAP; - info.si_errno =3D 0; - info.si_code =3D TARGET_TRAP_BRKPT; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case 0x81: - /* BUGCHK */ - info.si_signo =3D TARGET_SIGTRAP; - info.si_errno =3D 0; - info.si_code =3D 0; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case 0x83: - /* CALLSYS */ - trapnr =3D env->ir[IR_V0]; - sysret =3D do_syscall(env, trapnr, - env->ir[IR_A0], env->ir[IR_A1], - env->ir[IR_A2], env->ir[IR_A3], - env->ir[IR_A4], env->ir[IR_A5], - 0, 0); - if (sysret =3D=3D -TARGET_ERESTARTSYS) { - env->pc -=3D 4; - break; - } - if (sysret =3D=3D -TARGET_QEMU_ESIGRETURN) { - break; - } - /* Syscall writes 0 to V0 to bypass error check, similar - to how this is handled internal to Linux kernel. - (Ab)use trapnr temporarily as boolean indicating error.= */ - trapnr =3D (env->ir[IR_V0] !=3D 0 && sysret < 0); - env->ir[IR_V0] =3D (trapnr ? -sysret : sysret); - env->ir[IR_A3] =3D trapnr; - break; - case 0x86: - /* IMB */ - /* ??? We can probably elide the code using page_unprotect - that is checking for self-modifying code. Instead we - could simply call tb_flush here. Until we work out the - changes required to turn off the extra write protection, - this can be a no-op. */ - break; - case 0x9E: - /* RDUNIQUE */ - /* Handled in the translator for usermode. */ - abort(); - case 0x9F: - /* WRUNIQUE */ - /* Handled in the translator for usermode. */ - abort(); - case 0xAA: - /* GENTRAP */ - info.si_signo =3D TARGET_SIGFPE; - switch (env->ir[IR_A0]) { - case TARGET_GEN_INTOVF: - info.si_code =3D TARGET_FPE_INTOVF; - break; - case TARGET_GEN_INTDIV: - info.si_code =3D TARGET_FPE_INTDIV; - break; - case TARGET_GEN_FLTOVF: - info.si_code =3D TARGET_FPE_FLTOVF; - break; - case TARGET_GEN_FLTUND: - info.si_code =3D TARGET_FPE_FLTUND; - break; - case TARGET_GEN_FLTINV: - info.si_code =3D TARGET_FPE_FLTINV; - break; - case TARGET_GEN_FLTINE: - info.si_code =3D TARGET_FPE_FLTRES; - break; - case TARGET_GEN_ROPRAND: - info.si_code =3D 0; - break; - default: - info.si_signo =3D TARGET_SIGTRAP; - info.si_code =3D 0; - break; - } - info.si_errno =3D 0; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - default: - goto do_sigill; - } - break; - case EXCP_DEBUG: - info.si_signo =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (info.si_signo) { - info.si_errno =3D 0; - info.si_code =3D TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } else { - arch_interrupt =3D false; - } - break; - case EXCP_INTERRUPT: - /* Just indicate that signals should be handled asap. */ - break; - case EXCP_ATOMIC: - cpu_exec_step_atomic(cs); - arch_interrupt =3D false; - break; - default: - printf ("Unhandled trap: 0x%x\n", trapnr); - cpu_dump_state(cs, stderr, fprintf, 0); - exit(EXIT_FAILURE); - } - process_pending_signals (env); - - /* Most of the traps imply a transition through PALcode, which - implies an REI instruction has been executed. Which means - that RX and LOCK_ADDR should be cleared. But there are a - few exceptions for traps internal to QEMU. */ - if (arch_interrupt) { - env->flags &=3D ~ENV_FLAG_RX_FLAG; - env->lock_addr =3D -1; - } - } -} -#endif /* TARGET_ALPHA */ - #ifdef TARGET_S390X =20 /* s390x masks the fault address it reports in si_addr for SIGSEGV and SIG= BUS */ @@ -1911,16 +1717,6 @@ int main(int argc, char **argv, char **envp) env->pc =3D regs->sepc; env->gpr[xSP] =3D regs->sp; } -#elif defined(TARGET_ALPHA) - { - int i; - - for(i =3D 0; i < 28; i++) { - env->ir[i] =3D ((abi_ulong *)regs)[i]; - } - env->ir[IR_SP] =3D regs->usp; - env->pc =3D regs->pc; - } #elif defined(TARGET_S390X) { int i; --=20 2.14.3 From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522092392077837.9556232467625; Mon, 26 Mar 2018 12:26:32 -0700 (PDT) Received: from localhost ([::1]:58707 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0XlH-0003g8-52 for importer@patchew.org; Mon, 26 Mar 2018 15:26:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58683) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xbz-0003Ug-Ru for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0Xbx-0001hL-R1 for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:55 -0400 Received: from mout.kundenserver.de ([212.227.126.131]:50923) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0Xbx-0001h0-Fm; Mon, 26 Mar 2018 15:16:53 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0Mcctw-1fI4UZ0tE0-00Hfaz; Mon, 26 Mar 2018 21:16:39 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:15:59 +0200 Message-Id: <20180326191603.10217-16-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:7JOkf6lUH8ezScNKaR2fVA5L8VLEcQiNPmRcYicFbuhHaDy97Dq vGc43OACXd2QdK6ruN4gdT95WLoh2/Qe9Ksrh+ht3M1zJPDCrDnLNgSSRwN+B0eLkwxa93/ Poe8GgLi6dcOvI+oBYZOqScgzVhfbpepNbqocxPCtK79jRfdtk5hNNA94Ijt3jZdvayLVVh hLwVmNaJGCsUue4mfCZnA== X-UI-Out-Filterresults: notjunk:1;V01:K0:/xvCL0RcvQo=:o7Dt2h695Ub48CkE+oKVWq TLDZwDZz+OzTmjMaM5mwKU4svLRr4Sddlr9O6Q6hdj3oDZe900THYOndMSvoKM9ySi6O+gqEh Z4bJ9jkjEzPaFbIwDjZaqZbLVYSYXMg0GTyhukFIkZwtvtPYBRiGQbuvKUOsZ72gaCGiYvIeE AmDtaNeuZLj9LmnlmcMANTeYORikd+x+8Be4nrZWMY9tVGLYgUjI0S/1I+Q5ItoLF1kSgckfM jovrQfH/B3GDAYGowOmRwMmmZe+iwLWZeUPru1ormIak7UmtYGq5amv+64dfcoQug+ygPE6j7 xUG5EUAFDNzIycJfDz+oEcKj3FSKLyMV5HpLopFm5LHpVG+tqpA7bdfO4/eVyg4G1DekxSJZx pRWkBwKTyZtbTMVqXnyo9qQ1PHl2g9WoqzPX5vIFzqCUfB/lnPA78a6z3HSFHIP9Z1bZ/a6it EmdytkMNvSikx8aiQ2jo4d7kyyzBvrbAgCkbr6rexumr55w53sVr4h9PqrA/GK/1asyWMIj1n zNLNeI+8QHOypUHGfrseyZ02dnIBrczabI5XpcwjgUEE9OEdlqcWs2BwhgmDJQe6eKTAw3U/m hHYJs3pzKFIoizPIQNaQbERgZ56IyvkW6kT56VUdaS0Crs8sLrPajNYiZKZmdsZfNnogKhFSF /UEmMP7PHRnUBT3k8VykV7mcK+I4fudF4+JyuP6zT9r4vfduKLuriIL4LjHawtbGmJg1TbqVL roYEm5bbsG7l3dn8OlBkYd5KR/OEYzkRUx7Bdg== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.131 Subject: [Qemu-devel] [PATCH for 2.13 15/19] linux-user: move s390x cpu loop to s390x directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to s390x/cpu_loop.c. Signed-off-by: Laurent Vivier Acked-by: Cornelia Huck Reviewed-by: Richard Henderson --- linux-user/main.c | 146 ----------------------------------------= ---- linux-user/s390x/cpu_loop.c | 139 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 139 insertions(+), 146 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index a3c68dad36..9693383009 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -149,143 +149,6 @@ void fork_end(int child) } } =20 -#ifdef TARGET_S390X - -/* s390x masks the fault address it reports in si_addr for SIGSEGV and SIG= BUS */ -#define S390X_FAIL_ADDR_MASK -4096LL - -void cpu_loop(CPUS390XState *env) -{ - CPUState *cs =3D CPU(s390_env_get_cpu(env)); - int trapnr, n, sig; - target_siginfo_t info; - target_ulong addr; - abi_long ret; - - while (1) { - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - switch (trapnr) { - case EXCP_INTERRUPT: - /* Just indicate that signals should be handled asap. */ - break; - - case EXCP_SVC: - n =3D env->int_svc_code; - if (!n) { - /* syscalls > 255 */ - n =3D env->regs[1]; - } - env->psw.addr +=3D env->int_svc_ilen; - ret =3D do_syscall(env, n, env->regs[2], env->regs[3], - env->regs[4], env->regs[5], - env->regs[6], env->regs[7], 0, 0); - if (ret =3D=3D -TARGET_ERESTARTSYS) { - env->psw.addr -=3D env->int_svc_ilen; - } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { - env->regs[2] =3D ret; - } - break; - - case EXCP_DEBUG: - sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (sig) { - n =3D TARGET_TRAP_BRKPT; - goto do_signal_pc; - } - break; - case EXCP_PGM: - n =3D env->int_pgm_code; - switch (n) { - case PGM_OPERATION: - case PGM_PRIVILEGED: - sig =3D TARGET_SIGILL; - n =3D TARGET_ILL_ILLOPC; - goto do_signal_pc; - case PGM_PROTECTION: - case PGM_ADDRESSING: - sig =3D TARGET_SIGSEGV; - /* XXX: check env->error_code */ - n =3D TARGET_SEGV_MAPERR; - addr =3D env->__excp_addr & S390X_FAIL_ADDR_MASK; - goto do_signal; - case PGM_EXECUTE: - case PGM_SPECIFICATION: - case PGM_SPECIAL_OP: - case PGM_OPERAND: - do_sigill_opn: - sig =3D TARGET_SIGILL; - n =3D TARGET_ILL_ILLOPN; - goto do_signal_pc; - - case PGM_FIXPT_OVERFLOW: - sig =3D TARGET_SIGFPE; - n =3D TARGET_FPE_INTOVF; - goto do_signal_pc; - case PGM_FIXPT_DIVIDE: - sig =3D TARGET_SIGFPE; - n =3D TARGET_FPE_INTDIV; - goto do_signal_pc; - - case PGM_DATA: - n =3D (env->fpc >> 8) & 0xff; - if (n =3D=3D 0xff) { - /* compare-and-trap */ - goto do_sigill_opn; - } else { - /* An IEEE exception, simulated or otherwise. */ - if (n & 0x80) { - n =3D TARGET_FPE_FLTINV; - } else if (n & 0x40) { - n =3D TARGET_FPE_FLTDIV; - } else if (n & 0x20) { - n =3D TARGET_FPE_FLTOVF; - } else if (n & 0x10) { - n =3D TARGET_FPE_FLTUND; - } else if (n & 0x08) { - n =3D TARGET_FPE_FLTRES; - } else { - /* ??? Quantum exception; BFP, DFP error. */ - goto do_sigill_opn; - } - sig =3D TARGET_SIGFPE; - goto do_signal_pc; - } - - default: - fprintf(stderr, "Unhandled program exception: %#x\n", n); - cpu_dump_state(cs, stderr, fprintf, 0); - exit(EXIT_FAILURE); - } - break; - - do_signal_pc: - addr =3D env->psw.addr; - do_signal: - info.si_signo =3D sig; - info.si_errno =3D 0; - info.si_code =3D n; - info._sifields._sigfault._addr =3D addr; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - - case EXCP_ATOMIC: - cpu_exec_step_atomic(cs); - break; - default: - fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr); - cpu_dump_state(cs, stderr, fprintf, 0); - exit(EXIT_FAILURE); - } - process_pending_signals (env); - } -} - -#endif /* TARGET_S390X */ - #ifdef TARGET_TILEGX =20 static void gen_sigill_reg(CPUTLGState *env) @@ -1717,15 +1580,6 @@ int main(int argc, char **argv, char **envp) env->pc =3D regs->sepc; env->gpr[xSP] =3D regs->sp; } -#elif defined(TARGET_S390X) - { - int i; - for (i =3D 0; i < 16; i++) { - env->regs[i] =3D regs->gprs[i]; - } - env->psw.mask =3D regs->psw.mask; - env->psw.addr =3D regs->psw.addr; - } #elif defined(TARGET_TILEGX) { int i; diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c index b7700a5561..99f5f1594f 100644 --- a/linux-user/s390x/cpu_loop.c +++ b/linux-user/s390x/cpu_loop.c @@ -21,6 +21,145 @@ #include "qemu.h" #include "cpu_loop-common.h" =20 +/* s390x masks the fault address it reports in si_addr for SIGSEGV and SIG= BUS */ +#define S390X_FAIL_ADDR_MASK -4096LL + +void cpu_loop(CPUS390XState *env) +{ + CPUState *cs =3D CPU(s390_env_get_cpu(env)); + int trapnr, n, sig; + target_siginfo_t info; + target_ulong addr; + abi_long ret; + + while (1) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch (trapnr) { + case EXCP_INTERRUPT: + /* Just indicate that signals should be handled asap. */ + break; + + case EXCP_SVC: + n =3D env->int_svc_code; + if (!n) { + /* syscalls > 255 */ + n =3D env->regs[1]; + } + env->psw.addr +=3D env->int_svc_ilen; + ret =3D do_syscall(env, n, env->regs[2], env->regs[3], + env->regs[4], env->regs[5], + env->regs[6], env->regs[7], 0, 0); + if (ret =3D=3D -TARGET_ERESTARTSYS) { + env->psw.addr -=3D env->int_svc_ilen; + } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { + env->regs[2] =3D ret; + } + break; + + case EXCP_DEBUG: + sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); + if (sig) { + n =3D TARGET_TRAP_BRKPT; + goto do_signal_pc; + } + break; + case EXCP_PGM: + n =3D env->int_pgm_code; + switch (n) { + case PGM_OPERATION: + case PGM_PRIVILEGED: + sig =3D TARGET_SIGILL; + n =3D TARGET_ILL_ILLOPC; + goto do_signal_pc; + case PGM_PROTECTION: + case PGM_ADDRESSING: + sig =3D TARGET_SIGSEGV; + /* XXX: check env->error_code */ + n =3D TARGET_SEGV_MAPERR; + addr =3D env->__excp_addr & S390X_FAIL_ADDR_MASK; + goto do_signal; + case PGM_EXECUTE: + case PGM_SPECIFICATION: + case PGM_SPECIAL_OP: + case PGM_OPERAND: + do_sigill_opn: + sig =3D TARGET_SIGILL; + n =3D TARGET_ILL_ILLOPN; + goto do_signal_pc; + + case PGM_FIXPT_OVERFLOW: + sig =3D TARGET_SIGFPE; + n =3D TARGET_FPE_INTOVF; + goto do_signal_pc; + case PGM_FIXPT_DIVIDE: + sig =3D TARGET_SIGFPE; + n =3D TARGET_FPE_INTDIV; + goto do_signal_pc; + + case PGM_DATA: + n =3D (env->fpc >> 8) & 0xff; + if (n =3D=3D 0xff) { + /* compare-and-trap */ + goto do_sigill_opn; + } else { + /* An IEEE exception, simulated or otherwise. */ + if (n & 0x80) { + n =3D TARGET_FPE_FLTINV; + } else if (n & 0x40) { + n =3D TARGET_FPE_FLTDIV; + } else if (n & 0x20) { + n =3D TARGET_FPE_FLTOVF; + } else if (n & 0x10) { + n =3D TARGET_FPE_FLTUND; + } else if (n & 0x08) { + n =3D TARGET_FPE_FLTRES; + } else { + /* ??? Quantum exception; BFP, DFP error. */ + goto do_sigill_opn; + } + sig =3D TARGET_SIGFPE; + goto do_signal_pc; + } + + default: + fprintf(stderr, "Unhandled program exception: %#x\n", n); + cpu_dump_state(cs, stderr, fprintf, 0); + exit(EXIT_FAILURE); + } + break; + + do_signal_pc: + addr =3D env->psw.addr; + do_signal: + info.si_signo =3D sig; + info.si_errno =3D 0; + info.si_code =3D n; + info._sifields._sigfault._addr =3D addr; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + default: + fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr); + cpu_dump_state(cs, stderr, fprintf, 0); + exit(EXIT_FAILURE); + } + process_pending_signals (env); + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + int i; + for (i =3D 0; i < 16; i++) { + env->regs[i] =3D regs->gprs[i]; + } + env->psw.mask =3D regs->psw.mask; + env->psw.addr =3D regs->psw.addr; } --=20 2.14.3 From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522092604761573.1482026450948; Mon, 26 Mar 2018 12:30:04 -0700 (PDT) Received: from localhost ([::1]:58733 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xoc-00070q-Kj for importer@patchew.org; Mon, 26 Mar 2018 15:29:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58863) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xc8-0003g1-FT for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:17:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0Xc4-0001li-Vg for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:17:04 -0400 Received: from mout.kundenserver.de ([212.227.126.130]:45165) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0Xby-0001hW-RR; Mon, 26 Mar 2018 15:16:55 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MLEbl-1f0GUb1x0T-000HCa; Mon, 26 Mar 2018 21:16:41 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:16:00 +0200 Message-Id: <20180326191603.10217-17-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:fvuMLFNRg15qbEg25cznXr/xDOEYFySkOBGg1fAoBuhbKNTNpsH p8CWIcazV4Tw+8qmGY81oa0+3xklZS06VlyAiWL4nZP/RxyLjnUj7QlmOGRYI3Oqf9uCOJ6 a231G4kYs9buaZv3Ufh/bi5STV0epfuk0odc/hPkU+iLO2OX6SHnEXRUAsPJGj7Vs6X3gS2 cjAEPMfz0O3pmIEvFcY9A== X-UI-Out-Filterresults: notjunk:1;V01:K0:0SA5SWZHOC4=:CA0ilkgyGmcld9TD/pT0rB Y2CRrorqy8RQPFewb4KmymuZsr2IYhyrJxN00H8igjPSSwHAv5LHzZk0jNkSlq1HRgX6WvE6H lefDpAFdBkr2EHllvbiCzSFHm5WcXa/SxVYN7Q2yVf7ZWv0q8S3MtF7G9JVFNWqaRfnilyRcH DQ+SjEZtQ7PfMMBCwLy4kK3bYVVefez/XYj3oKr9t257ff1Qbm7mK+b/L7VTOLPzzwTw9h+c/ 2PaBEirFd98S0A0r1sdxJAKXqAEI5HPuYDO5iKfGozyvtWw/WyooyOaoj2mH5cdE+Qz3hQE+9 k6xE9g02PUwfmU84Y/C/44S2YfUu33q4Nfzz+ildE/xQAkY6e77jBdKRzJWDELTQEbUzKIjp7 IerhXi6M3NqWYfknmwU8RlrHw2brxsFinRHqN9CQisxKpNBWjZwghbytNJrOvxmzAp3PmySNo DIumpccKthdQ7gLTtaDbp6gC1tMPUmxpR0lNvFGLK2GkwM+/sDEy6E1MTzn8ki/IZAYX7a+Q7 6PHzrjS1QzLVzRZ5Q6nOtY5uVYpkof78eJ/JPwiUSDWwvZqbfmzn04B/QZZAaDTzIcRGWAqLR wElVTCZggjh8jCdmvOIXK9VN90W3eY9q5Le0BQcoEfFlmi2qrFxiuPAfTUGcUqCqDGFTi62sE z2HS4rxQm02CYnk6dHVuTT3k5i3Yjhik80b3Jogl38Ldqy83IKjFA1JsAvV1HkrlqADsJtIXp AMg0DInFIcy+8Df+pT7HiuIWvwEyUp5UBeb33w== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.130 Subject: [Qemu-devel] [PATCH for 2.13 16/19] linux-user: move tilegx cpu loop to tilegx directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to tilegx/cpu_loop.c. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- linux-user/main.c | 267 ---------------------------------------= ---- linux-user/tilegx/cpu_loop.c | 260 +++++++++++++++++++++++++++++++++++++++= ++ 2 files changed, 260 insertions(+), 267 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 9693383009..3b3613cb89 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -149,262 +149,6 @@ void fork_end(int child) } } =20 -#ifdef TARGET_TILEGX - -static void gen_sigill_reg(CPUTLGState *env) -{ - target_siginfo_t info; - - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D TARGET_ILL_PRVREG; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); -} - -static void do_signal(CPUTLGState *env, int signo, int sigcode) -{ - target_siginfo_t info; - - info.si_signo =3D signo; - info.si_errno =3D 0; - info._sifields._sigfault._addr =3D env->pc; - - if (signo =3D=3D TARGET_SIGSEGV) { - /* The passed in sigcode is a dummy; check for a page mapping - and pass either MAPERR or ACCERR. */ - target_ulong addr =3D env->excaddr; - info._sifields._sigfault._addr =3D addr; - if (page_check_range(addr, 1, PAGE_VALID) < 0) { - sigcode =3D TARGET_SEGV_MAPERR; - } else { - sigcode =3D TARGET_SEGV_ACCERR; - } - } - info.si_code =3D sigcode; - - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); -} - -static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr) -{ - env->excaddr =3D addr; - do_signal(env, TARGET_SIGSEGV, 0); -} - -static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val) -{ - if (unlikely(reg >=3D TILEGX_R_COUNT)) { - switch (reg) { - case TILEGX_R_SN: - case TILEGX_R_ZERO: - return; - case TILEGX_R_IDN0: - case TILEGX_R_IDN1: - case TILEGX_R_UDN0: - case TILEGX_R_UDN1: - case TILEGX_R_UDN2: - case TILEGX_R_UDN3: - gen_sigill_reg(env); - return; - default: - g_assert_not_reached(); - } - } - env->regs[reg] =3D val; -} - -/* - * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in - * memory at the address held in the first source register. If the values = are - * not equal, then no memory operation is performed. If the values are equ= al, - * the 8-byte quantity from the second source register is written into mem= ory - * at the address held in the first source register. In either case, the r= esult - * of the instruction is the value read from memory. The compare and write= to - * memory are atomic and thus can be used for synchronization purposes. Th= is - * instruction only operates for addresses aligned to a 8-byte boundary. - * Unaligned memory access causes an Unaligned Data Reference interrupt. - * - * Functional Description (64-bit) - * uint64_t memVal =3D memoryReadDoubleWord (rf[SrcA]); - * rf[Dest] =3D memVal; - * if (memVal =3D=3D SPR[CmpValueSPR]) - * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]); - * - * Functional Description (32-bit) - * uint64_t memVal =3D signExtend32 (memoryReadWord (rf[SrcA])); - * rf[Dest] =3D memVal; - * if (memVal =3D=3D signExtend32 (SPR[CmpValueSPR])) - * memoryWriteWord (rf[SrcA], rf[SrcB]); - * - * - * This function also processes exch and exch4 which need not process SPR. - */ -static void do_exch(CPUTLGState *env, bool quad, bool cmp) -{ - target_ulong addr; - target_long val, sprval; - - start_exclusive(); - - addr =3D env->atomic_srca; - if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { - goto sigsegv_maperr; - } - - if (cmp) { - if (quad) { - sprval =3D env->spregs[TILEGX_SPR_CMPEXCH]; - } else { - sprval =3D sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32); - } - } - - if (!cmp || val =3D=3D sprval) { - target_long valb =3D env->atomic_srcb; - if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) { - goto sigsegv_maperr; - } - } - - set_regval(env, env->atomic_dstr, val); - end_exclusive(); - return; - - sigsegv_maperr: - end_exclusive(); - gen_sigsegv_maperr(env, addr); -} - -static void do_fetch(CPUTLGState *env, int trapnr, bool quad) -{ - int8_t write =3D 1; - target_ulong addr; - target_long val, valb; - - start_exclusive(); - - addr =3D env->atomic_srca; - valb =3D env->atomic_srcb; - if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { - goto sigsegv_maperr; - } - - switch (trapnr) { - case TILEGX_EXCP_OPCODE_FETCHADD: - case TILEGX_EXCP_OPCODE_FETCHADD4: - valb +=3D val; - break; - case TILEGX_EXCP_OPCODE_FETCHADDGEZ: - valb +=3D val; - if (valb < 0) { - write =3D 0; - } - break; - case TILEGX_EXCP_OPCODE_FETCHADDGEZ4: - valb +=3D val; - if ((int32_t)valb < 0) { - write =3D 0; - } - break; - case TILEGX_EXCP_OPCODE_FETCHAND: - case TILEGX_EXCP_OPCODE_FETCHAND4: - valb &=3D val; - break; - case TILEGX_EXCP_OPCODE_FETCHOR: - case TILEGX_EXCP_OPCODE_FETCHOR4: - valb |=3D val; - break; - default: - g_assert_not_reached(); - } - - if (write) { - if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) { - goto sigsegv_maperr; - } - } - - set_regval(env, env->atomic_dstr, val); - end_exclusive(); - return; - - sigsegv_maperr: - end_exclusive(); - gen_sigsegv_maperr(env, addr); -} - -void cpu_loop(CPUTLGState *env) -{ - CPUState *cs =3D CPU(tilegx_env_get_cpu(env)); - int trapnr; - - while (1) { - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - switch (trapnr) { - case TILEGX_EXCP_SYSCALL: - { - abi_ulong ret =3D do_syscall(env, env->regs[TILEGX_R_NR], - env->regs[0], env->regs[1], - env->regs[2], env->regs[3], - env->regs[4], env->regs[5], - env->regs[6], env->regs[7]); - if (ret =3D=3D -TARGET_ERESTARTSYS) { - env->pc -=3D 8; - } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { - env->regs[TILEGX_R_RE] =3D ret; - env->regs[TILEGX_R_ERR] =3D TILEGX_IS_ERRNO(ret) ? -ret : = 0; - } - break; - } - case TILEGX_EXCP_OPCODE_EXCH: - do_exch(env, true, false); - break; - case TILEGX_EXCP_OPCODE_EXCH4: - do_exch(env, false, false); - break; - case TILEGX_EXCP_OPCODE_CMPEXCH: - do_exch(env, true, true); - break; - case TILEGX_EXCP_OPCODE_CMPEXCH4: - do_exch(env, false, true); - break; - case TILEGX_EXCP_OPCODE_FETCHADD: - case TILEGX_EXCP_OPCODE_FETCHADDGEZ: - case TILEGX_EXCP_OPCODE_FETCHAND: - case TILEGX_EXCP_OPCODE_FETCHOR: - do_fetch(env, trapnr, true); - break; - case TILEGX_EXCP_OPCODE_FETCHADD4: - case TILEGX_EXCP_OPCODE_FETCHADDGEZ4: - case TILEGX_EXCP_OPCODE_FETCHAND4: - case TILEGX_EXCP_OPCODE_FETCHOR4: - do_fetch(env, trapnr, false); - break; - case TILEGX_EXCP_SIGNAL: - do_signal(env, env->signo, env->sigcode); - break; - case TILEGX_EXCP_REG_IDN_ACCESS: - case TILEGX_EXCP_REG_UDN_ACCESS: - gen_sigill_reg(env); - break; - case EXCP_ATOMIC: - cpu_exec_step_atomic(cs); - break; - default: - fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr); - g_assert_not_reached(); - } - process_pending_signals(env); - } -} - -#endif - #ifdef TARGET_RISCV =20 void cpu_loop(CPURISCVState *env) @@ -1580,17 +1324,6 @@ int main(int argc, char **argv, char **envp) env->pc =3D regs->sepc; env->gpr[xSP] =3D regs->sp; } -#elif defined(TARGET_TILEGX) - { - int i; - for (i =3D 0; i < TILEGX_R_COUNT; i++) { - env->regs[i] =3D regs->regs[i]; - } - for (i =3D 0; i < TILEGX_SPR_COUNT; i++) { - env->spregs[i] =3D 0; - } - env->pc =3D regs->pc; - } #elif defined(TARGET_HPPA) { int i; diff --git a/linux-user/tilegx/cpu_loop.c b/linux-user/tilegx/cpu_loop.c index b7700a5561..4f39eb9ad3 100644 --- a/linux-user/tilegx/cpu_loop.c +++ b/linux-user/tilegx/cpu_loop.c @@ -21,6 +21,266 @@ #include "qemu.h" #include "cpu_loop-common.h" =20 +static void gen_sigill_reg(CPUTLGState *env) +{ + target_siginfo_t info; + + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D TARGET_ILL_PRVREG; + info._sifields._sigfault._addr =3D env->pc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); +} + +static void do_signal(CPUTLGState *env, int signo, int sigcode) +{ + target_siginfo_t info; + + info.si_signo =3D signo; + info.si_errno =3D 0; + info._sifields._sigfault._addr =3D env->pc; + + if (signo =3D=3D TARGET_SIGSEGV) { + /* The passed in sigcode is a dummy; check for a page mapping + and pass either MAPERR or ACCERR. */ + target_ulong addr =3D env->excaddr; + info._sifields._sigfault._addr =3D addr; + if (page_check_range(addr, 1, PAGE_VALID) < 0) { + sigcode =3D TARGET_SEGV_MAPERR; + } else { + sigcode =3D TARGET_SEGV_ACCERR; + } + } + info.si_code =3D sigcode; + + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); +} + +static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr) +{ + env->excaddr =3D addr; + do_signal(env, TARGET_SIGSEGV, 0); +} + +static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val) +{ + if (unlikely(reg >=3D TILEGX_R_COUNT)) { + switch (reg) { + case TILEGX_R_SN: + case TILEGX_R_ZERO: + return; + case TILEGX_R_IDN0: + case TILEGX_R_IDN1: + case TILEGX_R_UDN0: + case TILEGX_R_UDN1: + case TILEGX_R_UDN2: + case TILEGX_R_UDN3: + gen_sigill_reg(env); + return; + default: + g_assert_not_reached(); + } + } + env->regs[reg] =3D val; +} + +/* + * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in + * memory at the address held in the first source register. If the values = are + * not equal, then no memory operation is performed. If the values are equ= al, + * the 8-byte quantity from the second source register is written into mem= ory + * at the address held in the first source register. In either case, the r= esult + * of the instruction is the value read from memory. The compare and write= to + * memory are atomic and thus can be used for synchronization purposes. Th= is + * instruction only operates for addresses aligned to a 8-byte boundary. + * Unaligned memory access causes an Unaligned Data Reference interrupt. + * + * Functional Description (64-bit) + * uint64_t memVal =3D memoryReadDoubleWord (rf[SrcA]); + * rf[Dest] =3D memVal; + * if (memVal =3D=3D SPR[CmpValueSPR]) + * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]); + * + * Functional Description (32-bit) + * uint64_t memVal =3D signExtend32 (memoryReadWord (rf[SrcA])); + * rf[Dest] =3D memVal; + * if (memVal =3D=3D signExtend32 (SPR[CmpValueSPR])) + * memoryWriteWord (rf[SrcA], rf[SrcB]); + * + * + * This function also processes exch and exch4 which need not process SPR. + */ +static void do_exch(CPUTLGState *env, bool quad, bool cmp) +{ + target_ulong addr; + target_long val, sprval; + + start_exclusive(); + + addr =3D env->atomic_srca; + if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { + goto sigsegv_maperr; + } + + if (cmp) { + if (quad) { + sprval =3D env->spregs[TILEGX_SPR_CMPEXCH]; + } else { + sprval =3D sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32); + } + } + + if (!cmp || val =3D=3D sprval) { + target_long valb =3D env->atomic_srcb; + if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) { + goto sigsegv_maperr; + } + } + + set_regval(env, env->atomic_dstr, val); + end_exclusive(); + return; + + sigsegv_maperr: + end_exclusive(); + gen_sigsegv_maperr(env, addr); +} + +static void do_fetch(CPUTLGState *env, int trapnr, bool quad) +{ + int8_t write =3D 1; + target_ulong addr; + target_long val, valb; + + start_exclusive(); + + addr =3D env->atomic_srca; + valb =3D env->atomic_srcb; + if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { + goto sigsegv_maperr; + } + + switch (trapnr) { + case TILEGX_EXCP_OPCODE_FETCHADD: + case TILEGX_EXCP_OPCODE_FETCHADD4: + valb +=3D val; + break; + case TILEGX_EXCP_OPCODE_FETCHADDGEZ: + valb +=3D val; + if (valb < 0) { + write =3D 0; + } + break; + case TILEGX_EXCP_OPCODE_FETCHADDGEZ4: + valb +=3D val; + if ((int32_t)valb < 0) { + write =3D 0; + } + break; + case TILEGX_EXCP_OPCODE_FETCHAND: + case TILEGX_EXCP_OPCODE_FETCHAND4: + valb &=3D val; + break; + case TILEGX_EXCP_OPCODE_FETCHOR: + case TILEGX_EXCP_OPCODE_FETCHOR4: + valb |=3D val; + break; + default: + g_assert_not_reached(); + } + + if (write) { + if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) { + goto sigsegv_maperr; + } + } + + set_regval(env, env->atomic_dstr, val); + end_exclusive(); + return; + + sigsegv_maperr: + end_exclusive(); + gen_sigsegv_maperr(env, addr); +} + +void cpu_loop(CPUTLGState *env) +{ + CPUState *cs =3D CPU(tilegx_env_get_cpu(env)); + int trapnr; + + while (1) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch (trapnr) { + case TILEGX_EXCP_SYSCALL: + { + abi_ulong ret =3D do_syscall(env, env->regs[TILEGX_R_NR], + env->regs[0], env->regs[1], + env->regs[2], env->regs[3], + env->regs[4], env->regs[5], + env->regs[6], env->regs[7]); + if (ret =3D=3D -TARGET_ERESTARTSYS) { + env->pc -=3D 8; + } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { + env->regs[TILEGX_R_RE] =3D ret; + env->regs[TILEGX_R_ERR] =3D TILEGX_IS_ERRNO(ret) ? -ret : = 0; + } + break; + } + case TILEGX_EXCP_OPCODE_EXCH: + do_exch(env, true, false); + break; + case TILEGX_EXCP_OPCODE_EXCH4: + do_exch(env, false, false); + break; + case TILEGX_EXCP_OPCODE_CMPEXCH: + do_exch(env, true, true); + break; + case TILEGX_EXCP_OPCODE_CMPEXCH4: + do_exch(env, false, true); + break; + case TILEGX_EXCP_OPCODE_FETCHADD: + case TILEGX_EXCP_OPCODE_FETCHADDGEZ: + case TILEGX_EXCP_OPCODE_FETCHAND: + case TILEGX_EXCP_OPCODE_FETCHOR: + do_fetch(env, trapnr, true); + break; + case TILEGX_EXCP_OPCODE_FETCHADD4: + case TILEGX_EXCP_OPCODE_FETCHADDGEZ4: + case TILEGX_EXCP_OPCODE_FETCHAND4: + case TILEGX_EXCP_OPCODE_FETCHOR4: + do_fetch(env, trapnr, false); + break; + case TILEGX_EXCP_SIGNAL: + do_signal(env, env->signo, env->sigcode); + break; + case TILEGX_EXCP_REG_IDN_ACCESS: + case TILEGX_EXCP_REG_UDN_ACCESS: + gen_sigill_reg(env); + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + default: + fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr); + g_assert_not_reached(); + } + process_pending_signals(env); + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + int i; + for (i =3D 0; i < TILEGX_R_COUNT; i++) { + env->regs[i] =3D regs->regs[i]; + } + for (i =3D 0; i < TILEGX_SPR_COUNT; i++) { + env->spregs[i] =3D 0; + } + env->pc =3D regs->pc; } --=20 2.14.3 From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522092280608261.7686692146185; Mon, 26 Mar 2018 12:24:40 -0700 (PDT) Received: from localhost ([::1]:58686 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0XjK-0001n7-9g for importer@patchew.org; Mon, 26 Mar 2018 15:24:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58862) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xc8-0003g0-FI for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:17:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0Xc4-0001lX-PM for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:17:04 -0400 Received: from mout.kundenserver.de ([212.227.126.133]:55233) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0Xbz-0001hb-3k; Mon, 26 Mar 2018 15:16:55 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0M4x6g-1ee56V3ft0-00zHbz; Mon, 26 Mar 2018 21:16:42 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:16:01 +0200 Message-Id: <20180326191603.10217-18-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:lqxYf7EwlqOwequahxho5MVKlVuFk6Xx026UDShlMzFFpjnk2da 6i1VIT6asQMBjjx5p+z8IPZNud0dM18H7AaLPiSUUzLsn2oP993vBZz+IKj9bPAbCpLuljp 3MVorMdCK9BdV/M2e1a6xEfiYNNLO5QQcc5BJpo3vYcXwdmEv7Sze0Bx732FZ9IRzdeSyqh uQxiEFMBHTYwIsvxhsk4w== X-UI-Out-Filterresults: notjunk:1;V01:K0:aM/fDeLGSqE=:crDKLZllWgldQmU8LYAdS2 Z4ZOHDDqpKiFMKJ9dt5u2YxdMeHHvspaT0LdeU5tF3nDcrXPABQG9iA6shdLSlPMS1Xt4u7Y/ hOu9vkBmy0rwlAjuIgrUsXw6Pwq2lsTHg7zEDzdsIPiq3jvPv60x2EO2/RBNBLOicIIIo1ccM e29Kei7ygo8V9FRaffBzSqmhUWRg+lfiwA19k0nB0Mv8NF5NI2ndGC7zUbJt6M+MGGOR2fDma NsMIFX1/6bBqEKlC50ZzT3mfondXSuWrbH0+KhFBdo7sC9tqX+Eerl9392ovItOGpQbHnr2i7 ses2Z4hoqjSBTG2azcj+QGzdUrZ4EnKxhakeFGufpQ5xpg2mHDGKz8gokOz7FapYD8f75XGI3 zyEcL0j4hKkBNNoRTE2Ko4LpKm+I+WkAR/AhcVA+4R7esHrBqZfT1GrfCrMQ1sKQ74FVoalas 5YXjRE0S1mpLK7FiVtqefU4RDNkojRbxfdZljA/dlAm+0LiSgNVPjL6e+Sz4uBN6Oey+iQjE/ Zw9HxNgx1Uhg2Ez8lhs9MyEVPl+jhC3NbhPMKCW3WHTm2bgEyKszt2ixN4HCvYdToGail607Z BqleRX9hCbtY1zXiEfwOWuCtiAMqtlth09vn0cucgI7+SlVkfmrsyDSbWtZou+eElws1YOJQv dFQniVCjMJ8p72MkqFlhzlj8J/x8re62TiLISw9QQl0wzIOywv+YV+Brgbc0xsloN0zIXs8tG c+pJaRdQPcPmjxTArw2rluEwD743Cjp4mxUsiw== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.133 Subject: [Qemu-devel] [PATCH for 2.13 17/19] linux-user: move riscv cpu loop to riscv directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to riscv/cpu_loop.c. Signed-off-by: Laurent Vivier Reviewed-by: Michael Clark Reviewed-by: Richard Henderson --- linux-user/main.c | 101 +---------------------------------------= ---- linux-user/riscv/cpu_loop.c | 92 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 93 insertions(+), 100 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 3b3613cb89..78ff99bd00 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -149,100 +149,6 @@ void fork_end(int child) } } =20 -#ifdef TARGET_RISCV - -void cpu_loop(CPURISCVState *env) -{ - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); - int trapnr, signum, sigcode; - target_ulong sigaddr; - target_ulong ret; - - for (;;) { - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - signum =3D 0; - sigcode =3D 0; - sigaddr =3D 0; - - switch (trapnr) { - case EXCP_INTERRUPT: - /* just indicate that signals should be handled asap */ - break; - case EXCP_ATOMIC: - cpu_exec_step_atomic(cs); - break; - case RISCV_EXCP_U_ECALL: - env->pc +=3D 4; - if (env->gpr[xA7] =3D=3D TARGET_NR_arch_specific_syscall + 15)= { - /* riscv_flush_icache_syscall is a no-op in QEMU as - self-modifying code is automatically detected */ - ret =3D 0; - } else { - ret =3D do_syscall(env, - env->gpr[xA7], - env->gpr[xA0], - env->gpr[xA1], - env->gpr[xA2], - env->gpr[xA3], - env->gpr[xA4], - env->gpr[xA5], - 0, 0); - } - if (ret =3D=3D -TARGET_ERESTARTSYS) { - env->pc -=3D 4; - } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { - env->gpr[xA0] =3D ret; - } - if (cs->singlestep_enabled) { - goto gdbstep; - } - break; - case RISCV_EXCP_ILLEGAL_INST: - signum =3D TARGET_SIGILL; - sigcode =3D TARGET_ILL_ILLOPC; - break; - case RISCV_EXCP_BREAKPOINT: - signum =3D TARGET_SIGTRAP; - sigcode =3D TARGET_TRAP_BRKPT; - sigaddr =3D env->pc; - break; - case RISCV_EXCP_INST_PAGE_FAULT: - case RISCV_EXCP_LOAD_PAGE_FAULT: - case RISCV_EXCP_STORE_PAGE_FAULT: - signum =3D TARGET_SIGSEGV; - sigcode =3D TARGET_SEGV_MAPERR; - break; - case EXCP_DEBUG: - gdbstep: - signum =3D gdb_handlesig(cs, TARGET_SIGTRAP); - sigcode =3D TARGET_TRAP_BRKPT; - break; - default: - EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting= \n", - trapnr); - exit(EXIT_FAILURE); - } - - if (signum) { - target_siginfo_t info =3D { - .si_signo =3D signum, - .si_errno =3D 0, - .si_code =3D sigcode, - ._sifields._sigfault._addr =3D sigaddr - }; - queue_signal(env, info.si_signo, QEMU_SI_KILL, &info); - } - - process_pending_signals(env); - } -} - -#endif /* TARGET_RISCV */ - #ifdef TARGET_HPPA =20 static abi_ulong hppa_lws(CPUHPPAState *env) @@ -1319,12 +1225,7 @@ int main(int argc, char **argv, char **envp) =20 target_cpu_copy_regs(env, regs); =20 -#if defined(TARGET_RISCV) - { - env->pc =3D regs->sepc; - env->gpr[xSP] =3D regs->sp; - } -#elif defined(TARGET_HPPA) +#if defined(TARGET_HPPA) { int i; for (i =3D 1; i < 32; i++) { diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index b7700a5561..f137d39d7e 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -21,6 +21,98 @@ #include "qemu.h" #include "cpu_loop-common.h" =20 +void cpu_loop(CPURISCVState *env) +{ + CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + int trapnr, signum, sigcode; + target_ulong sigaddr; + target_ulong ret; + + for (;;) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + signum =3D 0; + sigcode =3D 0; + sigaddr =3D 0; + + switch (trapnr) { + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + case RISCV_EXCP_U_ECALL: + env->pc +=3D 4; + if (env->gpr[xA7] =3D=3D TARGET_NR_arch_specific_syscall + 15)= { + /* riscv_flush_icache_syscall is a no-op in QEMU as + self-modifying code is automatically detected */ + ret =3D 0; + } else { + ret =3D do_syscall(env, + env->gpr[xA7], + env->gpr[xA0], + env->gpr[xA1], + env->gpr[xA2], + env->gpr[xA3], + env->gpr[xA4], + env->gpr[xA5], + 0, 0); + } + if (ret =3D=3D -TARGET_ERESTARTSYS) { + env->pc -=3D 4; + } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { + env->gpr[xA0] =3D ret; + } + if (cs->singlestep_enabled) { + goto gdbstep; + } + break; + case RISCV_EXCP_ILLEGAL_INST: + signum =3D TARGET_SIGILL; + sigcode =3D TARGET_ILL_ILLOPC; + break; + case RISCV_EXCP_BREAKPOINT: + signum =3D TARGET_SIGTRAP; + sigcode =3D TARGET_TRAP_BRKPT; + sigaddr =3D env->pc; + break; + case RISCV_EXCP_INST_PAGE_FAULT: + case RISCV_EXCP_LOAD_PAGE_FAULT: + case RISCV_EXCP_STORE_PAGE_FAULT: + signum =3D TARGET_SIGSEGV; + sigcode =3D TARGET_SEGV_MAPERR; + break; + case EXCP_DEBUG: + gdbstep: + signum =3D gdb_handlesig(cs, TARGET_SIGTRAP); + sigcode =3D TARGET_TRAP_BRKPT; + break; + default: + EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting= \n", + trapnr); + exit(EXIT_FAILURE); + } + + if (signum) { + target_siginfo_t info =3D { + .si_signo =3D signum, + .si_errno =3D 0, + .si_code =3D sigcode, + ._sifields._sigfault._addr =3D sigaddr + }; + queue_signal(env, info.si_signo, QEMU_SI_KILL, &info); + } + + process_pending_signals(env); + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + env->pc =3D regs->sepc; + env->gpr[xSP] =3D regs->sp; } --=20 2.14.3 From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522092705240938.6914333628062; Mon, 26 Mar 2018 12:31:45 -0700 (PDT) Received: from localhost ([::1]:58751 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0XqK-0008SY-Ax for importer@patchew.org; Mon, 26 Mar 2018 15:31:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58964) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0XcO-0003qj-GZ for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:17:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0XcM-0001s5-Qa for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:17:20 -0400 Received: from mout.kundenserver.de ([212.227.126.130]:48471) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0XcF-0001px-EA; Mon, 26 Mar 2018 15:17:11 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0LnpfA-1eKuKB1hCC-00fxo9; Mon, 26 Mar 2018 21:16:44 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:16:02 +0200 Message-Id: <20180326191603.10217-19-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:JYi55ywV53rJF7sMwJJ7r6m7GzVSXWNzui/LR+PvySZ5vtEweo/ 1bgA8aHLfj9x2KECXT1OiOrK3IBEfvm5tfspp5BtbX64cZwLde45xlh3aJmquqI7p1NMXhr NbjVABe47dMofwdo1TCZtlVNThGJWnOZoJSVjxFshT4HLhaK+IcL+AYz5JQVDUCYy+eY71D A/aBNK6AQJHsICC5UpUdQ== X-UI-Out-Filterresults: notjunk:1;V01:K0:+OIAgIm8drI=:4zmHtYw6BynZybNObN+lmS HrV0Pe7JOp19IwZ0TsvM1MbZ7jtuZAOIelAHhnhtFKUnP3K0V2At6ur6mMrxStanFpLCQQIzL 7W6eTb8FISXNIeX0nm6BxAlurwdd7RuZ5ooPvY0jkdwQprAsCIzTVlZ9GR+taFD/AM/6xhOi7 Di2eIS3bOijNL0GGiZlWtXQNtJ8MwXRDqT2lvydrjd+te858E+RGTIzDYhjIrU3TWqGws8ffR gvH6hUlKKbs9VCgJzFVTJjnq9kPhSExKVrVnvaUnfK1qAOKInmjOvof1pjHWolsZAa6PiC1e+ oHh6V435/yi0G72qT/6G7ggtKvjwo+zGEa7Ke01U9tiKcufKlpjsG1Cz0ndRaZmrdIalb2aiO 0KiL+Rot58bA5R+n2PmxGBGbXN9lSArfGQlo27iGBs5ouR1qCMpgpNBA626iXdgJQQrdxUslI 0y6o16lW4ClzM/Q2t+aYnSDdUunghAGqHoyZRTt/IdIkO1fK00XSw9K/x7xNbtpjFsVNuGvux OvS2C34VVfoFuz3bSkXsatVaLf1n9p9kmhqrk+zShcA8ylqzpoYQt8oplHYv/w2cC7t41t4Og hSbAlZMtcwP5XAJNBUBn6ACbZlek928y8Ig7YixOJIaZrPFflZ0fBodfzWiMGfgmf54t+O6Ci 7Jzo3DBZpv/VpgIZvElEiGl6sNVqy9jsKdkvZulY5FvR1yiPGQSFXiTc9InwZx8z4EPozt4W3 Nl/CXqpP9s8NZTtf6CCqMa43nYZLOX03bp1XQQ== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.130 Subject: [Qemu-devel] [PATCH for 2.13 18/19] linux-user: move hppa cpu loop to hppa directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to hppa/cpu_loop.c. Signed-off-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- linux-user/hppa/cpu_loop.c | 185 ++++++++++++++++++++++++++++++++++++++++++ linux-user/main.c | 194 +----------------------------------------= ---- 2 files changed, 186 insertions(+), 193 deletions(-) diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index b7700a5561..0301c766c6 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -21,6 +21,191 @@ #include "qemu.h" #include "cpu_loop-common.h" =20 +static abi_ulong hppa_lws(CPUHPPAState *env) +{ + uint32_t which =3D env->gr[20]; + abi_ulong addr =3D env->gr[26]; + abi_ulong old =3D env->gr[25]; + abi_ulong new =3D env->gr[24]; + abi_ulong size, ret; + + switch (which) { + default: + return -TARGET_ENOSYS; + + case 0: /* elf32 atomic 32bit cmpxchg */ + if ((addr & 3) || !access_ok(VERIFY_WRITE, addr, 4)) { + return -TARGET_EFAULT; + } + old =3D tswap32(old); + new =3D tswap32(new); + ret =3D atomic_cmpxchg((uint32_t *)g2h(addr), old, new); + ret =3D tswap32(ret); + break; + + case 2: /* elf32 atomic "new" cmpxchg */ + size =3D env->gr[23]; + if (size >=3D 4) { + return -TARGET_ENOSYS; + } + if (((addr | old | new) & ((1 << size) - 1)) + || !access_ok(VERIFY_WRITE, addr, 1 << size) + || !access_ok(VERIFY_READ, old, 1 << size) + || !access_ok(VERIFY_READ, new, 1 << size)) { + return -TARGET_EFAULT; + } + /* Note that below we use host-endian loads so that the cmpxchg + can be host-endian as well. */ + switch (size) { + case 0: + old =3D *(uint8_t *)g2h(old); + new =3D *(uint8_t *)g2h(new); + ret =3D atomic_cmpxchg((uint8_t *)g2h(addr), old, new); + ret =3D ret !=3D old; + break; + case 1: + old =3D *(uint16_t *)g2h(old); + new =3D *(uint16_t *)g2h(new); + ret =3D atomic_cmpxchg((uint16_t *)g2h(addr), old, new); + ret =3D ret !=3D old; + break; + case 2: + old =3D *(uint32_t *)g2h(old); + new =3D *(uint32_t *)g2h(new); + ret =3D atomic_cmpxchg((uint32_t *)g2h(addr), old, new); + ret =3D ret !=3D old; + break; + case 3: + { + uint64_t o64, n64, r64; + o64 =3D *(uint64_t *)g2h(old); + n64 =3D *(uint64_t *)g2h(new); +#ifdef CONFIG_ATOMIC64 + r64 =3D atomic_cmpxchg__nocheck((uint64_t *)g2h(addr), o64= , n64); + ret =3D r64 !=3D o64; +#else + start_exclusive(); + r64 =3D *(uint64_t *)g2h(addr); + ret =3D 1; + if (r64 =3D=3D o64) { + *(uint64_t *)g2h(addr) =3D n64; + ret =3D 0; + } + end_exclusive(); +#endif + } + break; + } + break; + } + + env->gr[28] =3D ret; + return 0; +} + +void cpu_loop(CPUHPPAState *env) +{ + CPUState *cs =3D CPU(hppa_env_get_cpu(env)); + target_siginfo_t info; + abi_ulong ret; + int trapnr; + + while (1) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch (trapnr) { + case EXCP_SYSCALL: + ret =3D do_syscall(env, env->gr[20], + env->gr[26], env->gr[25], + env->gr[24], env->gr[23], + env->gr[22], env->gr[21], 0, 0); + switch (ret) { + default: + env->gr[28] =3D ret; + /* We arrived here by faking the gateway page. Return. */ + env->iaoq_f =3D env->gr[31]; + env->iaoq_b =3D env->gr[31] + 4; + break; + case -TARGET_ERESTARTSYS: + case -TARGET_QEMU_ESIGRETURN: + break; + } + break; + case EXCP_SYSCALL_LWS: + env->gr[21] =3D hppa_lws(env); + /* We arrived here by faking the gateway page. Return. */ + env->iaoq_f =3D env->gr[31]; + env->iaoq_b =3D env->gr[31] + 4; + break; + case EXCP_ITLB_MISS: + case EXCP_DTLB_MISS: + case EXCP_NA_ITLB_MISS: + case EXCP_NA_DTLB_MISS: + case EXCP_IMP: + case EXCP_DMP: + case EXCP_DMB: + case EXCP_PAGE_REF: + case EXCP_DMAR: + case EXCP_DMPI: + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info.si_code =3D TARGET_SEGV_ACCERR; + info._sifields._sigfault._addr =3D env->cr[CR_IOR]; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_UNALIGN: + info.si_signo =3D TARGET_SIGBUS; + info.si_errno =3D 0; + info.si_code =3D 0; + info._sifields._sigfault._addr =3D env->cr[CR_IOR]; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_ILL: + case EXCP_PRIV_OPR: + case EXCP_PRIV_REG: + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D TARGET_ILL_ILLOPN; + info._sifields._sigfault._addr =3D env->iaoq_f; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_OVERFLOW: + case EXCP_COND: + case EXCP_ASSIST: + info.si_signo =3D TARGET_SIGFPE; + info.si_errno =3D 0; + info.si_code =3D 0; + info._sifields._sigfault._addr =3D env->iaoq_f; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_DEBUG: + trapnr =3D gdb_handlesig(cs, TARGET_SIGTRAP); + if (trapnr) { + info.si_signo =3D trapnr; + info.si_errno =3D 0; + info.si_code =3D TARGET_TRAP_BRKPT; + queue_signal(env, trapnr, QEMU_SI_FAULT, &info); + } + break; + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + default: + g_assert_not_reached(); + } + process_pending_signals(env); + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + int i; + for (i =3D 1; i < 32; i++) { + env->gr[i] =3D regs->gr[i]; + } + env->iaoq_f =3D regs->iaoq[0]; + env->iaoq_b =3D regs->iaoq[1]; } diff --git a/linux-user/main.c b/linux-user/main.c index 78ff99bd00..8a0a5f9f39 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -149,189 +149,6 @@ void fork_end(int child) } } =20 -#ifdef TARGET_HPPA - -static abi_ulong hppa_lws(CPUHPPAState *env) -{ - uint32_t which =3D env->gr[20]; - abi_ulong addr =3D env->gr[26]; - abi_ulong old =3D env->gr[25]; - abi_ulong new =3D env->gr[24]; - abi_ulong size, ret; - - switch (which) { - default: - return -TARGET_ENOSYS; - - case 0: /* elf32 atomic 32bit cmpxchg */ - if ((addr & 3) || !access_ok(VERIFY_WRITE, addr, 4)) { - return -TARGET_EFAULT; - } - old =3D tswap32(old); - new =3D tswap32(new); - ret =3D atomic_cmpxchg((uint32_t *)g2h(addr), old, new); - ret =3D tswap32(ret); - break; - - case 2: /* elf32 atomic "new" cmpxchg */ - size =3D env->gr[23]; - if (size >=3D 4) { - return -TARGET_ENOSYS; - } - if (((addr | old | new) & ((1 << size) - 1)) - || !access_ok(VERIFY_WRITE, addr, 1 << size) - || !access_ok(VERIFY_READ, old, 1 << size) - || !access_ok(VERIFY_READ, new, 1 << size)) { - return -TARGET_EFAULT; - } - /* Note that below we use host-endian loads so that the cmpxchg - can be host-endian as well. */ - switch (size) { - case 0: - old =3D *(uint8_t *)g2h(old); - new =3D *(uint8_t *)g2h(new); - ret =3D atomic_cmpxchg((uint8_t *)g2h(addr), old, new); - ret =3D ret !=3D old; - break; - case 1: - old =3D *(uint16_t *)g2h(old); - new =3D *(uint16_t *)g2h(new); - ret =3D atomic_cmpxchg((uint16_t *)g2h(addr), old, new); - ret =3D ret !=3D old; - break; - case 2: - old =3D *(uint32_t *)g2h(old); - new =3D *(uint32_t *)g2h(new); - ret =3D atomic_cmpxchg((uint32_t *)g2h(addr), old, new); - ret =3D ret !=3D old; - break; - case 3: - { - uint64_t o64, n64, r64; - o64 =3D *(uint64_t *)g2h(old); - n64 =3D *(uint64_t *)g2h(new); -#ifdef CONFIG_ATOMIC64 - r64 =3D atomic_cmpxchg__nocheck((uint64_t *)g2h(addr), o64= , n64); - ret =3D r64 !=3D o64; -#else - start_exclusive(); - r64 =3D *(uint64_t *)g2h(addr); - ret =3D 1; - if (r64 =3D=3D o64) { - *(uint64_t *)g2h(addr) =3D n64; - ret =3D 0; - } - end_exclusive(); -#endif - } - break; - } - break; - } - - env->gr[28] =3D ret; - return 0; -} - -void cpu_loop(CPUHPPAState *env) -{ - CPUState *cs =3D CPU(hppa_env_get_cpu(env)); - target_siginfo_t info; - abi_ulong ret; - int trapnr; - - while (1) { - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - switch (trapnr) { - case EXCP_SYSCALL: - ret =3D do_syscall(env, env->gr[20], - env->gr[26], env->gr[25], - env->gr[24], env->gr[23], - env->gr[22], env->gr[21], 0, 0); - switch (ret) { - default: - env->gr[28] =3D ret; - /* We arrived here by faking the gateway page. Return. */ - env->iaoq_f =3D env->gr[31]; - env->iaoq_b =3D env->gr[31] + 4; - break; - case -TARGET_ERESTARTSYS: - case -TARGET_QEMU_ESIGRETURN: - break; - } - break; - case EXCP_SYSCALL_LWS: - env->gr[21] =3D hppa_lws(env); - /* We arrived here by faking the gateway page. Return. */ - env->iaoq_f =3D env->gr[31]; - env->iaoq_b =3D env->gr[31] + 4; - break; - case EXCP_ITLB_MISS: - case EXCP_DTLB_MISS: - case EXCP_NA_ITLB_MISS: - case EXCP_NA_DTLB_MISS: - case EXCP_IMP: - case EXCP_DMP: - case EXCP_DMB: - case EXCP_PAGE_REF: - case EXCP_DMAR: - case EXCP_DMPI: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr =3D env->cr[CR_IOR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_UNALIGN: - info.si_signo =3D TARGET_SIGBUS; - info.si_errno =3D 0; - info.si_code =3D 0; - info._sifields._sigfault._addr =3D env->cr[CR_IOR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_ILL: - case EXCP_PRIV_OPR: - case EXCP_PRIV_REG: - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D TARGET_ILL_ILLOPN; - info._sifields._sigfault._addr =3D env->iaoq_f; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_OVERFLOW: - case EXCP_COND: - case EXCP_ASSIST: - info.si_signo =3D TARGET_SIGFPE; - info.si_errno =3D 0; - info.si_code =3D 0; - info._sifields._sigfault._addr =3D env->iaoq_f; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_DEBUG: - trapnr =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (trapnr) { - info.si_signo =3D trapnr; - info.si_errno =3D 0; - info.si_code =3D TARGET_TRAP_BRKPT; - queue_signal(env, trapnr, QEMU_SI_FAULT, &info); - } - break; - case EXCP_INTERRUPT: - /* just indicate that signals should be handled asap */ - break; - default: - g_assert_not_reached(); - } - process_pending_signals(env); - } -} - -#endif /* TARGET_HPPA */ - #ifdef TARGET_XTENSA =20 static void xtensa_rfw(CPUXtensaState *env) @@ -1225,16 +1042,7 @@ int main(int argc, char **argv, char **envp) =20 target_cpu_copy_regs(env, regs); =20 -#if defined(TARGET_HPPA) - { - int i; - for (i =3D 1; i < 32; i++) { - env->gr[i] =3D regs->gr[i]; - } - env->iaoq_f =3D regs->iaoq[0]; - env->iaoq_b =3D regs->iaoq[1]; - } -#elif defined(TARGET_XTENSA) +#if defined(TARGET_XTENSA) { int i; for (i =3D 0; i < 16; ++i) { --=20 2.14.3 From nobody Fri May 3 01:17:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522092558402542.8384433027738; Mon, 26 Mar 2018 12:29:18 -0700 (PDT) Received: from localhost ([::1]:58726 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xnw-0006I3-G0 for importer@patchew.org; Mon, 26 Mar 2018 15:29:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58816) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xc5-0003cX-M4 for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:17:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0Xc3-0001ku-F5 for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:17:01 -0400 Received: from mout.kundenserver.de ([212.227.126.135]:49243) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0Xbv-0001g3-Ql; Mon, 26 Mar 2018 15:16:52 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MHQzX-1enfJO16sF-00E4iQ; Mon, 26 Mar 2018 21:16:45 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:16:03 +0200 Message-Id: <20180326191603.10217-20-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:jau1h27Co0NKXiKGt2xXveI5j+0cwwSuEdvByXoEQ1Prxxiu9cS guvUsyo7iUnTQXtpgEZ7jnTeezmghYFrqtAUhIwiO1oHSUaz1qsOdB6JbF0sU2XkIL5eO6f jew8R1j3nL1xyO/OHem/GUdPoaPDq2g9XMPAVpxjxI+3TRTbprx/30WX2OSDcmuk9rnIdN7 yt9/42xoxd7L+0RQg1DDQ== X-UI-Out-Filterresults: notjunk:1;V01:K0:v7mwVc2uP/w=:gF5h0c7j31n8+Us+p/nH/I 5bsht0lVfGQPDPybYwflddEDtKyIgbPInay7ChjdmO0TQpgti0sYT+tH5s4Qz4x6tklLyMxvP S6Kmsam1Z8V4f+lhQmKsnXArU55qtYSI0VyA5VefLYw2c04WtGxQ7UMEZXC9OfEpHsT7SW9Kk xwuhZB+lnDGdiJ/ZHz2+HxkMvKLZ8E6i/z73f/rGw++Nv/Ua48wXxnuXIah05etF7y75wPz3M JeCvbO8QStadJiOGIhxO3r42qcaoXnP3GNoAnfVc+Zva/sNTR3/BV/kpDodMv+RtRQ/5dESI+ 7JE3kj4UzuMyOpCnITf5Oj9AEc/ZDJQ47vpCzQgOQBEUEac+3iW1W9L4eL5qhxGEgsp9BfyQX kAFnmq5Ml9GHfEyM7C32KITCp/yAuWxGgwLSFamf0iXnLyoEy3eah07lU+SZgQYdYmr5azD8W 3zf+g8T7IBoq6sx6aCXmHlb4RehWZTnyPGRfLdFDPvE6+qDGUrh16okyKFdLr3MqsZfSXZes1 90Cz8vus2zji2sl6wqz4SBndv65eMaVT/izxIwPE5ZkQHdl20dk3e6mE9a1W6YWxh3iQwoK4s sKkxBFXJeYc8+l6PYp678FRo2yh9uxxz+ms4njHa/5AH4xV02td884tdwRAgTv9ZNFvFEYBzu bBjRjZK1UvSl3OFsXlPJummLMNyQlOvJTXHUSeAwpjmL8fszzkhu8ndnw37mFg/5TdwKNWAT1 LGOEC8Ur1a8jT54FJGgn0K60JlNhBeMgtGFe7A== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.135 Subject: [Qemu-devel] [PATCH for 2.13 19/19] linux-user: move xtensa cpu loop to xtensa directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to xtensa/cpu_loop.c. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- linux-user/main.c | 247 ---------------------------------------= ---- linux-user/xtensa/cpu_loop.c | 238 +++++++++++++++++++++++++++++++++++++++= ++ 2 files changed, 238 insertions(+), 247 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 8a0a5f9f39..32347545c9 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -149,242 +149,6 @@ void fork_end(int child) } } =20 -#ifdef TARGET_XTENSA - -static void xtensa_rfw(CPUXtensaState *env) -{ - xtensa_restore_owb(env); - env->pc =3D env->sregs[EPC1]; -} - -static void xtensa_rfwu(CPUXtensaState *env) -{ - env->sregs[WINDOW_START] |=3D (1 << env->sregs[WINDOW_BASE]); - xtensa_rfw(env); -} - -static void xtensa_rfwo(CPUXtensaState *env) -{ - env->sregs[WINDOW_START] &=3D ~(1 << env->sregs[WINDOW_BASE]); - xtensa_rfw(env); -} - -static void xtensa_overflow4(CPUXtensaState *env) -{ - put_user_ual(env->regs[0], env->regs[5] - 16); - put_user_ual(env->regs[1], env->regs[5] - 12); - put_user_ual(env->regs[2], env->regs[5] - 8); - put_user_ual(env->regs[3], env->regs[5] - 4); - xtensa_rfwo(env); -} - -static void xtensa_underflow4(CPUXtensaState *env) -{ - get_user_ual(env->regs[0], env->regs[5] - 16); - get_user_ual(env->regs[1], env->regs[5] - 12); - get_user_ual(env->regs[2], env->regs[5] - 8); - get_user_ual(env->regs[3], env->regs[5] - 4); - xtensa_rfwu(env); -} - -static void xtensa_overflow8(CPUXtensaState *env) -{ - put_user_ual(env->regs[0], env->regs[9] - 16); - get_user_ual(env->regs[0], env->regs[1] - 12); - put_user_ual(env->regs[1], env->regs[9] - 12); - put_user_ual(env->regs[2], env->regs[9] - 8); - put_user_ual(env->regs[3], env->regs[9] - 4); - put_user_ual(env->regs[4], env->regs[0] - 32); - put_user_ual(env->regs[5], env->regs[0] - 28); - put_user_ual(env->regs[6], env->regs[0] - 24); - put_user_ual(env->regs[7], env->regs[0] - 20); - xtensa_rfwo(env); -} - -static void xtensa_underflow8(CPUXtensaState *env) -{ - get_user_ual(env->regs[0], env->regs[9] - 16); - get_user_ual(env->regs[1], env->regs[9] - 12); - get_user_ual(env->regs[2], env->regs[9] - 8); - get_user_ual(env->regs[7], env->regs[1] - 12); - get_user_ual(env->regs[3], env->regs[9] - 4); - get_user_ual(env->regs[4], env->regs[7] - 32); - get_user_ual(env->regs[5], env->regs[7] - 28); - get_user_ual(env->regs[6], env->regs[7] - 24); - get_user_ual(env->regs[7], env->regs[7] - 20); - xtensa_rfwu(env); -} - -static void xtensa_overflow12(CPUXtensaState *env) -{ - put_user_ual(env->regs[0], env->regs[13] - 16); - get_user_ual(env->regs[0], env->regs[1] - 12); - put_user_ual(env->regs[1], env->regs[13] - 12); - put_user_ual(env->regs[2], env->regs[13] - 8); - put_user_ual(env->regs[3], env->regs[13] - 4); - put_user_ual(env->regs[4], env->regs[0] - 48); - put_user_ual(env->regs[5], env->regs[0] - 44); - put_user_ual(env->regs[6], env->regs[0] - 40); - put_user_ual(env->regs[7], env->regs[0] - 36); - put_user_ual(env->regs[8], env->regs[0] - 32); - put_user_ual(env->regs[9], env->regs[0] - 28); - put_user_ual(env->regs[10], env->regs[0] - 24); - put_user_ual(env->regs[11], env->regs[0] - 20); - xtensa_rfwo(env); -} - -static void xtensa_underflow12(CPUXtensaState *env) -{ - get_user_ual(env->regs[0], env->regs[13] - 16); - get_user_ual(env->regs[1], env->regs[13] - 12); - get_user_ual(env->regs[2], env->regs[13] - 8); - get_user_ual(env->regs[11], env->regs[1] - 12); - get_user_ual(env->regs[3], env->regs[13] - 4); - get_user_ual(env->regs[4], env->regs[11] - 48); - get_user_ual(env->regs[5], env->regs[11] - 44); - get_user_ual(env->regs[6], env->regs[11] - 40); - get_user_ual(env->regs[7], env->regs[11] - 36); - get_user_ual(env->regs[8], env->regs[11] - 32); - get_user_ual(env->regs[9], env->regs[11] - 28); - get_user_ual(env->regs[10], env->regs[11] - 24); - get_user_ual(env->regs[11], env->regs[11] - 20); - xtensa_rfwu(env); -} - -void cpu_loop(CPUXtensaState *env) -{ - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); - target_siginfo_t info; - abi_ulong ret; - int trapnr; - - while (1) { - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - env->sregs[PS] &=3D ~PS_EXCM; - switch (trapnr) { - case EXCP_INTERRUPT: - break; - - case EXC_WINDOW_OVERFLOW4: - xtensa_overflow4(env); - break; - case EXC_WINDOW_UNDERFLOW4: - xtensa_underflow4(env); - break; - case EXC_WINDOW_OVERFLOW8: - xtensa_overflow8(env); - break; - case EXC_WINDOW_UNDERFLOW8: - xtensa_underflow8(env); - break; - case EXC_WINDOW_OVERFLOW12: - xtensa_overflow12(env); - break; - case EXC_WINDOW_UNDERFLOW12: - xtensa_underflow12(env); - break; - - case EXC_USER: - switch (env->sregs[EXCCAUSE]) { - case ILLEGAL_INSTRUCTION_CAUSE: - case PRIVILEGED_CAUSE: - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D - env->sregs[EXCCAUSE] =3D=3D ILLEGAL_INSTRUCTION_CAUSE ? - TARGET_ILL_ILLOPC : TARGET_ILL_PRVOPC; - info._sifields._sigfault._addr =3D env->sregs[EPC1]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - - case SYSCALL_CAUSE: - env->pc +=3D 3; - ret =3D do_syscall(env, env->regs[2], - env->regs[6], env->regs[3], - env->regs[4], env->regs[5], - env->regs[8], env->regs[9], 0, 0); - switch (ret) { - default: - env->regs[2] =3D ret; - break; - - case -TARGET_ERESTARTSYS: - case -TARGET_QEMU_ESIGRETURN: - break; - } - break; - - case ALLOCA_CAUSE: - env->sregs[PS] =3D deposit32(env->sregs[PS], - PS_OWB_SHIFT, - PS_OWB_LEN, - env->sregs[WINDOW_BASE]); - - switch (env->regs[0] & 0xc0000000) { - case 0x00000000: - case 0x40000000: - xtensa_rotate_window(env, -1); - xtensa_underflow4(env); - break; - - case 0x80000000: - xtensa_rotate_window(env, -2); - xtensa_underflow8(env); - break; - - case 0xc0000000: - xtensa_rotate_window(env, -3); - xtensa_underflow12(env); - break; - } - break; - - case INTEGER_DIVIDE_BY_ZERO_CAUSE: - info.si_signo =3D TARGET_SIGFPE; - info.si_errno =3D 0; - info.si_code =3D TARGET_FPE_INTDIV; - info._sifields._sigfault._addr =3D env->sregs[EPC1]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - - case LOAD_PROHIBITED_CAUSE: - case STORE_PROHIBITED_CAUSE: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr =3D env->sregs[EXCVADDR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - - default: - fprintf(stderr, "exccause =3D %d\n", env->sregs[EXCCAUSE]); - g_assert_not_reached(); - } - break; - case EXCP_DEBUG: - trapnr =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (trapnr) { - info.si_signo =3D trapnr; - info.si_errno =3D 0; - info.si_code =3D TARGET_TRAP_BRKPT; - queue_signal(env, trapnr, QEMU_SI_FAULT, &info); - } - break; - case EXC_DEBUG: - default: - fprintf(stderr, "trapnr =3D %d\n", trapnr); - g_assert_not_reached(); - } - process_pending_signals(env); - } -} - -#endif /* TARGET_XTENSA */ - __thread CPUState *thread_cpu; =20 bool qemu_cpu_is_self(CPUState *cpu) @@ -1042,17 +806,6 @@ int main(int argc, char **argv, char **envp) =20 target_cpu_copy_regs(env, regs); =20 -#if defined(TARGET_XTENSA) - { - int i; - for (i =3D 0; i < 16; ++i) { - env->regs[i] =3D regs->areg[i]; - } - env->sregs[WINDOW_START] =3D regs->windowstart; - env->pc =3D regs->pc; - } -#endif - if (gdbstub_port) { if (gdbserver_start(gdbstub_port) < 0) { fprintf(stderr, "qemu: could not open gdbserver on port %d\n", diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c index b7700a5561..004da732e5 100644 --- a/linux-user/xtensa/cpu_loop.c +++ b/linux-user/xtensa/cpu_loop.c @@ -21,6 +21,244 @@ #include "qemu.h" #include "cpu_loop-common.h" =20 +static void xtensa_rfw(CPUXtensaState *env) +{ + xtensa_restore_owb(env); + env->pc =3D env->sregs[EPC1]; +} + +static void xtensa_rfwu(CPUXtensaState *env) +{ + env->sregs[WINDOW_START] |=3D (1 << env->sregs[WINDOW_BASE]); + xtensa_rfw(env); +} + +static void xtensa_rfwo(CPUXtensaState *env) +{ + env->sregs[WINDOW_START] &=3D ~(1 << env->sregs[WINDOW_BASE]); + xtensa_rfw(env); +} + +static void xtensa_overflow4(CPUXtensaState *env) +{ + put_user_ual(env->regs[0], env->regs[5] - 16); + put_user_ual(env->regs[1], env->regs[5] - 12); + put_user_ual(env->regs[2], env->regs[5] - 8); + put_user_ual(env->regs[3], env->regs[5] - 4); + xtensa_rfwo(env); +} + +static void xtensa_underflow4(CPUXtensaState *env) +{ + get_user_ual(env->regs[0], env->regs[5] - 16); + get_user_ual(env->regs[1], env->regs[5] - 12); + get_user_ual(env->regs[2], env->regs[5] - 8); + get_user_ual(env->regs[3], env->regs[5] - 4); + xtensa_rfwu(env); +} + +static void xtensa_overflow8(CPUXtensaState *env) +{ + put_user_ual(env->regs[0], env->regs[9] - 16); + get_user_ual(env->regs[0], env->regs[1] - 12); + put_user_ual(env->regs[1], env->regs[9] - 12); + put_user_ual(env->regs[2], env->regs[9] - 8); + put_user_ual(env->regs[3], env->regs[9] - 4); + put_user_ual(env->regs[4], env->regs[0] - 32); + put_user_ual(env->regs[5], env->regs[0] - 28); + put_user_ual(env->regs[6], env->regs[0] - 24); + put_user_ual(env->regs[7], env->regs[0] - 20); + xtensa_rfwo(env); +} + +static void xtensa_underflow8(CPUXtensaState *env) +{ + get_user_ual(env->regs[0], env->regs[9] - 16); + get_user_ual(env->regs[1], env->regs[9] - 12); + get_user_ual(env->regs[2], env->regs[9] - 8); + get_user_ual(env->regs[7], env->regs[1] - 12); + get_user_ual(env->regs[3], env->regs[9] - 4); + get_user_ual(env->regs[4], env->regs[7] - 32); + get_user_ual(env->regs[5], env->regs[7] - 28); + get_user_ual(env->regs[6], env->regs[7] - 24); + get_user_ual(env->regs[7], env->regs[7] - 20); + xtensa_rfwu(env); +} + +static void xtensa_overflow12(CPUXtensaState *env) +{ + put_user_ual(env->regs[0], env->regs[13] - 16); + get_user_ual(env->regs[0], env->regs[1] - 12); + put_user_ual(env->regs[1], env->regs[13] - 12); + put_user_ual(env->regs[2], env->regs[13] - 8); + put_user_ual(env->regs[3], env->regs[13] - 4); + put_user_ual(env->regs[4], env->regs[0] - 48); + put_user_ual(env->regs[5], env->regs[0] - 44); + put_user_ual(env->regs[6], env->regs[0] - 40); + put_user_ual(env->regs[7], env->regs[0] - 36); + put_user_ual(env->regs[8], env->regs[0] - 32); + put_user_ual(env->regs[9], env->regs[0] - 28); + put_user_ual(env->regs[10], env->regs[0] - 24); + put_user_ual(env->regs[11], env->regs[0] - 20); + xtensa_rfwo(env); +} + +static void xtensa_underflow12(CPUXtensaState *env) +{ + get_user_ual(env->regs[0], env->regs[13] - 16); + get_user_ual(env->regs[1], env->regs[13] - 12); + get_user_ual(env->regs[2], env->regs[13] - 8); + get_user_ual(env->regs[11], env->regs[1] - 12); + get_user_ual(env->regs[3], env->regs[13] - 4); + get_user_ual(env->regs[4], env->regs[11] - 48); + get_user_ual(env->regs[5], env->regs[11] - 44); + get_user_ual(env->regs[6], env->regs[11] - 40); + get_user_ual(env->regs[7], env->regs[11] - 36); + get_user_ual(env->regs[8], env->regs[11] - 32); + get_user_ual(env->regs[9], env->regs[11] - 28); + get_user_ual(env->regs[10], env->regs[11] - 24); + get_user_ual(env->regs[11], env->regs[11] - 20); + xtensa_rfwu(env); +} + +void cpu_loop(CPUXtensaState *env) +{ + CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + target_siginfo_t info; + abi_ulong ret; + int trapnr; + + while (1) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + env->sregs[PS] &=3D ~PS_EXCM; + switch (trapnr) { + case EXCP_INTERRUPT: + break; + + case EXC_WINDOW_OVERFLOW4: + xtensa_overflow4(env); + break; + case EXC_WINDOW_UNDERFLOW4: + xtensa_underflow4(env); + break; + case EXC_WINDOW_OVERFLOW8: + xtensa_overflow8(env); + break; + case EXC_WINDOW_UNDERFLOW8: + xtensa_underflow8(env); + break; + case EXC_WINDOW_OVERFLOW12: + xtensa_overflow12(env); + break; + case EXC_WINDOW_UNDERFLOW12: + xtensa_underflow12(env); + break; + + case EXC_USER: + switch (env->sregs[EXCCAUSE]) { + case ILLEGAL_INSTRUCTION_CAUSE: + case PRIVILEGED_CAUSE: + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D + env->sregs[EXCCAUSE] =3D=3D ILLEGAL_INSTRUCTION_CAUSE ? + TARGET_ILL_ILLOPC : TARGET_ILL_PRVOPC; + info._sifields._sigfault._addr =3D env->sregs[EPC1]; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + + case SYSCALL_CAUSE: + env->pc +=3D 3; + ret =3D do_syscall(env, env->regs[2], + env->regs[6], env->regs[3], + env->regs[4], env->regs[5], + env->regs[8], env->regs[9], 0, 0); + switch (ret) { + default: + env->regs[2] =3D ret; + break; + + case -TARGET_ERESTARTSYS: + case -TARGET_QEMU_ESIGRETURN: + break; + } + break; + + case ALLOCA_CAUSE: + env->sregs[PS] =3D deposit32(env->sregs[PS], + PS_OWB_SHIFT, + PS_OWB_LEN, + env->sregs[WINDOW_BASE]); + + switch (env->regs[0] & 0xc0000000) { + case 0x00000000: + case 0x40000000: + xtensa_rotate_window(env, -1); + xtensa_underflow4(env); + break; + + case 0x80000000: + xtensa_rotate_window(env, -2); + xtensa_underflow8(env); + break; + + case 0xc0000000: + xtensa_rotate_window(env, -3); + xtensa_underflow12(env); + break; + } + break; + + case INTEGER_DIVIDE_BY_ZERO_CAUSE: + info.si_signo =3D TARGET_SIGFPE; + info.si_errno =3D 0; + info.si_code =3D TARGET_FPE_INTDIV; + info._sifields._sigfault._addr =3D env->sregs[EPC1]; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + + case LOAD_PROHIBITED_CAUSE: + case STORE_PROHIBITED_CAUSE: + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info.si_code =3D TARGET_SEGV_ACCERR; + info._sifields._sigfault._addr =3D env->sregs[EXCVADDR]; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + + default: + fprintf(stderr, "exccause =3D %d\n", env->sregs[EXCCAUSE]); + g_assert_not_reached(); + } + break; + case EXCP_DEBUG: + trapnr =3D gdb_handlesig(cs, TARGET_SIGTRAP); + if (trapnr) { + info.si_signo =3D trapnr; + info.si_errno =3D 0; + info.si_code =3D TARGET_TRAP_BRKPT; + queue_signal(env, trapnr, QEMU_SI_FAULT, &info); + } + break; + case EXC_DEBUG: + default: + fprintf(stderr, "trapnr =3D %d\n", trapnr); + g_assert_not_reached(); + } + process_pending_signals(env); + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + int i; + for (i =3D 0; i < 16; ++i) { + env->regs[i] =3D regs->areg[i]; + } + env->sregs[WINDOW_START] =3D regs->windowstart; + env->pc =3D regs->pc; } --=20 2.14.3