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X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PULL 1/1] target/hppa: Include priv level in user-only iaoq X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" A recent glibc change relies on the fact that the iaoq must be 3, and computes an address based on that. QEMU had been ignoring the priv level for user-only, which produced an incorrect address. Reported-by: John David Anglin Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 4 ++-- target/hppa/translate.c | 12 ++++-------- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 19dd12a93e..861bbb1f16 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -305,8 +305,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *e= nv, target_ulong *pc, incomplete virtual address. This also means that we must separate out current cpu priviledge from the low bits of IAOQ_F. */ #ifdef CONFIG_USER_ONLY - *pc =3D env->iaoq_f; - *cs_base =3D env->iaoq_b; + *pc =3D env->iaoq_f & -4; + *cs_base =3D env->iaoq_b & -4; #else /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ flags |=3D env->psw & (PSW_W | PSW_C | PSW_D); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6499b392f9..c532889b1f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1909,9 +1909,6 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TC= Gv_reg dest, */ static TCGv_reg do_ibranch_priv(DisasContext *ctx, TCGv_reg offset) { -#ifdef CONFIG_USER_ONLY - return offset; -#else TCGv_reg dest; switch (ctx->privilege) { case 0: @@ -1931,7 +1928,6 @@ static TCGv_reg do_ibranch_priv(DisasContext *ctx, TC= Gv_reg offset) break; } return dest; -#endif } =20 #ifdef CONFIG_USER_ONLY @@ -1967,7 +1963,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) goto do_sigill; } =20 - switch (ctx->iaoq_f) { + switch (ctx->iaoq_f & -4) { case 0x00: /* Null pointer call */ gen_excp_1(EXCP_IMP); return DISAS_NORETURN; @@ -1978,7 +1974,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) =20 case 0xe0: /* SET_THREAD_POINTER */ tcg_gen_st_reg(cpu_gr[26], cpu_env, offsetof(CPUHPPAState, cr[27])= ); - tcg_gen_mov_reg(cpu_iaoq_f, cpu_gr[31]); + tcg_gen_ori_reg(cpu_iaoq_f, cpu_gr[31], 3); tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); return DISAS_IAQ_N_UPDATED; =20 @@ -4697,8 +4693,8 @@ static int hppa_tr_init_disas_context(DisasContextBas= e *dcbase, #ifdef CONFIG_USER_ONLY ctx->privilege =3D MMU_USER_IDX; ctx->mmu_idx =3D MMU_USER_IDX; - ctx->iaoq_f =3D ctx->base.pc_first; - ctx->iaoq_b =3D ctx->base.tb->cs_base; + ctx->iaoq_f =3D ctx->base.pc_first | MMU_USER_IDX; + ctx->iaoq_b =3D ctx->base.tb->cs_base | MMU_USER_IDX; #else ctx->privilege =3D (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; ctx->mmu_idx =3D (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_ID= X); --=20 2.14.3