From nobody Wed May 1 20:30:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521883666863157.28138661346884; Sat, 24 Mar 2018 02:27:46 -0700 (PDT) Received: from localhost ([::1]:41699 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezfSZ-0006Jr-LF for importer@patchew.org; Sat, 24 Mar 2018 05:27:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51476) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezfRZ-0005xK-Qz for qemu-devel@nongnu.org; Sat, 24 Mar 2018 05:26:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ezfRV-0003UO-4m for qemu-devel@nongnu.org; Sat, 24 Mar 2018 05:26:33 -0400 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:39546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ezfRU-0003UB-Ux for qemu-devel@nongnu.org; Sat, 24 Mar 2018 05:26:29 -0400 Received: by mail-pl0-x242.google.com with SMTP id k22-v6so8894177pls.6 for ; Sat, 24 Mar 2018 02:26:28 -0700 (PDT) Received: from cloudburst.twiddle.net ([116.212.193.82]) by smtp.gmail.com with ESMTPSA id b5sm19937957pfc.87.2018.03.24.02.26.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 24 Mar 2018 02:26:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=qUiTSSsq6c5rGqFbHBLcrdZhVbeg08PITJeEu1yNaMg=; b=fLCY1g1vgkjVyoqvhR+ZLn4WWMsF/fYO7FzNH29dRDkVbZ9WYatORwWYOXDnFs5rd7 sh7uM1yesq9cjgyx1dnMKUKDKecqUfS2nRbVMqizzvEVqMGgidiL9vPLiFGEvjyQEXuY GI8kIuMYv7a5SPvMpRk1MFGwD76ZJnbDBFsUk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=qUiTSSsq6c5rGqFbHBLcrdZhVbeg08PITJeEu1yNaMg=; b=KdbfOklDuReo2H0I8Fhx2ZLAQzeDV4YrM8z+bfEy8iiCDnHkdZ3CdrMR5QqxlUxbDj s+0j1UcjT3EnLdIYW2XFnJqujOTxXZYwgHxqJPrEoqrEyaJhMf4Yl4yAIPAS4YE+s2kF lD7oZlr+EobfWEZbCupnrolxL1zaPop7AK9taSOHGMW6KqaikAY7GK5yY4YVU4fPKnXL mV17bxc+sv5QLMSryzXqBCXOWYI72wmapoONLgeBvM5EvHyq8Ex2ONfg6dRH+/TiLDXA B8xhheROR2P/kZIYTEPBE1e5oRMZ3QpR/acpl9VT7BEqS9uw7AU3ajDrkQbLeYFlUyvj m9Jg== X-Gm-Message-State: AElRT7G9QYt39+8IktvbitbLVeJ09Aj26FbFgxsWRg2eJGjWXNTgAHSd HwySLHIgYNAYeMSYlXA+OZebpghwx4A= X-Google-Smtp-Source: AG47ELtM6JraZD89CgCSPmhf6kp5F30HinEwdIadKxVJs25nMUGrqU5CS5iXyjnQeGunLo4WTwchYA== X-Received: by 2002:a17:902:6ac1:: with SMTP id i1-v6mr29449923plt.152.1521883587239; Sat, 24 Mar 2018 02:26:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 24 Mar 2018 17:26:14 +0800 Message-Id: <20180324092614.6176-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH for-2.12] target/hppa: Include priv level in user-only iaoq X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: deller@gmx.de, dave.anglin@bell.net, law@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" A recent glibc change relies on the fact that the priv level in the iaoq must be 3, and computes an address based on that. QEMU had been ignoring the priv level for user-only, which produced an incorrect address. Reported-by: John David Anglin Signed-off-by: Richard Henderson --- I have not set up everything in order to test this vs current glibc, but since I'm forcing the value upon starting translation, I expect it to work. It does at least work with my current sysroot. r~ --- target/hppa/cpu.h | 4 ++-- target/hppa/translate.c | 12 ++++-------- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 19dd12a93e..861bbb1f16 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -305,8 +305,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *e= nv, target_ulong *pc, incomplete virtual address. This also means that we must separate out current cpu priviledge from the low bits of IAOQ_F. */ #ifdef CONFIG_USER_ONLY - *pc =3D env->iaoq_f; - *cs_base =3D env->iaoq_b; + *pc =3D env->iaoq_f & -4; + *cs_base =3D env->iaoq_b & -4; #else /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ flags |=3D env->psw & (PSW_W | PSW_C | PSW_D); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6499b392f9..c532889b1f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1909,9 +1909,6 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TC= Gv_reg dest, */ static TCGv_reg do_ibranch_priv(DisasContext *ctx, TCGv_reg offset) { -#ifdef CONFIG_USER_ONLY - return offset; -#else TCGv_reg dest; switch (ctx->privilege) { case 0: @@ -1931,7 +1928,6 @@ static TCGv_reg do_ibranch_priv(DisasContext *ctx, TC= Gv_reg offset) break; } return dest; -#endif } =20 #ifdef CONFIG_USER_ONLY @@ -1967,7 +1963,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) goto do_sigill; } =20 - switch (ctx->iaoq_f) { + switch (ctx->iaoq_f & -4) { case 0x00: /* Null pointer call */ gen_excp_1(EXCP_IMP); return DISAS_NORETURN; @@ -1978,7 +1974,7 @@ static DisasJumpType do_page_zero(DisasContext *ctx) =20 case 0xe0: /* SET_THREAD_POINTER */ tcg_gen_st_reg(cpu_gr[26], cpu_env, offsetof(CPUHPPAState, cr[27])= ); - tcg_gen_mov_reg(cpu_iaoq_f, cpu_gr[31]); + tcg_gen_ori_reg(cpu_iaoq_f, cpu_gr[31], 3); tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); return DISAS_IAQ_N_UPDATED; =20 @@ -4697,8 +4693,8 @@ static int hppa_tr_init_disas_context(DisasContextBas= e *dcbase, #ifdef CONFIG_USER_ONLY ctx->privilege =3D MMU_USER_IDX; ctx->mmu_idx =3D MMU_USER_IDX; - ctx->iaoq_f =3D ctx->base.pc_first; - ctx->iaoq_b =3D ctx->base.tb->cs_base; + ctx->iaoq_f =3D ctx->base.pc_first | MMU_USER_IDX; + ctx->iaoq_b =3D ctx->base.tb->cs_base | MMU_USER_IDX; #else ctx->privilege =3D (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; ctx->mmu_idx =3D (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_ID= X); --=20 2.14.3