From nobody Fri May 3 18:00:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521831295441305.4048695800044; Fri, 23 Mar 2018 11:54:55 -0700 (PDT) Received: from localhost ([::1]:39386 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRq2-0004ex-KN for importer@patchew.org; Fri, 23 Mar 2018 14:54:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49133) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRlM-00017c-O4 for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ezRlL-0004Ea-PF for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:04 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40508) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ezRlL-0004DB-HX for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:03 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ezRlI-0007dd-42 for qemu-devel@nongnu.org; Fri, 23 Mar 2018 18:50:00 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 23 Mar 2018 18:49:49 +0000 Message-Id: <20180323184958.14252-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180323184958.14252-1-peter.maydell@linaro.org> References: <20180323184958.14252-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 01/10] arm/translate-a64: treat DISAS_UPDATE as variant of DISAS_EXIT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Victor Kamensky In OE project 4.15 linux kernel boot hang was observed under single cpu aarch64 qemu. Kernel code was in a loop waiting for vtimer arrival, spinning in TC generated blocks, while interrupt was pending unprocessed. This happened because when qemu tried to handle vtimer interrupt target had interrupts disabled, as result flag indicating TCG exit, cpu->icount_decr.u16.high, was cleared but arm_cpu_exec_interrupt function did not call arm_cpu_do_interrupt to process interrupt. Later when target reenabled interrupts, it happened without exit into main loop, so following code that waited for result of interrupt execution run in infinite loop. To solve the problem instructions that operate on CPU sys state (i.e enable/disable interrupt), and marked as DISAS_UPDATE, should be considered as DISAS_EXIT variant, and should be forced to exit back to main loop so qemu will have a chance processing pending CPU state updates, including pending interrupts. This change brings consistency with how DISAS_UPDATE is treated in aarch32 case. CC: Peter Maydell CC: Alex Benn=C3=A9e CC: qemu-stable@nongnu.org Suggested-by: Peter Maydell Signed-off-by: Victor Kamensky Reviewed-by: Richard Henderson Message-id: 1521526368-1996-1-git-send-email-kamensky@cisco.com Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 31ff0479e6..327513ef40 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13378,12 +13378,12 @@ static void aarch64_tr_tb_stop(DisasContextBase *= dcbase, CPUState *cpu) case DISAS_UPDATE: gen_a64_set_pc_im(dc->pc); /* fall through */ - case DISAS_JUMP: - tcg_gen_lookup_and_goto_ptr(); - break; case DISAS_EXIT: tcg_gen_exit_tb(0); break; + case DISAS_JUMP: + tcg_gen_lookup_and_goto_ptr(); + break; case DISAS_NORETURN: case DISAS_SWI: break; --=20 2.16.2 From nobody Fri May 3 18:00:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521831151564266.22291179182594; Fri, 23 Mar 2018 11:52:31 -0700 (PDT) Received: from localhost ([::1]:39374 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRnd-0002Te-Tn for importer@patchew.org; Fri, 23 Mar 2018 14:52:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49099) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRlL-00017O-Bg for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ezRlK-0004DZ-Fw for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:03 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40506) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ezRlK-0004CA-9S for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:02 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ezRlI-0007e8-R0 for qemu-devel@nongnu.org; Fri, 23 Mar 2018 18:50:00 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 23 Mar 2018 18:49:50 +0000 Message-Id: <20180323184958.14252-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180323184958.14252-1-peter.maydell@linaro.org> References: <20180323184958.14252-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 02/10] sdhci: fix incorrect use of Error * X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Paolo Bonzini Detected by Coverity (CID 1386072, 1386073, 1386076, 1386077). local_err was unused, and this made the static analyzer unhappy. Signed-off-by: Paolo Bonzini Message-id: 20180320151355.25854-1-pbonzini@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/sd/sdhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 1b828b104d..63c44a4ee8 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1474,7 +1474,7 @@ static void sdhci_pci_realize(PCIDevice *dev, Error *= *errp) Error *local_err =3D NULL; =20 sdhci_initfn(s); - sdhci_common_realize(s, errp); + sdhci_common_realize(s, &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -1556,7 +1556,7 @@ static void sdhci_sysbus_realize(DeviceState *dev, Er= ror ** errp) SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); Error *local_err =3D NULL; =20 - sdhci_common_realize(s, errp); + sdhci_common_realize(s, &local_err); if (local_err) { error_propagate(errp, local_err); return; --=20 2.16.2 From nobody Fri May 3 18:00:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521831294324896.4897768720352; Fri, 23 Mar 2018 11:54:54 -0700 (PDT) Received: from localhost ([::1]:39385 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRq1-0004e9-FK for importer@patchew.org; Fri, 23 Mar 2018 14:54:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49115) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRlL-00017S-Tk for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ezRlK-0004Dp-R4 for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:04 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40508) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ezRlK-0004DB-Jm for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:02 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ezRlJ-0007ec-H5 for qemu-devel@nongnu.org; Fri, 23 Mar 2018 18:50:01 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 23 Mar 2018 18:49:51 +0000 Message-Id: <20180323184958.14252-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180323184958.14252-1-peter.maydell@linaro.org> References: <20180323184958.14252-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 03/10] hw/intc/arm_gicv3: Fix secure-GIC NS ICC_PMR and ICC_RPR accesses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" If the GIC has the security extension support enabled, then a non-secure access to ICC_PMR must take account of the non-secure view of interrupt priorities, where real priorities 0x00..0x7f are secure-only and not visible to the non-secure guest, and priorities 0x80..0xff are shown to the guest as if they were 0x00..0xff. We had the logic here wrong: * on reads, the priority is in the secure range if bit 7 is clear, not if it is set * on writes, we want to set bit 7, not mask everything else Our ICC_RPR read code had the same error as ICC_PMR. (Compare the GICv3 spec pseudocode functions ICC_RPR_EL1 and ICC_PMR_EL1.) Fixes: https://bugs.launchpad.net/qemu/+bug/1748434 Signed-off-by: Peter Maydell Reviewed-by: Andrew Jones Message-id: 20180315133441.24149-1-peter.maydell@linaro.org --- hw/intc/arm_gicv3_cpuif.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 5cbafaf497..26f5eeda94 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -836,7 +836,7 @@ static uint64_t icc_pmr_read(CPUARMState *env, const AR= MCPRegInfo *ri) /* NS access and Group 0 is inaccessible to NS: return the * NS view of the current priority */ - if (value & 0x80) { + if ((value & 0x80) =3D=3D 0) { /* Secure priorities not visible to NS */ value =3D 0; } else if (value !=3D 0xff) { @@ -871,7 +871,7 @@ static void icc_pmr_write(CPUARMState *env, const ARMCP= RegInfo *ri, /* Current PMR in the secure range, don't allow NS to change i= t */ return; } - value =3D (value >> 1) & 0x80; + value =3D (value >> 1) | 0x80; } cs->icc_pmr_el1 =3D value; gicv3_cpuif_update(cs); @@ -1609,7 +1609,7 @@ static uint64_t icc_rpr_read(CPUARMState *env, const = ARMCPRegInfo *ri) if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) && (env->cp15.scr_el3 & SCR_FIQ)) { /* NS GIC access and Group 0 is inaccessible to NS */ - if (prio & 0x80) { + if ((prio & 0x80) =3D=3D 0) { /* NS mustn't see priorities in the Secure half of the range */ prio =3D 0; } else if (prio !=3D 0xff) { --=20 2.16.2 From nobody Fri May 3 18:00:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521831149476813.969984195921; Fri, 23 Mar 2018 11:52:29 -0700 (PDT) Received: from localhost ([::1]:39373 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRnc-0002S0-AZ for importer@patchew.org; Fri, 23 Mar 2018 14:52:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49126) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRlM-00017b-Dq for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ezRlL-0004EF-Ej for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:04 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40506) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ezRlL-0004CA-6u for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:03 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ezRlK-0007et-6q for qemu-devel@nongnu.org; Fri, 23 Mar 2018 18:50:02 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 23 Mar 2018 18:49:52 +0000 Message-Id: <20180323184958.14252-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180323184958.14252-1-peter.maydell@linaro.org> References: <20180323184958.14252-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 04/10] hw/arm/bcm2836: Use the Cortex-A7 instead of Cortex-A15 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 The BCM2836 uses a Cortex-A7, not a Cortex-A15. Update the device to use the correct CPU. https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_= rev3.4.pdf When the BCM2836 was introduced (bad5623690b) the Cortex-A7 was not available, so the very similar Cortex-A15 was used. Since dcf578ed8ce we can model the correct core. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20180319110215.16755-1-peter.maydell@linaro.org --- hw/arm/bcm2836.c | 2 +- hw/arm/raspi.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 3e7e8ca791..3c4b44a53e 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -32,7 +32,7 @@ struct BCM283XInfo { static const BCM283XInfo bcm283x_socs[] =3D { { .name =3D TYPE_BCM2836, - .cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a15"), + .cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7"), .clusterid =3D 0xf, }, #ifdef TARGET_AARCH64 diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 06f1e08ca9..955a7c4e80 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -226,7 +226,7 @@ static void raspi2_machine_init(MachineClass *mc) mc->no_parallel =3D 1; mc->no_floppy =3D 1; mc->no_cdrom =3D 1; - mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a15"); + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7"); mc->max_cpus =3D BCM283X_NCPUS; mc->min_cpus =3D BCM283X_NCPUS; mc->default_cpus =3D BCM283X_NCPUS; --=20 2.16.2 From nobody Fri May 3 18:00:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521831293410347.73805857808486; Fri, 23 Mar 2018 11:54:53 -0700 (PDT) Received: from localhost ([::1]:39384 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRq0-0004cv-Gu for importer@patchew.org; Fri, 23 Mar 2018 14:54:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49140) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRlN-00017i-4y for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ezRlM-0004Et-5P for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:05 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40510) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ezRlL-0004EB-VW for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:04 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ezRlK-0007fP-Tu for qemu-devel@nongnu.org; Fri, 23 Mar 2018 18:50:02 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 23 Mar 2018 18:49:53 +0000 Message-Id: <20180323184958.14252-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180323184958.14252-1-peter.maydell@linaro.org> References: <20180323184958.14252-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 05/10] i.MX: Support serial RS-232 break properly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Trent Piepho Linux does not detect a break from this IMX serial driver as a magic sysrq. Nor does it note a break in the port error counts. The former is because the Linux driver uses the BRCD bit in the USR2 register to trigger the RS-232 break handler in the kernel, which is where sysrq hooks in. The emulated UART was not setting this status bit. The latter is because the Linux driver expects, in addition to the BRK bit, that the ERR bit is set when a break is read in the FIFO. A break should also count as a frame error, so add that bit too. Cc: Andrey Smirnov Signed-off-by: Trent Piepho Message-id: 20180320013657.25038-1-tpiepho@impinj.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/char/imx_serial.h | 1 + hw/char/imx_serial.c | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h index 5b99cee7cf..ee80da12e6 100644 --- a/include/hw/char/imx_serial.h +++ b/include/hw/char/imx_serial.h @@ -26,6 +26,7 @@ =20 #define URXD_CHARRDY (1<<15) /* character read is valid */ #define URXD_ERR (1<<14) /* Character has error */ +#define URXD_FRMERR (1<<12) /* Character has frame error */ #define URXD_BRK (1<<11) /* Break received */ =20 #define USR1_PARTYER (1<<15) /* Parity Error */ diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index 1e5540472b..0747db9f2b 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -308,6 +308,9 @@ static void imx_put_data(void *opaque, uint32_t value) s->usr2 |=3D USR2_RDR; s->uts1 &=3D ~UTS1_RXEMPTY; s->readbuff =3D value; + if (value & URXD_BRK) { + s->usr2 |=3D USR2_BRCD; + } imx_update(s); } =20 @@ -319,7 +322,7 @@ static void imx_receive(void *opaque, const uint8_t *bu= f, int size) static void imx_event(void *opaque, int event) { if (event =3D=3D CHR_EVENT_BREAK) { - imx_put_data(opaque, URXD_BRK); + imx_put_data(opaque, URXD_BRK | URXD_FRMERR | URXD_ERR); } } =20 --=20 2.16.2 From nobody Fri May 3 18:00:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521831151561219.24350565172938; Fri, 23 Mar 2018 11:52:31 -0700 (PDT) Received: from localhost ([::1]:39375 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRng-0002WL-7S for importer@patchew.org; Fri, 23 Mar 2018 14:52:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49155) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRlO-00018I-23 for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ezRlN-0004Fd-3a for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:06 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40510) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ezRlM-0004EB-Ss for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:05 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ezRlL-0007fu-JK for qemu-devel@nongnu.org; Fri, 23 Mar 2018 18:50:03 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 23 Mar 2018 18:49:54 +0000 Message-Id: <20180323184958.14252-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180323184958.14252-1-peter.maydell@linaro.org> References: <20180323184958.14252-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 06/10] mach-virt: Set VM's SMBIOS system version to mc->name X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Wei Huang Instead of using "1.0" as the system version of SMBIOS, we should use mc->name for mach-virt machine type to be consistent other architectures. With this patch, "dmidecode -t 1" (e.g., "-M virt-2.12,accel=3Dkvm") will show: Handle 0x0100, DMI type 1, 27 bytes System Information Manufacturer: QEMU Product Name: KVM Virtual Machine Version: virt-2.12 Serial Number: Not Specified ... instead of: Handle 0x0100, DMI type 1, 27 bytes System Information Manufacturer: QEMU Product Name: KVM Virtual Machine Version: 1.0 Serial Number: Not Specified ... For backward compatibility, we allow older machine types to keep "1.0" as the default system version. Signed-off-by: Wei Huang Reviewed-by: Andrew Jones Message-id: 20180322212318.7182-1-wei@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/virt.h | 1 + hw/arm/virt.c | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 33b0ff3892..ba0c1a4faa 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -85,6 +85,7 @@ typedef struct { bool no_its; bool no_pmu; bool claim_edge_triggered_timers; + bool smbios_old_sys_ver; } VirtMachineClass; =20 typedef struct { diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 2c07245047..94dcb125d3 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1132,6 +1132,8 @@ static void *machvirt_dtb(const struct arm_boot_info = *binfo, int *fdt_size) =20 static void virt_build_smbios(VirtMachineState *vms) { + MachineClass *mc =3D MACHINE_GET_CLASS(vms); + VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); uint8_t *smbios_tables, *smbios_anchor; size_t smbios_tables_len, smbios_anchor_len; const char *product =3D "QEMU Virtual Machine"; @@ -1145,7 +1147,8 @@ static void virt_build_smbios(VirtMachineState *vms) } =20 smbios_set_defaults("QEMU", product, - "1.0", false, true, SMBIOS_ENTRY_POINT_30); + vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, + true, SMBIOS_ENTRY_POINT_30); =20 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, &smbios_anchor, &smbios_anchor_len); @@ -1646,8 +1649,11 @@ static void virt_2_11_instance_init(Object *obj) =20 static void virt_machine_2_11_options(MachineClass *mc) { + VirtMachineClass *vmc =3D VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_2_12_options(mc); SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_11); + vmc->smbios_old_sys_ver =3D true; } DEFINE_VIRT_MACHINE(2, 11) =20 --=20 2.16.2 From nobody Fri May 3 18:00:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521831407621940.8444487089682; Fri, 23 Mar 2018 11:56:47 -0700 (PDT) Received: from localhost ([::1]:39397 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRrq-0006Fq-Pv for importer@patchew.org; Fri, 23 Mar 2018 14:56:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49165) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRlO-000198-Pv for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ezRlN-0004G7-JJ for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:06 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40512) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ezRlN-0004FG-Aq for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:05 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ezRlM-0007gb-9d for qemu-devel@nongnu.org; Fri, 23 Mar 2018 18:50:04 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 23 Mar 2018 18:49:55 +0000 Message-Id: <20180323184958.14252-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180323184958.14252-1-peter.maydell@linaro.org> References: <20180323184958.14252-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 07/10] target/arm: Honour MDCR_EL2.TDE when routing exceptions due to BKPT/BRK X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 The MDCR_EL2.TDE bit allows the exception level targeted by debug exceptions to be set to EL2 for code executing at EL0. We handle this in the arm_debug_target_el() function, but this is only used for hardware breakpoint and watchpoint exceptions, not for the exception generated when the guest executes an AArch32 BKPT or AArch64 BRK instruction. We don't have enough information for a translate-time equivalent of arm_debug_target_el(), so instead make BKPT and BRK call a special purpose helper which can do the routing, rather than the generic exception_with_syndrome helper. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20180320134114.30418-2-peter.maydell@linaro.org --- target/arm/helper.h | 1 + target/arm/op_helper.c | 8 ++++++++ target/arm/translate-a64.c | 15 +++++++++++++-- target/arm/translate.c | 19 ++++++++++++++----- 4 files changed, 36 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 0d2094f2be..34e8cc8904 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -47,6 +47,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(exception_internal, void, env, i32) DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32) +DEF_HELPER_2(exception_bkpt_insn, void, env, i32) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_1(wfe, void, env) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 7a88fd2c92..4b123d2bd6 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -483,6 +483,14 @@ void HELPER(exception_with_syndrome)(CPUARMState *env,= uint32_t excp, raise_exception(env, excp, syndrome, target_el); } =20 +/* Raise an EXCP_BKPT with the specified syndrome register value, + * targeting the correct exception level for debug exceptions. + */ +void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) +{ + raise_exception(env, EXCP_BKPT, syndrome, arm_debug_target_el(env)); +} + uint32_t HELPER(cpsr_read)(CPUARMState *env) { return cpsr_read(env) & ~(CPSR_EXEC | CPSR_RESERVED); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 327513ef40..c91329249d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -321,6 +321,18 @@ static void gen_exception_insn(DisasContext *s, int of= fset, int excp, s->base.is_jmp =3D DISAS_NORETURN; } =20 +static void gen_exception_bkpt_insn(DisasContext *s, int offset, + uint32_t syndrome) +{ + TCGv_i32 tcg_syn; + + gen_a64_set_pc_im(s->pc - offset); + tcg_syn =3D tcg_const_i32(syndrome); + gen_helper_exception_bkpt_insn(cpu_env, tcg_syn); + tcg_temp_free_i32(tcg_syn); + s->base.is_jmp =3D DISAS_NORETURN; +} + static void gen_ss_advance(DisasContext *s) { /* If the singlestep state is Active-not-pending, advance to @@ -1839,8 +1851,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) break; } /* BRK */ - gen_exception_insn(s, 4, EXCP_BKPT, syn_aa64_bkpt(imm16), - default_exception_el(s)); + gen_exception_bkpt_insn(s, 4, syn_aa64_bkpt(imm16)); break; case 2: if (op2_ll !=3D 0) { diff --git a/target/arm/translate.c b/target/arm/translate.c index ba6ab7d287..fc03b5b8c8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1248,6 +1248,18 @@ static void gen_exception_insn(DisasContext *s, int = offset, int excp, s->base.is_jmp =3D DISAS_NORETURN; } =20 +static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t = syn) +{ + TCGv_i32 tcg_syn; + + gen_set_condexec(s); + gen_set_pc_im(s, s->pc - offset); + tcg_syn =3D tcg_const_i32(syn); + gen_helper_exception_bkpt_insn(cpu_env, tcg_syn); + tcg_temp_free_i32(tcg_syn); + s->base.is_jmp =3D DISAS_NORETURN; +} + /* Force a TB lookup after an instruction that changes the CPU state. */ static inline void gen_lookup_tb(DisasContext *s) { @@ -8774,9 +8786,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) case 1: /* bkpt */ ARCH(5); - gen_exception_insn(s, 4, EXCP_BKPT, - syn_aa32_bkpt(imm16, false), - default_exception_el(s)); + gen_exception_bkpt_insn(s, 4, syn_aa32_bkpt(imm16, false)); break; case 2: /* Hypervisor call (v7) */ @@ -11983,8 +11993,7 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) { int imm8 =3D extract32(insn, 0, 8); ARCH(5); - gen_exception_insn(s, 2, EXCP_BKPT, syn_aa32_bkpt(imm8, true), - default_exception_el(s)); + gen_exception_bkpt_insn(s, 2, syn_aa32_bkpt(imm8, true)); break; } =20 --=20 2.16.2 From nobody Fri May 3 18:00:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521831524913398.80506111756006; Fri, 23 Mar 2018 11:58:44 -0700 (PDT) Received: from localhost ([::1]:39404 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRtW-0007ft-D1 for importer@patchew.org; Fri, 23 Mar 2018 14:58:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49178) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRlR-00019N-C7 for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ezRlO-0004Gn-HZ for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:07 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40512) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ezRlO-0004FG-9u for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:06 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ezRlM-0007gs-Va for qemu-devel@nongnu.org; Fri, 23 Mar 2018 18:50:04 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 23 Mar 2018 18:49:56 +0000 Message-Id: <20180323184958.14252-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180323184958.14252-1-peter.maydell@linaro.org> References: <20180323184958.14252-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 08/10] target/arm: Factor out code to calculate FSR for debug exceptions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 When a debug exception is taken to AArch32, it appears as a Prefetch Abort, and the Instruction Fault Status Register (IFSR) must be set. The IFSR has two possible formats, depending on whether LPAE is in use. Factor out the code in arm_debug_excp_handler() which picks an FSR value into its own utility function, update it to use arm_fi_to_lfsc() and arm_fi_to_sfsc() rather than hard-coded constants, and use the correct condition to select long or short format. In particular this fixes a bug where we could select the short format because we're at EL0 and the EL1 translation regime is not using LPAE, but then route the debug exception to EL2 because of MDCR_EL2.TDE and hand EL2 the wrong format FSR. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20180320134114.30418-3-peter.maydell@linaro.org --- target/arm/internals.h | 25 +++++++++++++++++++++++++ target/arm/op_helper.c | 12 ++---------- 2 files changed, 27 insertions(+), 10 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 47cc224a46..8ce944b7a0 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -763,4 +763,29 @@ static inline bool regime_is_secure(CPUARMState *env, = ARMMMUIdx mmu_idx) } } =20 +/* Return the FSR value for a debug exception (watchpoint, hardware + * breakpoint or BKPT insn) targeting the specified exception level. + */ +static inline uint32_t arm_debug_exception_fsr(CPUARMState *env) +{ + ARMMMUFaultInfo fi =3D { .type =3D ARMFault_Debug }; + int target_el =3D arm_debug_target_el(env); + bool using_lpae =3D false; + + if (target_el =3D=3D 2 || arm_el_is_aa64(env, target_el)) { + using_lpae =3D true; + } else { + if (arm_feature(env, ARM_FEATURE_LPAE) && + (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { + using_lpae =3D true; + } + } + + if (using_lpae) { + return arm_fi_to_lfsc(&fi); + } else { + return arm_fi_to_sfsc(&fi); + } +} + #endif diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 4b123d2bd6..75efff9edf 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -1330,11 +1330,7 @@ void arm_debug_excp_handler(CPUState *cs) =20 cs->watchpoint_hit =3D NULL; =20 - if (extended_addresses_enabled(env)) { - env->exception.fsr =3D (1 << 9) | 0x22; - } else { - env->exception.fsr =3D 0x2; - } + env->exception.fsr =3D arm_debug_exception_fsr(env); env->exception.vaddress =3D wp_hit->hitaddr; raise_exception(env, EXCP_DATA_ABORT, syn_watchpoint(same_el, 0, wnr), @@ -1354,11 +1350,7 @@ void arm_debug_excp_handler(CPUState *cs) return; } =20 - if (extended_addresses_enabled(env)) { - env->exception.fsr =3D (1 << 9) | 0x22; - } else { - env->exception.fsr =3D 0x2; - } + env->exception.fsr =3D arm_debug_exception_fsr(env); /* FAR is UNKNOWN, so doesn't need setting */ raise_exception(env, EXCP_PREFETCH_ABORT, syn_breakpoint(same_el), --=20 2.16.2 From nobody Fri May 3 18:00:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521831408786521.3355610104587; Fri, 23 Mar 2018 11:56:48 -0700 (PDT) Received: from localhost ([::1]:39398 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRrs-0006H1-15 for importer@patchew.org; Fri, 23 Mar 2018 14:56:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49183) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRlR-00019O-C5 for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ezRlP-0004H9-04 for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:08 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40514) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ezRlO-0004GT-PS for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:06 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ezRlN-0007hX-Mt for qemu-devel@nongnu.org; Fri, 23 Mar 2018 18:50:05 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 23 Mar 2018 18:49:57 +0000 Message-Id: <20180323184958.14252-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180323184958.14252-1-peter.maydell@linaro.org> References: <20180323184958.14252-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 09/10] target/arm: Set FSR for BKPT, BRK when raising exception X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Now that we have a helper function specifically for the BRK and BKPT instructions, we can set the exception.fsr there rather than in arm_cpu_do_interrupt_aarch32(). This allows us to use our new arm_debug_exception_fsr() helper. In particular this fixes a bug where we were hardcoding the short-form IFSR value, which is wrong if the target exception level has LPAE enabled. Fixes: https://bugs.launchpad.net/qemu/+bug/1756927 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20180320134114.30418-4-peter.maydell@linaro.org --- target/arm/helper.c | 1 - target/arm/op_helper.c | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 09893e3f72..dcb8476d9e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7910,7 +7910,6 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) offset =3D 0; break; case EXCP_BKPT: - env->exception.fsr =3D 2; /* Fall through to prefetch abort. */ case EXCP_PREFETCH_ABORT: A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 75efff9edf..8e1e521193 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -488,6 +488,8 @@ void HELPER(exception_with_syndrome)(CPUARMState *env, = uint32_t excp, */ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) { + /* FSR will only be used if the debug target EL is AArch32. */ + env->exception.fsr =3D arm_debug_exception_fsr(env); raise_exception(env, EXCP_BKPT, syndrome, arm_debug_target_el(env)); } =20 --=20 2.16.2 From nobody Fri May 3 18:00:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521831519756136.1053773072682; Fri, 23 Mar 2018 11:58:39 -0700 (PDT) Received: from localhost ([::1]:39403 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRtV-0007ev-RW for importer@patchew.org; Fri, 23 Mar 2018 14:58:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49188) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ezRlR-00019P-C5 for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ezRlP-0004Hi-TD for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:09 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40514) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ezRlP-0004GT-M7 for qemu-devel@nongnu.org; Fri, 23 Mar 2018 14:50:07 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ezRlO-0007ho-DG for qemu-devel@nongnu.org; Fri, 23 Mar 2018 18:50:06 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 23 Mar 2018 18:49:58 +0000 Message-Id: <20180323184958.14252-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180323184958.14252-1-peter.maydell@linaro.org> References: <20180323184958.14252-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/10] target/arm: Always set FAR to a known unknown value for debug exceptions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 For debug exceptions due to breakpoints or the BKPT instruction which are taken to AArch32, the Fault Address Register is architecturally UNKNOWN. We were using that as license to simply not set env->exception.vaddress, but this isn't correct, because it will expose to the guest whatever old value was in that field when arm_cpu_do_interrupt_aarch32() writes it to the guest IFSR. That old value might be a FAR for a previous guest EL2 or secure exception, in which case we shouldn't show it to an EL1 or non-secure exception handler. It might also be a non-deterministic value, which is bad for record-and-replay. Clear env->exception.vaddress before taking breakpoint debug exceptions, to avoid this minor information leak. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20180320134114.30418-5-peter.maydell@linaro.org --- target/arm/op_helper.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 8e1e521193..a266cc0116 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -490,6 +490,11 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uin= t32_t syndrome) { /* FSR will only be used if the debug target EL is AArch32. */ env->exception.fsr =3D arm_debug_exception_fsr(env); + /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing + * values to the guest that it shouldn't be able to see at its + * exception/security level. + */ + env->exception.vaddress =3D 0; raise_exception(env, EXCP_BKPT, syndrome, arm_debug_target_el(env)); } =20 @@ -1353,7 +1358,11 @@ void arm_debug_excp_handler(CPUState *cs) } =20 env->exception.fsr =3D arm_debug_exception_fsr(env); - /* FAR is UNKNOWN, so doesn't need setting */ + /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing + * values to the guest that it shouldn't be able to see at its + * exception/security level. + */ + env->exception.vaddress =3D 0; raise_exception(env, EXCP_PREFETCH_ABORT, syn_breakpoint(same_el), arm_debug_target_el(env)); --=20 2.16.2